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ARM: imx: Change the way nand devices are registered (imx35)
[linux-2.6/kvm.git] / arch / arm / mach-mx3 / devices.c
blobc8db84942bff320483b9a75a1d3294b323849381
1 /*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
18 */
19
20 #include <linux/dma-mapping.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial.h>
24 #include <linux/gpio.h>
25 #include <mach/hardware.h>
26 #include <mach/irqs.h>
27 #include <mach/common.h>
28 #include <mach/imx-uart.h>
29 #include <mach/mx3_camera.h>
30
31 #include "devices.h"
32
33 static struct resource uart0[] = {
34 {
35 .start = UART1_BASE_ADDR,
36 .end = UART1_BASE_ADDR + 0x0B5,
37 .flags = IORESOURCE_MEM,
38 }, {
39 .start = MXC_INT_UART1,
40 .end = MXC_INT_UART1,
41 .flags = IORESOURCE_IRQ,
42 },
43 };
44
45 struct platform_device mxc_uart_device0 = {
46 .name = "imx-uart",
47 .id = 0,
48 .resource = uart0,
49 .num_resources = ARRAY_SIZE(uart0),
50 };
51
52 static struct resource uart1[] = {
53 {
54 .start = UART2_BASE_ADDR,
55 .end = UART2_BASE_ADDR + 0x0B5,
56 .flags = IORESOURCE_MEM,
57 }, {
58 .start = MXC_INT_UART2,
59 .end = MXC_INT_UART2,
60 .flags = IORESOURCE_IRQ,
61 },
62 };
63
64 struct platform_device mxc_uart_device1 = {
65 .name = "imx-uart",
66 .id = 1,
67 .resource = uart1,
68 .num_resources = ARRAY_SIZE(uart1),
69 };
70
71 static struct resource uart2[] = {
72 {
73 .start = UART3_BASE_ADDR,
74 .end = UART3_BASE_ADDR + 0x0B5,
75 .flags = IORESOURCE_MEM,
76 }, {
77 .start = MXC_INT_UART3,
78 .end = MXC_INT_UART3,
79 .flags = IORESOURCE_IRQ,
80 },
81 };
82
83 struct platform_device mxc_uart_device2 = {
84 .name = "imx-uart",
85 .id = 2,
86 .resource = uart2,
87 .num_resources = ARRAY_SIZE(uart2),
88 };
89
90 #ifdef CONFIG_ARCH_MX31
91 static struct resource uart3[] = {
92 {
93 .start = UART4_BASE_ADDR,
94 .end = UART4_BASE_ADDR + 0x0B5,
95 .flags = IORESOURCE_MEM,
96 }, {
97 .start = MXC_INT_UART4,
98 .end = MXC_INT_UART4,
99 .flags = IORESOURCE_IRQ,
100 },
101 };
102
103 struct platform_device mxc_uart_device3 = {
104 .name = "imx-uart",
105 .id = 3,
106 .resource = uart3,
107 .num_resources = ARRAY_SIZE(uart3),
108 };
109
110 static struct resource uart4[] = {
111 {
112 .start = UART5_BASE_ADDR,
113 .end = UART5_BASE_ADDR + 0x0B5,
114 .flags = IORESOURCE_MEM,
115 }, {
116 .start = MXC_INT_UART5,
117 .end = MXC_INT_UART5,
118 .flags = IORESOURCE_IRQ,
119 },
120 };
121
122 struct platform_device mxc_uart_device4 = {
123 .name = "imx-uart",
124 .id = 4,
125 .resource = uart4,
126 .num_resources = ARRAY_SIZE(uart4),
127 };
128 #endif /* CONFIG_ARCH_MX31 */
129
130 /* GPIO port description */
131 static struct mxc_gpio_port imx_gpio_ports[] = {
132 {
133 .chip.label = "gpio-0",
134 .base = IO_ADDRESS(GPIO1_BASE_ADDR),
135 .irq = MXC_INT_GPIO1,
136 .virtual_irq_start = MXC_GPIO_IRQ_START,
137 }, {
138 .chip.label = "gpio-1",
139 .base = IO_ADDRESS(GPIO2_BASE_ADDR),
140 .irq = MXC_INT_GPIO2,
141 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
142 }, {
143 .chip.label = "gpio-2",
144 .base = IO_ADDRESS(GPIO3_BASE_ADDR),
145 .irq = MXC_INT_GPIO3,
146 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
147 }
148 };
149
150 int __init imx3x_register_gpios(void)
151 {
152 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
153 }
154
155 static struct resource mxc_w1_master_resources[] = {
156 {
157 .start = OWIRE_BASE_ADDR,
158 .end = OWIRE_BASE_ADDR + SZ_4K - 1,
159 .flags = IORESOURCE_MEM,
160 },
161 };
162
163 struct platform_device mxc_w1_master_device = {
164 .name = "mxc_w1",
165 .id = 0,
166 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
167 .resource = mxc_w1_master_resources,
168 };
169
170 static struct resource mxc_i2c0_resources[] = {
171 {
172 .start = I2C_BASE_ADDR,
173 .end = I2C_BASE_ADDR + SZ_4K - 1,
174 .flags = IORESOURCE_MEM,
175 }, {
176 .start = MXC_INT_I2C,
177 .end = MXC_INT_I2C,
178 .flags = IORESOURCE_IRQ,
179 },
180 };
181
182 struct platform_device mxc_i2c_device0 = {
183 .name = "imx-i2c",
184 .id = 0,
185 .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
186 .resource = mxc_i2c0_resources,
187 };
188
189 static struct resource mxc_i2c1_resources[] = {
190 {
191 .start = I2C2_BASE_ADDR,
192 .end = I2C2_BASE_ADDR + SZ_4K - 1,
193 .flags = IORESOURCE_MEM,
194 }, {
195 .start = MXC_INT_I2C2,
196 .end = MXC_INT_I2C2,
197 .flags = IORESOURCE_IRQ,
198 },
199 };
200
201 struct platform_device mxc_i2c_device1 = {
202 .name = "imx-i2c",
203 .id = 1,
204 .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
205 .resource = mxc_i2c1_resources,
206 };
207
208 static struct resource mxc_i2c2_resources[] = {
209 {
210 .start = I2C3_BASE_ADDR,
211 .end = I2C3_BASE_ADDR + SZ_4K - 1,
212 .flags = IORESOURCE_MEM,
213 }, {
214 .start = MXC_INT_I2C3,
215 .end = MXC_INT_I2C3,
216 .flags = IORESOURCE_IRQ,
217 },
218 };
219
220 struct platform_device mxc_i2c_device2 = {
221 .name = "imx-i2c",
222 .id = 2,
223 .num_resources = ARRAY_SIZE(mxc_i2c2_resources),
224 .resource = mxc_i2c2_resources,
225 };
226
227 #ifdef CONFIG_ARCH_MX31
228 static struct resource mxcsdhc0_resources[] = {
229 {
230 .start = MMC_SDHC1_BASE_ADDR,
231 .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
232 .flags = IORESOURCE_MEM,
233 }, {
234 .start = MXC_INT_MMC_SDHC1,
235 .end = MXC_INT_MMC_SDHC1,
236 .flags = IORESOURCE_IRQ,
237 },
238 };
239
240 static struct resource mxcsdhc1_resources[] = {
241 {
242 .start = MMC_SDHC2_BASE_ADDR,
243 .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
244 .flags = IORESOURCE_MEM,
245 }, {
246 .start = MXC_INT_MMC_SDHC2,
247 .end = MXC_INT_MMC_SDHC2,
248 .flags = IORESOURCE_IRQ,
249 },
250 };
251
252 struct platform_device mxcsdhc_device0 = {
253 .name = "mxc-mmc",
254 .id = 0,
255 .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
256 .resource = mxcsdhc0_resources,
257 };
258
259 struct platform_device mxcsdhc_device1 = {
260 .name = "mxc-mmc",
261 .id = 1,
262 .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
263 .resource = mxcsdhc1_resources,
264 };
265
266 static struct resource rnga_resources[] = {
267 {
268 .start = RNGA_BASE_ADDR,
269 .end = RNGA_BASE_ADDR + 0x28,
270 .flags = IORESOURCE_MEM,
271 },
272 };
273
274 struct platform_device mxc_rnga_device = {
275 .name = "mxc_rnga",
276 .id = -1,
277 .num_resources = 1,
278 .resource = rnga_resources,
279 };
280 #endif /* CONFIG_ARCH_MX31 */
281
282 /* i.MX31 Image Processing Unit */
283
284 /* The resource order is important! */
285 static struct resource mx3_ipu_rsrc[] = {
286 {
287 .start = IPU_CTRL_BASE_ADDR,
288 .end = IPU_CTRL_BASE_ADDR + 0x5F,
289 .flags = IORESOURCE_MEM,
290 }, {
291 .start = IPU_CTRL_BASE_ADDR + 0x88,
292 .end = IPU_CTRL_BASE_ADDR + 0xB3,
293 .flags = IORESOURCE_MEM,
294 }, {
295 .start = MXC_INT_IPU_SYN,
296 .end = MXC_INT_IPU_SYN,
297 .flags = IORESOURCE_IRQ,
298 }, {
299 .start = MXC_INT_IPU_ERR,
300 .end = MXC_INT_IPU_ERR,
301 .flags = IORESOURCE_IRQ,
302 },
303 };
304
305 struct platform_device mx3_ipu = {
306 .name = "ipu-core",
307 .id = -1,
308 .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
309 .resource = mx3_ipu_rsrc,
310 };
311
312 static struct resource fb_resources[] = {
313 {
314 .start = IPU_CTRL_BASE_ADDR + 0xB4,
315 .end = IPU_CTRL_BASE_ADDR + 0x1BF,
316 .flags = IORESOURCE_MEM,
317 },
318 };
319
320 struct platform_device mx3_fb = {
321 .name = "mx3_sdc_fb",
322 .id = -1,
323 .num_resources = ARRAY_SIZE(fb_resources),
324 .resource = fb_resources,
325 .dev = {
326 .coherent_dma_mask = DMA_BIT_MASK(32),
327 },
328 };
329
330 static struct resource camera_resources[] = {
331 {
332 .start = IPU_CTRL_BASE_ADDR + 0x60,
333 .end = IPU_CTRL_BASE_ADDR + 0x87,
334 .flags = IORESOURCE_MEM,
335 },
336 };
337
338 struct platform_device mx3_camera = {
339 .name = "mx3-camera",
340 .id = 0,
341 .num_resources = ARRAY_SIZE(camera_resources),
342 .resource = camera_resources,
343 .dev = {
344 .coherent_dma_mask = DMA_BIT_MASK(32),
345 },
346 };
347
348 static struct resource otg_resources[] = {
349 {
350 .start = MX31_OTG_BASE_ADDR,
351 .end = MX31_OTG_BASE_ADDR + 0x1ff,
352 .flags = IORESOURCE_MEM,
353 }, {
354 .start = MXC_INT_USB3,
355 .end = MXC_INT_USB3,
356 .flags = IORESOURCE_IRQ,
357 },
358 };
359
360 static u64 otg_dmamask = DMA_BIT_MASK(32);
361
362 /* OTG gadget device */
363 struct platform_device mxc_otg_udc_device = {
364 .name = "fsl-usb2-udc",
365 .id = -1,
366 .dev = {
367 .dma_mask = &otg_dmamask,
368 .coherent_dma_mask = DMA_BIT_MASK(32),
369 },
370 .resource = otg_resources,
371 .num_resources = ARRAY_SIZE(otg_resources),
372 };
373
374 /* OTG host */
375 struct platform_device mxc_otg_host = {
376 .name = "mxc-ehci",
377 .id = 0,
378 .dev = {
379 .coherent_dma_mask = 0xffffffff,
380 .dma_mask = &otg_dmamask,
381 },
382 .resource = otg_resources,
383 .num_resources = ARRAY_SIZE(otg_resources),
384 };
385
386 /* USB host 1 */
387
388 static u64 usbh1_dmamask = ~(u32)0;
389
390 static struct resource mxc_usbh1_resources[] = {
391 {
392 .start = MX31_OTG_BASE_ADDR + 0x200,
393 .end = MX31_OTG_BASE_ADDR + 0x3ff,
394 .flags = IORESOURCE_MEM,
395 }, {
396 .start = MXC_INT_USB1,
397 .end = MXC_INT_USB1,
398 .flags = IORESOURCE_IRQ,
399 },
400 };
401
402 struct platform_device mxc_usbh1 = {
403 .name = "mxc-ehci",
404 .id = 1,
405 .dev = {
406 .coherent_dma_mask = 0xffffffff,
407 .dma_mask = &usbh1_dmamask,
408 },
409 .resource = mxc_usbh1_resources,
410 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
411 };
412
413 /* USB host 2 */
414 static u64 usbh2_dmamask = ~(u32)0;
415
416 static struct resource mxc_usbh2_resources[] = {
417 {
418 .start = MX31_OTG_BASE_ADDR + 0x400,
419 .end = MX31_OTG_BASE_ADDR + 0x5ff,
420 .flags = IORESOURCE_MEM,
421 }, {
422 .start = MXC_INT_USB2,
423 .end = MXC_INT_USB2,
424 .flags = IORESOURCE_IRQ,
425 },
426 };
427
428 struct platform_device mxc_usbh2 = {
429 .name = "mxc-ehci",
430 .id = 2,
431 .dev = {
432 .coherent_dma_mask = 0xffffffff,
433 .dma_mask = &usbh2_dmamask,
434 },
435 .resource = mxc_usbh2_resources,
436 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
437 };
438
439 /*
440 * SPI master controller
441 * 3 channels
442 */
443 static struct resource mxc_spi_0_resources[] = {
444 {
445 .start = CSPI1_BASE_ADDR,
446 .end = CSPI1_BASE_ADDR + SZ_4K - 1,
447 .flags = IORESOURCE_MEM,
448 }, {
449 .start = MXC_INT_CSPI1,
450 .end = MXC_INT_CSPI1,
451 .flags = IORESOURCE_IRQ,
452 },
453 };
454
455 static struct resource mxc_spi_1_resources[] = {
456 {
457 .start = CSPI2_BASE_ADDR,
458 .end = CSPI2_BASE_ADDR + SZ_4K - 1,
459 .flags = IORESOURCE_MEM,
460 }, {
461 .start = MXC_INT_CSPI2,
462 .end = MXC_INT_CSPI2,
463 .flags = IORESOURCE_IRQ,
464 },
465 };
466
467 static struct resource mxc_spi_2_resources[] = {
468 {
469 .start = CSPI3_BASE_ADDR,
470 .end = CSPI3_BASE_ADDR + SZ_4K - 1,
471 .flags = IORESOURCE_MEM,
472 }, {
473 .start = MXC_INT_CSPI3,
474 .end = MXC_INT_CSPI3,
475 .flags = IORESOURCE_IRQ,
476 },
477 };
478
479 struct platform_device mxc_spi_device0 = {
480 .name = "spi_imx",
481 .id = 0,
482 .num_resources = ARRAY_SIZE(mxc_spi_0_resources),
483 .resource = mxc_spi_0_resources,
484 };
485
486 struct platform_device mxc_spi_device1 = {
487 .name = "spi_imx",
488 .id = 1,
489 .num_resources = ARRAY_SIZE(mxc_spi_1_resources),
490 .resource = mxc_spi_1_resources,
491 };
492
493 struct platform_device mxc_spi_device2 = {
494 .name = "spi_imx",
495 .id = 2,
496 .num_resources = ARRAY_SIZE(mxc_spi_2_resources),
497 .resource = mxc_spi_2_resources,
498 };
499
500 #ifdef CONFIG_ARCH_MX35
501 static struct resource mxc_fec_resources[] = {
502 {
503 .start = MXC_FEC_BASE_ADDR,
504 .end = MXC_FEC_BASE_ADDR + 0xfff,
505 .flags = IORESOURCE_MEM,
506 }, {
507 .start = MXC_INT_FEC,
508 .end = MXC_INT_FEC,
509 .flags = IORESOURCE_IRQ,
510 },
511 };
512
513 struct platform_device mxc_fec_device = {
514 .name = "fec",
515 .id = 0,
516 .num_resources = ARRAY_SIZE(mxc_fec_resources),
517 .resource = mxc_fec_resources,
518 };
519 #endif
520
521 static struct resource imx_ssi_resources0[] = {
522 {
523 .start = SSI1_BASE_ADDR,
524 .end = SSI1_BASE_ADDR + 0xfff,
525 .flags = IORESOURCE_MEM,
526 }, {
527 .start = MX31_INT_SSI1,
528 .end = MX31_INT_SSI1,
529 .flags = IORESOURCE_IRQ,
530 },
531 };
532
533 static struct resource imx_ssi_resources1[] = {
534 {
535 .start = SSI2_BASE_ADDR,
536 .end = SSI2_BASE_ADDR + 0xfff,
537 .flags = IORESOURCE_MEM
538 }, {
539 .start = MX31_INT_SSI2,
540 .end = MX31_INT_SSI2,
541 .flags = IORESOURCE_IRQ,
542 },
543 };
544
545 struct platform_device imx_ssi_device0 = {
546 .name = "imx-ssi",
547 .id = 0,
548 .num_resources = ARRAY_SIZE(imx_ssi_resources0),
549 .resource = imx_ssi_resources0,
550 };
551
552 struct platform_device imx_ssi_device1 = {
553 .name = "imx-ssi",
554 .id = 1,
555 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
556 .resource = imx_ssi_resources1,
557 };
558
559 static struct resource imx_wdt_resources[] = {
560 {
561 .flags = IORESOURCE_MEM,
562 },
563 };
564
565 struct platform_device imx_wdt_device0 = {
566 .name = "imx2-wdt",
567 .id = 0,
568 .num_resources = ARRAY_SIZE(imx_wdt_resources),
569 .resource = imx_wdt_resources,
570 };
571
572 static struct resource imx_rtc_resources[] = {
573 {
574 .start = MX31_RTC_BASE_ADDR,
575 .end = MX31_RTC_BASE_ADDR + 0x3fff,
576 .flags = IORESOURCE_MEM,
577 },
578 {
579 .start = MX31_INT_RTC,
580 .flags = IORESOURCE_IRQ,
581 },
582 };
583
584 struct platform_device imx_rtc_device0 = {
585 .name = "mxc_rtc",
586 .id = -1,
587 .num_resources = ARRAY_SIZE(imx_rtc_resources),
588 .resource = imx_rtc_resources,
589 };
590
591 static struct resource imx_kpp_resources[] = {
592 {
593 .start = MX3x_KPP_BASE_ADDR,
594 .end = MX3x_KPP_BASE_ADDR + 0xf,
595 .flags = IORESOURCE_MEM
596 }, {
597 .start = MX3x_INT_KPP,
598 .end = MX3x_INT_KPP,
599 .flags = IORESOURCE_IRQ,
600 },
601 };
602
603 struct platform_device imx_kpp_device = {
604 .name = "imx-keypad",
605 .id = -1,
606 .num_resources = ARRAY_SIZE(imx_kpp_resources),
607 .resource = imx_kpp_resources,
608 };
609
610 static int __init mx3_devices_init(void)
611 {
612 #if defined(CONFIG_ARCH_MX31)
613 if (cpu_is_mx31()) {
614 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
615 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
616 mxc_register_device(&mxc_rnga_device, NULL);
617 }
618 #endif
619 #if defined(CONFIG_ARCH_MX35)
620 if (cpu_is_mx35()) {
621 otg_resources[0].start = MX35_OTG_BASE_ADDR;
622 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
623 otg_resources[1].start = MXC_INT_USBOTG;
624 otg_resources[1].end = MXC_INT_USBOTG;
625 mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
626 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
627 mxc_usbh1_resources[1].start = MXC_INT_USBHS;
628 mxc_usbh1_resources[1].end = MXC_INT_USBHS;
629 imx_ssi_resources0[1].start = MX35_INT_SSI1;
630 imx_ssi_resources0[1].end = MX35_INT_SSI1;
631 imx_ssi_resources1[1].start = MX35_INT_SSI2;
632 imx_ssi_resources1[1].end = MX35_INT_SSI2;
633 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
634 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
635 }
636 #endif
637
638 return 0;
639 }
640
641 subsys_initcall(mx3_devices_init);
kernel-based virtual machine