2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
4 * Copyright (C) 2009-2010 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
14 #include <plat/omap_hwmod.h>
15 #include <mach/irqs.h>
18 #include <plat/serial.h>
20 #include <plat/gpio.h>
21 #include <plat/mcbsp.h>
22 #include <plat/mcspi.h>
23 #include <plat/dmtimer.h>
25 #include <plat/l3_2xxx.h>
27 #include "omap_hwmod_common_data.h"
29 #include "prm-regbits-24xx.h"
30 #include "cm-regbits-24xx.h"
34 * OMAP2430 hardware module integration data
36 * ALl of the data in this section should be autogeneratable from the
37 * TI hardware database or other technical documentation. Data that
38 * is driver-specific or driver-kernel integration-specific belongs
42 static struct omap_hwmod omap2430_mpu_hwmod
;
43 static struct omap_hwmod omap2430_iva_hwmod
;
44 static struct omap_hwmod omap2430_l3_main_hwmod
;
45 static struct omap_hwmod omap2430_l4_core_hwmod
;
46 static struct omap_hwmod omap2430_dss_core_hwmod
;
47 static struct omap_hwmod omap2430_dss_dispc_hwmod
;
48 static struct omap_hwmod omap2430_dss_rfbi_hwmod
;
49 static struct omap_hwmod omap2430_dss_venc_hwmod
;
50 static struct omap_hwmod omap2430_wd_timer2_hwmod
;
51 static struct omap_hwmod omap2430_gpio1_hwmod
;
52 static struct omap_hwmod omap2430_gpio2_hwmod
;
53 static struct omap_hwmod omap2430_gpio3_hwmod
;
54 static struct omap_hwmod omap2430_gpio4_hwmod
;
55 static struct omap_hwmod omap2430_gpio5_hwmod
;
56 static struct omap_hwmod omap2430_dma_system_hwmod
;
57 static struct omap_hwmod omap2430_mcbsp1_hwmod
;
58 static struct omap_hwmod omap2430_mcbsp2_hwmod
;
59 static struct omap_hwmod omap2430_mcbsp3_hwmod
;
60 static struct omap_hwmod omap2430_mcbsp4_hwmod
;
61 static struct omap_hwmod omap2430_mcbsp5_hwmod
;
62 static struct omap_hwmod omap2430_mcspi1_hwmod
;
63 static struct omap_hwmod omap2430_mcspi2_hwmod
;
64 static struct omap_hwmod omap2430_mcspi3_hwmod
;
65 static struct omap_hwmod omap2430_mmc1_hwmod
;
66 static struct omap_hwmod omap2430_mmc2_hwmod
;
68 /* L3 -> L4_CORE interface */
69 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core
= {
70 .master
= &omap2430_l3_main_hwmod
,
71 .slave
= &omap2430_l4_core_hwmod
,
72 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
75 /* MPU -> L3 interface */
76 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main
= {
77 .master
= &omap2430_mpu_hwmod
,
78 .slave
= &omap2430_l3_main_hwmod
,
82 /* Slave interfaces on the L3 interconnect */
83 static struct omap_hwmod_ocp_if
*omap2430_l3_main_slaves
[] = {
84 &omap2430_mpu__l3_main
,
88 static struct omap_hwmod_ocp_if omap2430_dss__l3
= {
89 .master
= &omap2430_dss_core_hwmod
,
90 .slave
= &omap2430_l3_main_hwmod
,
93 .l3_perm_bit
= OMAP2_L3_CORE_FW_CONNID_DSS
,
94 .flags
= OMAP_FIREWALL_L3
,
97 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
100 /* Master interfaces on the L3 interconnect */
101 static struct omap_hwmod_ocp_if
*omap2430_l3_main_masters
[] = {
102 &omap2430_l3_main__l4_core
,
106 static struct omap_hwmod omap2430_l3_main_hwmod
= {
108 .class = &l3_hwmod_class
,
109 .masters
= omap2430_l3_main_masters
,
110 .masters_cnt
= ARRAY_SIZE(omap2430_l3_main_masters
),
111 .slaves
= omap2430_l3_main_slaves
,
112 .slaves_cnt
= ARRAY_SIZE(omap2430_l3_main_slaves
),
113 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
114 .flags
= HWMOD_NO_IDLEST
,
117 static struct omap_hwmod omap2430_l4_wkup_hwmod
;
118 static struct omap_hwmod omap2430_uart1_hwmod
;
119 static struct omap_hwmod omap2430_uart2_hwmod
;
120 static struct omap_hwmod omap2430_uart3_hwmod
;
121 static struct omap_hwmod omap2430_i2c1_hwmod
;
122 static struct omap_hwmod omap2430_i2c2_hwmod
;
124 static struct omap_hwmod omap2430_usbhsotg_hwmod
;
126 /* l3_core -> usbhsotg interface */
127 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3
= {
128 .master
= &omap2430_usbhsotg_hwmod
,
129 .slave
= &omap2430_l3_main_hwmod
,
131 .user
= OCP_USER_MPU
,
134 /* I2C IP block address space length (in bytes) */
135 #define OMAP2_I2C_AS_LEN 128
137 /* L4 CORE -> I2C1 interface */
138 static struct omap_hwmod_addr_space omap2430_i2c1_addr_space
[] = {
140 .pa_start
= 0x48070000,
141 .pa_end
= 0x48070000 + OMAP2_I2C_AS_LEN
- 1,
142 .flags
= ADDR_TYPE_RT
,
146 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1
= {
147 .master
= &omap2430_l4_core_hwmod
,
148 .slave
= &omap2430_i2c1_hwmod
,
150 .addr
= omap2430_i2c1_addr_space
,
151 .addr_cnt
= ARRAY_SIZE(omap2430_i2c1_addr_space
),
152 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
155 /* L4 CORE -> I2C2 interface */
156 static struct omap_hwmod_addr_space omap2430_i2c2_addr_space
[] = {
158 .pa_start
= 0x48072000,
159 .pa_end
= 0x48072000 + OMAP2_I2C_AS_LEN
- 1,
160 .flags
= ADDR_TYPE_RT
,
164 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2
= {
165 .master
= &omap2430_l4_core_hwmod
,
166 .slave
= &omap2430_i2c2_hwmod
,
168 .addr
= omap2430_i2c2_addr_space
,
169 .addr_cnt
= ARRAY_SIZE(omap2430_i2c2_addr_space
),
170 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
173 /* L4_CORE -> L4_WKUP interface */
174 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup
= {
175 .master
= &omap2430_l4_core_hwmod
,
176 .slave
= &omap2430_l4_wkup_hwmod
,
177 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
180 /* L4 CORE -> UART1 interface */
181 static struct omap_hwmod_addr_space omap2430_uart1_addr_space
[] = {
183 .pa_start
= OMAP2_UART1_BASE
,
184 .pa_end
= OMAP2_UART1_BASE
+ SZ_8K
- 1,
185 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
189 static struct omap_hwmod_ocp_if omap2_l4_core__uart1
= {
190 .master
= &omap2430_l4_core_hwmod
,
191 .slave
= &omap2430_uart1_hwmod
,
193 .addr
= omap2430_uart1_addr_space
,
194 .addr_cnt
= ARRAY_SIZE(omap2430_uart1_addr_space
),
195 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
198 /* L4 CORE -> UART2 interface */
199 static struct omap_hwmod_addr_space omap2430_uart2_addr_space
[] = {
201 .pa_start
= OMAP2_UART2_BASE
,
202 .pa_end
= OMAP2_UART2_BASE
+ SZ_1K
- 1,
203 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
207 static struct omap_hwmod_ocp_if omap2_l4_core__uart2
= {
208 .master
= &omap2430_l4_core_hwmod
,
209 .slave
= &omap2430_uart2_hwmod
,
211 .addr
= omap2430_uart2_addr_space
,
212 .addr_cnt
= ARRAY_SIZE(omap2430_uart2_addr_space
),
213 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
216 /* L4 PER -> UART3 interface */
217 static struct omap_hwmod_addr_space omap2430_uart3_addr_space
[] = {
219 .pa_start
= OMAP2_UART3_BASE
,
220 .pa_end
= OMAP2_UART3_BASE
+ SZ_1K
- 1,
221 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
225 static struct omap_hwmod_ocp_if omap2_l4_core__uart3
= {
226 .master
= &omap2430_l4_core_hwmod
,
227 .slave
= &omap2430_uart3_hwmod
,
229 .addr
= omap2430_uart3_addr_space
,
230 .addr_cnt
= ARRAY_SIZE(omap2430_uart3_addr_space
),
231 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
235 * usbhsotg interface data
237 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs
[] = {
239 .pa_start
= OMAP243X_HS_BASE
,
240 .pa_end
= OMAP243X_HS_BASE
+ SZ_4K
- 1,
241 .flags
= ADDR_TYPE_RT
245 /* l4_core ->usbhsotg interface */
246 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg
= {
247 .master
= &omap2430_l4_core_hwmod
,
248 .slave
= &omap2430_usbhsotg_hwmod
,
250 .addr
= omap2430_usbhsotg_addrs
,
251 .addr_cnt
= ARRAY_SIZE(omap2430_usbhsotg_addrs
),
252 .user
= OCP_USER_MPU
,
255 static struct omap_hwmod_ocp_if
*omap2430_usbhsotg_masters
[] = {
256 &omap2430_usbhsotg__l3
,
259 static struct omap_hwmod_ocp_if
*omap2430_usbhsotg_slaves
[] = {
260 &omap2430_l4_core__usbhsotg
,
263 /* L4 CORE -> MMC1 interface */
264 static struct omap_hwmod_addr_space omap2430_mmc1_addr_space
[] = {
266 .pa_start
= 0x4809c000,
267 .pa_end
= 0x4809c1ff,
268 .flags
= ADDR_TYPE_RT
,
272 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1
= {
273 .master
= &omap2430_l4_core_hwmod
,
274 .slave
= &omap2430_mmc1_hwmod
,
276 .addr
= omap2430_mmc1_addr_space
,
277 .addr_cnt
= ARRAY_SIZE(omap2430_mmc1_addr_space
),
278 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
281 /* L4 CORE -> MMC2 interface */
282 static struct omap_hwmod_addr_space omap2430_mmc2_addr_space
[] = {
284 .pa_start
= 0x480b4000,
285 .pa_end
= 0x480b41ff,
286 .flags
= ADDR_TYPE_RT
,
290 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2
= {
291 .master
= &omap2430_l4_core_hwmod
,
292 .slave
= &omap2430_mmc2_hwmod
,
293 .addr
= omap2430_mmc2_addr_space
,
295 .addr_cnt
= ARRAY_SIZE(omap2430_mmc2_addr_space
),
296 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
299 /* Slave interfaces on the L4_CORE interconnect */
300 static struct omap_hwmod_ocp_if
*omap2430_l4_core_slaves
[] = {
301 &omap2430_l3_main__l4_core
,
304 /* Master interfaces on the L4_CORE interconnect */
305 static struct omap_hwmod_ocp_if
*omap2430_l4_core_masters
[] = {
306 &omap2430_l4_core__l4_wkup
,
307 &omap2430_l4_core__mmc1
,
308 &omap2430_l4_core__mmc2
,
312 static struct omap_hwmod omap2430_l4_core_hwmod
= {
314 .class = &l4_hwmod_class
,
315 .masters
= omap2430_l4_core_masters
,
316 .masters_cnt
= ARRAY_SIZE(omap2430_l4_core_masters
),
317 .slaves
= omap2430_l4_core_slaves
,
318 .slaves_cnt
= ARRAY_SIZE(omap2430_l4_core_slaves
),
319 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
320 .flags
= HWMOD_NO_IDLEST
,
323 /* Slave interfaces on the L4_WKUP interconnect */
324 static struct omap_hwmod_ocp_if
*omap2430_l4_wkup_slaves
[] = {
325 &omap2430_l4_core__l4_wkup
,
326 &omap2_l4_core__uart1
,
327 &omap2_l4_core__uart2
,
328 &omap2_l4_core__uart3
,
331 /* Master interfaces on the L4_WKUP interconnect */
332 static struct omap_hwmod_ocp_if
*omap2430_l4_wkup_masters
[] = {
335 /* l4 core -> mcspi1 interface */
336 static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space
[] = {
338 .pa_start
= 0x48098000,
339 .pa_end
= 0x480980ff,
340 .flags
= ADDR_TYPE_RT
,
344 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1
= {
345 .master
= &omap2430_l4_core_hwmod
,
346 .slave
= &omap2430_mcspi1_hwmod
,
348 .addr
= omap2430_mcspi1_addr_space
,
349 .addr_cnt
= ARRAY_SIZE(omap2430_mcspi1_addr_space
),
350 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
353 /* l4 core -> mcspi2 interface */
354 static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space
[] = {
356 .pa_start
= 0x4809a000,
357 .pa_end
= 0x4809a0ff,
358 .flags
= ADDR_TYPE_RT
,
362 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2
= {
363 .master
= &omap2430_l4_core_hwmod
,
364 .slave
= &omap2430_mcspi2_hwmod
,
366 .addr
= omap2430_mcspi2_addr_space
,
367 .addr_cnt
= ARRAY_SIZE(omap2430_mcspi2_addr_space
),
368 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
371 /* l4 core -> mcspi3 interface */
372 static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space
[] = {
374 .pa_start
= 0x480b8000,
375 .pa_end
= 0x480b80ff,
376 .flags
= ADDR_TYPE_RT
,
380 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3
= {
381 .master
= &omap2430_l4_core_hwmod
,
382 .slave
= &omap2430_mcspi3_hwmod
,
384 .addr
= omap2430_mcspi3_addr_space
,
385 .addr_cnt
= ARRAY_SIZE(omap2430_mcspi3_addr_space
),
386 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
390 static struct omap_hwmod omap2430_l4_wkup_hwmod
= {
392 .class = &l4_hwmod_class
,
393 .masters
= omap2430_l4_wkup_masters
,
394 .masters_cnt
= ARRAY_SIZE(omap2430_l4_wkup_masters
),
395 .slaves
= omap2430_l4_wkup_slaves
,
396 .slaves_cnt
= ARRAY_SIZE(omap2430_l4_wkup_slaves
),
397 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
398 .flags
= HWMOD_NO_IDLEST
,
401 /* Master interfaces on the MPU device */
402 static struct omap_hwmod_ocp_if
*omap2430_mpu_masters
[] = {
403 &omap2430_mpu__l3_main
,
407 static struct omap_hwmod omap2430_mpu_hwmod
= {
409 .class = &mpu_hwmod_class
,
410 .main_clk
= "mpu_ck",
411 .masters
= omap2430_mpu_masters
,
412 .masters_cnt
= ARRAY_SIZE(omap2430_mpu_masters
),
413 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
417 * IVA2_1 interface data
420 /* IVA2 <- L3 interface */
421 static struct omap_hwmod_ocp_if omap2430_l3__iva
= {
422 .master
= &omap2430_l3_main_hwmod
,
423 .slave
= &omap2430_iva_hwmod
,
425 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
428 static struct omap_hwmod_ocp_if
*omap2430_iva_masters
[] = {
436 static struct omap_hwmod omap2430_iva_hwmod
= {
438 .class = &iva_hwmod_class
,
439 .masters
= omap2430_iva_masters
,
440 .masters_cnt
= ARRAY_SIZE(omap2430_iva_masters
),
441 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
445 static struct omap_hwmod_class_sysconfig omap2430_timer_sysc
= {
449 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
450 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
452 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
453 .sysc_fields
= &omap_hwmod_sysc_type1
,
456 static struct omap_hwmod_class omap2430_timer_hwmod_class
= {
458 .sysc
= &omap2430_timer_sysc
,
459 .rev
= OMAP_TIMER_IP_VERSION_1
,
463 static struct omap_hwmod omap2430_timer1_hwmod
;
464 static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs
[] = {
468 static struct omap_hwmod_addr_space omap2430_timer1_addrs
[] = {
470 .pa_start
= 0x49018000,
471 .pa_end
= 0x49018000 + SZ_1K
- 1,
472 .flags
= ADDR_TYPE_RT
476 /* l4_wkup -> timer1 */
477 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1
= {
478 .master
= &omap2430_l4_wkup_hwmod
,
479 .slave
= &omap2430_timer1_hwmod
,
481 .addr
= omap2430_timer1_addrs
,
482 .addr_cnt
= ARRAY_SIZE(omap2430_timer1_addrs
),
483 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
486 /* timer1 slave port */
487 static struct omap_hwmod_ocp_if
*omap2430_timer1_slaves
[] = {
488 &omap2430_l4_wkup__timer1
,
492 static struct omap_hwmod omap2430_timer1_hwmod
= {
494 .mpu_irqs
= omap2430_timer1_mpu_irqs
,
495 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer1_mpu_irqs
),
496 .main_clk
= "gpt1_fck",
500 .module_bit
= OMAP24XX_EN_GPT1_SHIFT
,
501 .module_offs
= WKUP_MOD
,
503 .idlest_idle_bit
= OMAP24XX_ST_GPT1_SHIFT
,
506 .slaves
= omap2430_timer1_slaves
,
507 .slaves_cnt
= ARRAY_SIZE(omap2430_timer1_slaves
),
508 .class = &omap2430_timer_hwmod_class
,
509 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
513 static struct omap_hwmod omap2430_timer2_hwmod
;
514 static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs
[] = {
518 static struct omap_hwmod_addr_space omap2430_timer2_addrs
[] = {
520 .pa_start
= 0x4802a000,
521 .pa_end
= 0x4802a000 + SZ_1K
- 1,
522 .flags
= ADDR_TYPE_RT
526 /* l4_core -> timer2 */
527 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2
= {
528 .master
= &omap2430_l4_core_hwmod
,
529 .slave
= &omap2430_timer2_hwmod
,
531 .addr
= omap2430_timer2_addrs
,
532 .addr_cnt
= ARRAY_SIZE(omap2430_timer2_addrs
),
533 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
536 /* timer2 slave port */
537 static struct omap_hwmod_ocp_if
*omap2430_timer2_slaves
[] = {
538 &omap2430_l4_core__timer2
,
542 static struct omap_hwmod omap2430_timer2_hwmod
= {
544 .mpu_irqs
= omap2430_timer2_mpu_irqs
,
545 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer2_mpu_irqs
),
546 .main_clk
= "gpt2_fck",
550 .module_bit
= OMAP24XX_EN_GPT2_SHIFT
,
551 .module_offs
= CORE_MOD
,
553 .idlest_idle_bit
= OMAP24XX_ST_GPT2_SHIFT
,
556 .slaves
= omap2430_timer2_slaves
,
557 .slaves_cnt
= ARRAY_SIZE(omap2430_timer2_slaves
),
558 .class = &omap2430_timer_hwmod_class
,
559 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
563 static struct omap_hwmod omap2430_timer3_hwmod
;
564 static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs
[] = {
568 static struct omap_hwmod_addr_space omap2430_timer3_addrs
[] = {
570 .pa_start
= 0x48078000,
571 .pa_end
= 0x48078000 + SZ_1K
- 1,
572 .flags
= ADDR_TYPE_RT
576 /* l4_core -> timer3 */
577 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3
= {
578 .master
= &omap2430_l4_core_hwmod
,
579 .slave
= &omap2430_timer3_hwmod
,
581 .addr
= omap2430_timer3_addrs
,
582 .addr_cnt
= ARRAY_SIZE(omap2430_timer3_addrs
),
583 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
586 /* timer3 slave port */
587 static struct omap_hwmod_ocp_if
*omap2430_timer3_slaves
[] = {
588 &omap2430_l4_core__timer3
,
592 static struct omap_hwmod omap2430_timer3_hwmod
= {
594 .mpu_irqs
= omap2430_timer3_mpu_irqs
,
595 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer3_mpu_irqs
),
596 .main_clk
= "gpt3_fck",
600 .module_bit
= OMAP24XX_EN_GPT3_SHIFT
,
601 .module_offs
= CORE_MOD
,
603 .idlest_idle_bit
= OMAP24XX_ST_GPT3_SHIFT
,
606 .slaves
= omap2430_timer3_slaves
,
607 .slaves_cnt
= ARRAY_SIZE(omap2430_timer3_slaves
),
608 .class = &omap2430_timer_hwmod_class
,
609 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
613 static struct omap_hwmod omap2430_timer4_hwmod
;
614 static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs
[] = {
618 static struct omap_hwmod_addr_space omap2430_timer4_addrs
[] = {
620 .pa_start
= 0x4807a000,
621 .pa_end
= 0x4807a000 + SZ_1K
- 1,
622 .flags
= ADDR_TYPE_RT
626 /* l4_core -> timer4 */
627 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4
= {
628 .master
= &omap2430_l4_core_hwmod
,
629 .slave
= &omap2430_timer4_hwmod
,
631 .addr
= omap2430_timer4_addrs
,
632 .addr_cnt
= ARRAY_SIZE(omap2430_timer4_addrs
),
633 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
636 /* timer4 slave port */
637 static struct omap_hwmod_ocp_if
*omap2430_timer4_slaves
[] = {
638 &omap2430_l4_core__timer4
,
642 static struct omap_hwmod omap2430_timer4_hwmod
= {
644 .mpu_irqs
= omap2430_timer4_mpu_irqs
,
645 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer4_mpu_irqs
),
646 .main_clk
= "gpt4_fck",
650 .module_bit
= OMAP24XX_EN_GPT4_SHIFT
,
651 .module_offs
= CORE_MOD
,
653 .idlest_idle_bit
= OMAP24XX_ST_GPT4_SHIFT
,
656 .slaves
= omap2430_timer4_slaves
,
657 .slaves_cnt
= ARRAY_SIZE(omap2430_timer4_slaves
),
658 .class = &omap2430_timer_hwmod_class
,
659 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
663 static struct omap_hwmod omap2430_timer5_hwmod
;
664 static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs
[] = {
668 static struct omap_hwmod_addr_space omap2430_timer5_addrs
[] = {
670 .pa_start
= 0x4807c000,
671 .pa_end
= 0x4807c000 + SZ_1K
- 1,
672 .flags
= ADDR_TYPE_RT
676 /* l4_core -> timer5 */
677 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5
= {
678 .master
= &omap2430_l4_core_hwmod
,
679 .slave
= &omap2430_timer5_hwmod
,
681 .addr
= omap2430_timer5_addrs
,
682 .addr_cnt
= ARRAY_SIZE(omap2430_timer5_addrs
),
683 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
686 /* timer5 slave port */
687 static struct omap_hwmod_ocp_if
*omap2430_timer5_slaves
[] = {
688 &omap2430_l4_core__timer5
,
692 static struct omap_hwmod omap2430_timer5_hwmod
= {
694 .mpu_irqs
= omap2430_timer5_mpu_irqs
,
695 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer5_mpu_irqs
),
696 .main_clk
= "gpt5_fck",
700 .module_bit
= OMAP24XX_EN_GPT5_SHIFT
,
701 .module_offs
= CORE_MOD
,
703 .idlest_idle_bit
= OMAP24XX_ST_GPT5_SHIFT
,
706 .slaves
= omap2430_timer5_slaves
,
707 .slaves_cnt
= ARRAY_SIZE(omap2430_timer5_slaves
),
708 .class = &omap2430_timer_hwmod_class
,
709 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
713 static struct omap_hwmod omap2430_timer6_hwmod
;
714 static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs
[] = {
718 static struct omap_hwmod_addr_space omap2430_timer6_addrs
[] = {
720 .pa_start
= 0x4807e000,
721 .pa_end
= 0x4807e000 + SZ_1K
- 1,
722 .flags
= ADDR_TYPE_RT
726 /* l4_core -> timer6 */
727 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6
= {
728 .master
= &omap2430_l4_core_hwmod
,
729 .slave
= &omap2430_timer6_hwmod
,
731 .addr
= omap2430_timer6_addrs
,
732 .addr_cnt
= ARRAY_SIZE(omap2430_timer6_addrs
),
733 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
736 /* timer6 slave port */
737 static struct omap_hwmod_ocp_if
*omap2430_timer6_slaves
[] = {
738 &omap2430_l4_core__timer6
,
742 static struct omap_hwmod omap2430_timer6_hwmod
= {
744 .mpu_irqs
= omap2430_timer6_mpu_irqs
,
745 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer6_mpu_irqs
),
746 .main_clk
= "gpt6_fck",
750 .module_bit
= OMAP24XX_EN_GPT6_SHIFT
,
751 .module_offs
= CORE_MOD
,
753 .idlest_idle_bit
= OMAP24XX_ST_GPT6_SHIFT
,
756 .slaves
= omap2430_timer6_slaves
,
757 .slaves_cnt
= ARRAY_SIZE(omap2430_timer6_slaves
),
758 .class = &omap2430_timer_hwmod_class
,
759 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
763 static struct omap_hwmod omap2430_timer7_hwmod
;
764 static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs
[] = {
768 static struct omap_hwmod_addr_space omap2430_timer7_addrs
[] = {
770 .pa_start
= 0x48080000,
771 .pa_end
= 0x48080000 + SZ_1K
- 1,
772 .flags
= ADDR_TYPE_RT
776 /* l4_core -> timer7 */
777 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7
= {
778 .master
= &omap2430_l4_core_hwmod
,
779 .slave
= &omap2430_timer7_hwmod
,
781 .addr
= omap2430_timer7_addrs
,
782 .addr_cnt
= ARRAY_SIZE(omap2430_timer7_addrs
),
783 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
786 /* timer7 slave port */
787 static struct omap_hwmod_ocp_if
*omap2430_timer7_slaves
[] = {
788 &omap2430_l4_core__timer7
,
792 static struct omap_hwmod omap2430_timer7_hwmod
= {
794 .mpu_irqs
= omap2430_timer7_mpu_irqs
,
795 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer7_mpu_irqs
),
796 .main_clk
= "gpt7_fck",
800 .module_bit
= OMAP24XX_EN_GPT7_SHIFT
,
801 .module_offs
= CORE_MOD
,
803 .idlest_idle_bit
= OMAP24XX_ST_GPT7_SHIFT
,
806 .slaves
= omap2430_timer7_slaves
,
807 .slaves_cnt
= ARRAY_SIZE(omap2430_timer7_slaves
),
808 .class = &omap2430_timer_hwmod_class
,
809 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
813 static struct omap_hwmod omap2430_timer8_hwmod
;
814 static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs
[] = {
818 static struct omap_hwmod_addr_space omap2430_timer8_addrs
[] = {
820 .pa_start
= 0x48082000,
821 .pa_end
= 0x48082000 + SZ_1K
- 1,
822 .flags
= ADDR_TYPE_RT
826 /* l4_core -> timer8 */
827 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8
= {
828 .master
= &omap2430_l4_core_hwmod
,
829 .slave
= &omap2430_timer8_hwmod
,
831 .addr
= omap2430_timer8_addrs
,
832 .addr_cnt
= ARRAY_SIZE(omap2430_timer8_addrs
),
833 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
836 /* timer8 slave port */
837 static struct omap_hwmod_ocp_if
*omap2430_timer8_slaves
[] = {
838 &omap2430_l4_core__timer8
,
842 static struct omap_hwmod omap2430_timer8_hwmod
= {
844 .mpu_irqs
= omap2430_timer8_mpu_irqs
,
845 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer8_mpu_irqs
),
846 .main_clk
= "gpt8_fck",
850 .module_bit
= OMAP24XX_EN_GPT8_SHIFT
,
851 .module_offs
= CORE_MOD
,
853 .idlest_idle_bit
= OMAP24XX_ST_GPT8_SHIFT
,
856 .slaves
= omap2430_timer8_slaves
,
857 .slaves_cnt
= ARRAY_SIZE(omap2430_timer8_slaves
),
858 .class = &omap2430_timer_hwmod_class
,
859 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
863 static struct omap_hwmod omap2430_timer9_hwmod
;
864 static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs
[] = {
868 static struct omap_hwmod_addr_space omap2430_timer9_addrs
[] = {
870 .pa_start
= 0x48084000,
871 .pa_end
= 0x48084000 + SZ_1K
- 1,
872 .flags
= ADDR_TYPE_RT
876 /* l4_core -> timer9 */
877 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9
= {
878 .master
= &omap2430_l4_core_hwmod
,
879 .slave
= &omap2430_timer9_hwmod
,
881 .addr
= omap2430_timer9_addrs
,
882 .addr_cnt
= ARRAY_SIZE(omap2430_timer9_addrs
),
883 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
886 /* timer9 slave port */
887 static struct omap_hwmod_ocp_if
*omap2430_timer9_slaves
[] = {
888 &omap2430_l4_core__timer9
,
892 static struct omap_hwmod omap2430_timer9_hwmod
= {
894 .mpu_irqs
= omap2430_timer9_mpu_irqs
,
895 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer9_mpu_irqs
),
896 .main_clk
= "gpt9_fck",
900 .module_bit
= OMAP24XX_EN_GPT9_SHIFT
,
901 .module_offs
= CORE_MOD
,
903 .idlest_idle_bit
= OMAP24XX_ST_GPT9_SHIFT
,
906 .slaves
= omap2430_timer9_slaves
,
907 .slaves_cnt
= ARRAY_SIZE(omap2430_timer9_slaves
),
908 .class = &omap2430_timer_hwmod_class
,
909 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
913 static struct omap_hwmod omap2430_timer10_hwmod
;
914 static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs
[] = {
918 static struct omap_hwmod_addr_space omap2430_timer10_addrs
[] = {
920 .pa_start
= 0x48086000,
921 .pa_end
= 0x48086000 + SZ_1K
- 1,
922 .flags
= ADDR_TYPE_RT
926 /* l4_core -> timer10 */
927 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10
= {
928 .master
= &omap2430_l4_core_hwmod
,
929 .slave
= &omap2430_timer10_hwmod
,
931 .addr
= omap2430_timer10_addrs
,
932 .addr_cnt
= ARRAY_SIZE(omap2430_timer10_addrs
),
933 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
936 /* timer10 slave port */
937 static struct omap_hwmod_ocp_if
*omap2430_timer10_slaves
[] = {
938 &omap2430_l4_core__timer10
,
942 static struct omap_hwmod omap2430_timer10_hwmod
= {
944 .mpu_irqs
= omap2430_timer10_mpu_irqs
,
945 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer10_mpu_irqs
),
946 .main_clk
= "gpt10_fck",
950 .module_bit
= OMAP24XX_EN_GPT10_SHIFT
,
951 .module_offs
= CORE_MOD
,
953 .idlest_idle_bit
= OMAP24XX_ST_GPT10_SHIFT
,
956 .slaves
= omap2430_timer10_slaves
,
957 .slaves_cnt
= ARRAY_SIZE(omap2430_timer10_slaves
),
958 .class = &omap2430_timer_hwmod_class
,
959 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
963 static struct omap_hwmod omap2430_timer11_hwmod
;
964 static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs
[] = {
968 static struct omap_hwmod_addr_space omap2430_timer11_addrs
[] = {
970 .pa_start
= 0x48088000,
971 .pa_end
= 0x48088000 + SZ_1K
- 1,
972 .flags
= ADDR_TYPE_RT
976 /* l4_core -> timer11 */
977 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11
= {
978 .master
= &omap2430_l4_core_hwmod
,
979 .slave
= &omap2430_timer11_hwmod
,
981 .addr
= omap2430_timer11_addrs
,
982 .addr_cnt
= ARRAY_SIZE(omap2430_timer11_addrs
),
983 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
986 /* timer11 slave port */
987 static struct omap_hwmod_ocp_if
*omap2430_timer11_slaves
[] = {
988 &omap2430_l4_core__timer11
,
992 static struct omap_hwmod omap2430_timer11_hwmod
= {
994 .mpu_irqs
= omap2430_timer11_mpu_irqs
,
995 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer11_mpu_irqs
),
996 .main_clk
= "gpt11_fck",
1000 .module_bit
= OMAP24XX_EN_GPT11_SHIFT
,
1001 .module_offs
= CORE_MOD
,
1003 .idlest_idle_bit
= OMAP24XX_ST_GPT11_SHIFT
,
1006 .slaves
= omap2430_timer11_slaves
,
1007 .slaves_cnt
= ARRAY_SIZE(omap2430_timer11_slaves
),
1008 .class = &omap2430_timer_hwmod_class
,
1009 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
1013 static struct omap_hwmod omap2430_timer12_hwmod
;
1014 static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs
[] = {
1018 static struct omap_hwmod_addr_space omap2430_timer12_addrs
[] = {
1020 .pa_start
= 0x4808a000,
1021 .pa_end
= 0x4808a000 + SZ_1K
- 1,
1022 .flags
= ADDR_TYPE_RT
1026 /* l4_core -> timer12 */
1027 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12
= {
1028 .master
= &omap2430_l4_core_hwmod
,
1029 .slave
= &omap2430_timer12_hwmod
,
1031 .addr
= omap2430_timer12_addrs
,
1032 .addr_cnt
= ARRAY_SIZE(omap2430_timer12_addrs
),
1033 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1036 /* timer12 slave port */
1037 static struct omap_hwmod_ocp_if
*omap2430_timer12_slaves
[] = {
1038 &omap2430_l4_core__timer12
,
1042 static struct omap_hwmod omap2430_timer12_hwmod
= {
1044 .mpu_irqs
= omap2430_timer12_mpu_irqs
,
1045 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_timer12_mpu_irqs
),
1046 .main_clk
= "gpt12_fck",
1050 .module_bit
= OMAP24XX_EN_GPT12_SHIFT
,
1051 .module_offs
= CORE_MOD
,
1053 .idlest_idle_bit
= OMAP24XX_ST_GPT12_SHIFT
,
1056 .slaves
= omap2430_timer12_slaves
,
1057 .slaves_cnt
= ARRAY_SIZE(omap2430_timer12_slaves
),
1058 .class = &omap2430_timer_hwmod_class
,
1059 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
1062 /* l4_wkup -> wd_timer2 */
1063 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs
[] = {
1065 .pa_start
= 0x49016000,
1066 .pa_end
= 0x4901607f,
1067 .flags
= ADDR_TYPE_RT
1071 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2
= {
1072 .master
= &omap2430_l4_wkup_hwmod
,
1073 .slave
= &omap2430_wd_timer2_hwmod
,
1074 .clk
= "mpu_wdt_ick",
1075 .addr
= omap2430_wd_timer2_addrs
,
1076 .addr_cnt
= ARRAY_SIZE(omap2430_wd_timer2_addrs
),
1077 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1082 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1083 * overflow condition
1086 static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc
= {
1088 .sysc_offs
= 0x0010,
1089 .syss_offs
= 0x0014,
1090 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SOFTRESET
|
1091 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
1092 .sysc_fields
= &omap_hwmod_sysc_type1
,
1095 static struct omap_hwmod_class omap2430_wd_timer_hwmod_class
= {
1097 .sysc
= &omap2430_wd_timer_sysc
,
1098 .pre_shutdown
= &omap2_wd_timer_disable
1102 static struct omap_hwmod_ocp_if
*omap2430_wd_timer2_slaves
[] = {
1103 &omap2430_l4_wkup__wd_timer2
,
1106 static struct omap_hwmod omap2430_wd_timer2_hwmod
= {
1107 .name
= "wd_timer2",
1108 .class = &omap2430_wd_timer_hwmod_class
,
1109 .main_clk
= "mpu_wdt_fck",
1113 .module_bit
= OMAP24XX_EN_MPU_WDT_SHIFT
,
1114 .module_offs
= WKUP_MOD
,
1116 .idlest_idle_bit
= OMAP24XX_ST_MPU_WDT_SHIFT
,
1119 .slaves
= omap2430_wd_timer2_slaves
,
1120 .slaves_cnt
= ARRAY_SIZE(omap2430_wd_timer2_slaves
),
1121 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1126 static struct omap_hwmod_class_sysconfig uart_sysc
= {
1130 .sysc_flags
= (SYSC_HAS_SIDLEMODE
|
1131 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1132 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
1133 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1134 .sysc_fields
= &omap_hwmod_sysc_type1
,
1137 static struct omap_hwmod_class uart_class
= {
1144 static struct omap_hwmod_irq_info uart1_mpu_irqs
[] = {
1145 { .irq
= INT_24XX_UART1_IRQ
, },
1148 static struct omap_hwmod_dma_info uart1_sdma_reqs
[] = {
1149 { .name
= "rx", .dma_req
= OMAP24XX_DMA_UART1_RX
, },
1150 { .name
= "tx", .dma_req
= OMAP24XX_DMA_UART1_TX
, },
1153 static struct omap_hwmod_ocp_if
*omap2430_uart1_slaves
[] = {
1154 &omap2_l4_core__uart1
,
1157 static struct omap_hwmod omap2430_uart1_hwmod
= {
1159 .mpu_irqs
= uart1_mpu_irqs
,
1160 .mpu_irqs_cnt
= ARRAY_SIZE(uart1_mpu_irqs
),
1161 .sdma_reqs
= uart1_sdma_reqs
,
1162 .sdma_reqs_cnt
= ARRAY_SIZE(uart1_sdma_reqs
),
1163 .main_clk
= "uart1_fck",
1166 .module_offs
= CORE_MOD
,
1168 .module_bit
= OMAP24XX_EN_UART1_SHIFT
,
1170 .idlest_idle_bit
= OMAP24XX_EN_UART1_SHIFT
,
1173 .slaves
= omap2430_uart1_slaves
,
1174 .slaves_cnt
= ARRAY_SIZE(omap2430_uart1_slaves
),
1175 .class = &uart_class
,
1176 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1181 static struct omap_hwmod_irq_info uart2_mpu_irqs
[] = {
1182 { .irq
= INT_24XX_UART2_IRQ
, },
1185 static struct omap_hwmod_dma_info uart2_sdma_reqs
[] = {
1186 { .name
= "rx", .dma_req
= OMAP24XX_DMA_UART2_RX
, },
1187 { .name
= "tx", .dma_req
= OMAP24XX_DMA_UART2_TX
, },
1190 static struct omap_hwmod_ocp_if
*omap2430_uart2_slaves
[] = {
1191 &omap2_l4_core__uart2
,
1194 static struct omap_hwmod omap2430_uart2_hwmod
= {
1196 .mpu_irqs
= uart2_mpu_irqs
,
1197 .mpu_irqs_cnt
= ARRAY_SIZE(uart2_mpu_irqs
),
1198 .sdma_reqs
= uart2_sdma_reqs
,
1199 .sdma_reqs_cnt
= ARRAY_SIZE(uart2_sdma_reqs
),
1200 .main_clk
= "uart2_fck",
1203 .module_offs
= CORE_MOD
,
1205 .module_bit
= OMAP24XX_EN_UART2_SHIFT
,
1207 .idlest_idle_bit
= OMAP24XX_EN_UART2_SHIFT
,
1210 .slaves
= omap2430_uart2_slaves
,
1211 .slaves_cnt
= ARRAY_SIZE(omap2430_uart2_slaves
),
1212 .class = &uart_class
,
1213 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1218 static struct omap_hwmod_irq_info uart3_mpu_irqs
[] = {
1219 { .irq
= INT_24XX_UART3_IRQ
, },
1222 static struct omap_hwmod_dma_info uart3_sdma_reqs
[] = {
1223 { .name
= "rx", .dma_req
= OMAP24XX_DMA_UART3_RX
, },
1224 { .name
= "tx", .dma_req
= OMAP24XX_DMA_UART3_TX
, },
1227 static struct omap_hwmod_ocp_if
*omap2430_uart3_slaves
[] = {
1228 &omap2_l4_core__uart3
,
1231 static struct omap_hwmod omap2430_uart3_hwmod
= {
1233 .mpu_irqs
= uart3_mpu_irqs
,
1234 .mpu_irqs_cnt
= ARRAY_SIZE(uart3_mpu_irqs
),
1235 .sdma_reqs
= uart3_sdma_reqs
,
1236 .sdma_reqs_cnt
= ARRAY_SIZE(uart3_sdma_reqs
),
1237 .main_clk
= "uart3_fck",
1240 .module_offs
= CORE_MOD
,
1242 .module_bit
= OMAP24XX_EN_UART3_SHIFT
,
1244 .idlest_idle_bit
= OMAP24XX_EN_UART3_SHIFT
,
1247 .slaves
= omap2430_uart3_slaves
,
1248 .slaves_cnt
= ARRAY_SIZE(omap2430_uart3_slaves
),
1249 .class = &uart_class
,
1250 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1255 * display sub-system
1258 static struct omap_hwmod_class_sysconfig omap2430_dss_sysc
= {
1260 .sysc_offs
= 0x0010,
1261 .syss_offs
= 0x0014,
1262 .sysc_flags
= (SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1263 .sysc_fields
= &omap_hwmod_sysc_type1
,
1266 static struct omap_hwmod_class omap2430_dss_hwmod_class
= {
1268 .sysc
= &omap2430_dss_sysc
,
1271 static struct omap_hwmod_dma_info omap2430_dss_sdma_chs
[] = {
1272 { .name
= "dispc", .dma_req
= 5 },
1276 /* dss master ports */
1277 static struct omap_hwmod_ocp_if
*omap2430_dss_masters
[] = {
1281 static struct omap_hwmod_addr_space omap2430_dss_addrs
[] = {
1283 .pa_start
= 0x48050000,
1284 .pa_end
= 0x480503FF,
1285 .flags
= ADDR_TYPE_RT
1289 /* l4_core -> dss */
1290 static struct omap_hwmod_ocp_if omap2430_l4_core__dss
= {
1291 .master
= &omap2430_l4_core_hwmod
,
1292 .slave
= &omap2430_dss_core_hwmod
,
1294 .addr
= omap2430_dss_addrs
,
1295 .addr_cnt
= ARRAY_SIZE(omap2430_dss_addrs
),
1296 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1299 /* dss slave ports */
1300 static struct omap_hwmod_ocp_if
*omap2430_dss_slaves
[] = {
1301 &omap2430_l4_core__dss
,
1304 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
1305 { .role
= "tv_clk", .clk
= "dss_54m_fck" },
1306 { .role
= "sys_clk", .clk
= "dss2_fck" },
1309 static struct omap_hwmod omap2430_dss_core_hwmod
= {
1311 .class = &omap2430_dss_hwmod_class
,
1312 .main_clk
= "dss1_fck", /* instead of dss_fck */
1313 .sdma_reqs
= omap2430_dss_sdma_chs
,
1314 .sdma_reqs_cnt
= ARRAY_SIZE(omap2430_dss_sdma_chs
),
1318 .module_bit
= OMAP24XX_EN_DSS1_SHIFT
,
1319 .module_offs
= CORE_MOD
,
1321 .idlest_stdby_bit
= OMAP24XX_ST_DSS_SHIFT
,
1324 .opt_clks
= dss_opt_clks
,
1325 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
1326 .slaves
= omap2430_dss_slaves
,
1327 .slaves_cnt
= ARRAY_SIZE(omap2430_dss_slaves
),
1328 .masters
= omap2430_dss_masters
,
1329 .masters_cnt
= ARRAY_SIZE(omap2430_dss_masters
),
1330 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1331 .flags
= HWMOD_NO_IDLEST
,
1336 * display controller
1339 static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc
= {
1341 .sysc_offs
= 0x0010,
1342 .syss_offs
= 0x0014,
1343 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
1344 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1345 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1346 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1347 .sysc_fields
= &omap_hwmod_sysc_type1
,
1350 static struct omap_hwmod_class omap2430_dispc_hwmod_class
= {
1352 .sysc
= &omap2430_dispc_sysc
,
1355 static struct omap_hwmod_irq_info omap2430_dispc_irqs
[] = {
1359 static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs
[] = {
1361 .pa_start
= 0x48050400,
1362 .pa_end
= 0x480507FF,
1363 .flags
= ADDR_TYPE_RT
1367 /* l4_core -> dss_dispc */
1368 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc
= {
1369 .master
= &omap2430_l4_core_hwmod
,
1370 .slave
= &omap2430_dss_dispc_hwmod
,
1372 .addr
= omap2430_dss_dispc_addrs
,
1373 .addr_cnt
= ARRAY_SIZE(omap2430_dss_dispc_addrs
),
1374 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1377 /* dss_dispc slave ports */
1378 static struct omap_hwmod_ocp_if
*omap2430_dss_dispc_slaves
[] = {
1379 &omap2430_l4_core__dss_dispc
,
1382 static struct omap_hwmod omap2430_dss_dispc_hwmod
= {
1383 .name
= "dss_dispc",
1384 .class = &omap2430_dispc_hwmod_class
,
1385 .mpu_irqs
= omap2430_dispc_irqs
,
1386 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_dispc_irqs
),
1387 .main_clk
= "dss1_fck",
1391 .module_bit
= OMAP24XX_EN_DSS1_SHIFT
,
1392 .module_offs
= CORE_MOD
,
1394 .idlest_stdby_bit
= OMAP24XX_ST_DSS_SHIFT
,
1397 .slaves
= omap2430_dss_dispc_slaves
,
1398 .slaves_cnt
= ARRAY_SIZE(omap2430_dss_dispc_slaves
),
1399 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1400 .flags
= HWMOD_NO_IDLEST
,
1405 * remote frame buffer interface
1408 static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc
= {
1410 .sysc_offs
= 0x0010,
1411 .syss_offs
= 0x0014,
1412 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1414 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1415 .sysc_fields
= &omap_hwmod_sysc_type1
,
1418 static struct omap_hwmod_class omap2430_rfbi_hwmod_class
= {
1420 .sysc
= &omap2430_rfbi_sysc
,
1423 static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs
[] = {
1425 .pa_start
= 0x48050800,
1426 .pa_end
= 0x48050BFF,
1427 .flags
= ADDR_TYPE_RT
1431 /* l4_core -> dss_rfbi */
1432 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi
= {
1433 .master
= &omap2430_l4_core_hwmod
,
1434 .slave
= &omap2430_dss_rfbi_hwmod
,
1436 .addr
= omap2430_dss_rfbi_addrs
,
1437 .addr_cnt
= ARRAY_SIZE(omap2430_dss_rfbi_addrs
),
1438 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1441 /* dss_rfbi slave ports */
1442 static struct omap_hwmod_ocp_if
*omap2430_dss_rfbi_slaves
[] = {
1443 &omap2430_l4_core__dss_rfbi
,
1446 static struct omap_hwmod omap2430_dss_rfbi_hwmod
= {
1448 .class = &omap2430_rfbi_hwmod_class
,
1449 .main_clk
= "dss1_fck",
1453 .module_bit
= OMAP24XX_EN_DSS1_SHIFT
,
1454 .module_offs
= CORE_MOD
,
1457 .slaves
= omap2430_dss_rfbi_slaves
,
1458 .slaves_cnt
= ARRAY_SIZE(omap2430_dss_rfbi_slaves
),
1459 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1460 .flags
= HWMOD_NO_IDLEST
,
1468 static struct omap_hwmod_class omap2430_venc_hwmod_class
= {
1473 static struct omap_hwmod_addr_space omap2430_dss_venc_addrs
[] = {
1475 .pa_start
= 0x48050C00,
1476 .pa_end
= 0x48050FFF,
1477 .flags
= ADDR_TYPE_RT
1481 /* l4_core -> dss_venc */
1482 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc
= {
1483 .master
= &omap2430_l4_core_hwmod
,
1484 .slave
= &omap2430_dss_venc_hwmod
,
1485 .clk
= "dss_54m_fck",
1486 .addr
= omap2430_dss_venc_addrs
,
1487 .addr_cnt
= ARRAY_SIZE(omap2430_dss_venc_addrs
),
1488 .flags
= OCPIF_SWSUP_IDLE
,
1489 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1492 /* dss_venc slave ports */
1493 static struct omap_hwmod_ocp_if
*omap2430_dss_venc_slaves
[] = {
1494 &omap2430_l4_core__dss_venc
,
1497 static struct omap_hwmod omap2430_dss_venc_hwmod
= {
1499 .class = &omap2430_venc_hwmod_class
,
1500 .main_clk
= "dss1_fck",
1504 .module_bit
= OMAP24XX_EN_DSS1_SHIFT
,
1505 .module_offs
= CORE_MOD
,
1508 .slaves
= omap2430_dss_venc_slaves
,
1509 .slaves_cnt
= ARRAY_SIZE(omap2430_dss_venc_slaves
),
1510 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1511 .flags
= HWMOD_NO_IDLEST
,
1515 static struct omap_hwmod_class_sysconfig i2c_sysc
= {
1519 .sysc_flags
= (SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
1520 SYSS_HAS_RESET_STATUS
),
1521 .sysc_fields
= &omap_hwmod_sysc_type1
,
1524 static struct omap_hwmod_class i2c_class
= {
1529 static struct omap_i2c_dev_attr i2c_dev_attr
= {
1530 .fifo_depth
= 8, /* bytes */
1535 static struct omap_hwmod_irq_info i2c1_mpu_irqs
[] = {
1536 { .irq
= INT_24XX_I2C1_IRQ
, },
1539 static struct omap_hwmod_dma_info i2c1_sdma_reqs
[] = {
1540 { .name
= "tx", .dma_req
= OMAP24XX_DMA_I2C1_TX
},
1541 { .name
= "rx", .dma_req
= OMAP24XX_DMA_I2C1_RX
},
1544 static struct omap_hwmod_ocp_if
*omap2430_i2c1_slaves
[] = {
1545 &omap2430_l4_core__i2c1
,
1548 static struct omap_hwmod omap2430_i2c1_hwmod
= {
1550 .mpu_irqs
= i2c1_mpu_irqs
,
1551 .mpu_irqs_cnt
= ARRAY_SIZE(i2c1_mpu_irqs
),
1552 .sdma_reqs
= i2c1_sdma_reqs
,
1553 .sdma_reqs_cnt
= ARRAY_SIZE(i2c1_sdma_reqs
),
1554 .main_clk
= "i2chs1_fck",
1558 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1559 * I2CHS IP's do not follow the usual pattern.
1560 * prcm_reg_id alone cannot be used to program
1561 * the iclk and fclk. Needs to be handled using
1562 * additonal flags when clk handling is moved
1563 * to hwmod framework.
1565 .module_offs
= CORE_MOD
,
1567 .module_bit
= OMAP2430_EN_I2CHS1_SHIFT
,
1569 .idlest_idle_bit
= OMAP2430_ST_I2CHS1_SHIFT
,
1572 .slaves
= omap2430_i2c1_slaves
,
1573 .slaves_cnt
= ARRAY_SIZE(omap2430_i2c1_slaves
),
1574 .class = &i2c_class
,
1575 .dev_attr
= &i2c_dev_attr
,
1576 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1581 static struct omap_hwmod_irq_info i2c2_mpu_irqs
[] = {
1582 { .irq
= INT_24XX_I2C2_IRQ
, },
1585 static struct omap_hwmod_dma_info i2c2_sdma_reqs
[] = {
1586 { .name
= "tx", .dma_req
= OMAP24XX_DMA_I2C2_TX
},
1587 { .name
= "rx", .dma_req
= OMAP24XX_DMA_I2C2_RX
},
1590 static struct omap_hwmod_ocp_if
*omap2430_i2c2_slaves
[] = {
1591 &omap2430_l4_core__i2c2
,
1594 static struct omap_hwmod omap2430_i2c2_hwmod
= {
1596 .mpu_irqs
= i2c2_mpu_irqs
,
1597 .mpu_irqs_cnt
= ARRAY_SIZE(i2c2_mpu_irqs
),
1598 .sdma_reqs
= i2c2_sdma_reqs
,
1599 .sdma_reqs_cnt
= ARRAY_SIZE(i2c2_sdma_reqs
),
1600 .main_clk
= "i2chs2_fck",
1603 .module_offs
= CORE_MOD
,
1605 .module_bit
= OMAP2430_EN_I2CHS2_SHIFT
,
1607 .idlest_idle_bit
= OMAP2430_ST_I2CHS2_SHIFT
,
1610 .slaves
= omap2430_i2c2_slaves
,
1611 .slaves_cnt
= ARRAY_SIZE(omap2430_i2c2_slaves
),
1612 .class = &i2c_class
,
1613 .dev_attr
= &i2c_dev_attr
,
1614 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1617 /* l4_wkup -> gpio1 */
1618 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space
[] = {
1620 .pa_start
= 0x4900C000,
1621 .pa_end
= 0x4900C1ff,
1622 .flags
= ADDR_TYPE_RT
1626 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1
= {
1627 .master
= &omap2430_l4_wkup_hwmod
,
1628 .slave
= &omap2430_gpio1_hwmod
,
1630 .addr
= omap2430_gpio1_addr_space
,
1631 .addr_cnt
= ARRAY_SIZE(omap2430_gpio1_addr_space
),
1632 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1635 /* l4_wkup -> gpio2 */
1636 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space
[] = {
1638 .pa_start
= 0x4900E000,
1639 .pa_end
= 0x4900E1ff,
1640 .flags
= ADDR_TYPE_RT
1644 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2
= {
1645 .master
= &omap2430_l4_wkup_hwmod
,
1646 .slave
= &omap2430_gpio2_hwmod
,
1648 .addr
= omap2430_gpio2_addr_space
,
1649 .addr_cnt
= ARRAY_SIZE(omap2430_gpio2_addr_space
),
1650 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1653 /* l4_wkup -> gpio3 */
1654 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space
[] = {
1656 .pa_start
= 0x49010000,
1657 .pa_end
= 0x490101ff,
1658 .flags
= ADDR_TYPE_RT
1662 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3
= {
1663 .master
= &omap2430_l4_wkup_hwmod
,
1664 .slave
= &omap2430_gpio3_hwmod
,
1666 .addr
= omap2430_gpio3_addr_space
,
1667 .addr_cnt
= ARRAY_SIZE(omap2430_gpio3_addr_space
),
1668 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1671 /* l4_wkup -> gpio4 */
1672 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space
[] = {
1674 .pa_start
= 0x49012000,
1675 .pa_end
= 0x490121ff,
1676 .flags
= ADDR_TYPE_RT
1680 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4
= {
1681 .master
= &omap2430_l4_wkup_hwmod
,
1682 .slave
= &omap2430_gpio4_hwmod
,
1684 .addr
= omap2430_gpio4_addr_space
,
1685 .addr_cnt
= ARRAY_SIZE(omap2430_gpio4_addr_space
),
1686 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1689 /* l4_core -> gpio5 */
1690 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space
[] = {
1692 .pa_start
= 0x480B6000,
1693 .pa_end
= 0x480B61ff,
1694 .flags
= ADDR_TYPE_RT
1698 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5
= {
1699 .master
= &omap2430_l4_core_hwmod
,
1700 .slave
= &omap2430_gpio5_hwmod
,
1702 .addr
= omap2430_gpio5_addr_space
,
1703 .addr_cnt
= ARRAY_SIZE(omap2430_gpio5_addr_space
),
1704 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1708 static struct omap_gpio_dev_attr gpio_dev_attr
= {
1713 static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc
= {
1715 .sysc_offs
= 0x0010,
1716 .syss_offs
= 0x0014,
1717 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1718 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
1719 SYSS_HAS_RESET_STATUS
),
1720 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1721 .sysc_fields
= &omap_hwmod_sysc_type1
,
1726 * general purpose io module
1728 static struct omap_hwmod_class omap243x_gpio_hwmod_class
= {
1730 .sysc
= &omap243x_gpio_sysc
,
1735 static struct omap_hwmod_irq_info omap243x_gpio1_irqs
[] = {
1736 { .irq
= 29 }, /* INT_24XX_GPIO_BANK1 */
1739 static struct omap_hwmod_ocp_if
*omap2430_gpio1_slaves
[] = {
1740 &omap2430_l4_wkup__gpio1
,
1743 static struct omap_hwmod omap2430_gpio1_hwmod
= {
1745 .mpu_irqs
= omap243x_gpio1_irqs
,
1746 .mpu_irqs_cnt
= ARRAY_SIZE(omap243x_gpio1_irqs
),
1747 .main_clk
= "gpios_fck",
1751 .module_bit
= OMAP24XX_EN_GPIOS_SHIFT
,
1752 .module_offs
= WKUP_MOD
,
1754 .idlest_idle_bit
= OMAP24XX_EN_GPIOS_SHIFT
,
1757 .slaves
= omap2430_gpio1_slaves
,
1758 .slaves_cnt
= ARRAY_SIZE(omap2430_gpio1_slaves
),
1759 .class = &omap243x_gpio_hwmod_class
,
1760 .dev_attr
= &gpio_dev_attr
,
1761 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1765 static struct omap_hwmod_irq_info omap243x_gpio2_irqs
[] = {
1766 { .irq
= 30 }, /* INT_24XX_GPIO_BANK2 */
1769 static struct omap_hwmod_ocp_if
*omap2430_gpio2_slaves
[] = {
1770 &omap2430_l4_wkup__gpio2
,
1773 static struct omap_hwmod omap2430_gpio2_hwmod
= {
1775 .mpu_irqs
= omap243x_gpio2_irqs
,
1776 .mpu_irqs_cnt
= ARRAY_SIZE(omap243x_gpio2_irqs
),
1777 .main_clk
= "gpios_fck",
1781 .module_bit
= OMAP24XX_EN_GPIOS_SHIFT
,
1782 .module_offs
= WKUP_MOD
,
1784 .idlest_idle_bit
= OMAP24XX_ST_GPIOS_SHIFT
,
1787 .slaves
= omap2430_gpio2_slaves
,
1788 .slaves_cnt
= ARRAY_SIZE(omap2430_gpio2_slaves
),
1789 .class = &omap243x_gpio_hwmod_class
,
1790 .dev_attr
= &gpio_dev_attr
,
1791 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1795 static struct omap_hwmod_irq_info omap243x_gpio3_irqs
[] = {
1796 { .irq
= 31 }, /* INT_24XX_GPIO_BANK3 */
1799 static struct omap_hwmod_ocp_if
*omap2430_gpio3_slaves
[] = {
1800 &omap2430_l4_wkup__gpio3
,
1803 static struct omap_hwmod omap2430_gpio3_hwmod
= {
1805 .mpu_irqs
= omap243x_gpio3_irqs
,
1806 .mpu_irqs_cnt
= ARRAY_SIZE(omap243x_gpio3_irqs
),
1807 .main_clk
= "gpios_fck",
1811 .module_bit
= OMAP24XX_EN_GPIOS_SHIFT
,
1812 .module_offs
= WKUP_MOD
,
1814 .idlest_idle_bit
= OMAP24XX_ST_GPIOS_SHIFT
,
1817 .slaves
= omap2430_gpio3_slaves
,
1818 .slaves_cnt
= ARRAY_SIZE(omap2430_gpio3_slaves
),
1819 .class = &omap243x_gpio_hwmod_class
,
1820 .dev_attr
= &gpio_dev_attr
,
1821 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1825 static struct omap_hwmod_irq_info omap243x_gpio4_irqs
[] = {
1826 { .irq
= 32 }, /* INT_24XX_GPIO_BANK4 */
1829 static struct omap_hwmod_ocp_if
*omap2430_gpio4_slaves
[] = {
1830 &omap2430_l4_wkup__gpio4
,
1833 static struct omap_hwmod omap2430_gpio4_hwmod
= {
1835 .mpu_irqs
= omap243x_gpio4_irqs
,
1836 .mpu_irqs_cnt
= ARRAY_SIZE(omap243x_gpio4_irqs
),
1837 .main_clk
= "gpios_fck",
1841 .module_bit
= OMAP24XX_EN_GPIOS_SHIFT
,
1842 .module_offs
= WKUP_MOD
,
1844 .idlest_idle_bit
= OMAP24XX_ST_GPIOS_SHIFT
,
1847 .slaves
= omap2430_gpio4_slaves
,
1848 .slaves_cnt
= ARRAY_SIZE(omap2430_gpio4_slaves
),
1849 .class = &omap243x_gpio_hwmod_class
,
1850 .dev_attr
= &gpio_dev_attr
,
1851 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1855 static struct omap_hwmod_irq_info omap243x_gpio5_irqs
[] = {
1856 { .irq
= 33 }, /* INT_24XX_GPIO_BANK5 */
1859 static struct omap_hwmod_ocp_if
*omap2430_gpio5_slaves
[] = {
1860 &omap2430_l4_core__gpio5
,
1863 static struct omap_hwmod omap2430_gpio5_hwmod
= {
1865 .mpu_irqs
= omap243x_gpio5_irqs
,
1866 .mpu_irqs_cnt
= ARRAY_SIZE(omap243x_gpio5_irqs
),
1867 .main_clk
= "gpio5_fck",
1871 .module_bit
= OMAP2430_EN_GPIO5_SHIFT
,
1872 .module_offs
= CORE_MOD
,
1874 .idlest_idle_bit
= OMAP2430_ST_GPIO5_SHIFT
,
1877 .slaves
= omap2430_gpio5_slaves
,
1878 .slaves_cnt
= ARRAY_SIZE(omap2430_gpio5_slaves
),
1879 .class = &omap243x_gpio_hwmod_class
,
1880 .dev_attr
= &gpio_dev_attr
,
1881 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1885 static struct omap_hwmod_class_sysconfig omap2430_dma_sysc
= {
1887 .sysc_offs
= 0x002c,
1888 .syss_offs
= 0x0028,
1889 .sysc_flags
= (SYSC_HAS_SOFTRESET
| SYSC_HAS_MIDLEMODE
|
1890 SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_EMUFREE
|
1891 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
1892 .idlemodes
= (MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1893 .sysc_fields
= &omap_hwmod_sysc_type1
,
1896 static struct omap_hwmod_class omap2430_dma_hwmod_class
= {
1898 .sysc
= &omap2430_dma_sysc
,
1901 /* dma attributes */
1902 static struct omap_dma_dev_attr dma_dev_attr
= {
1903 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
1904 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
1908 static struct omap_hwmod_irq_info omap2430_dma_system_irqs
[] = {
1909 { .name
= "0", .irq
= 12 }, /* INT_24XX_SDMA_IRQ0 */
1910 { .name
= "1", .irq
= 13 }, /* INT_24XX_SDMA_IRQ1 */
1911 { .name
= "2", .irq
= 14 }, /* INT_24XX_SDMA_IRQ2 */
1912 { .name
= "3", .irq
= 15 }, /* INT_24XX_SDMA_IRQ3 */
1915 static struct omap_hwmod_addr_space omap2430_dma_system_addrs
[] = {
1917 .pa_start
= 0x48056000,
1918 .pa_end
= 0x4a0560ff,
1919 .flags
= ADDR_TYPE_RT
1923 /* dma_system -> L3 */
1924 static struct omap_hwmod_ocp_if omap2430_dma_system__l3
= {
1925 .master
= &omap2430_dma_system_hwmod
,
1926 .slave
= &omap2430_l3_main_hwmod
,
1927 .clk
= "core_l3_ck",
1928 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1931 /* dma_system master ports */
1932 static struct omap_hwmod_ocp_if
*omap2430_dma_system_masters
[] = {
1933 &omap2430_dma_system__l3
,
1936 /* l4_core -> dma_system */
1937 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system
= {
1938 .master
= &omap2430_l4_core_hwmod
,
1939 .slave
= &omap2430_dma_system_hwmod
,
1941 .addr
= omap2430_dma_system_addrs
,
1942 .addr_cnt
= ARRAY_SIZE(omap2430_dma_system_addrs
),
1943 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1946 /* dma_system slave ports */
1947 static struct omap_hwmod_ocp_if
*omap2430_dma_system_slaves
[] = {
1948 &omap2430_l4_core__dma_system
,
1951 static struct omap_hwmod omap2430_dma_system_hwmod
= {
1953 .class = &omap2430_dma_hwmod_class
,
1954 .mpu_irqs
= omap2430_dma_system_irqs
,
1955 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_dma_system_irqs
),
1956 .main_clk
= "core_l3_ck",
1957 .slaves
= omap2430_dma_system_slaves
,
1958 .slaves_cnt
= ARRAY_SIZE(omap2430_dma_system_slaves
),
1959 .masters
= omap2430_dma_system_masters
,
1960 .masters_cnt
= ARRAY_SIZE(omap2430_dma_system_masters
),
1961 .dev_attr
= &dma_dev_attr
,
1962 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
1963 .flags
= HWMOD_NO_IDLEST
,
1968 * mailbox module allowing communication between the on-chip processors
1969 * using a queued mailbox-interrupt mechanism.
1972 static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc
= {
1976 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1977 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1978 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1979 .sysc_fields
= &omap_hwmod_sysc_type1
,
1982 static struct omap_hwmod_class omap2430_mailbox_hwmod_class
= {
1984 .sysc
= &omap2430_mailbox_sysc
,
1988 static struct omap_hwmod omap2430_mailbox_hwmod
;
1989 static struct omap_hwmod_irq_info omap2430_mailbox_irqs
[] = {
1993 static struct omap_hwmod_addr_space omap2430_mailbox_addrs
[] = {
1995 .pa_start
= 0x48094000,
1996 .pa_end
= 0x480941ff,
1997 .flags
= ADDR_TYPE_RT
,
2001 /* l4_core -> mailbox */
2002 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox
= {
2003 .master
= &omap2430_l4_core_hwmod
,
2004 .slave
= &omap2430_mailbox_hwmod
,
2005 .addr
= omap2430_mailbox_addrs
,
2006 .addr_cnt
= ARRAY_SIZE(omap2430_mailbox_addrs
),
2007 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2010 /* mailbox slave ports */
2011 static struct omap_hwmod_ocp_if
*omap2430_mailbox_slaves
[] = {
2012 &omap2430_l4_core__mailbox
,
2015 static struct omap_hwmod omap2430_mailbox_hwmod
= {
2017 .class = &omap2430_mailbox_hwmod_class
,
2018 .mpu_irqs
= omap2430_mailbox_irqs
,
2019 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_mailbox_irqs
),
2020 .main_clk
= "mailboxes_ick",
2024 .module_bit
= OMAP24XX_EN_MAILBOXES_SHIFT
,
2025 .module_offs
= CORE_MOD
,
2027 .idlest_idle_bit
= OMAP24XX_ST_MAILBOXES_SHIFT
,
2030 .slaves
= omap2430_mailbox_slaves
,
2031 .slaves_cnt
= ARRAY_SIZE(omap2430_mailbox_slaves
),
2032 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
2037 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2041 static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc
= {
2043 .sysc_offs
= 0x0010,
2044 .syss_offs
= 0x0014,
2045 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
2046 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
2047 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
2048 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2049 .sysc_fields
= &omap_hwmod_sysc_type1
,
2052 static struct omap_hwmod_class omap2430_mcspi_class
= {
2054 .sysc
= &omap2430_mcspi_sysc
,
2055 .rev
= OMAP2_MCSPI_REV
,
2059 static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs
[] = {
2063 static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs
[] = {
2064 { .name
= "tx0", .dma_req
= 35 }, /* DMA_SPI1_TX0 */
2065 { .name
= "rx0", .dma_req
= 36 }, /* DMA_SPI1_RX0 */
2066 { .name
= "tx1", .dma_req
= 37 }, /* DMA_SPI1_TX1 */
2067 { .name
= "rx1", .dma_req
= 38 }, /* DMA_SPI1_RX1 */
2068 { .name
= "tx2", .dma_req
= 39 }, /* DMA_SPI1_TX2 */
2069 { .name
= "rx2", .dma_req
= 40 }, /* DMA_SPI1_RX2 */
2070 { .name
= "tx3", .dma_req
= 41 }, /* DMA_SPI1_TX3 */
2071 { .name
= "rx3", .dma_req
= 42 }, /* DMA_SPI1_RX3 */
2074 static struct omap_hwmod_ocp_if
*omap2430_mcspi1_slaves
[] = {
2075 &omap2430_l4_core__mcspi1
,
2078 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr
= {
2079 .num_chipselect
= 4,
2082 static struct omap_hwmod omap2430_mcspi1_hwmod
= {
2083 .name
= "mcspi1_hwmod",
2084 .mpu_irqs
= omap2430_mcspi1_mpu_irqs
,
2085 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_mcspi1_mpu_irqs
),
2086 .sdma_reqs
= omap2430_mcspi1_sdma_reqs
,
2087 .sdma_reqs_cnt
= ARRAY_SIZE(omap2430_mcspi1_sdma_reqs
),
2088 .main_clk
= "mcspi1_fck",
2091 .module_offs
= CORE_MOD
,
2093 .module_bit
= OMAP24XX_EN_MCSPI1_SHIFT
,
2095 .idlest_idle_bit
= OMAP24XX_ST_MCSPI1_SHIFT
,
2098 .slaves
= omap2430_mcspi1_slaves
,
2099 .slaves_cnt
= ARRAY_SIZE(omap2430_mcspi1_slaves
),
2100 .class = &omap2430_mcspi_class
,
2101 .dev_attr
= &omap_mcspi1_dev_attr
,
2102 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
2106 static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs
[] = {
2110 static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs
[] = {
2111 { .name
= "tx0", .dma_req
= 43 }, /* DMA_SPI2_TX0 */
2112 { .name
= "rx0", .dma_req
= 44 }, /* DMA_SPI2_RX0 */
2113 { .name
= "tx1", .dma_req
= 45 }, /* DMA_SPI2_TX1 */
2114 { .name
= "rx1", .dma_req
= 46 }, /* DMA_SPI2_RX1 */
2117 static struct omap_hwmod_ocp_if
*omap2430_mcspi2_slaves
[] = {
2118 &omap2430_l4_core__mcspi2
,
2121 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr
= {
2122 .num_chipselect
= 2,
2125 static struct omap_hwmod omap2430_mcspi2_hwmod
= {
2126 .name
= "mcspi2_hwmod",
2127 .mpu_irqs
= omap2430_mcspi2_mpu_irqs
,
2128 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_mcspi2_mpu_irqs
),
2129 .sdma_reqs
= omap2430_mcspi2_sdma_reqs
,
2130 .sdma_reqs_cnt
= ARRAY_SIZE(omap2430_mcspi2_sdma_reqs
),
2131 .main_clk
= "mcspi2_fck",
2134 .module_offs
= CORE_MOD
,
2136 .module_bit
= OMAP24XX_EN_MCSPI2_SHIFT
,
2138 .idlest_idle_bit
= OMAP24XX_ST_MCSPI2_SHIFT
,
2141 .slaves
= omap2430_mcspi2_slaves
,
2142 .slaves_cnt
= ARRAY_SIZE(omap2430_mcspi2_slaves
),
2143 .class = &omap2430_mcspi_class
,
2144 .dev_attr
= &omap_mcspi2_dev_attr
,
2145 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
2149 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs
[] = {
2153 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs
[] = {
2154 { .name
= "tx0", .dma_req
= 15 }, /* DMA_SPI3_TX0 */
2155 { .name
= "rx0", .dma_req
= 16 }, /* DMA_SPI3_RX0 */
2156 { .name
= "tx1", .dma_req
= 23 }, /* DMA_SPI3_TX1 */
2157 { .name
= "rx1", .dma_req
= 24 }, /* DMA_SPI3_RX1 */
2160 static struct omap_hwmod_ocp_if
*omap2430_mcspi3_slaves
[] = {
2161 &omap2430_l4_core__mcspi3
,
2164 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr
= {
2165 .num_chipselect
= 2,
2168 static struct omap_hwmod omap2430_mcspi3_hwmod
= {
2169 .name
= "mcspi3_hwmod",
2170 .mpu_irqs
= omap2430_mcspi3_mpu_irqs
,
2171 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_mcspi3_mpu_irqs
),
2172 .sdma_reqs
= omap2430_mcspi3_sdma_reqs
,
2173 .sdma_reqs_cnt
= ARRAY_SIZE(omap2430_mcspi3_sdma_reqs
),
2174 .main_clk
= "mcspi3_fck",
2177 .module_offs
= CORE_MOD
,
2179 .module_bit
= OMAP2430_EN_MCSPI3_SHIFT
,
2181 .idlest_idle_bit
= OMAP2430_ST_MCSPI3_SHIFT
,
2184 .slaves
= omap2430_mcspi3_slaves
,
2185 .slaves_cnt
= ARRAY_SIZE(omap2430_mcspi3_slaves
),
2186 .class = &omap2430_mcspi_class
,
2187 .dev_attr
= &omap_mcspi3_dev_attr
,
2188 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
2194 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc
= {
2196 .sysc_offs
= 0x0404,
2197 .syss_offs
= 0x0408,
2198 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
2199 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
2201 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2202 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
2203 .sysc_fields
= &omap_hwmod_sysc_type1
,
2206 static struct omap_hwmod_class usbotg_class
= {
2208 .sysc
= &omap2430_usbhsotg_sysc
,
2212 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs
[] = {
2214 { .name
= "mc", .irq
= 92 },
2215 { .name
= "dma", .irq
= 93 },
2218 static struct omap_hwmod omap2430_usbhsotg_hwmod
= {
2219 .name
= "usb_otg_hs",
2220 .mpu_irqs
= omap2430_usbhsotg_mpu_irqs
,
2221 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs
),
2222 .main_clk
= "usbhs_ick",
2226 .module_bit
= OMAP2430_EN_USBHS_MASK
,
2227 .module_offs
= CORE_MOD
,
2229 .idlest_idle_bit
= OMAP2430_ST_USBHS_SHIFT
,
2232 .masters
= omap2430_usbhsotg_masters
,
2233 .masters_cnt
= ARRAY_SIZE(omap2430_usbhsotg_masters
),
2234 .slaves
= omap2430_usbhsotg_slaves
,
2235 .slaves_cnt
= ARRAY_SIZE(omap2430_usbhsotg_slaves
),
2236 .class = &usbotg_class
,
2238 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
2239 * broken when autoidle is enabled
2240 * workaround is to disable the autoidle bit at module level.
2242 .flags
= HWMOD_NO_OCP_AUTOIDLE
| HWMOD_SWSUP_SIDLE
2243 | HWMOD_SWSUP_MSTANDBY
,
2244 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
)
2249 * multi channel buffered serial port controller
2252 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc
= {
2254 .sysc_offs
= 0x008C,
2255 .sysc_flags
= (SYSC_HAS_SOFTRESET
),
2256 .sysc_fields
= &omap_hwmod_sysc_type1
,
2259 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class
= {
2261 .sysc
= &omap2430_mcbsp_sysc
,
2262 .rev
= MCBSP_CONFIG_TYPE2
,
2266 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs
[] = {
2267 { .name
= "tx", .irq
= 59 },
2268 { .name
= "rx", .irq
= 60 },
2269 { .name
= "ovr", .irq
= 61 },
2270 { .name
= "common", .irq
= 64 },
2273 static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs
[] = {
2274 { .name
= "rx", .dma_req
= 32 },
2275 { .name
= "tx", .dma_req
= 31 },
2278 static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs
[] = {
2281 .pa_start
= 0x48074000,
2282 .pa_end
= 0x480740ff,
2283 .flags
= ADDR_TYPE_RT
2287 /* l4_core -> mcbsp1 */
2288 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1
= {
2289 .master
= &omap2430_l4_core_hwmod
,
2290 .slave
= &omap2430_mcbsp1_hwmod
,
2291 .clk
= "mcbsp1_ick",
2292 .addr
= omap2430_mcbsp1_addrs
,
2293 .addr_cnt
= ARRAY_SIZE(omap2430_mcbsp1_addrs
),
2294 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2297 /* mcbsp1 slave ports */
2298 static struct omap_hwmod_ocp_if
*omap2430_mcbsp1_slaves
[] = {
2299 &omap2430_l4_core__mcbsp1
,
2302 static struct omap_hwmod omap2430_mcbsp1_hwmod
= {
2304 .class = &omap2430_mcbsp_hwmod_class
,
2305 .mpu_irqs
= omap2430_mcbsp1_irqs
,
2306 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_mcbsp1_irqs
),
2307 .sdma_reqs
= omap2430_mcbsp1_sdma_chs
,
2308 .sdma_reqs_cnt
= ARRAY_SIZE(omap2430_mcbsp1_sdma_chs
),
2309 .main_clk
= "mcbsp1_fck",
2313 .module_bit
= OMAP24XX_EN_MCBSP1_SHIFT
,
2314 .module_offs
= CORE_MOD
,
2316 .idlest_idle_bit
= OMAP24XX_ST_MCBSP1_SHIFT
,
2319 .slaves
= omap2430_mcbsp1_slaves
,
2320 .slaves_cnt
= ARRAY_SIZE(omap2430_mcbsp1_slaves
),
2321 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
2325 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs
[] = {
2326 { .name
= "tx", .irq
= 62 },
2327 { .name
= "rx", .irq
= 63 },
2328 { .name
= "common", .irq
= 16 },
2331 static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs
[] = {
2332 { .name
= "rx", .dma_req
= 34 },
2333 { .name
= "tx", .dma_req
= 33 },
2336 static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs
[] = {
2339 .pa_start
= 0x48076000,
2340 .pa_end
= 0x480760ff,
2341 .flags
= ADDR_TYPE_RT
2345 /* l4_core -> mcbsp2 */
2346 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2
= {
2347 .master
= &omap2430_l4_core_hwmod
,
2348 .slave
= &omap2430_mcbsp2_hwmod
,
2349 .clk
= "mcbsp2_ick",
2350 .addr
= omap2430_mcbsp2_addrs
,
2351 .addr_cnt
= ARRAY_SIZE(omap2430_mcbsp2_addrs
),
2352 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2355 /* mcbsp2 slave ports */
2356 static struct omap_hwmod_ocp_if
*omap2430_mcbsp2_slaves
[] = {
2357 &omap2430_l4_core__mcbsp2
,
2360 static struct omap_hwmod omap2430_mcbsp2_hwmod
= {
2362 .class = &omap2430_mcbsp_hwmod_class
,
2363 .mpu_irqs
= omap2430_mcbsp2_irqs
,
2364 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_mcbsp2_irqs
),
2365 .sdma_reqs
= omap2430_mcbsp2_sdma_chs
,
2366 .sdma_reqs_cnt
= ARRAY_SIZE(omap2430_mcbsp2_sdma_chs
),
2367 .main_clk
= "mcbsp2_fck",
2371 .module_bit
= OMAP24XX_EN_MCBSP2_SHIFT
,
2372 .module_offs
= CORE_MOD
,
2374 .idlest_idle_bit
= OMAP24XX_ST_MCBSP2_SHIFT
,
2377 .slaves
= omap2430_mcbsp2_slaves
,
2378 .slaves_cnt
= ARRAY_SIZE(omap2430_mcbsp2_slaves
),
2379 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
2383 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs
[] = {
2384 { .name
= "tx", .irq
= 89 },
2385 { .name
= "rx", .irq
= 90 },
2386 { .name
= "common", .irq
= 17 },
2389 static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs
[] = {
2390 { .name
= "rx", .dma_req
= 18 },
2391 { .name
= "tx", .dma_req
= 17 },
2394 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs
[] = {
2397 .pa_start
= 0x4808C000,
2398 .pa_end
= 0x4808C0ff,
2399 .flags
= ADDR_TYPE_RT
2403 /* l4_core -> mcbsp3 */
2404 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3
= {
2405 .master
= &omap2430_l4_core_hwmod
,
2406 .slave
= &omap2430_mcbsp3_hwmod
,
2407 .clk
= "mcbsp3_ick",
2408 .addr
= omap2430_mcbsp3_addrs
,
2409 .addr_cnt
= ARRAY_SIZE(omap2430_mcbsp3_addrs
),
2410 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2413 /* mcbsp3 slave ports */
2414 static struct omap_hwmod_ocp_if
*omap2430_mcbsp3_slaves
[] = {
2415 &omap2430_l4_core__mcbsp3
,
2418 static struct omap_hwmod omap2430_mcbsp3_hwmod
= {
2420 .class = &omap2430_mcbsp_hwmod_class
,
2421 .mpu_irqs
= omap2430_mcbsp3_irqs
,
2422 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_mcbsp3_irqs
),
2423 .sdma_reqs
= omap2430_mcbsp3_sdma_chs
,
2424 .sdma_reqs_cnt
= ARRAY_SIZE(omap2430_mcbsp3_sdma_chs
),
2425 .main_clk
= "mcbsp3_fck",
2429 .module_bit
= OMAP2430_EN_MCBSP3_SHIFT
,
2430 .module_offs
= CORE_MOD
,
2432 .idlest_idle_bit
= OMAP2430_ST_MCBSP3_SHIFT
,
2435 .slaves
= omap2430_mcbsp3_slaves
,
2436 .slaves_cnt
= ARRAY_SIZE(omap2430_mcbsp3_slaves
),
2437 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
2441 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs
[] = {
2442 { .name
= "tx", .irq
= 54 },
2443 { .name
= "rx", .irq
= 55 },
2444 { .name
= "common", .irq
= 18 },
2447 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs
[] = {
2448 { .name
= "rx", .dma_req
= 20 },
2449 { .name
= "tx", .dma_req
= 19 },
2452 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs
[] = {
2455 .pa_start
= 0x4808E000,
2456 .pa_end
= 0x4808E0ff,
2457 .flags
= ADDR_TYPE_RT
2461 /* l4_core -> mcbsp4 */
2462 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4
= {
2463 .master
= &omap2430_l4_core_hwmod
,
2464 .slave
= &omap2430_mcbsp4_hwmod
,
2465 .clk
= "mcbsp4_ick",
2466 .addr
= omap2430_mcbsp4_addrs
,
2467 .addr_cnt
= ARRAY_SIZE(omap2430_mcbsp4_addrs
),
2468 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2471 /* mcbsp4 slave ports */
2472 static struct omap_hwmod_ocp_if
*omap2430_mcbsp4_slaves
[] = {
2473 &omap2430_l4_core__mcbsp4
,
2476 static struct omap_hwmod omap2430_mcbsp4_hwmod
= {
2478 .class = &omap2430_mcbsp_hwmod_class
,
2479 .mpu_irqs
= omap2430_mcbsp4_irqs
,
2480 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_mcbsp4_irqs
),
2481 .sdma_reqs
= omap2430_mcbsp4_sdma_chs
,
2482 .sdma_reqs_cnt
= ARRAY_SIZE(omap2430_mcbsp4_sdma_chs
),
2483 .main_clk
= "mcbsp4_fck",
2487 .module_bit
= OMAP2430_EN_MCBSP4_SHIFT
,
2488 .module_offs
= CORE_MOD
,
2490 .idlest_idle_bit
= OMAP2430_ST_MCBSP4_SHIFT
,
2493 .slaves
= omap2430_mcbsp4_slaves
,
2494 .slaves_cnt
= ARRAY_SIZE(omap2430_mcbsp4_slaves
),
2495 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
2499 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs
[] = {
2500 { .name
= "tx", .irq
= 81 },
2501 { .name
= "rx", .irq
= 82 },
2502 { .name
= "common", .irq
= 19 },
2505 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs
[] = {
2506 { .name
= "rx", .dma_req
= 22 },
2507 { .name
= "tx", .dma_req
= 21 },
2510 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs
[] = {
2513 .pa_start
= 0x48096000,
2514 .pa_end
= 0x480960ff,
2515 .flags
= ADDR_TYPE_RT
2519 /* l4_core -> mcbsp5 */
2520 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5
= {
2521 .master
= &omap2430_l4_core_hwmod
,
2522 .slave
= &omap2430_mcbsp5_hwmod
,
2523 .clk
= "mcbsp5_ick",
2524 .addr
= omap2430_mcbsp5_addrs
,
2525 .addr_cnt
= ARRAY_SIZE(omap2430_mcbsp5_addrs
),
2526 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2529 /* mcbsp5 slave ports */
2530 static struct omap_hwmod_ocp_if
*omap2430_mcbsp5_slaves
[] = {
2531 &omap2430_l4_core__mcbsp5
,
2534 static struct omap_hwmod omap2430_mcbsp5_hwmod
= {
2536 .class = &omap2430_mcbsp_hwmod_class
,
2537 .mpu_irqs
= omap2430_mcbsp5_irqs
,
2538 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_mcbsp5_irqs
),
2539 .sdma_reqs
= omap2430_mcbsp5_sdma_chs
,
2540 .sdma_reqs_cnt
= ARRAY_SIZE(omap2430_mcbsp5_sdma_chs
),
2541 .main_clk
= "mcbsp5_fck",
2545 .module_bit
= OMAP2430_EN_MCBSP5_SHIFT
,
2546 .module_offs
= CORE_MOD
,
2548 .idlest_idle_bit
= OMAP2430_ST_MCBSP5_SHIFT
,
2551 .slaves
= omap2430_mcbsp5_slaves
,
2552 .slaves_cnt
= ARRAY_SIZE(omap2430_mcbsp5_slaves
),
2553 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
2556 /* MMC/SD/SDIO common */
2558 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc
= {
2562 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
2563 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
2564 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
2565 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2566 .sysc_fields
= &omap_hwmod_sysc_type1
,
2569 static struct omap_hwmod_class omap2430_mmc_class
= {
2571 .sysc
= &omap2430_mmc_sysc
,
2576 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs
[] = {
2580 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs
[] = {
2581 { .name
= "tx", .dma_req
= 61 }, /* DMA_MMC1_TX */
2582 { .name
= "rx", .dma_req
= 62 }, /* DMA_MMC1_RX */
2585 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks
[] = {
2586 { .role
= "dbck", .clk
= "mmchsdb1_fck" },
2589 static struct omap_hwmod_ocp_if
*omap2430_mmc1_slaves
[] = {
2590 &omap2430_l4_core__mmc1
,
2593 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
2594 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
2597 static struct omap_hwmod omap2430_mmc1_hwmod
= {
2599 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
2600 .mpu_irqs
= omap2430_mmc1_mpu_irqs
,
2601 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_mmc1_mpu_irqs
),
2602 .sdma_reqs
= omap2430_mmc1_sdma_reqs
,
2603 .sdma_reqs_cnt
= ARRAY_SIZE(omap2430_mmc1_sdma_reqs
),
2604 .opt_clks
= omap2430_mmc1_opt_clks
,
2605 .opt_clks_cnt
= ARRAY_SIZE(omap2430_mmc1_opt_clks
),
2606 .main_clk
= "mmchs1_fck",
2609 .module_offs
= CORE_MOD
,
2611 .module_bit
= OMAP2430_EN_MMCHS1_SHIFT
,
2613 .idlest_idle_bit
= OMAP2430_ST_MMCHS1_SHIFT
,
2616 .dev_attr
= &mmc1_dev_attr
,
2617 .slaves
= omap2430_mmc1_slaves
,
2618 .slaves_cnt
= ARRAY_SIZE(omap2430_mmc1_slaves
),
2619 .class = &omap2430_mmc_class
,
2620 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
2625 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs
[] = {
2629 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs
[] = {
2630 { .name
= "tx", .dma_req
= 47 }, /* DMA_MMC2_TX */
2631 { .name
= "rx", .dma_req
= 48 }, /* DMA_MMC2_RX */
2634 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks
[] = {
2635 { .role
= "dbck", .clk
= "mmchsdb2_fck" },
2638 static struct omap_hwmod_ocp_if
*omap2430_mmc2_slaves
[] = {
2639 &omap2430_l4_core__mmc2
,
2642 static struct omap_hwmod omap2430_mmc2_hwmod
= {
2644 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
2645 .mpu_irqs
= omap2430_mmc2_mpu_irqs
,
2646 .mpu_irqs_cnt
= ARRAY_SIZE(omap2430_mmc2_mpu_irqs
),
2647 .sdma_reqs
= omap2430_mmc2_sdma_reqs
,
2648 .sdma_reqs_cnt
= ARRAY_SIZE(omap2430_mmc2_sdma_reqs
),
2649 .opt_clks
= omap2430_mmc2_opt_clks
,
2650 .opt_clks_cnt
= ARRAY_SIZE(omap2430_mmc2_opt_clks
),
2651 .main_clk
= "mmchs2_fck",
2654 .module_offs
= CORE_MOD
,
2656 .module_bit
= OMAP2430_EN_MMCHS2_SHIFT
,
2658 .idlest_idle_bit
= OMAP2430_ST_MMCHS2_SHIFT
,
2661 .slaves
= omap2430_mmc2_slaves
,
2662 .slaves_cnt
= ARRAY_SIZE(omap2430_mmc2_slaves
),
2663 .class = &omap2430_mmc_class
,
2664 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP2430
),
2667 static __initdata
struct omap_hwmod
*omap2430_hwmods
[] = {
2668 &omap2430_l3_main_hwmod
,
2669 &omap2430_l4_core_hwmod
,
2670 &omap2430_l4_wkup_hwmod
,
2671 &omap2430_mpu_hwmod
,
2672 &omap2430_iva_hwmod
,
2674 &omap2430_timer1_hwmod
,
2675 &omap2430_timer2_hwmod
,
2676 &omap2430_timer3_hwmod
,
2677 &omap2430_timer4_hwmod
,
2678 &omap2430_timer5_hwmod
,
2679 &omap2430_timer6_hwmod
,
2680 &omap2430_timer7_hwmod
,
2681 &omap2430_timer8_hwmod
,
2682 &omap2430_timer9_hwmod
,
2683 &omap2430_timer10_hwmod
,
2684 &omap2430_timer11_hwmod
,
2685 &omap2430_timer12_hwmod
,
2687 &omap2430_wd_timer2_hwmod
,
2688 &omap2430_uart1_hwmod
,
2689 &omap2430_uart2_hwmod
,
2690 &omap2430_uart3_hwmod
,
2692 &omap2430_dss_core_hwmod
,
2693 &omap2430_dss_dispc_hwmod
,
2694 &omap2430_dss_rfbi_hwmod
,
2695 &omap2430_dss_venc_hwmod
,
2697 &omap2430_i2c1_hwmod
,
2698 &omap2430_i2c2_hwmod
,
2699 &omap2430_mmc1_hwmod
,
2700 &omap2430_mmc2_hwmod
,
2703 &omap2430_gpio1_hwmod
,
2704 &omap2430_gpio2_hwmod
,
2705 &omap2430_gpio3_hwmod
,
2706 &omap2430_gpio4_hwmod
,
2707 &omap2430_gpio5_hwmod
,
2709 /* dma_system class*/
2710 &omap2430_dma_system_hwmod
,
2713 &omap2430_mcbsp1_hwmod
,
2714 &omap2430_mcbsp2_hwmod
,
2715 &omap2430_mcbsp3_hwmod
,
2716 &omap2430_mcbsp4_hwmod
,
2717 &omap2430_mcbsp5_hwmod
,
2720 &omap2430_mailbox_hwmod
,
2723 &omap2430_mcspi1_hwmod
,
2724 &omap2430_mcspi2_hwmod
,
2725 &omap2430_mcspi3_hwmod
,
2728 &omap2430_usbhsotg_hwmod
,
2733 int __init
omap2430_hwmod_init(void)
2735 return omap_hwmod_register(omap2430_hwmods
);