2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
33 MODULE_AUTHOR("Qumranet");
34 MODULE_LICENSE("GPL");
36 static int bypass_guest_pf
= 1;
37 module_param(bypass_guest_pf
, bool, 0);
39 static int enable_vpid
= 1;
40 module_param(enable_vpid
, bool, 0);
42 static int flexpriority_enabled
= 1;
43 module_param(flexpriority_enabled
, bool, 0);
45 static int enable_ept
;
46 module_param(enable_ept
, bool, 0);
58 u32 idt_vectoring_info
;
59 struct kvm_msr_entry
*guest_msrs
;
60 struct kvm_msr_entry
*host_msrs
;
65 int msr_offset_kernel_gs_base
;
70 u16 fs_sel
, gs_sel
, ldt_sel
;
71 int gs_ldt_reload_needed
;
73 int guest_efer_loaded
;
85 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
87 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
90 static int init_rmode_tss(struct kvm
*kvm
);
92 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
93 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
95 static struct page
*vmx_io_bitmap_a
;
96 static struct page
*vmx_io_bitmap_b
;
97 static struct page
*vmx_msr_bitmap
;
99 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
100 static DEFINE_SPINLOCK(vmx_vpid_lock
);
102 static struct vmcs_config
{
106 u32 pin_based_exec_ctrl
;
107 u32 cpu_based_exec_ctrl
;
108 u32 cpu_based_2nd_exec_ctrl
;
113 struct vmx_capability
{
118 #define VMX_SEGMENT_FIELD(seg) \
119 [VCPU_SREG_##seg] = { \
120 .selector = GUEST_##seg##_SELECTOR, \
121 .base = GUEST_##seg##_BASE, \
122 .limit = GUEST_##seg##_LIMIT, \
123 .ar_bytes = GUEST_##seg##_AR_BYTES, \
126 static struct kvm_vmx_segment_field
{
131 } kvm_vmx_segment_fields
[] = {
132 VMX_SEGMENT_FIELD(CS
),
133 VMX_SEGMENT_FIELD(DS
),
134 VMX_SEGMENT_FIELD(ES
),
135 VMX_SEGMENT_FIELD(FS
),
136 VMX_SEGMENT_FIELD(GS
),
137 VMX_SEGMENT_FIELD(SS
),
138 VMX_SEGMENT_FIELD(TR
),
139 VMX_SEGMENT_FIELD(LDTR
),
143 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
144 * away by decrementing the array size.
146 static const u32 vmx_msr_index
[] = {
148 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
, MSR_KERNEL_GS_BASE
,
150 MSR_EFER
, MSR_K6_STAR
,
152 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
154 static void load_msrs(struct kvm_msr_entry
*e
, int n
)
158 for (i
= 0; i
< n
; ++i
)
159 wrmsrl(e
[i
].index
, e
[i
].data
);
162 static void save_msrs(struct kvm_msr_entry
*e
, int n
)
166 for (i
= 0; i
< n
; ++i
)
167 rdmsrl(e
[i
].index
, e
[i
].data
);
170 static inline int is_page_fault(u32 intr_info
)
172 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
173 INTR_INFO_VALID_MASK
)) ==
174 (INTR_TYPE_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
177 static inline int is_no_device(u32 intr_info
)
179 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
180 INTR_INFO_VALID_MASK
)) ==
181 (INTR_TYPE_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
184 static inline int is_invalid_opcode(u32 intr_info
)
186 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
187 INTR_INFO_VALID_MASK
)) ==
188 (INTR_TYPE_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
191 static inline int is_external_interrupt(u32 intr_info
)
193 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
194 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
197 static inline int cpu_has_vmx_msr_bitmap(void)
199 return (vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
);
202 static inline int cpu_has_vmx_tpr_shadow(void)
204 return (vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
);
207 static inline int vm_need_tpr_shadow(struct kvm
*kvm
)
209 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
)));
212 static inline int cpu_has_secondary_exec_ctrls(void)
214 return (vmcs_config
.cpu_based_exec_ctrl
&
215 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
);
218 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
220 return flexpriority_enabled
221 && (vmcs_config
.cpu_based_2nd_exec_ctrl
&
222 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
225 static inline int cpu_has_vmx_invept_individual_addr(void)
227 return (!!(vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
));
230 static inline int cpu_has_vmx_invept_context(void)
232 return (!!(vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
));
235 static inline int cpu_has_vmx_invept_global(void)
237 return (!!(vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
));
240 static inline int cpu_has_vmx_ept(void)
242 return (vmcs_config
.cpu_based_2nd_exec_ctrl
&
243 SECONDARY_EXEC_ENABLE_EPT
);
246 static inline int vm_need_ept(void)
248 return (cpu_has_vmx_ept() && enable_ept
);
251 static inline int vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
253 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
254 (irqchip_in_kernel(kvm
)));
257 static inline int cpu_has_vmx_vpid(void)
259 return (vmcs_config
.cpu_based_2nd_exec_ctrl
&
260 SECONDARY_EXEC_ENABLE_VPID
);
263 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
267 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
268 if (vmx
->guest_msrs
[i
].index
== msr
)
273 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
279 } operand
= { vpid
, 0, gva
};
281 asm volatile (ASM_VMX_INVVPID
282 /* CF==1 or ZF==1 --> rc = -1 */
284 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
287 static struct kvm_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
291 i
= __find_msr_index(vmx
, msr
);
293 return &vmx
->guest_msrs
[i
];
297 static void vmcs_clear(struct vmcs
*vmcs
)
299 u64 phys_addr
= __pa(vmcs
);
302 asm volatile (ASM_VMX_VMCLEAR_RAX
"; setna %0"
303 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
306 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
310 static void __vcpu_clear(void *arg
)
312 struct vcpu_vmx
*vmx
= arg
;
313 int cpu
= raw_smp_processor_id();
315 if (vmx
->vcpu
.cpu
== cpu
)
316 vmcs_clear(vmx
->vmcs
);
317 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
318 per_cpu(current_vmcs
, cpu
) = NULL
;
319 rdtscll(vmx
->vcpu
.arch
.host_tsc
);
322 static void vcpu_clear(struct vcpu_vmx
*vmx
)
324 if (vmx
->vcpu
.cpu
== -1)
326 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
, vmx
, 0, 1);
330 static inline void vpid_sync_vcpu_all(struct vcpu_vmx
*vmx
)
335 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
338 static unsigned long vmcs_readl(unsigned long field
)
342 asm volatile (ASM_VMX_VMREAD_RDX_RAX
343 : "=a"(value
) : "d"(field
) : "cc");
347 static u16
vmcs_read16(unsigned long field
)
349 return vmcs_readl(field
);
352 static u32
vmcs_read32(unsigned long field
)
354 return vmcs_readl(field
);
357 static u64
vmcs_read64(unsigned long field
)
360 return vmcs_readl(field
);
362 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
366 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
368 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
369 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
373 static void vmcs_writel(unsigned long field
, unsigned long value
)
377 asm volatile (ASM_VMX_VMWRITE_RAX_RDX
"; setna %0"
378 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
380 vmwrite_error(field
, value
);
383 static void vmcs_write16(unsigned long field
, u16 value
)
385 vmcs_writel(field
, value
);
388 static void vmcs_write32(unsigned long field
, u32 value
)
390 vmcs_writel(field
, value
);
393 static void vmcs_write64(unsigned long field
, u64 value
)
396 vmcs_writel(field
, value
);
398 vmcs_writel(field
, value
);
400 vmcs_writel(field
+1, value
>> 32);
404 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
406 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
409 static void vmcs_set_bits(unsigned long field
, u32 mask
)
411 vmcs_writel(field
, vmcs_readl(field
) | mask
);
414 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
418 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
);
419 if (!vcpu
->fpu_active
)
420 eb
|= 1u << NM_VECTOR
;
421 if (vcpu
->guest_debug
.enabled
)
423 if (vcpu
->arch
.rmode
.active
)
425 vmcs_write32(EXCEPTION_BITMAP
, eb
);
428 static void reload_tss(void)
431 * VT restores TR but not its size. Useless.
433 struct descriptor_table gdt
;
434 struct desc_struct
*descs
;
437 descs
= (void *)gdt
.base
;
438 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
442 static void load_transition_efer(struct vcpu_vmx
*vmx
)
444 int efer_offset
= vmx
->msr_offset_efer
;
445 u64 host_efer
= vmx
->host_msrs
[efer_offset
].data
;
446 u64 guest_efer
= vmx
->guest_msrs
[efer_offset
].data
;
452 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
455 ignore_bits
= EFER_NX
| EFER_SCE
;
457 ignore_bits
|= EFER_LMA
| EFER_LME
;
458 /* SCE is meaningful only in long mode on Intel */
459 if (guest_efer
& EFER_LMA
)
460 ignore_bits
&= ~(u64
)EFER_SCE
;
462 if ((guest_efer
& ~ignore_bits
) == (host_efer
& ~ignore_bits
))
465 vmx
->host_state
.guest_efer_loaded
= 1;
466 guest_efer
&= ~ignore_bits
;
467 guest_efer
|= host_efer
& ignore_bits
;
468 wrmsrl(MSR_EFER
, guest_efer
);
469 vmx
->vcpu
.stat
.efer_reload
++;
472 static void reload_host_efer(struct vcpu_vmx
*vmx
)
474 if (vmx
->host_state
.guest_efer_loaded
) {
475 vmx
->host_state
.guest_efer_loaded
= 0;
476 load_msrs(vmx
->host_msrs
+ vmx
->msr_offset_efer
, 1);
480 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
482 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
484 if (vmx
->host_state
.loaded
)
487 vmx
->host_state
.loaded
= 1;
489 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
490 * allow segment selectors with cpl > 0 or ti == 1.
492 vmx
->host_state
.ldt_sel
= read_ldt();
493 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
494 vmx
->host_state
.fs_sel
= read_fs();
495 if (!(vmx
->host_state
.fs_sel
& 7)) {
496 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
497 vmx
->host_state
.fs_reload_needed
= 0;
499 vmcs_write16(HOST_FS_SELECTOR
, 0);
500 vmx
->host_state
.fs_reload_needed
= 1;
502 vmx
->host_state
.gs_sel
= read_gs();
503 if (!(vmx
->host_state
.gs_sel
& 7))
504 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
506 vmcs_write16(HOST_GS_SELECTOR
, 0);
507 vmx
->host_state
.gs_ldt_reload_needed
= 1;
511 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
512 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
514 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
515 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
519 if (is_long_mode(&vmx
->vcpu
))
520 save_msrs(vmx
->host_msrs
+
521 vmx
->msr_offset_kernel_gs_base
, 1);
524 load_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
525 load_transition_efer(vmx
);
528 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
532 if (!vmx
->host_state
.loaded
)
535 ++vmx
->vcpu
.stat
.host_state_reload
;
536 vmx
->host_state
.loaded
= 0;
537 if (vmx
->host_state
.fs_reload_needed
)
538 load_fs(vmx
->host_state
.fs_sel
);
539 if (vmx
->host_state
.gs_ldt_reload_needed
) {
540 load_ldt(vmx
->host_state
.ldt_sel
);
542 * If we have to reload gs, we must take care to
543 * preserve our gs base.
545 local_irq_save(flags
);
546 load_gs(vmx
->host_state
.gs_sel
);
548 wrmsrl(MSR_GS_BASE
, vmcs_readl(HOST_GS_BASE
));
550 local_irq_restore(flags
);
553 save_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
554 load_msrs(vmx
->host_msrs
, vmx
->save_nmsrs
);
555 reload_host_efer(vmx
);
559 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
560 * vcpu mutex is already taken.
562 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
564 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
565 u64 phys_addr
= __pa(vmx
->vmcs
);
566 u64 tsc_this
, delta
, new_offset
;
568 if (vcpu
->cpu
!= cpu
) {
570 kvm_migrate_apic_timer(vcpu
);
571 vpid_sync_vcpu_all(vmx
);
574 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
577 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
578 asm volatile (ASM_VMX_VMPTRLD_RAX
"; setna %0"
579 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
582 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
583 vmx
->vmcs
, phys_addr
);
586 if (vcpu
->cpu
!= cpu
) {
587 struct descriptor_table dt
;
588 unsigned long sysenter_esp
;
592 * Linux uses per-cpu TSS and GDT, so set these when switching
595 vmcs_writel(HOST_TR_BASE
, read_tr_base()); /* 22.2.4 */
597 vmcs_writel(HOST_GDTR_BASE
, dt
.base
); /* 22.2.4 */
599 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
600 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
603 * Make sure the time stamp counter is monotonous.
606 if (tsc_this
< vcpu
->arch
.host_tsc
) {
607 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
608 new_offset
= vmcs_read64(TSC_OFFSET
) + delta
;
609 vmcs_write64(TSC_OFFSET
, new_offset
);
614 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
616 vmx_load_host_state(to_vmx(vcpu
));
619 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
621 if (vcpu
->fpu_active
)
623 vcpu
->fpu_active
= 1;
624 vmcs_clear_bits(GUEST_CR0
, X86_CR0_TS
);
625 if (vcpu
->arch
.cr0
& X86_CR0_TS
)
626 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
627 update_exception_bitmap(vcpu
);
630 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
632 if (!vcpu
->fpu_active
)
634 vcpu
->fpu_active
= 0;
635 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
636 update_exception_bitmap(vcpu
);
639 static void vmx_vcpu_decache(struct kvm_vcpu
*vcpu
)
641 vcpu_clear(to_vmx(vcpu
));
644 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
646 return vmcs_readl(GUEST_RFLAGS
);
649 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
651 if (vcpu
->arch
.rmode
.active
)
652 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
653 vmcs_writel(GUEST_RFLAGS
, rflags
);
656 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
659 u32 interruptibility
;
661 rip
= vmcs_readl(GUEST_RIP
);
662 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
663 vmcs_writel(GUEST_RIP
, rip
);
666 * We emulated an instruction, so temporary interrupt blocking
667 * should be removed, if set.
669 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
670 if (interruptibility
& 3)
671 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
672 interruptibility
& ~3);
673 vcpu
->arch
.interrupt_window_open
= 1;
676 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
677 bool has_error_code
, u32 error_code
)
679 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
680 nr
| INTR_TYPE_EXCEPTION
681 | (has_error_code
? INTR_INFO_DELIVER_CODE_MASK
: 0)
682 | INTR_INFO_VALID_MASK
);
684 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
687 static bool vmx_exception_injected(struct kvm_vcpu
*vcpu
)
689 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
691 return !(vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
695 * Swap MSR entry in host/guest MSR entry array.
698 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
700 struct kvm_msr_entry tmp
;
702 tmp
= vmx
->guest_msrs
[to
];
703 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
704 vmx
->guest_msrs
[from
] = tmp
;
705 tmp
= vmx
->host_msrs
[to
];
706 vmx
->host_msrs
[to
] = vmx
->host_msrs
[from
];
707 vmx
->host_msrs
[from
] = tmp
;
712 * Set up the vmcs to automatically save and restore system
713 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
714 * mode, as fiddling with msrs is very expensive.
716 static void setup_msrs(struct vcpu_vmx
*vmx
)
720 vmx_load_host_state(vmx
);
723 if (is_long_mode(&vmx
->vcpu
)) {
726 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
728 move_msr_up(vmx
, index
, save_nmsrs
++);
729 index
= __find_msr_index(vmx
, MSR_LSTAR
);
731 move_msr_up(vmx
, index
, save_nmsrs
++);
732 index
= __find_msr_index(vmx
, MSR_CSTAR
);
734 move_msr_up(vmx
, index
, save_nmsrs
++);
735 index
= __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
737 move_msr_up(vmx
, index
, save_nmsrs
++);
739 * MSR_K6_STAR is only needed on long mode guests, and only
740 * if efer.sce is enabled.
742 index
= __find_msr_index(vmx
, MSR_K6_STAR
);
743 if ((index
>= 0) && (vmx
->vcpu
.arch
.shadow_efer
& EFER_SCE
))
744 move_msr_up(vmx
, index
, save_nmsrs
++);
747 vmx
->save_nmsrs
= save_nmsrs
;
750 vmx
->msr_offset_kernel_gs_base
=
751 __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
753 vmx
->msr_offset_efer
= __find_msr_index(vmx
, MSR_EFER
);
757 * reads and returns guest's timestamp counter "register"
758 * guest_tsc = host_tsc + tsc_offset -- 21.3
760 static u64
guest_read_tsc(void)
762 u64 host_tsc
, tsc_offset
;
765 tsc_offset
= vmcs_read64(TSC_OFFSET
);
766 return host_tsc
+ tsc_offset
;
770 * writes 'guest_tsc' into guest's timestamp counter "register"
771 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
773 static void guest_write_tsc(u64 guest_tsc
)
778 vmcs_write64(TSC_OFFSET
, guest_tsc
- host_tsc
);
782 * Reads an msr value (of 'msr_index') into 'pdata'.
783 * Returns 0 on success, non-0 otherwise.
784 * Assumes vcpu_load() was already called.
786 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
789 struct kvm_msr_entry
*msr
;
792 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
799 data
= vmcs_readl(GUEST_FS_BASE
);
802 data
= vmcs_readl(GUEST_GS_BASE
);
805 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
807 case MSR_IA32_TIME_STAMP_COUNTER
:
808 data
= guest_read_tsc();
810 case MSR_IA32_SYSENTER_CS
:
811 data
= vmcs_read32(GUEST_SYSENTER_CS
);
813 case MSR_IA32_SYSENTER_EIP
:
814 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
816 case MSR_IA32_SYSENTER_ESP
:
817 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
820 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
825 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
833 * Writes msr value into into the appropriate "register".
834 * Returns 0 on success, non-0 otherwise.
835 * Assumes vcpu_load() was already called.
837 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
839 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
840 struct kvm_msr_entry
*msr
;
846 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
847 if (vmx
->host_state
.loaded
) {
848 reload_host_efer(vmx
);
849 load_transition_efer(vmx
);
853 vmcs_writel(GUEST_FS_BASE
, data
);
856 vmcs_writel(GUEST_GS_BASE
, data
);
859 case MSR_IA32_SYSENTER_CS
:
860 vmcs_write32(GUEST_SYSENTER_CS
, data
);
862 case MSR_IA32_SYSENTER_EIP
:
863 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
865 case MSR_IA32_SYSENTER_ESP
:
866 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
868 case MSR_IA32_TIME_STAMP_COUNTER
:
869 guest_write_tsc(data
);
872 msr
= find_msr_entry(vmx
, msr_index
);
875 if (vmx
->host_state
.loaded
)
876 load_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
879 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
886 * Sync the rsp and rip registers into the vcpu structure. This allows
887 * registers to be accessed by indexing vcpu->arch.regs.
889 static void vcpu_load_rsp_rip(struct kvm_vcpu
*vcpu
)
891 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
892 vcpu
->arch
.rip
= vmcs_readl(GUEST_RIP
);
896 * Syncs rsp and rip back into the vmcs. Should be called after possible
899 static void vcpu_put_rsp_rip(struct kvm_vcpu
*vcpu
)
901 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
902 vmcs_writel(GUEST_RIP
, vcpu
->arch
.rip
);
905 static int set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_debug_guest
*dbg
)
907 unsigned long dr7
= 0x400;
910 old_singlestep
= vcpu
->guest_debug
.singlestep
;
912 vcpu
->guest_debug
.enabled
= dbg
->enabled
;
913 if (vcpu
->guest_debug
.enabled
) {
916 dr7
|= 0x200; /* exact */
917 for (i
= 0; i
< 4; ++i
) {
918 if (!dbg
->breakpoints
[i
].enabled
)
920 vcpu
->guest_debug
.bp
[i
] = dbg
->breakpoints
[i
].address
;
921 dr7
|= 2 << (i
*2); /* global enable */
922 dr7
|= 0 << (i
*4+16); /* execution breakpoint */
925 vcpu
->guest_debug
.singlestep
= dbg
->singlestep
;
927 vcpu
->guest_debug
.singlestep
= 0;
929 if (old_singlestep
&& !vcpu
->guest_debug
.singlestep
) {
932 flags
= vmcs_readl(GUEST_RFLAGS
);
933 flags
&= ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
934 vmcs_writel(GUEST_RFLAGS
, flags
);
937 update_exception_bitmap(vcpu
);
938 vmcs_writel(GUEST_DR7
, dr7
);
943 static int vmx_get_irq(struct kvm_vcpu
*vcpu
)
945 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
948 idtv_info_field
= vmx
->idt_vectoring_info
;
949 if (idtv_info_field
& INTR_INFO_VALID_MASK
) {
950 if (is_external_interrupt(idtv_info_field
))
951 return idtv_info_field
& VECTORING_INFO_VECTOR_MASK
;
953 printk(KERN_DEBUG
"pending exception: not handled yet\n");
958 static __init
int cpu_has_kvm_support(void)
960 unsigned long ecx
= cpuid_ecx(1);
961 return test_bit(5, &ecx
); /* CPUID.1:ECX.VMX[bit 5] -> VT */
964 static __init
int vmx_disabled_by_bios(void)
968 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
969 return (msr
& (MSR_IA32_FEATURE_CONTROL_LOCKED
|
970 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
))
971 == MSR_IA32_FEATURE_CONTROL_LOCKED
;
972 /* locked but not enabled */
975 static void hardware_enable(void *garbage
)
977 int cpu
= raw_smp_processor_id();
978 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
981 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
982 if ((old
& (MSR_IA32_FEATURE_CONTROL_LOCKED
|
983 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
))
984 != (MSR_IA32_FEATURE_CONTROL_LOCKED
|
985 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
))
986 /* enable and lock */
987 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
|
988 MSR_IA32_FEATURE_CONTROL_LOCKED
|
989 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
);
990 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
991 asm volatile (ASM_VMX_VMXON_RAX
: : "a"(&phys_addr
), "m"(phys_addr
)
995 static void hardware_disable(void *garbage
)
997 asm volatile (ASM_VMX_VMXOFF
: : : "cc");
1000 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
1001 u32 msr
, u32
*result
)
1003 u32 vmx_msr_low
, vmx_msr_high
;
1004 u32 ctl
= ctl_min
| ctl_opt
;
1006 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1008 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
1009 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
1011 /* Ensure minimum (required) set of control bits are supported. */
1019 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
1021 u32 vmx_msr_low
, vmx_msr_high
;
1022 u32 min
, opt
, min2
, opt2
;
1023 u32 _pin_based_exec_control
= 0;
1024 u32 _cpu_based_exec_control
= 0;
1025 u32 _cpu_based_2nd_exec_control
= 0;
1026 u32 _vmexit_control
= 0;
1027 u32 _vmentry_control
= 0;
1029 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
1031 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
1032 &_pin_based_exec_control
) < 0)
1035 min
= CPU_BASED_HLT_EXITING
|
1036 #ifdef CONFIG_X86_64
1037 CPU_BASED_CR8_LOAD_EXITING
|
1038 CPU_BASED_CR8_STORE_EXITING
|
1040 CPU_BASED_CR3_LOAD_EXITING
|
1041 CPU_BASED_CR3_STORE_EXITING
|
1042 CPU_BASED_USE_IO_BITMAPS
|
1043 CPU_BASED_MOV_DR_EXITING
|
1044 CPU_BASED_USE_TSC_OFFSETING
;
1045 opt
= CPU_BASED_TPR_SHADOW
|
1046 CPU_BASED_USE_MSR_BITMAPS
|
1047 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1048 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1049 &_cpu_based_exec_control
) < 0)
1051 #ifdef CONFIG_X86_64
1052 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1053 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1054 ~CPU_BASED_CR8_STORE_EXITING
;
1056 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1058 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1059 SECONDARY_EXEC_WBINVD_EXITING
|
1060 SECONDARY_EXEC_ENABLE_VPID
|
1061 SECONDARY_EXEC_ENABLE_EPT
;
1062 if (adjust_vmx_controls(min2
, opt2
,
1063 MSR_IA32_VMX_PROCBASED_CTLS2
,
1064 &_cpu_based_2nd_exec_control
) < 0)
1067 #ifndef CONFIG_X86_64
1068 if (!(_cpu_based_2nd_exec_control
&
1069 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1070 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1072 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
1073 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1074 min
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
1075 CPU_BASED_CR3_STORE_EXITING
);
1076 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1077 &_cpu_based_exec_control
) < 0)
1079 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
1080 vmx_capability
.ept
, vmx_capability
.vpid
);
1084 #ifdef CONFIG_X86_64
1085 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1088 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1089 &_vmexit_control
) < 0)
1093 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1094 &_vmentry_control
) < 0)
1097 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1099 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1100 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1103 #ifdef CONFIG_X86_64
1104 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1105 if (vmx_msr_high
& (1u<<16))
1109 /* Require Write-Back (WB) memory type for VMCS accesses. */
1110 if (((vmx_msr_high
>> 18) & 15) != 6)
1113 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
1114 vmcs_conf
->order
= get_order(vmcs_config
.size
);
1115 vmcs_conf
->revision_id
= vmx_msr_low
;
1117 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
1118 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
1119 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
1120 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
1121 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
1126 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
1128 int node
= cpu_to_node(cpu
);
1132 pages
= alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
1135 vmcs
= page_address(pages
);
1136 memset(vmcs
, 0, vmcs_config
.size
);
1137 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
1141 static struct vmcs
*alloc_vmcs(void)
1143 return alloc_vmcs_cpu(raw_smp_processor_id());
1146 static void free_vmcs(struct vmcs
*vmcs
)
1148 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
1151 static void free_kvm_area(void)
1155 for_each_online_cpu(cpu
)
1156 free_vmcs(per_cpu(vmxarea
, cpu
));
1159 static __init
int alloc_kvm_area(void)
1163 for_each_online_cpu(cpu
) {
1166 vmcs
= alloc_vmcs_cpu(cpu
);
1172 per_cpu(vmxarea
, cpu
) = vmcs
;
1177 static __init
int hardware_setup(void)
1179 if (setup_vmcs_config(&vmcs_config
) < 0)
1182 if (boot_cpu_has(X86_FEATURE_NX
))
1183 kvm_enable_efer_bits(EFER_NX
);
1185 return alloc_kvm_area();
1188 static __exit
void hardware_unsetup(void)
1193 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
1195 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1197 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
1198 vmcs_write16(sf
->selector
, save
->selector
);
1199 vmcs_writel(sf
->base
, save
->base
);
1200 vmcs_write32(sf
->limit
, save
->limit
);
1201 vmcs_write32(sf
->ar_bytes
, save
->ar
);
1203 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
1205 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1209 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1211 unsigned long flags
;
1213 vcpu
->arch
.rmode
.active
= 0;
1215 vmcs_writel(GUEST_TR_BASE
, vcpu
->arch
.rmode
.tr
.base
);
1216 vmcs_write32(GUEST_TR_LIMIT
, vcpu
->arch
.rmode
.tr
.limit
);
1217 vmcs_write32(GUEST_TR_AR_BYTES
, vcpu
->arch
.rmode
.tr
.ar
);
1219 flags
= vmcs_readl(GUEST_RFLAGS
);
1220 flags
&= ~(X86_EFLAGS_IOPL
| X86_EFLAGS_VM
);
1221 flags
|= (vcpu
->arch
.rmode
.save_iopl
<< IOPL_SHIFT
);
1222 vmcs_writel(GUEST_RFLAGS
, flags
);
1224 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1225 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1227 update_exception_bitmap(vcpu
);
1229 fix_pmode_dataseg(VCPU_SREG_ES
, &vcpu
->arch
.rmode
.es
);
1230 fix_pmode_dataseg(VCPU_SREG_DS
, &vcpu
->arch
.rmode
.ds
);
1231 fix_pmode_dataseg(VCPU_SREG_GS
, &vcpu
->arch
.rmode
.gs
);
1232 fix_pmode_dataseg(VCPU_SREG_FS
, &vcpu
->arch
.rmode
.fs
);
1234 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1235 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1237 vmcs_write16(GUEST_CS_SELECTOR
,
1238 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1239 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1242 static gva_t
rmode_tss_base(struct kvm
*kvm
)
1244 if (!kvm
->arch
.tss_addr
) {
1245 gfn_t base_gfn
= kvm
->memslots
[0].base_gfn
+
1246 kvm
->memslots
[0].npages
- 3;
1247 return base_gfn
<< PAGE_SHIFT
;
1249 return kvm
->arch
.tss_addr
;
1252 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1254 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1256 save
->selector
= vmcs_read16(sf
->selector
);
1257 save
->base
= vmcs_readl(sf
->base
);
1258 save
->limit
= vmcs_read32(sf
->limit
);
1259 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1260 vmcs_write16(sf
->selector
, save
->base
>> 4);
1261 vmcs_write32(sf
->base
, save
->base
& 0xfffff);
1262 vmcs_write32(sf
->limit
, 0xffff);
1263 vmcs_write32(sf
->ar_bytes
, 0xf3);
1266 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1268 unsigned long flags
;
1270 vcpu
->arch
.rmode
.active
= 1;
1272 vcpu
->arch
.rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1273 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1275 vcpu
->arch
.rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1276 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1278 vcpu
->arch
.rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1279 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1281 flags
= vmcs_readl(GUEST_RFLAGS
);
1282 vcpu
->arch
.rmode
.save_iopl
1283 = (flags
& X86_EFLAGS_IOPL
) >> IOPL_SHIFT
;
1285 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1287 vmcs_writel(GUEST_RFLAGS
, flags
);
1288 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1289 update_exception_bitmap(vcpu
);
1291 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1292 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1293 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1295 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1296 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1297 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1298 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1299 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1301 fix_rmode_seg(VCPU_SREG_ES
, &vcpu
->arch
.rmode
.es
);
1302 fix_rmode_seg(VCPU_SREG_DS
, &vcpu
->arch
.rmode
.ds
);
1303 fix_rmode_seg(VCPU_SREG_GS
, &vcpu
->arch
.rmode
.gs
);
1304 fix_rmode_seg(VCPU_SREG_FS
, &vcpu
->arch
.rmode
.fs
);
1306 kvm_mmu_reset_context(vcpu
);
1307 init_rmode_tss(vcpu
->kvm
);
1310 #ifdef CONFIG_X86_64
1312 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1316 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1317 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1318 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1320 vmcs_write32(GUEST_TR_AR_BYTES
,
1321 (guest_tr_ar
& ~AR_TYPE_MASK
)
1322 | AR_TYPE_BUSY_64_TSS
);
1325 vcpu
->arch
.shadow_efer
|= EFER_LMA
;
1327 find_msr_entry(to_vmx(vcpu
), MSR_EFER
)->data
|= EFER_LMA
| EFER_LME
;
1328 vmcs_write32(VM_ENTRY_CONTROLS
,
1329 vmcs_read32(VM_ENTRY_CONTROLS
)
1330 | VM_ENTRY_IA32E_MODE
);
1333 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1335 vcpu
->arch
.shadow_efer
&= ~EFER_LMA
;
1337 vmcs_write32(VM_ENTRY_CONTROLS
,
1338 vmcs_read32(VM_ENTRY_CONTROLS
)
1339 & ~VM_ENTRY_IA32E_MODE
);
1344 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
1346 vpid_sync_vcpu_all(to_vmx(vcpu
));
1349 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1351 vcpu
->arch
.cr4
&= KVM_GUEST_CR4_MASK
;
1352 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & ~KVM_GUEST_CR4_MASK
;
1355 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1357 vmx_fpu_deactivate(vcpu
);
1359 if (vcpu
->arch
.rmode
.active
&& (cr0
& X86_CR0_PE
))
1362 if (!vcpu
->arch
.rmode
.active
&& !(cr0
& X86_CR0_PE
))
1365 #ifdef CONFIG_X86_64
1366 if (vcpu
->arch
.shadow_efer
& EFER_LME
) {
1367 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1369 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1374 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1375 vmcs_writel(GUEST_CR0
,
1376 (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
);
1377 vcpu
->arch
.cr0
= cr0
;
1379 if (!(cr0
& X86_CR0_TS
) || !(cr0
& X86_CR0_PE
))
1380 vmx_fpu_activate(vcpu
);
1383 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1385 vmx_flush_tlb(vcpu
);
1386 vmcs_writel(GUEST_CR3
, cr3
);
1387 if (vcpu
->arch
.cr0
& X86_CR0_PE
)
1388 vmx_fpu_deactivate(vcpu
);
1391 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1393 vmcs_writel(CR4_READ_SHADOW
, cr4
);
1394 vmcs_writel(GUEST_CR4
, cr4
| (vcpu
->arch
.rmode
.active
?
1395 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
));
1396 vcpu
->arch
.cr4
= cr4
;
1399 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1401 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1402 struct kvm_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1404 vcpu
->arch
.shadow_efer
= efer
;
1407 if (efer
& EFER_LMA
) {
1408 vmcs_write32(VM_ENTRY_CONTROLS
,
1409 vmcs_read32(VM_ENTRY_CONTROLS
) |
1410 VM_ENTRY_IA32E_MODE
);
1414 vmcs_write32(VM_ENTRY_CONTROLS
,
1415 vmcs_read32(VM_ENTRY_CONTROLS
) &
1416 ~VM_ENTRY_IA32E_MODE
);
1418 msr
->data
= efer
& ~EFER_LME
;
1423 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1425 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1427 return vmcs_readl(sf
->base
);
1430 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
1431 struct kvm_segment
*var
, int seg
)
1433 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1436 var
->base
= vmcs_readl(sf
->base
);
1437 var
->limit
= vmcs_read32(sf
->limit
);
1438 var
->selector
= vmcs_read16(sf
->selector
);
1439 ar
= vmcs_read32(sf
->ar_bytes
);
1440 if (ar
& AR_UNUSABLE_MASK
)
1442 var
->type
= ar
& 15;
1443 var
->s
= (ar
>> 4) & 1;
1444 var
->dpl
= (ar
>> 5) & 3;
1445 var
->present
= (ar
>> 7) & 1;
1446 var
->avl
= (ar
>> 12) & 1;
1447 var
->l
= (ar
>> 13) & 1;
1448 var
->db
= (ar
>> 14) & 1;
1449 var
->g
= (ar
>> 15) & 1;
1450 var
->unusable
= (ar
>> 16) & 1;
1453 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
1455 struct kvm_segment kvm_seg
;
1457 if (!(vcpu
->arch
.cr0
& X86_CR0_PE
)) /* if real mode */
1460 if (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) /* if virtual 8086 */
1463 vmx_get_segment(vcpu
, &kvm_seg
, VCPU_SREG_CS
);
1464 return kvm_seg
.selector
& 3;
1467 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
1474 ar
= var
->type
& 15;
1475 ar
|= (var
->s
& 1) << 4;
1476 ar
|= (var
->dpl
& 3) << 5;
1477 ar
|= (var
->present
& 1) << 7;
1478 ar
|= (var
->avl
& 1) << 12;
1479 ar
|= (var
->l
& 1) << 13;
1480 ar
|= (var
->db
& 1) << 14;
1481 ar
|= (var
->g
& 1) << 15;
1483 if (ar
== 0) /* a 0 value means unusable */
1484 ar
= AR_UNUSABLE_MASK
;
1489 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
1490 struct kvm_segment
*var
, int seg
)
1492 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1495 if (vcpu
->arch
.rmode
.active
&& seg
== VCPU_SREG_TR
) {
1496 vcpu
->arch
.rmode
.tr
.selector
= var
->selector
;
1497 vcpu
->arch
.rmode
.tr
.base
= var
->base
;
1498 vcpu
->arch
.rmode
.tr
.limit
= var
->limit
;
1499 vcpu
->arch
.rmode
.tr
.ar
= vmx_segment_access_rights(var
);
1502 vmcs_writel(sf
->base
, var
->base
);
1503 vmcs_write32(sf
->limit
, var
->limit
);
1504 vmcs_write16(sf
->selector
, var
->selector
);
1505 if (vcpu
->arch
.rmode
.active
&& var
->s
) {
1507 * Hack real-mode segments into vm86 compatibility.
1509 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
1510 vmcs_writel(sf
->base
, 0xf0000);
1513 ar
= vmx_segment_access_rights(var
);
1514 vmcs_write32(sf
->ar_bytes
, ar
);
1517 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
1519 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
1521 *db
= (ar
>> 14) & 1;
1522 *l
= (ar
>> 13) & 1;
1525 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1527 dt
->limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
1528 dt
->base
= vmcs_readl(GUEST_IDTR_BASE
);
1531 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1533 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->limit
);
1534 vmcs_writel(GUEST_IDTR_BASE
, dt
->base
);
1537 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1539 dt
->limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
1540 dt
->base
= vmcs_readl(GUEST_GDTR_BASE
);
1543 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1545 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->limit
);
1546 vmcs_writel(GUEST_GDTR_BASE
, dt
->base
);
1549 static int init_rmode_tss(struct kvm
*kvm
)
1551 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
1556 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
1559 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
1560 r
= kvm_write_guest_page(kvm
, fn
++, &data
, 0x66, sizeof(u16
));
1563 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
1566 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
1570 r
= kvm_write_guest_page(kvm
, fn
, &data
,
1571 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
1581 static void seg_setup(int seg
)
1583 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1585 vmcs_write16(sf
->selector
, 0);
1586 vmcs_writel(sf
->base
, 0);
1587 vmcs_write32(sf
->limit
, 0xffff);
1588 vmcs_write32(sf
->ar_bytes
, 0x93);
1591 static int alloc_apic_access_page(struct kvm
*kvm
)
1593 struct kvm_userspace_memory_region kvm_userspace_mem
;
1596 down_write(&kvm
->slots_lock
);
1597 if (kvm
->arch
.apic_access_page
)
1599 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
1600 kvm_userspace_mem
.flags
= 0;
1601 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
1602 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
1603 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
1607 down_read(¤t
->mm
->mmap_sem
);
1608 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
1609 up_read(¤t
->mm
->mmap_sem
);
1611 up_write(&kvm
->slots_lock
);
1615 static void allocate_vpid(struct vcpu_vmx
*vmx
)
1620 if (!enable_vpid
|| !cpu_has_vmx_vpid())
1622 spin_lock(&vmx_vpid_lock
);
1623 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
1624 if (vpid
< VMX_NR_VPIDS
) {
1626 __set_bit(vpid
, vmx_vpid_bitmap
);
1628 spin_unlock(&vmx_vpid_lock
);
1631 void vmx_disable_intercept_for_msr(struct page
*msr_bitmap
, u32 msr
)
1635 if (!cpu_has_vmx_msr_bitmap())
1639 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1640 * have the write-low and read-high bitmap offsets the wrong way round.
1641 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1643 va
= kmap(msr_bitmap
);
1644 if (msr
<= 0x1fff) {
1645 __clear_bit(msr
, va
+ 0x000); /* read-low */
1646 __clear_bit(msr
, va
+ 0x800); /* write-low */
1647 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
1649 __clear_bit(msr
, va
+ 0x400); /* read-high */
1650 __clear_bit(msr
, va
+ 0xc00); /* write-high */
1656 * Sets up the vmcs for emulated real mode.
1658 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
1660 u32 host_sysenter_cs
;
1663 struct descriptor_table dt
;
1665 unsigned long kvm_vmx_return
;
1669 vmcs_write64(IO_BITMAP_A
, page_to_phys(vmx_io_bitmap_a
));
1670 vmcs_write64(IO_BITMAP_B
, page_to_phys(vmx_io_bitmap_b
));
1672 if (cpu_has_vmx_msr_bitmap())
1673 vmcs_write64(MSR_BITMAP
, page_to_phys(vmx_msr_bitmap
));
1675 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
1678 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
1679 vmcs_config
.pin_based_exec_ctrl
);
1681 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
1682 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
1683 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1684 #ifdef CONFIG_X86_64
1685 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
1686 CPU_BASED_CR8_LOAD_EXITING
;
1690 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
1691 CPU_BASED_CR3_LOAD_EXITING
;
1692 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
1694 if (cpu_has_secondary_exec_ctrls()) {
1695 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
1696 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
1698 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1700 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
1702 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
1703 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
1706 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
1707 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
1708 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
1710 vmcs_writel(HOST_CR0
, read_cr0()); /* 22.2.3 */
1711 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
1712 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1714 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
1715 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
1716 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
1717 vmcs_write16(HOST_FS_SELECTOR
, read_fs()); /* 22.2.4 */
1718 vmcs_write16(HOST_GS_SELECTOR
, read_gs()); /* 22.2.4 */
1719 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
1720 #ifdef CONFIG_X86_64
1721 rdmsrl(MSR_FS_BASE
, a
);
1722 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
1723 rdmsrl(MSR_GS_BASE
, a
);
1724 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
1726 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
1727 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
1730 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
1733 vmcs_writel(HOST_IDTR_BASE
, dt
.base
); /* 22.2.4 */
1735 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
1736 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
1737 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
1738 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
1739 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
1741 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
1742 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
1743 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
1744 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
1745 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
1746 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
1748 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
1749 u32 index
= vmx_msr_index
[i
];
1750 u32 data_low
, data_high
;
1754 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
1756 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
1758 data
= data_low
| ((u64
)data_high
<< 32);
1759 vmx
->host_msrs
[j
].index
= index
;
1760 vmx
->host_msrs
[j
].reserved
= 0;
1761 vmx
->host_msrs
[j
].data
= data
;
1762 vmx
->guest_msrs
[j
] = vmx
->host_msrs
[j
];
1766 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
1768 /* 22.2.1, 20.8.1 */
1769 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
1771 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
1772 vmcs_writel(CR4_GUEST_HOST_MASK
, KVM_GUEST_CR4_MASK
);
1778 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
1780 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1784 down_read(&vcpu
->kvm
->slots_lock
);
1785 if (!init_rmode_tss(vmx
->vcpu
.kvm
)) {
1790 vmx
->vcpu
.arch
.rmode
.active
= 0;
1792 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
1793 kvm_set_cr8(&vmx
->vcpu
, 0);
1794 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
1795 if (vmx
->vcpu
.vcpu_id
== 0)
1796 msr
|= MSR_IA32_APICBASE_BSP
;
1797 kvm_set_apic_base(&vmx
->vcpu
, msr
);
1799 fx_init(&vmx
->vcpu
);
1802 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1803 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1805 if (vmx
->vcpu
.vcpu_id
== 0) {
1806 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
1807 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
1809 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
1810 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
1812 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1813 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1815 seg_setup(VCPU_SREG_DS
);
1816 seg_setup(VCPU_SREG_ES
);
1817 seg_setup(VCPU_SREG_FS
);
1818 seg_setup(VCPU_SREG_GS
);
1819 seg_setup(VCPU_SREG_SS
);
1821 vmcs_write16(GUEST_TR_SELECTOR
, 0);
1822 vmcs_writel(GUEST_TR_BASE
, 0);
1823 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
1824 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1826 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
1827 vmcs_writel(GUEST_LDTR_BASE
, 0);
1828 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
1829 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
1831 vmcs_write32(GUEST_SYSENTER_CS
, 0);
1832 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
1833 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
1835 vmcs_writel(GUEST_RFLAGS
, 0x02);
1836 if (vmx
->vcpu
.vcpu_id
== 0)
1837 vmcs_writel(GUEST_RIP
, 0xfff0);
1839 vmcs_writel(GUEST_RIP
, 0);
1840 vmcs_writel(GUEST_RSP
, 0);
1842 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1843 vmcs_writel(GUEST_DR7
, 0x400);
1845 vmcs_writel(GUEST_GDTR_BASE
, 0);
1846 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
1848 vmcs_writel(GUEST_IDTR_BASE
, 0);
1849 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
1851 vmcs_write32(GUEST_ACTIVITY_STATE
, 0);
1852 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
1853 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
1857 /* Special registers */
1858 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
1862 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
1864 if (cpu_has_vmx_tpr_shadow()) {
1865 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
1866 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
1867 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
1868 page_to_phys(vmx
->vcpu
.arch
.apic
->regs_page
));
1869 vmcs_write32(TPR_THRESHOLD
, 0);
1872 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
1873 vmcs_write64(APIC_ACCESS_ADDR
,
1874 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
1877 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
1879 vmx
->vcpu
.arch
.cr0
= 0x60000010;
1880 vmx_set_cr0(&vmx
->vcpu
, vmx
->vcpu
.arch
.cr0
); /* enter rmode */
1881 vmx_set_cr4(&vmx
->vcpu
, 0);
1882 vmx_set_efer(&vmx
->vcpu
, 0);
1883 vmx_fpu_activate(&vmx
->vcpu
);
1884 update_exception_bitmap(&vmx
->vcpu
);
1886 vpid_sync_vcpu_all(vmx
);
1891 up_read(&vcpu
->kvm
->slots_lock
);
1895 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
, int irq
)
1897 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1899 KVMTRACE_1D(INJ_VIRQ
, vcpu
, (u32
)irq
, handler
);
1901 if (vcpu
->arch
.rmode
.active
) {
1902 vmx
->rmode
.irq
.pending
= true;
1903 vmx
->rmode
.irq
.vector
= irq
;
1904 vmx
->rmode
.irq
.rip
= vmcs_readl(GUEST_RIP
);
1905 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
1906 irq
| INTR_TYPE_SOFT_INTR
| INTR_INFO_VALID_MASK
);
1907 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
1908 vmcs_writel(GUEST_RIP
, vmx
->rmode
.irq
.rip
- 1);
1911 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
1912 irq
| INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1915 static void kvm_do_inject_irq(struct kvm_vcpu
*vcpu
)
1917 int word_index
= __ffs(vcpu
->arch
.irq_summary
);
1918 int bit_index
= __ffs(vcpu
->arch
.irq_pending
[word_index
]);
1919 int irq
= word_index
* BITS_PER_LONG
+ bit_index
;
1921 clear_bit(bit_index
, &vcpu
->arch
.irq_pending
[word_index
]);
1922 if (!vcpu
->arch
.irq_pending
[word_index
])
1923 clear_bit(word_index
, &vcpu
->arch
.irq_summary
);
1924 vmx_inject_irq(vcpu
, irq
);
1928 static void do_interrupt_requests(struct kvm_vcpu
*vcpu
,
1929 struct kvm_run
*kvm_run
)
1931 u32 cpu_based_vm_exec_control
;
1933 vcpu
->arch
.interrupt_window_open
=
1934 ((vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
1935 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & 3) == 0);
1937 if (vcpu
->arch
.interrupt_window_open
&&
1938 vcpu
->arch
.irq_summary
&&
1939 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
) & INTR_INFO_VALID_MASK
))
1941 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1943 kvm_do_inject_irq(vcpu
);
1945 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
1946 if (!vcpu
->arch
.interrupt_window_open
&&
1947 (vcpu
->arch
.irq_summary
|| kvm_run
->request_interrupt_window
))
1949 * Interrupts blocked. Wait for unblock.
1951 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
1953 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
1954 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
1957 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
1960 struct kvm_userspace_memory_region tss_mem
= {
1962 .guest_phys_addr
= addr
,
1963 .memory_size
= PAGE_SIZE
* 3,
1967 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
1970 kvm
->arch
.tss_addr
= addr
;
1974 static void kvm_guest_debug_pre(struct kvm_vcpu
*vcpu
)
1976 struct kvm_guest_debug
*dbg
= &vcpu
->guest_debug
;
1978 set_debugreg(dbg
->bp
[0], 0);
1979 set_debugreg(dbg
->bp
[1], 1);
1980 set_debugreg(dbg
->bp
[2], 2);
1981 set_debugreg(dbg
->bp
[3], 3);
1983 if (dbg
->singlestep
) {
1984 unsigned long flags
;
1986 flags
= vmcs_readl(GUEST_RFLAGS
);
1987 flags
|= X86_EFLAGS_TF
| X86_EFLAGS_RF
;
1988 vmcs_writel(GUEST_RFLAGS
, flags
);
1992 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
1993 int vec
, u32 err_code
)
1995 if (!vcpu
->arch
.rmode
.active
)
1999 * Instruction with address size override prefix opcode 0x67
2000 * Cause the #SS fault with 0 error code in VM86 mode.
2002 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
2003 if (emulate_instruction(vcpu
, NULL
, 0, 0, 0) == EMULATE_DONE
)
2008 static int handle_exception(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2010 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2011 u32 intr_info
, error_code
;
2012 unsigned long cr2
, rip
;
2014 enum emulation_result er
;
2016 vect_info
= vmx
->idt_vectoring_info
;
2017 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
2019 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
2020 !is_page_fault(intr_info
))
2021 printk(KERN_ERR
"%s: unexpected, vectoring info 0x%x "
2022 "intr info 0x%x\n", __func__
, vect_info
, intr_info
);
2024 if (!irqchip_in_kernel(vcpu
->kvm
) && is_external_interrupt(vect_info
)) {
2025 int irq
= vect_info
& VECTORING_INFO_VECTOR_MASK
;
2026 set_bit(irq
, vcpu
->arch
.irq_pending
);
2027 set_bit(irq
/ BITS_PER_LONG
, &vcpu
->arch
.irq_summary
);
2030 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == 0x200) /* nmi */
2031 return 1; /* already handled by vmx_vcpu_run() */
2033 if (is_no_device(intr_info
)) {
2034 vmx_fpu_activate(vcpu
);
2038 if (is_invalid_opcode(intr_info
)) {
2039 er
= emulate_instruction(vcpu
, kvm_run
, 0, 0, EMULTYPE_TRAP_UD
);
2040 if (er
!= EMULATE_DONE
)
2041 kvm_queue_exception(vcpu
, UD_VECTOR
);
2046 rip
= vmcs_readl(GUEST_RIP
);
2047 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
2048 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
2049 if (is_page_fault(intr_info
)) {
2050 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
2051 KVMTRACE_3D(PAGE_FAULT
, vcpu
, error_code
, (u32
)cr2
,
2052 (u32
)((u64
)cr2
>> 32), handler
);
2053 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
);
2056 if (vcpu
->arch
.rmode
.active
&&
2057 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
2059 if (vcpu
->arch
.halt_request
) {
2060 vcpu
->arch
.halt_request
= 0;
2061 return kvm_emulate_halt(vcpu
);
2066 if ((intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
)) ==
2067 (INTR_TYPE_EXCEPTION
| 1)) {
2068 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2071 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
2072 kvm_run
->ex
.exception
= intr_info
& INTR_INFO_VECTOR_MASK
;
2073 kvm_run
->ex
.error_code
= error_code
;
2077 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
,
2078 struct kvm_run
*kvm_run
)
2080 ++vcpu
->stat
.irq_exits
;
2081 KVMTRACE_1D(INTR
, vcpu
, vmcs_read32(VM_EXIT_INTR_INFO
), handler
);
2085 static int handle_triple_fault(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2087 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2091 static int handle_io(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2093 unsigned long exit_qualification
;
2094 int size
, down
, in
, string
, rep
;
2097 ++vcpu
->stat
.io_exits
;
2098 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2099 string
= (exit_qualification
& 16) != 0;
2102 if (emulate_instruction(vcpu
,
2103 kvm_run
, 0, 0, 0) == EMULATE_DO_MMIO
)
2108 size
= (exit_qualification
& 7) + 1;
2109 in
= (exit_qualification
& 8) != 0;
2110 down
= (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_DF
) != 0;
2111 rep
= (exit_qualification
& 32) != 0;
2112 port
= exit_qualification
>> 16;
2114 return kvm_emulate_pio(vcpu
, kvm_run
, in
, size
, port
);
2118 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2121 * Patch in the VMCALL instruction:
2123 hypercall
[0] = 0x0f;
2124 hypercall
[1] = 0x01;
2125 hypercall
[2] = 0xc1;
2128 static int handle_cr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2130 unsigned long exit_qualification
;
2134 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2135 cr
= exit_qualification
& 15;
2136 reg
= (exit_qualification
>> 8) & 15;
2137 switch ((exit_qualification
>> 4) & 3) {
2138 case 0: /* mov to cr */
2139 KVMTRACE_3D(CR_WRITE
, vcpu
, (u32
)cr
, (u32
)vcpu
->arch
.regs
[reg
],
2140 (u32
)((u64
)vcpu
->arch
.regs
[reg
] >> 32), handler
);
2143 vcpu_load_rsp_rip(vcpu
);
2144 kvm_set_cr0(vcpu
, vcpu
->arch
.regs
[reg
]);
2145 skip_emulated_instruction(vcpu
);
2148 vcpu_load_rsp_rip(vcpu
);
2149 kvm_set_cr3(vcpu
, vcpu
->arch
.regs
[reg
]);
2150 skip_emulated_instruction(vcpu
);
2153 vcpu_load_rsp_rip(vcpu
);
2154 kvm_set_cr4(vcpu
, vcpu
->arch
.regs
[reg
]);
2155 skip_emulated_instruction(vcpu
);
2158 vcpu_load_rsp_rip(vcpu
);
2159 kvm_set_cr8(vcpu
, vcpu
->arch
.regs
[reg
]);
2160 skip_emulated_instruction(vcpu
);
2161 if (irqchip_in_kernel(vcpu
->kvm
))
2163 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2168 vcpu_load_rsp_rip(vcpu
);
2169 vmx_fpu_deactivate(vcpu
);
2170 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
2171 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2172 vmx_fpu_activate(vcpu
);
2173 KVMTRACE_0D(CLTS
, vcpu
, handler
);
2174 skip_emulated_instruction(vcpu
);
2176 case 1: /*mov from cr*/
2179 vcpu_load_rsp_rip(vcpu
);
2180 vcpu
->arch
.regs
[reg
] = vcpu
->arch
.cr3
;
2181 vcpu_put_rsp_rip(vcpu
);
2182 KVMTRACE_3D(CR_READ
, vcpu
, (u32
)cr
,
2183 (u32
)vcpu
->arch
.regs
[reg
],
2184 (u32
)((u64
)vcpu
->arch
.regs
[reg
] >> 32),
2186 skip_emulated_instruction(vcpu
);
2189 vcpu_load_rsp_rip(vcpu
);
2190 vcpu
->arch
.regs
[reg
] = kvm_get_cr8(vcpu
);
2191 vcpu_put_rsp_rip(vcpu
);
2192 KVMTRACE_2D(CR_READ
, vcpu
, (u32
)cr
,
2193 (u32
)vcpu
->arch
.regs
[reg
], handler
);
2194 skip_emulated_instruction(vcpu
);
2199 kvm_lmsw(vcpu
, (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f);
2201 skip_emulated_instruction(vcpu
);
2206 kvm_run
->exit_reason
= 0;
2207 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
2208 (int)(exit_qualification
>> 4) & 3, cr
);
2212 static int handle_dr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2214 unsigned long exit_qualification
;
2219 * FIXME: this code assumes the host is debugging the guest.
2220 * need to deal with guest debugging itself too.
2222 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2223 dr
= exit_qualification
& 7;
2224 reg
= (exit_qualification
>> 8) & 15;
2225 vcpu_load_rsp_rip(vcpu
);
2226 if (exit_qualification
& 16) {
2238 vcpu
->arch
.regs
[reg
] = val
;
2239 KVMTRACE_2D(DR_READ
, vcpu
, (u32
)dr
, (u32
)val
, handler
);
2243 vcpu_put_rsp_rip(vcpu
);
2244 skip_emulated_instruction(vcpu
);
2248 static int handle_cpuid(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2250 kvm_emulate_cpuid(vcpu
);
2254 static int handle_rdmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2256 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
2259 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
2260 kvm_inject_gp(vcpu
, 0);
2264 KVMTRACE_3D(MSR_READ
, vcpu
, ecx
, (u32
)data
, (u32
)(data
>> 32),
2267 /* FIXME: handling of bits 32:63 of rax, rdx */
2268 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
2269 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
2270 skip_emulated_instruction(vcpu
);
2274 static int handle_wrmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2276 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
2277 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
2278 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2280 KVMTRACE_3D(MSR_WRITE
, vcpu
, ecx
, (u32
)data
, (u32
)(data
>> 32),
2283 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
2284 kvm_inject_gp(vcpu
, 0);
2288 skip_emulated_instruction(vcpu
);
2292 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
,
2293 struct kvm_run
*kvm_run
)
2298 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
,
2299 struct kvm_run
*kvm_run
)
2301 u32 cpu_based_vm_exec_control
;
2303 /* clear pending irq */
2304 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2305 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
2306 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2308 KVMTRACE_0D(PEND_INTR
, vcpu
, handler
);
2311 * If the user space waits to inject interrupts, exit as soon as
2314 if (kvm_run
->request_interrupt_window
&&
2315 !vcpu
->arch
.irq_summary
) {
2316 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2317 ++vcpu
->stat
.irq_window_exits
;
2323 static int handle_halt(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2325 skip_emulated_instruction(vcpu
);
2326 return kvm_emulate_halt(vcpu
);
2329 static int handle_vmcall(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2331 skip_emulated_instruction(vcpu
);
2332 kvm_emulate_hypercall(vcpu
);
2336 static int handle_wbinvd(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2338 skip_emulated_instruction(vcpu
);
2339 /* TODO: Add support for VT-d/pass-through device */
2343 static int handle_apic_access(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2345 u64 exit_qualification
;
2346 enum emulation_result er
;
2347 unsigned long offset
;
2349 exit_qualification
= vmcs_read64(EXIT_QUALIFICATION
);
2350 offset
= exit_qualification
& 0xffful
;
2352 KVMTRACE_1D(APIC_ACCESS
, vcpu
, (u32
)offset
, handler
);
2354 er
= emulate_instruction(vcpu
, kvm_run
, 0, 0, 0);
2356 if (er
!= EMULATE_DONE
) {
2358 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2365 static int handle_task_switch(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2367 unsigned long exit_qualification
;
2371 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2373 reason
= (u32
)exit_qualification
>> 30;
2374 tss_selector
= exit_qualification
;
2376 return kvm_task_switch(vcpu
, tss_selector
, reason
);
2380 * The exit handlers return 1 if the exit was handled fully and guest execution
2381 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2382 * to be done to userspace and return 0.
2384 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
,
2385 struct kvm_run
*kvm_run
) = {
2386 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
2387 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
2388 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
2389 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
2390 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
2391 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
2392 [EXIT_REASON_CPUID
] = handle_cpuid
,
2393 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
2394 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
2395 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
2396 [EXIT_REASON_HLT
] = handle_halt
,
2397 [EXIT_REASON_VMCALL
] = handle_vmcall
,
2398 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
2399 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
2400 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
2401 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
2404 static const int kvm_vmx_max_exit_handlers
=
2405 ARRAY_SIZE(kvm_vmx_exit_handlers
);
2408 * The guest has exited. See if we can fix it or if we need userspace
2411 static int kvm_handle_exit(struct kvm_run
*kvm_run
, struct kvm_vcpu
*vcpu
)
2413 u32 exit_reason
= vmcs_read32(VM_EXIT_REASON
);
2414 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2415 u32 vectoring_info
= vmx
->idt_vectoring_info
;
2417 KVMTRACE_3D(VMEXIT
, vcpu
, exit_reason
, (u32
)vmcs_readl(GUEST_RIP
),
2418 (u32
)((u64
)vmcs_readl(GUEST_RIP
) >> 32), entryexit
);
2420 if (unlikely(vmx
->fail
)) {
2421 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2422 kvm_run
->fail_entry
.hardware_entry_failure_reason
2423 = vmcs_read32(VM_INSTRUCTION_ERROR
);
2427 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
2428 exit_reason
!= EXIT_REASON_EXCEPTION_NMI
)
2429 printk(KERN_WARNING
"%s: unexpected, valid vectoring info and "
2430 "exit reason is 0x%x\n", __func__
, exit_reason
);
2431 if (exit_reason
< kvm_vmx_max_exit_handlers
2432 && kvm_vmx_exit_handlers
[exit_reason
])
2433 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
, kvm_run
);
2435 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2436 kvm_run
->hw
.hardware_exit_reason
= exit_reason
;
2441 static void update_tpr_threshold(struct kvm_vcpu
*vcpu
)
2445 if (!vm_need_tpr_shadow(vcpu
->kvm
))
2448 if (!kvm_lapic_enabled(vcpu
) ||
2449 ((max_irr
= kvm_lapic_find_highest_irr(vcpu
)) == -1)) {
2450 vmcs_write32(TPR_THRESHOLD
, 0);
2454 tpr
= (kvm_lapic_get_cr8(vcpu
) & 0x0f) << 4;
2455 vmcs_write32(TPR_THRESHOLD
, (max_irr
> tpr
) ? tpr
>> 4 : max_irr
>> 4);
2458 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2460 u32 cpu_based_vm_exec_control
;
2462 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2463 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
2464 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2467 static void vmx_intr_assist(struct kvm_vcpu
*vcpu
)
2469 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2470 u32 idtv_info_field
, intr_info_field
;
2471 int has_ext_irq
, interrupt_window_open
;
2474 update_tpr_threshold(vcpu
);
2476 has_ext_irq
= kvm_cpu_has_interrupt(vcpu
);
2477 intr_info_field
= vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
);
2478 idtv_info_field
= vmx
->idt_vectoring_info
;
2479 if (intr_info_field
& INTR_INFO_VALID_MASK
) {
2480 if (idtv_info_field
& INTR_INFO_VALID_MASK
) {
2481 /* TODO: fault when IDT_Vectoring */
2482 if (printk_ratelimit())
2483 printk(KERN_ERR
"Fault when IDT_Vectoring\n");
2486 enable_irq_window(vcpu
);
2489 if (unlikely(idtv_info_field
& INTR_INFO_VALID_MASK
)) {
2490 if ((idtv_info_field
& VECTORING_INFO_TYPE_MASK
)
2491 == INTR_TYPE_EXT_INTR
2492 && vcpu
->arch
.rmode
.active
) {
2493 u8 vect
= idtv_info_field
& VECTORING_INFO_VECTOR_MASK
;
2495 vmx_inject_irq(vcpu
, vect
);
2496 if (unlikely(has_ext_irq
))
2497 enable_irq_window(vcpu
);
2501 KVMTRACE_1D(REDELIVER_EVT
, vcpu
, idtv_info_field
, handler
);
2503 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, idtv_info_field
);
2504 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2505 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
2507 if (unlikely(idtv_info_field
& INTR_INFO_DELIVER_CODE_MASK
))
2508 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
2509 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
2510 if (unlikely(has_ext_irq
))
2511 enable_irq_window(vcpu
);
2516 interrupt_window_open
=
2517 ((vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
2518 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & 3) == 0);
2519 if (interrupt_window_open
) {
2520 vector
= kvm_cpu_get_interrupt(vcpu
);
2521 vmx_inject_irq(vcpu
, vector
);
2522 kvm_timer_intr_post(vcpu
, vector
);
2524 enable_irq_window(vcpu
);
2528 * Failure to inject an interrupt should give us the information
2529 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2530 * when fetching the interrupt redirection bitmap in the real-mode
2531 * tss, this doesn't happen. So we do it ourselves.
2533 static void fixup_rmode_irq(struct vcpu_vmx
*vmx
)
2535 vmx
->rmode
.irq
.pending
= 0;
2536 if (vmcs_readl(GUEST_RIP
) + 1 != vmx
->rmode
.irq
.rip
)
2538 vmcs_writel(GUEST_RIP
, vmx
->rmode
.irq
.rip
);
2539 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
2540 vmx
->idt_vectoring_info
&= ~VECTORING_INFO_TYPE_MASK
;
2541 vmx
->idt_vectoring_info
|= INTR_TYPE_EXT_INTR
;
2544 vmx
->idt_vectoring_info
=
2545 VECTORING_INFO_VALID_MASK
2546 | INTR_TYPE_EXT_INTR
2547 | vmx
->rmode
.irq
.vector
;
2550 static void vmx_vcpu_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2552 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2556 * Loading guest fpu may have cleared host cr0.ts
2558 vmcs_writel(HOST_CR0
, read_cr0());
2561 /* Store host registers */
2562 #ifdef CONFIG_X86_64
2563 "push %%rdx; push %%rbp;"
2566 "push %%edx; push %%ebp;"
2569 ASM_VMX_VMWRITE_RSP_RDX
"\n\t"
2570 /* Check if vmlaunch of vmresume is needed */
2571 "cmpl $0, %c[launched](%0) \n\t"
2572 /* Load guest registers. Don't clobber flags. */
2573 #ifdef CONFIG_X86_64
2574 "mov %c[cr2](%0), %%rax \n\t"
2575 "mov %%rax, %%cr2 \n\t"
2576 "mov %c[rax](%0), %%rax \n\t"
2577 "mov %c[rbx](%0), %%rbx \n\t"
2578 "mov %c[rdx](%0), %%rdx \n\t"
2579 "mov %c[rsi](%0), %%rsi \n\t"
2580 "mov %c[rdi](%0), %%rdi \n\t"
2581 "mov %c[rbp](%0), %%rbp \n\t"
2582 "mov %c[r8](%0), %%r8 \n\t"
2583 "mov %c[r9](%0), %%r9 \n\t"
2584 "mov %c[r10](%0), %%r10 \n\t"
2585 "mov %c[r11](%0), %%r11 \n\t"
2586 "mov %c[r12](%0), %%r12 \n\t"
2587 "mov %c[r13](%0), %%r13 \n\t"
2588 "mov %c[r14](%0), %%r14 \n\t"
2589 "mov %c[r15](%0), %%r15 \n\t"
2590 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2592 "mov %c[cr2](%0), %%eax \n\t"
2593 "mov %%eax, %%cr2 \n\t"
2594 "mov %c[rax](%0), %%eax \n\t"
2595 "mov %c[rbx](%0), %%ebx \n\t"
2596 "mov %c[rdx](%0), %%edx \n\t"
2597 "mov %c[rsi](%0), %%esi \n\t"
2598 "mov %c[rdi](%0), %%edi \n\t"
2599 "mov %c[rbp](%0), %%ebp \n\t"
2600 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2602 /* Enter guest mode */
2603 "jne .Llaunched \n\t"
2604 ASM_VMX_VMLAUNCH
"\n\t"
2605 "jmp .Lkvm_vmx_return \n\t"
2606 ".Llaunched: " ASM_VMX_VMRESUME
"\n\t"
2607 ".Lkvm_vmx_return: "
2608 /* Save guest registers, load host registers, keep flags */
2609 #ifdef CONFIG_X86_64
2610 "xchg %0, (%%rsp) \n\t"
2611 "mov %%rax, %c[rax](%0) \n\t"
2612 "mov %%rbx, %c[rbx](%0) \n\t"
2613 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2614 "mov %%rdx, %c[rdx](%0) \n\t"
2615 "mov %%rsi, %c[rsi](%0) \n\t"
2616 "mov %%rdi, %c[rdi](%0) \n\t"
2617 "mov %%rbp, %c[rbp](%0) \n\t"
2618 "mov %%r8, %c[r8](%0) \n\t"
2619 "mov %%r9, %c[r9](%0) \n\t"
2620 "mov %%r10, %c[r10](%0) \n\t"
2621 "mov %%r11, %c[r11](%0) \n\t"
2622 "mov %%r12, %c[r12](%0) \n\t"
2623 "mov %%r13, %c[r13](%0) \n\t"
2624 "mov %%r14, %c[r14](%0) \n\t"
2625 "mov %%r15, %c[r15](%0) \n\t"
2626 "mov %%cr2, %%rax \n\t"
2627 "mov %%rax, %c[cr2](%0) \n\t"
2629 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
2631 "xchg %0, (%%esp) \n\t"
2632 "mov %%eax, %c[rax](%0) \n\t"
2633 "mov %%ebx, %c[rbx](%0) \n\t"
2634 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2635 "mov %%edx, %c[rdx](%0) \n\t"
2636 "mov %%esi, %c[rsi](%0) \n\t"
2637 "mov %%edi, %c[rdi](%0) \n\t"
2638 "mov %%ebp, %c[rbp](%0) \n\t"
2639 "mov %%cr2, %%eax \n\t"
2640 "mov %%eax, %c[cr2](%0) \n\t"
2642 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2644 "setbe %c[fail](%0) \n\t"
2645 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
2646 [launched
]"i"(offsetof(struct vcpu_vmx
, launched
)),
2647 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
2648 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
2649 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
2650 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
2651 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
2652 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
2653 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
2654 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
2655 #ifdef CONFIG_X86_64
2656 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
2657 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
2658 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
2659 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
2660 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
2661 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
2662 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
2663 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
2665 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
))
2667 #ifdef CONFIG_X86_64
2668 , "rbx", "rdi", "rsi"
2669 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2671 , "ebx", "edi", "rsi"
2675 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
2676 if (vmx
->rmode
.irq
.pending
)
2677 fixup_rmode_irq(vmx
);
2679 vcpu
->arch
.interrupt_window_open
=
2680 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & 3) == 0;
2682 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
2685 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
2687 /* We need to handle NMIs before interrupts are enabled */
2688 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == 0x200) { /* nmi */
2689 KVMTRACE_0D(NMI
, vcpu
, handler
);
2694 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
2696 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2699 on_each_cpu(__vcpu_clear
, vmx
, 0, 1);
2700 free_vmcs(vmx
->vmcs
);
2705 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
2707 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2709 spin_lock(&vmx_vpid_lock
);
2711 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
2712 spin_unlock(&vmx_vpid_lock
);
2713 vmx_free_vmcs(vcpu
);
2714 kfree(vmx
->host_msrs
);
2715 kfree(vmx
->guest_msrs
);
2716 kvm_vcpu_uninit(vcpu
);
2717 kmem_cache_free(kvm_vcpu_cache
, vmx
);
2720 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
2723 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
2727 return ERR_PTR(-ENOMEM
);
2731 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
2735 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
2736 if (!vmx
->guest_msrs
) {
2741 vmx
->host_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
2742 if (!vmx
->host_msrs
)
2743 goto free_guest_msrs
;
2745 vmx
->vmcs
= alloc_vmcs();
2749 vmcs_clear(vmx
->vmcs
);
2752 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
2753 err
= vmx_vcpu_setup(vmx
);
2754 vmx_vcpu_put(&vmx
->vcpu
);
2758 if (vm_need_virtualize_apic_accesses(kvm
))
2759 if (alloc_apic_access_page(kvm
) != 0)
2765 free_vmcs(vmx
->vmcs
);
2767 kfree(vmx
->host_msrs
);
2769 kfree(vmx
->guest_msrs
);
2771 kvm_vcpu_uninit(&vmx
->vcpu
);
2773 kmem_cache_free(kvm_vcpu_cache
, vmx
);
2774 return ERR_PTR(err
);
2777 static void __init
vmx_check_processor_compat(void *rtn
)
2779 struct vmcs_config vmcs_conf
;
2782 if (setup_vmcs_config(&vmcs_conf
) < 0)
2784 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
2785 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
2786 smp_processor_id());
2791 static struct kvm_x86_ops vmx_x86_ops
= {
2792 .cpu_has_kvm_support
= cpu_has_kvm_support
,
2793 .disabled_by_bios
= vmx_disabled_by_bios
,
2794 .hardware_setup
= hardware_setup
,
2795 .hardware_unsetup
= hardware_unsetup
,
2796 .check_processor_compatibility
= vmx_check_processor_compat
,
2797 .hardware_enable
= hardware_enable
,
2798 .hardware_disable
= hardware_disable
,
2799 .cpu_has_accelerated_tpr
= cpu_has_vmx_virtualize_apic_accesses
,
2801 .vcpu_create
= vmx_create_vcpu
,
2802 .vcpu_free
= vmx_free_vcpu
,
2803 .vcpu_reset
= vmx_vcpu_reset
,
2805 .prepare_guest_switch
= vmx_save_host_state
,
2806 .vcpu_load
= vmx_vcpu_load
,
2807 .vcpu_put
= vmx_vcpu_put
,
2808 .vcpu_decache
= vmx_vcpu_decache
,
2810 .set_guest_debug
= set_guest_debug
,
2811 .guest_debug_pre
= kvm_guest_debug_pre
,
2812 .get_msr
= vmx_get_msr
,
2813 .set_msr
= vmx_set_msr
,
2814 .get_segment_base
= vmx_get_segment_base
,
2815 .get_segment
= vmx_get_segment
,
2816 .set_segment
= vmx_set_segment
,
2817 .get_cpl
= vmx_get_cpl
,
2818 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
2819 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
2820 .set_cr0
= vmx_set_cr0
,
2821 .set_cr3
= vmx_set_cr3
,
2822 .set_cr4
= vmx_set_cr4
,
2823 .set_efer
= vmx_set_efer
,
2824 .get_idt
= vmx_get_idt
,
2825 .set_idt
= vmx_set_idt
,
2826 .get_gdt
= vmx_get_gdt
,
2827 .set_gdt
= vmx_set_gdt
,
2828 .cache_regs
= vcpu_load_rsp_rip
,
2829 .decache_regs
= vcpu_put_rsp_rip
,
2830 .get_rflags
= vmx_get_rflags
,
2831 .set_rflags
= vmx_set_rflags
,
2833 .tlb_flush
= vmx_flush_tlb
,
2835 .run
= vmx_vcpu_run
,
2836 .handle_exit
= kvm_handle_exit
,
2837 .skip_emulated_instruction
= skip_emulated_instruction
,
2838 .patch_hypercall
= vmx_patch_hypercall
,
2839 .get_irq
= vmx_get_irq
,
2840 .set_irq
= vmx_inject_irq
,
2841 .queue_exception
= vmx_queue_exception
,
2842 .exception_injected
= vmx_exception_injected
,
2843 .inject_pending_irq
= vmx_intr_assist
,
2844 .inject_pending_vectors
= do_interrupt_requests
,
2846 .set_tss_addr
= vmx_set_tss_addr
,
2849 static int __init
vmx_init(void)
2854 vmx_io_bitmap_a
= alloc_page(GFP_KERNEL
| __GFP_HIGHMEM
);
2855 if (!vmx_io_bitmap_a
)
2858 vmx_io_bitmap_b
= alloc_page(GFP_KERNEL
| __GFP_HIGHMEM
);
2859 if (!vmx_io_bitmap_b
) {
2864 vmx_msr_bitmap
= alloc_page(GFP_KERNEL
| __GFP_HIGHMEM
);
2865 if (!vmx_msr_bitmap
) {
2871 * Allow direct access to the PC debug port (it is often used for I/O
2872 * delays, but the vmexits simply slow things down).
2874 va
= kmap(vmx_io_bitmap_a
);
2875 memset(va
, 0xff, PAGE_SIZE
);
2876 clear_bit(0x80, va
);
2877 kunmap(vmx_io_bitmap_a
);
2879 va
= kmap(vmx_io_bitmap_b
);
2880 memset(va
, 0xff, PAGE_SIZE
);
2881 kunmap(vmx_io_bitmap_b
);
2883 va
= kmap(vmx_msr_bitmap
);
2884 memset(va
, 0xff, PAGE_SIZE
);
2885 kunmap(vmx_msr_bitmap
);
2887 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
2889 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
), THIS_MODULE
);
2893 vmx_disable_intercept_for_msr(vmx_msr_bitmap
, MSR_FS_BASE
);
2894 vmx_disable_intercept_for_msr(vmx_msr_bitmap
, MSR_GS_BASE
);
2895 vmx_disable_intercept_for_msr(vmx_msr_bitmap
, MSR_IA32_SYSENTER_CS
);
2896 vmx_disable_intercept_for_msr(vmx_msr_bitmap
, MSR_IA32_SYSENTER_ESP
);
2897 vmx_disable_intercept_for_msr(vmx_msr_bitmap
, MSR_IA32_SYSENTER_EIP
);
2899 if (bypass_guest_pf
)
2900 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
2905 __free_page(vmx_msr_bitmap
);
2907 __free_page(vmx_io_bitmap_b
);
2909 __free_page(vmx_io_bitmap_a
);
2913 static void __exit
vmx_exit(void)
2915 __free_page(vmx_msr_bitmap
);
2916 __free_page(vmx_io_bitmap_b
);
2917 __free_page(vmx_io_bitmap_a
);
2922 module_init(vmx_init
)
2923 module_exit(vmx_exit
)