arch/arm/mach-ux500/cpu.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8 #include <linux/platform_device.h>
   9 #include <linux/amba/bus.h>
  10 #include <linux/io.h>
  11 #include <linux/clk.h>
  12
  13 #include <asm/hardware/cache-l2x0.h>
  14 #include <asm/hardware/gic.h>
  15 #include <asm/mach/map.h>
  16 #include <asm/localtimer.h>
  17
  18 #include <plat/mtu.h>
  19 #include <mach/hardware.h>
  20 #include <mach/setup.h>
  21 #include <mach/devices.h>
  22
  23 #include "clock.h"
  24
  25 static struct map_desc ux500_io_desc[] __initdata = {
  26         __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K),
  27         __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K),
  28
  29         __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K),
  30         __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K),
  31         __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K),
  32         __IO_DEV_DESC(UX500_TWD_BASE, SZ_4K),
  33         __IO_DEV_DESC(UX500_SCU_BASE, SZ_4K),
  34
  35         __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K),
  36         __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K),
  37         __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K),
  38         __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K),
  39         __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K),
  40
  41         __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K),
  42         __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K),
  43
  44         __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K),
  45 };
  46
  47 static struct amba_device *ux500_amba_devs[] __initdata = {
  48         &ux500_pl031_device,
  49 };
  50
  51 void __init ux500_map_io(void)
  52 {
  53         iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc));
  54 }
  55
  56 void __init ux500_init_devices(void)
  57 {
  58         amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs));
  59 }
  60
  61 void __init ux500_init_irq(void)
  62 {
  63         gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29);
  64         gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
  65
  66         /*
  67          * Init clocks here so that they are available for system timer
  68          * initialization.
  69          */
  70         clk_init();
  71 }
  72
  73 #ifdef CONFIG_CACHE_L2X0
  74 static int ux500_l2x0_init(void)
  75 {
  76         void __iomem *l2x0_base;
  77
  78         l2x0_base = __io_address(UX500_L2CC_BASE);
  79
  80         /* 64KB way size, 8 way associativity, force WA */
  81         l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
  82
  83         return 0;
  84 }
  85 early_initcall(ux500_l2x0_init);
  86 #endif
  87
  88 static void __init ux500_timer_init(void)
  89 {
  90 #ifdef CONFIG_LOCAL_TIMERS
  91         /* Setup the local timer base */
  92         twd_base = __io_address(UX500_TWD_BASE);
  93 #endif
  94         /* Setup the MTU base */
  95         if (cpu_is_u8500ed())
  96                 mtu_base = __io_address(U8500_MTU0_BASE_ED);
  97         else
  98                 mtu_base = __io_address(UX500_MTU0_BASE);
  99
 100         nmdk_timer_init();
 101 }
 102
 103 struct sys_timer ux500_timer = {
 104         .init   = ux500_timer_init,
 105 };