drivers/media/video/saa7191.h

   1 /*
   2  *  saa7191.h - Philips SAA7191 video decoder driver
   3  *
   4  *  Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
   5  *  Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 as
   9  *  published by the Free Software Foundation.
  10  */
  11
  12 #ifndef _SAA7191_H_
  13 #define _SAA7191_H_
  14
  15 /* Philips SAA7191 DMSD I2C bus address */
  16 #define SAA7191_ADDR            0x8a
  17
  18 /* Register subaddresses. */
  19 #define SAA7191_REG_IDEL        0x00
  20 #define SAA7191_REG_HSYB        0x01
  21 #define SAA7191_REG_HSYS        0x02
  22 #define SAA7191_REG_HCLB        0x03
  23 #define SAA7191_REG_HCLS        0x04
  24 #define SAA7191_REG_HPHI        0x05
  25 #define SAA7191_REG_LUMA        0x06
  26 #define SAA7191_REG_HUEC        0x07
  27 #define SAA7191_REG_CKTQ        0x08
  28 #define SAA7191_REG_CKTS        0x09
  29 #define SAA7191_REG_PLSE        0x0a
  30 #define SAA7191_REG_SESE        0x0b
  31 #define SAA7191_REG_GAIN        0x0c
  32 #define SAA7191_REG_STDC        0x0d
  33 #define SAA7191_REG_IOCK        0x0e
  34 #define SAA7191_REG_CTL3        0x0f
  35 #define SAA7191_REG_CTL4        0x10
  36 #define SAA7191_REG_CHCV        0x11
  37 #define SAA7191_REG_HS6B        0x14
  38 #define SAA7191_REG_HS6S        0x15
  39 #define SAA7191_REG_HC6B        0x16
  40 #define SAA7191_REG_HC6S        0x17
  41 #define SAA7191_REG_HP6I        0x18
  42 #define SAA7191_REG_STATUS      0xff    /* not really a subaddress */
  43
  44 /* Status Register definitions */
  45 #define SAA7191_STATUS_CODE     0x01    /* color detected flag */
  46 #define SAA7191_STATUS_FIDT     0x20    /* format type NTSC/PAL */
  47 #define SAA7191_STATUS_HLCK     0x40    /* PLL unlocked/locked */
  48 #define SAA7191_STATUS_STTC     0x80    /* tv/vtr time constant */
  49
  50 /* Luminance Control Register definitions */
  51 #define SAA7191_LUMA_BYPS       0x80
  52
  53 /* Chroma Gain Control Settings Register definitions */
  54 /* 0=automatic colour-killer enabled, 1=forced colour on */
  55 #define SAA7191_GAIN_COLO       0x80
  56
  57 /* Standard/Mode Control Register definitions */
  58 /* tv/vtr mode bit: 0=TV mode (slow time constant),
  59  * 1=VTR mode (fast time constant) */
  60 #define SAA7191_STDC_VTRC       0x80
  61 /* SECAM mode bit: 0=other standards, 1=SECAM */
  62 #define SAA7191_STDC_SECS       0x01
  63 /* the bit fields above must be or'd with this value */
  64 #define SAA7191_STDC_VALUE      0x0c
  65
  66 /* I/O and Clock Control Register definitions */
  67 /* horizontal clock PLL: 0=PLL closed,
  68  * 1=PLL circuit open and horizontal freq fixed */
  69 #define SAA7191_IOCK_HPLL       0x80
  70 /* S-VHS bit (chrominance from CVBS or from chrominance input):
  71  * 0=controlled by BYPS-bit, 1=from chrominance input */
  72 #define SAA7191_IOCK_CHRS       0x04
  73 /* general purpose switch 2
  74  * VINO-specific: 0=used with CVBS, 1=used with S-Video */
  75 #define SAA7191_IOCK_GPSW2      0x02
  76 /* general purpose switch 1 */
  77 /* VINO-specific: 0=always, 1=not used!*/
  78 #define SAA7191_IOCK_GPSW1      0x01
  79
  80 /* Miscellaneous Control #1 Register definitions */
  81 /* automatic field detection (50/60Hz standard) */
  82 #define SAA7191_CTL3_AUFD       0x80
  83 /* field select: (if AUFD=0)
  84  * 0=50Hz (625 lines), 1=60Hz (525 lines) */
  85 #define SAA7191_CTL3_FSEL       0x40
  86 /* the bit fields above must be or'd with this value */
  87 #define SAA7191_CTL3_VALUE      0x19
  88
  89 /* Chrominance Gain Control Register definitions
  90  * (nominal value for UV CCIR level) */
  91 #define SAA7191_CHCV_NTSC       0x2c
  92 #define SAA7191_CHCV_PAL        0x59
  93
  94 /* Driver interface definitions */
  95 #define SAA7191_INPUT_COMPOSITE 0
  96 #define SAA7191_INPUT_SVIDEO    1
  97
  98 #define SAA7191_NORM_AUTO       0
  99 #define SAA7191_NORM_PAL        1
 100 #define SAA7191_NORM_NTSC       2
 101 #define SAA7191_NORM_SECAM      3
 102
 103 #define SAA7191_VALUE_ENABLED           1
 104 #define SAA7191_VALUE_DISABLED          0
 105 #define SAA7191_VALUE_UNCHANGED         -1
 106
 107 struct saa7191_status {
 108         /* 0=no signal, 1=signal active*/
 109         int signal;
 110         /* 0=50hz (pal) signal, 1=60hz (ntsc) signal */
 111         int ntsc;
 112         /* 0=no color detected, 1=color detected */
 113         int color;
 114
 115         /* current SAA7191_INPUT_ */
 116         int input;
 117         /* current SAA7191_NORM_ */
 118         int norm;
 119 };
 120
 121 #define SAA7191_HUE_MIN         0x00
 122 #define SAA7191_HUE_MAX         0xff
 123 #define SAA7191_HUE_DEFAULT     0x80
 124
 125 #define SAA7191_VTRC_MIN        0x00
 126 #define SAA7191_VTRC_MAX        0x01
 127 #define SAA7191_VTRC_DEFAULT    0x00
 128
 129 struct saa7191_control {
 130         int hue;
 131         int vtrc;
 132 };
 133
 134 #define DECODER_SAA7191_GET_STATUS      _IOR('d', 195, struct saa7191_status)
 135 #define DECODER_SAA7191_SET_NORM        _IOW('d', 196, int)
 136 #define DECODER_SAA7191_GET_CONTROLS    _IOR('d', 197, struct saa7191_control)
 137 #define DECODER_SAA7191_SET_CONTROLS    _IOW('d', 198, struct saa7191_control)
 138
 139 #endif