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bnx2x: White spaces
[linux-2.6/kvm.git] / drivers / net / bnx2x.h
blobbdfe084b8abeefb19a1b2851d0ce0c1b899abb90
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 /* compilation time flags */
18
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
22
23 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24 #define BCM_VLAN 1
25 #endif
26
27 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
28 #define BCM_CNIC 1
29 #include "cnic_if.h"
30 #endif
31
32 #define BNX2X_MULTI_QUEUE
33
34 #define BNX2X_NEW_NAPI
35
36
37
38 #include <linux/mdio.h>
39 #include "bnx2x_reg.h"
40 #include "bnx2x_fw_defs.h"
41 #include "bnx2x_hsi.h"
42 #include "bnx2x_link.h"
43
44 /* error/debug prints */
45
46 #define DRV_MODULE_NAME "bnx2x"
47
48 /* for messages that are currently off */
49 #define BNX2X_MSG_OFF 0
50 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
51 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
52 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
53 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
54 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
55 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
56
57 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
58
59 /* regular debug print */
60 #define DP(__mask, __fmt, __args...) \
61 do { \
62 if (bp->msg_enable & (__mask)) \
63 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
64 __func__, __LINE__, \
65 bp->dev ? (bp->dev->name) : "?", \
66 ##__args); \
67 } while (0)
68
69 /* errors debug print */
70 #define BNX2X_DBG_ERR(__fmt, __args...) \
71 do { \
72 if (netif_msg_probe(bp)) \
73 pr_err("[%s:%d(%s)]" __fmt, \
74 __func__, __LINE__, \
75 bp->dev ? (bp->dev->name) : "?", \
76 ##__args); \
77 } while (0)
78
79 /* for errors (never masked) */
80 #define BNX2X_ERR(__fmt, __args...) \
81 do { \
82 pr_err("[%s:%d(%s)]" __fmt, \
83 __func__, __LINE__, \
84 bp->dev ? (bp->dev->name) : "?", \
85 ##__args); \
86 } while (0)
87
88 #define BNX2X_ERROR(__fmt, __args...) do { \
89 pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
90 } while (0)
91
92
93 /* before we have a dev->name use dev_info() */
94 #define BNX2X_DEV_INFO(__fmt, __args...) \
95 do { \
96 if (netif_msg_probe(bp)) \
97 dev_info(&bp->pdev->dev, __fmt, ##__args); \
98 } while (0)
99
100
101 #ifdef BNX2X_STOP_ON_ERROR
102 #define bnx2x_panic() do { \
103 bp->panic = 1; \
104 BNX2X_ERR("driver assert\n"); \
105 bnx2x_int_disable(bp); \
106 bnx2x_panic_dump(bp); \
107 } while (0)
108 #else
109 #define bnx2x_panic() do { \
110 bp->panic = 1; \
111 BNX2X_ERR("driver assert\n"); \
112 bnx2x_panic_dump(bp); \
113 } while (0)
114 #endif
115
116
117 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
118 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
119 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
120
121
122 #define REG_ADDR(bp, offset) (bp->regview + offset)
123
124 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
125 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
126
127 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
128 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
129 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
130
131 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
132 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
133
134 #define REG_RD_DMAE(bp, offset, valp, len32) \
135 do { \
136 bnx2x_read_dmae(bp, offset, len32);\
137 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
138 } while (0)
139
140 #define REG_WR_DMAE(bp, offset, valp, len32) \
141 do { \
142 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
143 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
144 offset, len32); \
145 } while (0)
146
147 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
148 do { \
149 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
150 bnx2x_write_big_buf_wb(bp, addr, len32); \
151 } while (0)
152
153 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
154 offsetof(struct shmem_region, field))
155 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
156 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
157
158 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
159 offsetof(struct shmem2_region, field))
160 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
161 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
162
163 #define MF_CFG_RD(bp, field) SHMEM_RD(bp, mf_cfg.field)
164 #define MF_CFG_WR(bp, field, val) SHMEM_WR(bp, mf_cfg.field, val)
165
166 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
167 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
168
169 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
170 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
171
172
173 /* fast path */
174
175 struct sw_rx_bd {
176 struct sk_buff *skb;
177 DEFINE_DMA_UNMAP_ADDR(mapping);
178 };
179
180 struct sw_tx_bd {
181 struct sk_buff *skb;
182 u16 first_bd;
183 u8 flags;
184 /* Set on the first BD descriptor when there is a split BD */
185 #define BNX2X_TSO_SPLIT_BD (1<<0)
186 };
187
188 struct sw_rx_page {
189 struct page *page;
190 DEFINE_DMA_UNMAP_ADDR(mapping);
191 };
192
193 union db_prod {
194 struct doorbell_set_prod data;
195 u32 raw;
196 };
197
198
199 /* MC hsi */
200 #define BCM_PAGE_SHIFT 12
201 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
202 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
203 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
204
205 #define PAGES_PER_SGE_SHIFT 0
206 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
207 #define SGE_PAGE_SIZE PAGE_SIZE
208 #define SGE_PAGE_SHIFT PAGE_SHIFT
209 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
210
211 /* SGE ring related macros */
212 #define NUM_RX_SGE_PAGES 2
213 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
214 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
215 /* RX_SGE_CNT is promised to be a power of 2 */
216 #define RX_SGE_MASK (RX_SGE_CNT - 1)
217 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
218 #define MAX_RX_SGE (NUM_RX_SGE - 1)
219 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
220 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
221 #define RX_SGE(x) ((x) & MAX_RX_SGE)
222
223 /* SGE producer mask related macros */
224 /* Number of bits in one sge_mask array element */
225 #define RX_SGE_MASK_ELEM_SZ 64
226 #define RX_SGE_MASK_ELEM_SHIFT 6
227 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
228
229 /* Creates a bitmask of all ones in less significant bits.
230 idx - index of the most significant bit in the created mask */
231 #define RX_SGE_ONES_MASK(idx) \
232 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
233 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
234
235 /* Number of u64 elements in SGE mask array */
236 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
237 RX_SGE_MASK_ELEM_SZ)
238 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
239 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
240
241
242 struct bnx2x_eth_q_stats {
243 u32 total_bytes_received_hi;
244 u32 total_bytes_received_lo;
245 u32 total_bytes_transmitted_hi;
246 u32 total_bytes_transmitted_lo;
247 u32 total_unicast_packets_received_hi;
248 u32 total_unicast_packets_received_lo;
249 u32 total_multicast_packets_received_hi;
250 u32 total_multicast_packets_received_lo;
251 u32 total_broadcast_packets_received_hi;
252 u32 total_broadcast_packets_received_lo;
253 u32 total_unicast_packets_transmitted_hi;
254 u32 total_unicast_packets_transmitted_lo;
255 u32 total_multicast_packets_transmitted_hi;
256 u32 total_multicast_packets_transmitted_lo;
257 u32 total_broadcast_packets_transmitted_hi;
258 u32 total_broadcast_packets_transmitted_lo;
259 u32 valid_bytes_received_hi;
260 u32 valid_bytes_received_lo;
261
262 u32 error_bytes_received_hi;
263 u32 error_bytes_received_lo;
264 u32 etherstatsoverrsizepkts_hi;
265 u32 etherstatsoverrsizepkts_lo;
266 u32 no_buff_discard_hi;
267 u32 no_buff_discard_lo;
268
269 u32 driver_xoff;
270 u32 rx_err_discard_pkt;
271 u32 rx_skb_alloc_failed;
272 u32 hw_csum_err;
273 };
274
275 #define BNX2X_NUM_Q_STATS 11
276 #define Q_STATS_OFFSET32(stat_name) \
277 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
278
279 struct bnx2x_fastpath {
280
281 struct napi_struct napi;
282 struct host_status_block *status_blk;
283 dma_addr_t status_blk_mapping;
284
285 struct sw_tx_bd *tx_buf_ring;
286
287 union eth_tx_bd_types *tx_desc_ring;
288 dma_addr_t tx_desc_mapping;
289
290 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
291 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
292
293 struct eth_rx_bd *rx_desc_ring;
294 dma_addr_t rx_desc_mapping;
295
296 union eth_rx_cqe *rx_comp_ring;
297 dma_addr_t rx_comp_mapping;
298
299 /* SGE ring */
300 struct eth_rx_sge *rx_sge_ring;
301 dma_addr_t rx_sge_mapping;
302
303 u64 sge_mask[RX_SGE_MASK_LEN];
304
305 int state;
306 #define BNX2X_FP_STATE_CLOSED 0
307 #define BNX2X_FP_STATE_IRQ 0x80000
308 #define BNX2X_FP_STATE_OPENING 0x90000
309 #define BNX2X_FP_STATE_OPEN 0xa0000
310 #define BNX2X_FP_STATE_HALTING 0xb0000
311 #define BNX2X_FP_STATE_HALTED 0xc0000
312
313 u8 index; /* number in fp array */
314 u8 cl_id; /* eth client id */
315 u8 sb_id; /* status block number in HW */
316
317 union db_prod tx_db;
318
319 u16 tx_pkt_prod;
320 u16 tx_pkt_cons;
321 u16 tx_bd_prod;
322 u16 tx_bd_cons;
323 __le16 *tx_cons_sb;
324
325 __le16 fp_c_idx;
326 __le16 fp_u_idx;
327
328 u16 rx_bd_prod;
329 u16 rx_bd_cons;
330 u16 rx_comp_prod;
331 u16 rx_comp_cons;
332 u16 rx_sge_prod;
333 /* The last maximal completed SGE */
334 u16 last_max_sge;
335 __le16 *rx_cons_sb;
336 __le16 *rx_bd_cons_sb;
337
338
339 unsigned long tx_pkt,
340 rx_pkt,
341 rx_calls;
342
343 /* TPA related */
344 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
345 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
346 #define BNX2X_TPA_START 1
347 #define BNX2X_TPA_STOP 2
348 u8 disable_tpa;
349 #ifdef BNX2X_STOP_ON_ERROR
350 u64 tpa_queue_used;
351 #endif
352
353 struct tstorm_per_client_stats old_tclient;
354 struct ustorm_per_client_stats old_uclient;
355 struct xstorm_per_client_stats old_xclient;
356 struct bnx2x_eth_q_stats eth_q_stats;
357
358 /* The size is calculated using the following:
359 sizeof name field from netdev structure +
360 4 ('-Xx-' string) +
361 4 (for the digits and to make it DWORD aligned) */
362 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
363 char name[FP_NAME_SIZE];
364 struct bnx2x *bp; /* parent */
365 };
366
367 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
368
369
370 /* MC hsi */
371 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
372 #define RX_COPY_THRESH 92
373
374 #define NUM_TX_RINGS 16
375 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
376 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
377 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
378 #define MAX_TX_BD (NUM_TX_BD - 1)
379 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
380 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
381 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
382 #define TX_BD(x) ((x) & MAX_TX_BD)
383 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
384
385 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
386 #define NUM_RX_RINGS 8
387 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
388 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
389 #define RX_DESC_MASK (RX_DESC_CNT - 1)
390 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
391 #define MAX_RX_BD (NUM_RX_BD - 1)
392 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
393 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
394 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
395 #define RX_BD(x) ((x) & MAX_RX_BD)
396
397 /* As long as CQE is 4 times bigger than BD entry we have to allocate
398 4 times more pages for CQ ring in order to keep it balanced with
399 BD ring */
400 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
401 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
402 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
403 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
404 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
405 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
406 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
407 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
408 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
409
410
411 /* This is needed for determining of last_max */
412 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
413
414 #define __SGE_MASK_SET_BIT(el, bit) \
415 do { \
416 el = ((el) | ((u64)0x1 << (bit))); \
417 } while (0)
418
419 #define __SGE_MASK_CLEAR_BIT(el, bit) \
420 do { \
421 el = ((el) & (~((u64)0x1 << (bit)))); \
422 } while (0)
423
424 #define SGE_MASK_SET_BIT(fp, idx) \
425 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
426 ((idx) & RX_SGE_MASK_ELEM_MASK))
427
428 #define SGE_MASK_CLEAR_BIT(fp, idx) \
429 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
430 ((idx) & RX_SGE_MASK_ELEM_MASK))
431
432
433 /* used on a CID received from the HW */
434 #define SW_CID(x) (le32_to_cpu(x) & \
435 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
436 #define CQE_CMD(x) (le32_to_cpu(x) >> \
437 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
438
439 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
440 le32_to_cpu((bd)->addr_lo))
441 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
442
443
444 #define DPM_TRIGER_TYPE 0x40
445 #define DOORBELL(bp, cid, val) \
446 do { \
447 writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
448 DPM_TRIGER_TYPE); \
449 } while (0)
450
451
452 /* TX CSUM helpers */
453 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
454 skb->csum_offset)
455 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
456 skb->csum_offset))
457
458 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
459
460 #define XMIT_PLAIN 0
461 #define XMIT_CSUM_V4 0x1
462 #define XMIT_CSUM_V6 0x2
463 #define XMIT_CSUM_TCP 0x4
464 #define XMIT_GSO_V4 0x8
465 #define XMIT_GSO_V6 0x10
466
467 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
468 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
469
470
471 /* stuff added to make the code fit 80Col */
472
473 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
474
475 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
476 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
477 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
478 (TPA_TYPE_START | TPA_TYPE_END))
479
480 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
481
482 #define BNX2X_IP_CSUM_ERR(cqe) \
483 (!((cqe)->fast_path_cqe.status_flags & \
484 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
485 ((cqe)->fast_path_cqe.type_error_flags & \
486 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
487
488 #define BNX2X_L4_CSUM_ERR(cqe) \
489 (!((cqe)->fast_path_cqe.status_flags & \
490 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
491 ((cqe)->fast_path_cqe.type_error_flags & \
492 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
493
494 #define BNX2X_RX_CSUM_OK(cqe) \
495 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
496
497 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
498 (((le16_to_cpu(flags) & \
499 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
500 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
501 == PRS_FLAG_OVERETH_IPV4)
502 #define BNX2X_RX_SUM_FIX(cqe) \
503 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
504
505
506 #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
507 #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
508
509 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
510 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
511 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
512
513 #define BNX2X_RX_SB_INDEX \
514 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
515
516 #define BNX2X_RX_SB_BD_INDEX \
517 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
518
519 #define BNX2X_RX_SB_INDEX_NUM \
520 (((U_SB_ETH_RX_CQ_INDEX << \
521 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
522 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
523 ((U_SB_ETH_RX_BD_INDEX << \
524 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
525 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
526
527 #define BNX2X_TX_SB_INDEX \
528 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
529
530
531 /* end of fast path */
532
533 /* common */
534
535 struct bnx2x_common {
536
537 u32 chip_id;
538 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
539 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
540
541 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
542 #define CHIP_NUM_57710 0x164e
543 #define CHIP_NUM_57711 0x164f
544 #define CHIP_NUM_57711E 0x1650
545 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
546 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
547 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
548 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
549 CHIP_IS_57711E(bp))
550 #define IS_E1H_OFFSET CHIP_IS_E1H(bp)
551
552 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
553 #define CHIP_REV_Ax 0x00000000
554 /* assume maximum 5 revisions */
555 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
556 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
557 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
558 !(CHIP_REV(bp) & 0x00001000))
559 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
560 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
561 (CHIP_REV(bp) & 0x00001000))
562
563 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
564 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
565
566 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
567 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
568
569 int flash_size;
570 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
571 #define NVRAM_TIMEOUT_COUNT 30000
572 #define NVRAM_PAGE_SIZE 256
573
574 u32 shmem_base;
575 u32 shmem2_base;
576
577 u32 hw_config;
578
579 u32 bc_ver;
580 };
581
582
583 /* end of common */
584
585 /* port */
586
587 struct nig_stats {
588 u32 brb_discard;
589 u32 brb_packet;
590 u32 brb_truncate;
591 u32 flow_ctrl_discard;
592 u32 flow_ctrl_octets;
593 u32 flow_ctrl_packet;
594 u32 mng_discard;
595 u32 mng_octet_inp;
596 u32 mng_octet_out;
597 u32 mng_packet_inp;
598 u32 mng_packet_out;
599 u32 pbf_octets;
600 u32 pbf_packet;
601 u32 safc_inp;
602 u32 egress_mac_pkt0_lo;
603 u32 egress_mac_pkt0_hi;
604 u32 egress_mac_pkt1_lo;
605 u32 egress_mac_pkt1_hi;
606 };
607
608 struct bnx2x_port {
609 u32 pmf;
610
611 u32 link_config;
612
613 u32 supported;
614 /* link settings - missing defines */
615 #define SUPPORTED_2500baseX_Full (1 << 15)
616
617 u32 advertising;
618 /* link settings - missing defines */
619 #define ADVERTISED_2500baseX_Full (1 << 15)
620
621 u32 phy_addr;
622
623 /* used to synchronize phy accesses */
624 struct mutex phy_mutex;
625 int need_hw_lock;
626
627 u32 port_stx;
628
629 struct nig_stats old_nig_stats;
630 };
631
632 /* end of port */
633
634
635 enum bnx2x_stats_event {
636 STATS_EVENT_PMF = 0,
637 STATS_EVENT_LINK_UP,
638 STATS_EVENT_UPDATE,
639 STATS_EVENT_STOP,
640 STATS_EVENT_MAX
641 };
642
643 enum bnx2x_stats_state {
644 STATS_STATE_DISABLED = 0,
645 STATS_STATE_ENABLED,
646 STATS_STATE_MAX
647 };
648
649 struct bnx2x_eth_stats {
650 u32 total_bytes_received_hi;
651 u32 total_bytes_received_lo;
652 u32 total_bytes_transmitted_hi;
653 u32 total_bytes_transmitted_lo;
654 u32 total_unicast_packets_received_hi;
655 u32 total_unicast_packets_received_lo;
656 u32 total_multicast_packets_received_hi;
657 u32 total_multicast_packets_received_lo;
658 u32 total_broadcast_packets_received_hi;
659 u32 total_broadcast_packets_received_lo;
660 u32 total_unicast_packets_transmitted_hi;
661 u32 total_unicast_packets_transmitted_lo;
662 u32 total_multicast_packets_transmitted_hi;
663 u32 total_multicast_packets_transmitted_lo;
664 u32 total_broadcast_packets_transmitted_hi;
665 u32 total_broadcast_packets_transmitted_lo;
666 u32 valid_bytes_received_hi;
667 u32 valid_bytes_received_lo;
668
669 u32 error_bytes_received_hi;
670 u32 error_bytes_received_lo;
671 u32 etherstatsoverrsizepkts_hi;
672 u32 etherstatsoverrsizepkts_lo;
673 u32 no_buff_discard_hi;
674 u32 no_buff_discard_lo;
675
676 u32 rx_stat_ifhcinbadoctets_hi;
677 u32 rx_stat_ifhcinbadoctets_lo;
678 u32 tx_stat_ifhcoutbadoctets_hi;
679 u32 tx_stat_ifhcoutbadoctets_lo;
680 u32 rx_stat_dot3statsfcserrors_hi;
681 u32 rx_stat_dot3statsfcserrors_lo;
682 u32 rx_stat_dot3statsalignmenterrors_hi;
683 u32 rx_stat_dot3statsalignmenterrors_lo;
684 u32 rx_stat_dot3statscarriersenseerrors_hi;
685 u32 rx_stat_dot3statscarriersenseerrors_lo;
686 u32 rx_stat_falsecarriererrors_hi;
687 u32 rx_stat_falsecarriererrors_lo;
688 u32 rx_stat_etherstatsundersizepkts_hi;
689 u32 rx_stat_etherstatsundersizepkts_lo;
690 u32 rx_stat_dot3statsframestoolong_hi;
691 u32 rx_stat_dot3statsframestoolong_lo;
692 u32 rx_stat_etherstatsfragments_hi;
693 u32 rx_stat_etherstatsfragments_lo;
694 u32 rx_stat_etherstatsjabbers_hi;
695 u32 rx_stat_etherstatsjabbers_lo;
696 u32 rx_stat_maccontrolframesreceived_hi;
697 u32 rx_stat_maccontrolframesreceived_lo;
698 u32 rx_stat_bmac_xpf_hi;
699 u32 rx_stat_bmac_xpf_lo;
700 u32 rx_stat_bmac_xcf_hi;
701 u32 rx_stat_bmac_xcf_lo;
702 u32 rx_stat_xoffstateentered_hi;
703 u32 rx_stat_xoffstateentered_lo;
704 u32 rx_stat_xonpauseframesreceived_hi;
705 u32 rx_stat_xonpauseframesreceived_lo;
706 u32 rx_stat_xoffpauseframesreceived_hi;
707 u32 rx_stat_xoffpauseframesreceived_lo;
708 u32 tx_stat_outxonsent_hi;
709 u32 tx_stat_outxonsent_lo;
710 u32 tx_stat_outxoffsent_hi;
711 u32 tx_stat_outxoffsent_lo;
712 u32 tx_stat_flowcontroldone_hi;
713 u32 tx_stat_flowcontroldone_lo;
714 u32 tx_stat_etherstatscollisions_hi;
715 u32 tx_stat_etherstatscollisions_lo;
716 u32 tx_stat_dot3statssinglecollisionframes_hi;
717 u32 tx_stat_dot3statssinglecollisionframes_lo;
718 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
719 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
720 u32 tx_stat_dot3statsdeferredtransmissions_hi;
721 u32 tx_stat_dot3statsdeferredtransmissions_lo;
722 u32 tx_stat_dot3statsexcessivecollisions_hi;
723 u32 tx_stat_dot3statsexcessivecollisions_lo;
724 u32 tx_stat_dot3statslatecollisions_hi;
725 u32 tx_stat_dot3statslatecollisions_lo;
726 u32 tx_stat_etherstatspkts64octets_hi;
727 u32 tx_stat_etherstatspkts64octets_lo;
728 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
729 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
730 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
731 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
732 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
733 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
734 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
735 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
736 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
737 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
738 u32 tx_stat_etherstatspktsover1522octets_hi;
739 u32 tx_stat_etherstatspktsover1522octets_lo;
740 u32 tx_stat_bmac_2047_hi;
741 u32 tx_stat_bmac_2047_lo;
742 u32 tx_stat_bmac_4095_hi;
743 u32 tx_stat_bmac_4095_lo;
744 u32 tx_stat_bmac_9216_hi;
745 u32 tx_stat_bmac_9216_lo;
746 u32 tx_stat_bmac_16383_hi;
747 u32 tx_stat_bmac_16383_lo;
748 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
749 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
750 u32 tx_stat_bmac_ufl_hi;
751 u32 tx_stat_bmac_ufl_lo;
752
753 u32 pause_frames_received_hi;
754 u32 pause_frames_received_lo;
755 u32 pause_frames_sent_hi;
756 u32 pause_frames_sent_lo;
757
758 u32 etherstatspkts1024octetsto1522octets_hi;
759 u32 etherstatspkts1024octetsto1522octets_lo;
760 u32 etherstatspktsover1522octets_hi;
761 u32 etherstatspktsover1522octets_lo;
762
763 u32 brb_drop_hi;
764 u32 brb_drop_lo;
765 u32 brb_truncate_hi;
766 u32 brb_truncate_lo;
767
768 u32 mac_filter_discard;
769 u32 xxoverflow_discard;
770 u32 brb_truncate_discard;
771 u32 mac_discard;
772
773 u32 driver_xoff;
774 u32 rx_err_discard_pkt;
775 u32 rx_skb_alloc_failed;
776 u32 hw_csum_err;
777
778 u32 nig_timer_max;
779 };
780
781 #define BNX2X_NUM_STATS 41
782 #define STATS_OFFSET32(stat_name) \
783 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
784
785
786 #ifdef BCM_CNIC
787 #define MAX_CONTEXT 15
788 #else
789 #define MAX_CONTEXT 16
790 #endif
791
792 union cdu_context {
793 struct eth_context eth;
794 char pad[1024];
795 };
796
797 #define MAX_DMAE_C 8
798
799 /* DMA memory not used in fastpath */
800 struct bnx2x_slowpath {
801 union cdu_context context[MAX_CONTEXT];
802 struct eth_stats_query fw_stats;
803 struct mac_configuration_cmd mac_config;
804 struct mac_configuration_cmd mcast_config;
805
806 /* used by dmae command executer */
807 struct dmae_command dmae[MAX_DMAE_C];
808
809 u32 stats_comp;
810 union mac_stats mac_stats;
811 struct nig_stats nig_stats;
812 struct host_port_stats port_stats;
813 struct host_func_stats func_stats;
814 struct host_func_stats func_stats_base;
815
816 u32 wb_comp;
817 u32 wb_data[4];
818 };
819
820 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
821 #define bnx2x_sp_mapping(bp, var) \
822 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
823
824
825 /* attn group wiring */
826 #define MAX_DYNAMIC_ATTN_GRPS 8
827
828 struct attn_route {
829 u32 sig[4];
830 };
831
832 typedef enum {
833 BNX2X_RECOVERY_DONE,
834 BNX2X_RECOVERY_INIT,
835 BNX2X_RECOVERY_WAIT,
836 } bnx2x_recovery_state_t;
837
838 struct bnx2x {
839 /* Fields used in the tx and intr/napi performance paths
840 * are grouped together in the beginning of the structure
841 */
842 struct bnx2x_fastpath fp[MAX_CONTEXT];
843 void __iomem *regview;
844 void __iomem *doorbells;
845 #ifdef BCM_CNIC
846 #define BNX2X_DB_SIZE (18*BCM_PAGE_SIZE)
847 #else
848 #define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
849 #endif
850
851 struct net_device *dev;
852 struct pci_dev *pdev;
853
854 atomic_t intr_sem;
855
856 bnx2x_recovery_state_t recovery_state;
857 int is_leader;
858 #ifdef BCM_CNIC
859 struct msix_entry msix_table[MAX_CONTEXT+2];
860 #else
861 struct msix_entry msix_table[MAX_CONTEXT+1];
862 #endif
863 #define INT_MODE_INTx 1
864 #define INT_MODE_MSI 2
865 #define INT_MODE_MSIX 3
866
867 int tx_ring_size;
868
869 #ifdef BCM_VLAN
870 struct vlan_group *vlgrp;
871 #endif
872
873 u32 rx_csum;
874 u32 rx_buf_size;
875 #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
876 #define ETH_MIN_PACKET_SIZE 60
877 #define ETH_MAX_PACKET_SIZE 1500
878 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
879
880 /* Max supported alignment is 256 (8 shift) */
881 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
882 L1_CACHE_SHIFT : 8)
883 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
884
885 struct host_def_status_block *def_status_blk;
886 #define DEF_SB_ID 16
887 __le16 def_c_idx;
888 __le16 def_u_idx;
889 __le16 def_x_idx;
890 __le16 def_t_idx;
891 __le16 def_att_idx;
892 u32 attn_state;
893 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
894
895 /* slow path ring */
896 struct eth_spe *spq;
897 dma_addr_t spq_mapping;
898 u16 spq_prod_idx;
899 struct eth_spe *spq_prod_bd;
900 struct eth_spe *spq_last_bd;
901 __le16 *dsb_sp_prod;
902 u16 spq_left; /* serialize spq */
903 /* used to synchronize spq accesses */
904 spinlock_t spq_lock;
905
906 /* Flags for marking that there is a STAT_QUERY or
907 SET_MAC ramrod pending */
908 int stats_pending;
909 int set_mac_pending;
910
911 /* End of fields used in the performance code paths */
912
913 int panic;
914 int msg_enable;
915
916 u32 flags;
917 #define PCIX_FLAG 1
918 #define PCI_32BIT_FLAG 2
919 #define ONE_PORT_FLAG 4
920 #define NO_WOL_FLAG 8
921 #define USING_DAC_FLAG 0x10
922 #define USING_MSIX_FLAG 0x20
923 #define USING_MSI_FLAG 0x40
924 #define TPA_ENABLE_FLAG 0x80
925 #define NO_MCP_FLAG 0x100
926 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
927 #define HW_VLAN_TX_FLAG 0x400
928 #define HW_VLAN_RX_FLAG 0x800
929 #define MF_FUNC_DIS 0x1000
930
931 int func;
932 #define BP_PORT(bp) (bp->func % PORT_MAX)
933 #define BP_FUNC(bp) (bp->func)
934 #define BP_E1HVN(bp) (bp->func >> 1)
935 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
936
937 #ifdef BCM_CNIC
938 #define BCM_CNIC_CID_START 16
939 #define BCM_ISCSI_ETH_CL_ID 17
940 #endif
941
942 int pm_cap;
943 int pcie_cap;
944 int mrrs;
945
946 struct delayed_work sp_task;
947 struct delayed_work reset_task;
948 struct timer_list timer;
949 int current_interval;
950
951 u16 fw_seq;
952 u16 fw_drv_pulse_wr_seq;
953 u32 func_stx;
954
955 struct link_params link_params;
956 struct link_vars link_vars;
957 struct mdio_if_info mdio;
958
959 struct bnx2x_common common;
960 struct bnx2x_port port;
961
962 struct cmng_struct_per_port cmng;
963 u32 vn_weight_sum;
964
965 u32 mf_config;
966 u16 e1hov;
967 u8 e1hmf;
968 #define IS_E1HMF(bp) (bp->e1hmf != 0)
969
970 u8 wol;
971
972 int rx_ring_size;
973
974 u16 tx_quick_cons_trip_int;
975 u16 tx_quick_cons_trip;
976 u16 tx_ticks_int;
977 u16 tx_ticks;
978
979 u16 rx_quick_cons_trip_int;
980 u16 rx_quick_cons_trip;
981 u16 rx_ticks_int;
982 u16 rx_ticks;
983 /* Maximal coalescing timeout in us */
984 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
985
986 u32 lin_cnt;
987
988 int state;
989 #define BNX2X_STATE_CLOSED 0
990 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
991 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
992 #define BNX2X_STATE_OPEN 0x3000
993 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
994 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
995 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
996 #define BNX2X_STATE_DIAG 0xe000
997 #define BNX2X_STATE_ERROR 0xf000
998
999 int multi_mode;
1000 int num_queues;
1001
1002 u32 rx_mode;
1003 #define BNX2X_RX_MODE_NONE 0
1004 #define BNX2X_RX_MODE_NORMAL 1
1005 #define BNX2X_RX_MODE_ALLMULTI 2
1006 #define BNX2X_RX_MODE_PROMISC 3
1007 #define BNX2X_MAX_MULTICAST 64
1008 #define BNX2X_MAX_EMUL_MULTI 16
1009
1010 u32 rx_mode_cl_mask;
1011
1012 dma_addr_t def_status_blk_mapping;
1013
1014 struct bnx2x_slowpath *slowpath;
1015 dma_addr_t slowpath_mapping;
1016
1017 int dropless_fc;
1018
1019 #ifdef BCM_CNIC
1020 u32 cnic_flags;
1021 #define BNX2X_CNIC_FLAG_MAC_SET 1
1022
1023 void *t1;
1024 dma_addr_t t1_mapping;
1025 void *t2;
1026 dma_addr_t t2_mapping;
1027 void *timers;
1028 dma_addr_t timers_mapping;
1029 void *qm;
1030 dma_addr_t qm_mapping;
1031 struct cnic_ops *cnic_ops;
1032 void *cnic_data;
1033 u32 cnic_tag;
1034 struct cnic_eth_dev cnic_eth_dev;
1035 struct host_status_block *cnic_sb;
1036 dma_addr_t cnic_sb_mapping;
1037 #define CNIC_SB_ID(bp) BP_L_ID(bp)
1038 struct eth_spe *cnic_kwq;
1039 struct eth_spe *cnic_kwq_prod;
1040 struct eth_spe *cnic_kwq_cons;
1041 struct eth_spe *cnic_kwq_last;
1042 u16 cnic_kwq_pending;
1043 u16 cnic_spq_pending;
1044 struct mutex cnic_mutex;
1045 u8 iscsi_mac[6];
1046 #endif
1047
1048 int dmae_ready;
1049 /* used to synchronize dmae accesses */
1050 struct mutex dmae_mutex;
1051
1052 /* used to protect the FW mail box */
1053 struct mutex fw_mb_mutex;
1054
1055 /* used to synchronize stats collecting */
1056 int stats_state;
1057 /* used by dmae command loader */
1058 struct dmae_command stats_dmae;
1059 int executer_idx;
1060
1061 u16 stats_counter;
1062 struct bnx2x_eth_stats eth_stats;
1063
1064 struct z_stream_s *strm;
1065 void *gunzip_buf;
1066 dma_addr_t gunzip_mapping;
1067 int gunzip_outlen;
1068 #define FW_BUF_SIZE 0x8000
1069 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1070 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1071 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1072
1073 struct raw_op *init_ops;
1074 /* Init blocks offsets inside init_ops */
1075 u16 *init_ops_offsets;
1076 /* Data blob - has 32 bit granularity */
1077 u32 *init_data;
1078 /* Zipped PRAM blobs - raw data */
1079 const u8 *tsem_int_table_data;
1080 const u8 *tsem_pram_data;
1081 const u8 *usem_int_table_data;
1082 const u8 *usem_pram_data;
1083 const u8 *xsem_int_table_data;
1084 const u8 *xsem_pram_data;
1085 const u8 *csem_int_table_data;
1086 const u8 *csem_pram_data;
1087 #define INIT_OPS(bp) (bp->init_ops)
1088 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1089 #define INIT_DATA(bp) (bp->init_data)
1090 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1091 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1092 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1093 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1094 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1095 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1096 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1097 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1098
1099 char fw_ver[32];
1100 const struct firmware *firmware;
1101 };
1102
1103
1104 #define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/E1HVN_MAX) \
1105 : MAX_CONTEXT)
1106 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1107 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1108
1109 #define for_each_queue(bp, var) \
1110 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1111 #define for_each_nondefault_queue(bp, var) \
1112 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
1113
1114
1115 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1116 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1117 u32 len32);
1118 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1119 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1120 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1121 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
1122 void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
1123 void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
1124 u32 addr, u32 len);
1125
1126 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1127 int wait)
1128 {
1129 u32 val;
1130
1131 do {
1132 val = REG_RD(bp, reg);
1133 if (val == expected)
1134 break;
1135 ms -= wait;
1136 msleep(wait);
1137
1138 } while (ms > 0);
1139
1140 return val;
1141 }
1142
1143
1144 /* load/unload mode */
1145 #define LOAD_NORMAL 0
1146 #define LOAD_OPEN 1
1147 #define LOAD_DIAG 2
1148 #define UNLOAD_NORMAL 0
1149 #define UNLOAD_CLOSE 1
1150 #define UNLOAD_RECOVERY 2
1151
1152
1153 /* DMAE command defines */
1154 #define DMAE_CMD_SRC_PCI 0
1155 #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1156
1157 #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1158 #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1159
1160 #define DMAE_CMD_C_DST_PCI 0
1161 #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1162
1163 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1164
1165 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1166 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1167 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1168 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1169
1170 #define DMAE_CMD_PORT_0 0
1171 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1172
1173 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1174 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1175 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1176
1177 #define DMAE_LEN32_RD_MAX 0x80
1178 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1179
1180 #define DMAE_COMP_VAL 0xe0d0d0ae
1181
1182 #define MAX_DMAE_C_PER_PORT 8
1183 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1184 BP_E1HVN(bp))
1185 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1186 E1HVN_MAX)
1187
1188
1189 /* PCIE link and speed */
1190 #define PCICFG_LINK_WIDTH 0x1f00000
1191 #define PCICFG_LINK_WIDTH_SHIFT 20
1192 #define PCICFG_LINK_SPEED 0xf0000
1193 #define PCICFG_LINK_SPEED_SHIFT 16
1194
1195
1196 #define BNX2X_NUM_TESTS 7
1197
1198 #define BNX2X_PHY_LOOPBACK 0
1199 #define BNX2X_MAC_LOOPBACK 1
1200 #define BNX2X_PHY_LOOPBACK_FAILED 1
1201 #define BNX2X_MAC_LOOPBACK_FAILED 2
1202 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1203 BNX2X_PHY_LOOPBACK_FAILED)
1204
1205
1206 #define STROM_ASSERT_ARRAY_SIZE 50
1207
1208
1209 /* must be used on a CID before placing it on a HW ring */
1210 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1211 (BP_E1HVN(bp) << 17) | (x))
1212
1213 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1214 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1215
1216
1217 #define BNX2X_BTR 1
1218 #define MAX_SPQ_PENDING 8
1219
1220
1221 /* CMNG constants
1222 derived from lab experiments, and not from system spec calculations !!! */
1223 #define DEF_MIN_RATE 100
1224 /* resolution of the rate shaping timer - 100 usec */
1225 #define RS_PERIODIC_TIMEOUT_USEC 100
1226 /* resolution of fairness algorithm in usecs -
1227 coefficient for calculating the actual t fair */
1228 #define T_FAIR_COEF 10000000
1229 /* number of bytes in single QM arbitration cycle -
1230 coefficient for calculating the fairness timer */
1231 #define QM_ARB_BYTES 40000
1232 #define FAIR_MEM 2
1233
1234
1235 #define ATTN_NIG_FOR_FUNC (1L << 8)
1236 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1237 #define GPIO_2_FUNC (1L << 10)
1238 #define GPIO_3_FUNC (1L << 11)
1239 #define GPIO_4_FUNC (1L << 12)
1240 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1241 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1242 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1243 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1244 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1245 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1246
1247 #define ATTN_HARD_WIRED_MASK 0xff00
1248 #define ATTENTION_ID 4
1249
1250
1251 /* stuff added to make the code fit 80Col */
1252
1253 #define BNX2X_PMF_LINK_ASSERT \
1254 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1255
1256 #define BNX2X_MC_ASSERT_BITS \
1257 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1258 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1259 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1260 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1261
1262 #define BNX2X_MCP_ASSERT \
1263 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1264
1265 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1266 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1267 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1268 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1269 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1270 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1271 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1272
1273 #define HW_INTERRUT_ASSERT_SET_0 \
1274 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1275 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1276 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1277 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1278 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1279 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1280 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1281 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1282 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1283 #define HW_INTERRUT_ASSERT_SET_1 \
1284 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1285 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1286 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1287 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1288 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1289 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1290 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1291 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1292 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1293 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1294 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1295 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1296 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1297 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1298 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1299 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1300 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1301 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1302 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1303 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1304 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1305 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1306 #define HW_INTERRUT_ASSERT_SET_2 \
1307 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1308 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1309 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1310 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1311 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1312 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1313 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1314 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1315 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1316 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1317 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1318 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1319
1320 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1321 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1322 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1323 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1324
1325 #define MULTI_FLAGS(bp) \
1326 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1327 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1328 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1329 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1330 (bp->multi_mode << \
1331 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1332 #define MULTI_MASK 0x7f
1333
1334
1335 #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1336 #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1337 #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1338 #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1339
1340 #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1341
1342 #define BNX2X_SP_DSB_INDEX \
1343 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1344
1345
1346 #define CAM_IS_INVALID(x) \
1347 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1348
1349 #define CAM_INVALIDATE(x) \
1350 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1351
1352
1353 /* Number of u32 elements in MC hash array */
1354 #define MC_HASH_SIZE 8
1355 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1356 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1357
1358
1359 #ifndef PXP2_REG_PXP2_INT_STS
1360 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1361 #endif
1362
1363 #define BNX2X_VPD_LEN 128
1364 #define VENDOR_ID_LEN 4
1365
1366 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1367
1368 #endif /* bnx2x.h */
kernel-based virtual machine