drivers/net/pcmcia/nmclan_cs.c

   1 /* ----------------------------------------------------------------------------
   2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
   3   nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
   4
   5   The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
   6   Access Controller for Ethernet (MACE).  It is essentially the Am2150
   7   PCMCIA Ethernet card contained in the Am2150 Demo Kit.
   8
   9 Written by Roger C. Pao <rpao@paonet.org>
  10   Copyright 1995 Roger C. Pao
  11   Linux 2.5 cleanups Copyright Red Hat 2003
  12
  13   This software may be used and distributed according to the terms of
  14   the GNU General Public License.
  15
  16 Ported to Linux 1.3.* network driver environment by
  17   Matti Aarnio <mea@utu.fi>
  18
  19 References
  20
  21   Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
  22   Am79C940 (MACE) Data Sheet, 1994
  23   Am79C90 (C-LANCE) Data Sheet, 1994
  24   Linux PCMCIA Programmer's Guide v1.17
  25   /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
  26
  27   Eric Mears, New Media Corporation
  28   Tom Pollard, New Media Corporation
  29   Dean Siasoyco, New Media Corporation
  30   Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
  31   Donald Becker <becker@scyld.com>
  32   David Hinds <dahinds@users.sourceforge.net>
  33
  34   The Linux client driver is based on the 3c589_cs.c client driver by
  35   David Hinds.
  36
  37   The Linux network driver outline is based on the 3c589_cs.c driver,
  38   the 8390.c driver, and the example skeleton.c kernel code, which are
  39   by Donald Becker.
  40
  41   The Am2150 network driver hardware interface code is based on the
  42   OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
  43
  44   Special thanks for testing and help in debugging this driver goes
  45   to Ken Lesniak.
  46
  47 -------------------------------------------------------------------------------
  48 Driver Notes and Issues
  49 -------------------------------------------------------------------------------
  50
  51 1. Developed on a Dell 320SLi
  52    PCMCIA Card Services 2.6.2
  53    Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
  54
  55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
  56    'insmod pcmcia_core.o io_speed=300'.
  57    This will avoid problems with fast systems which causes rx_framecnt
  58    to return random values.
  59
  60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
  61    before extraction.
  62
  63 4. There is a bad slow-down problem in this driver.
  64
  65 5. Future: Multicast processing.  In the meantime, do _not_ compile your
  66    kernel with multicast ip enabled.
  67
  68 -------------------------------------------------------------------------------
  69 History
  70 -------------------------------------------------------------------------------
  71 Log: nmclan_cs.c,v
  72  * 2.5.75-ac1 2003/07/11 Alan Cox <alan@redhat.com>
  73  * Fixed hang on card eject as we probe it
  74  * Cleaned up to use new style locking.
  75  *
  76  * Revision 0.16  1995/07/01  06:42:17  rpao
  77  * Bug fix: nmclan_reset() called CardServices incorrectly.
  78  *
  79  * Revision 0.15  1995/05/24  08:09:47  rpao
  80  * Re-implement MULTI_TX dev->tbusy handling.
  81  *
  82  * Revision 0.14  1995/05/23  03:19:30  rpao
  83  * Added, in nmclan_config(), "tuple.Attributes = 0;".
  84  * Modified MACE ID check to ignore chip revision level.
  85  * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
  86  *
  87  * Revision 0.13  1995/05/18  05:56:34  rpao
  88  * Statistics changes.
  89  * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
  90  * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT.  Fixes driver lockup.
  91  *
  92  * Revision 0.12  1995/05/14  00:12:23  rpao
  93  * Statistics overhaul.
  94  *
  95
  96 95/05/13 rpao   V0.10a
  97                 Bug fix: MACE statistics counters used wrong I/O ports.
  98                 Bug fix: mace_interrupt() needed to allow statistics to be
  99                 processed without RX or TX interrupts pending.
 100 95/05/11 rpao   V0.10
 101                 Multiple transmit request processing.
 102                 Modified statistics to use MACE counters where possible.
 103 95/05/10 rpao   V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
 104                 *Released
 105 95/05/10 rpao   V0.08
 106                 Bug fix: Make all non-exported functions private by using
 107                 static keyword.
 108                 Bug fix: Test IntrCnt _before_ reading MACE_IR.
 109 95/05/10 rpao   V0.07 Statistics.
 110 95/05/09 rpao   V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
 111
 112 ---------------------------------------------------------------------------- */
 113
 114 #define DRV_NAME        "nmclan_cs"
 115 #define DRV_VERSION     "0.16"
 116
 117
 118 /* ----------------------------------------------------------------------------
 119 Conditional Compilation Options
 120 ---------------------------------------------------------------------------- */
 121
 122 #define MULTI_TX                        0
 123 #define RESET_ON_TIMEOUT                1
 124 #define TX_INTERRUPTABLE                1
 125 #define RESET_XILINX                    0
 126
 127 /* ----------------------------------------------------------------------------
 128 Include Files
 129 ---------------------------------------------------------------------------- */
 130
 131 #include <linux/module.h>
 132 #include <linux/kernel.h>
 133 #include <linux/init.h>
 134 #include <linux/ptrace.h>
 135 #include <linux/slab.h>
 136 #include <linux/string.h>
 137 #include <linux/timer.h>
 138 #include <linux/interrupt.h>
 139 #include <linux/in.h>
 140 #include <linux/delay.h>
 141 #include <linux/ethtool.h>
 142 #include <linux/netdevice.h>
 143 #include <linux/etherdevice.h>
 144 #include <linux/skbuff.h>
 145 #include <linux/if_arp.h>
 146 #include <linux/ioport.h>
 147 #include <linux/bitops.h>
 148
 149 #include <pcmcia/cs_types.h>
 150 #include <pcmcia/cs.h>
 151 #include <pcmcia/cisreg.h>
 152 #include <pcmcia/cistpl.h>
 153 #include <pcmcia/ds.h>
 154
 155 #include <asm/uaccess.h>
 156 #include <asm/io.h>
 157 #include <asm/system.h>
 158
 159 /* ----------------------------------------------------------------------------
 160 Defines
 161 ---------------------------------------------------------------------------- */
 162
 163 #define ETHER_ADDR_LEN                  ETH_ALEN
 164                                         /* 6 bytes in an Ethernet Address */
 165 #define MACE_LADRF_LEN                  8
 166                                         /* 8 bytes in Logical Address Filter */
 167
 168 /* Loop Control Defines */
 169 #define MACE_MAX_IR_ITERATIONS          10
 170 #define MACE_MAX_RX_ITERATIONS          12
 171         /*
 172         TBD: Dean brought this up, and I assumed the hardware would
 173         handle it:
 174
 175         If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
 176         non-zero when the isr exits.  We may not get another interrupt
 177         to process the remaining packets for some time.
 178         */
 179
 180 /*
 181 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
 182 which manages the interface between the MACE and the PCMCIA bus.  It
 183 also includes buffer management for the 32K x 8 SRAM to control up to
 184 four transmit and 12 receive frames at a time.
 185 */
 186 #define AM2150_MAX_TX_FRAMES            4
 187 #define AM2150_MAX_RX_FRAMES            12
 188
 189 /* Am2150 Ethernet Card I/O Mapping */
 190 #define AM2150_RCV                      0x00
 191 #define AM2150_XMT                      0x04
 192 #define AM2150_XMT_SKIP                 0x09
 193 #define AM2150_RCV_NEXT                 0x0A
 194 #define AM2150_RCV_FRAME_COUNT          0x0B
 195 #define AM2150_MACE_BANK                0x0C
 196 #define AM2150_MACE_BASE                0x10
 197
 198 /* MACE Registers */
 199 #define MACE_RCVFIFO                    0
 200 #define MACE_XMTFIFO                    1
 201 #define MACE_XMTFC                      2
 202 #define MACE_XMTFS                      3
 203 #define MACE_XMTRC                      4
 204 #define MACE_RCVFC                      5
 205 #define MACE_RCVFS                      6
 206 #define MACE_FIFOFC                     7
 207 #define MACE_IR                         8
 208 #define MACE_IMR                        9
 209 #define MACE_PR                         10
 210 #define MACE_BIUCC                      11
 211 #define MACE_FIFOCC                     12
 212 #define MACE_MACCC                      13
 213 #define MACE_PLSCC                      14
 214 #define MACE_PHYCC                      15
 215 #define MACE_CHIPIDL                    16
 216 #define MACE_CHIPIDH                    17
 217 #define MACE_IAC                        18
 218 /* Reserved */
 219 #define MACE_LADRF                      20
 220 #define MACE_PADR                       21
 221 /* Reserved */
 222 /* Reserved */
 223 #define MACE_MPC                        24
 224 /* Reserved */
 225 #define MACE_RNTPC                      26
 226 #define MACE_RCVCC                      27
 227 /* Reserved */
 228 #define MACE_UTR                        29
 229 #define MACE_RTR1                       30
 230 #define MACE_RTR2                       31
 231
 232 /* MACE Bit Masks */
 233 #define MACE_XMTRC_EXDEF                0x80
 234 #define MACE_XMTRC_XMTRC                0x0F
 235
 236 #define MACE_XMTFS_XMTSV                0x80
 237 #define MACE_XMTFS_UFLO                 0x40
 238 #define MACE_XMTFS_LCOL                 0x20
 239 #define MACE_XMTFS_MORE                 0x10
 240 #define MACE_XMTFS_ONE                  0x08
 241 #define MACE_XMTFS_DEFER                0x04
 242 #define MACE_XMTFS_LCAR                 0x02
 243 #define MACE_XMTFS_RTRY                 0x01
 244
 245 #define MACE_RCVFS_RCVSTS               0xF000
 246 #define MACE_RCVFS_OFLO                 0x8000
 247 #define MACE_RCVFS_CLSN                 0x4000
 248 #define MACE_RCVFS_FRAM                 0x2000
 249 #define MACE_RCVFS_FCS                  0x1000
 250
 251 #define MACE_FIFOFC_RCVFC               0xF0
 252 #define MACE_FIFOFC_XMTFC               0x0F
 253
 254 #define MACE_IR_JAB                     0x80
 255 #define MACE_IR_BABL                    0x40
 256 #define MACE_IR_CERR                    0x20
 257 #define MACE_IR_RCVCCO                  0x10
 258 #define MACE_IR_RNTPCO                  0x08
 259 #define MACE_IR_MPCO                    0x04
 260 #define MACE_IR_RCVINT                  0x02
 261 #define MACE_IR_XMTINT                  0x01
 262
 263 #define MACE_MACCC_PROM                 0x80
 264 #define MACE_MACCC_DXMT2PD              0x40
 265 #define MACE_MACCC_EMBA                 0x20
 266 #define MACE_MACCC_RESERVED             0x10
 267 #define MACE_MACCC_DRCVPA               0x08
 268 #define MACE_MACCC_DRCVBC               0x04
 269 #define MACE_MACCC_ENXMT                0x02
 270 #define MACE_MACCC_ENRCV                0x01
 271
 272 #define MACE_PHYCC_LNKFL                0x80
 273 #define MACE_PHYCC_DLNKTST              0x40
 274 #define MACE_PHYCC_REVPOL               0x20
 275 #define MACE_PHYCC_DAPC                 0x10
 276 #define MACE_PHYCC_LRT                  0x08
 277 #define MACE_PHYCC_ASEL                 0x04
 278 #define MACE_PHYCC_RWAKE                0x02
 279 #define MACE_PHYCC_AWAKE                0x01
 280
 281 #define MACE_IAC_ADDRCHG                0x80
 282 #define MACE_IAC_PHYADDR                0x04
 283 #define MACE_IAC_LOGADDR                0x02
 284
 285 #define MACE_UTR_RTRE                   0x80
 286 #define MACE_UTR_RTRD                   0x40
 287 #define MACE_UTR_RPA                    0x20
 288 #define MACE_UTR_FCOLL                  0x10
 289 #define MACE_UTR_RCVFCSE                0x08
 290 #define MACE_UTR_LOOP_INCL_MENDEC       0x06
 291 #define MACE_UTR_LOOP_NO_MENDEC         0x04
 292 #define MACE_UTR_LOOP_EXTERNAL          0x02
 293 #define MACE_UTR_LOOP_NONE              0x00
 294 #define MACE_UTR_RESERVED               0x01
 295
 296 /* Switch MACE register bank (only 0 and 1 are valid) */
 297 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
 298
 299 #define MACE_IMR_DEFAULT \
 300   (0xFF - \
 301     ( \
 302       MACE_IR_CERR | \
 303       MACE_IR_RCVCCO | \
 304       MACE_IR_RNTPCO | \
 305       MACE_IR_MPCO | \
 306       MACE_IR_RCVINT | \
 307       MACE_IR_XMTINT \
 308     ) \
 309   )
 310 #undef MACE_IMR_DEFAULT
 311 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
 312
 313 #define TX_TIMEOUT              ((400*HZ)/1000)
 314
 315 /* ----------------------------------------------------------------------------
 316 Type Definitions
 317 ---------------------------------------------------------------------------- */
 318
 319 typedef struct _mace_statistics {
 320     /* MACE_XMTFS */
 321     int xmtsv;
 322     int uflo;
 323     int lcol;
 324     int more;
 325     int one;
 326     int defer;
 327     int lcar;
 328     int rtry;
 329
 330     /* MACE_XMTRC */
 331     int exdef;
 332     int xmtrc;
 333
 334     /* RFS1--Receive Status (RCVSTS) */
 335     int oflo;
 336     int clsn;
 337     int fram;
 338     int fcs;
 339
 340     /* RFS2--Runt Packet Count (RNTPC) */
 341     int rfs_rntpc;
 342
 343     /* RFS3--Receive Collision Count (RCVCC) */
 344     int rfs_rcvcc;
 345
 346     /* MACE_IR */
 347     int jab;
 348     int babl;
 349     int cerr;
 350     int rcvcco;
 351     int rntpco;
 352     int mpco;
 353
 354     /* MACE_MPC */
 355     int mpc;
 356
 357     /* MACE_RNTPC */
 358     int rntpc;
 359
 360     /* MACE_RCVCC */
 361     int rcvcc;
 362 } mace_statistics;
 363
 364 typedef struct _mace_private {
 365     dev_link_t link;
 366     dev_node_t node;
 367     struct net_device_stats linux_stats; /* Linux statistics counters */
 368     mace_statistics mace_stats; /* MACE chip statistics counters */
 369
 370     /* restore_multicast_list() state variables */
 371     int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
 372     int multicast_num_addrs;
 373
 374     char tx_free_frames; /* Number of free transmit frame buffers */
 375     char tx_irq_disabled; /* MACE TX interrupt disabled */
 376
 377     spinlock_t bank_lock; /* Must be held if you step off bank 0 */
 378 } mace_private;
 379
 380 /* ----------------------------------------------------------------------------
 381 Private Global Variables
 382 ---------------------------------------------------------------------------- */
 383
 384 #ifdef PCMCIA_DEBUG
 385 static char rcsid[] =
 386 "nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
 387 static char *version =
 388 DRV_NAME " " DRV_VERSION " (Roger C. Pao)";
 389 #endif
 390
 391 static dev_info_t dev_info="nmclan_cs";
 392 static dev_link_t *dev_list;
 393
 394 static char *if_names[]={
 395     "Auto", "10baseT", "BNC",
 396 };
 397
 398 /* ----------------------------------------------------------------------------
 399 Parameters
 400         These are the parameters that can be set during loading with
 401         'insmod'.
 402 ---------------------------------------------------------------------------- */
 403
 404 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
 405 MODULE_LICENSE("GPL");
 406
 407 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
 408
 409 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
 410 INT_MODULE_PARM(if_port, 0);
 411
 412 #ifdef PCMCIA_DEBUG
 413 INT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);
 414 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
 415 #else
 416 #define DEBUG(n, args...)
 417 #endif
 418
 419 /* ----------------------------------------------------------------------------
 420 Function Prototypes
 421 ---------------------------------------------------------------------------- */
 422
 423 static void nmclan_config(dev_link_t *link);
 424 static void nmclan_release(dev_link_t *link);
 425 static int nmclan_event(event_t event, int priority,
 426                         event_callback_args_t *args);
 427
 428 static void nmclan_reset(struct net_device *dev);
 429 static int mace_config(struct net_device *dev, struct ifmap *map);
 430 static int mace_open(struct net_device *dev);
 431 static int mace_close(struct net_device *dev);
 432 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);
 433 static void mace_tx_timeout(struct net_device *dev);
 434 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 435 static struct net_device_stats *mace_get_stats(struct net_device *dev);
 436 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
 437 static void restore_multicast_list(struct net_device *dev);
 438 static void set_multicast_list(struct net_device *dev);
 439 static struct ethtool_ops netdev_ethtool_ops;
 440
 441
 442 static dev_link_t *nmclan_attach(void);
 443 static void nmclan_detach(struct pcmcia_device *p_dev);
 444
 445 /* ----------------------------------------------------------------------------
 446 nmclan_attach
 447         Creates an "instance" of the driver, allocating local data
 448         structures for one device.  The device is registered with Card
 449         Services.
 450 ---------------------------------------------------------------------------- */
 451
 452 static dev_link_t *nmclan_attach(void)
 453 {
 454     mace_private *lp;
 455     dev_link_t *link;
 456     struct net_device *dev;
 457     client_reg_t client_reg;
 458     int ret;
 459
 460     DEBUG(0, "nmclan_attach()\n");
 461     DEBUG(1, "%s\n", rcsid);
 462
 463     /* Create new ethernet device */
 464     dev = alloc_etherdev(sizeof(mace_private));
 465     if (!dev)
 466         return NULL;
 467     lp = netdev_priv(dev);
 468     link = &lp->link;
 469     link->priv = dev;
 470
 471     spin_lock_init(&lp->bank_lock);
 472     link->io.NumPorts1 = 32;
 473     link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
 474     link->io.IOAddrLines = 5;
 475     link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
 476     link->irq.IRQInfo1 = IRQ_LEVEL_ID;
 477     link->irq.Handler = &mace_interrupt;
 478     link->irq.Instance = dev;
 479     link->conf.Attributes = CONF_ENABLE_IRQ;
 480     link->conf.Vcc = 50;
 481     link->conf.IntType = INT_MEMORY_AND_IO;
 482     link->conf.ConfigIndex = 1;
 483     link->conf.Present = PRESENT_OPTION;
 484
 485     lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 486
 487     SET_MODULE_OWNER(dev);
 488     dev->hard_start_xmit = &mace_start_xmit;
 489     dev->set_config = &mace_config;
 490     dev->get_stats = &mace_get_stats;
 491     dev->set_multicast_list = &set_multicast_list;
 492     SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
 493     dev->open = &mace_open;
 494     dev->stop = &mace_close;
 495 #ifdef HAVE_TX_TIMEOUT
 496     dev->tx_timeout = mace_tx_timeout;
 497     dev->watchdog_timeo = TX_TIMEOUT;
 498 #endif
 499
 500     /* Register with Card Services */
 501     link->next = dev_list;
 502     dev_list = link;
 503     client_reg.dev_info = &dev_info;
 504     client_reg.Version = 0x0210;
 505     client_reg.event_callback_args.client_data = link;
 506     ret = pcmcia_register_client(&link->handle, &client_reg);
 507     if (ret != 0) {
 508         cs_error(link->handle, RegisterClient, ret);
 509         nmclan_detach(link->handle);
 510         return NULL;
 511     }
 512
 513     return link;
 514 } /* nmclan_attach */
 515
 516 /* ----------------------------------------------------------------------------
 517 nmclan_detach
 518         This deletes a driver "instance".  The device is de-registered
 519         with Card Services.  If it has been released, all local data
 520         structures are freed.  Otherwise, the structures will be freed
 521         when the device is released.
 522 ---------------------------------------------------------------------------- */
 523
 524 static void nmclan_detach(struct pcmcia_device *p_dev)
 525 {
 526     dev_link_t *link = dev_to_instance(p_dev);
 527     struct net_device *dev = link->priv;
 528     dev_link_t **linkp;
 529
 530     DEBUG(0, "nmclan_detach(0x%p)\n", link);
 531
 532     /* Locate device structure */
 533     for (linkp = &dev_list; *linkp; linkp = &(*linkp)->next)
 534         if (*linkp == link) break;
 535     if (*linkp == NULL)
 536         return;
 537
 538     if (link->dev)
 539         unregister_netdev(dev);
 540
 541     if (link->state & DEV_CONFIG)
 542         nmclan_release(link);
 543
 544     /* Unlink device structure, free bits */
 545     *linkp = link->next;
 546     free_netdev(dev);
 547 } /* nmclan_detach */
 548
 549 /* ----------------------------------------------------------------------------
 550 mace_read
 551         Reads a MACE register.  This is bank independent; however, the
 552         caller must ensure that this call is not interruptable.  We are
 553         assuming that during normal operation, the MACE is always in
 554         bank 0.
 555 ---------------------------------------------------------------------------- */
 556 static int mace_read(mace_private *lp, kio_addr_t ioaddr, int reg)
 557 {
 558   int data = 0xFF;
 559   unsigned long flags;
 560
 561   switch (reg >> 4) {
 562     case 0: /* register 0-15 */
 563       data = inb(ioaddr + AM2150_MACE_BASE + reg);
 564       break;
 565     case 1: /* register 16-31 */
 566       spin_lock_irqsave(&lp->bank_lock, flags);
 567       MACEBANK(1);
 568       data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 569       MACEBANK(0);
 570       spin_unlock_irqrestore(&lp->bank_lock, flags);
 571       break;
 572   }
 573   return (data & 0xFF);
 574 } /* mace_read */
 575
 576 /* ----------------------------------------------------------------------------
 577 mace_write
 578         Writes to a MACE register.  This is bank independent; however,
 579         the caller must ensure that this call is not interruptable.  We
 580         are assuming that during normal operation, the MACE is always in
 581         bank 0.
 582 ---------------------------------------------------------------------------- */
 583 static void mace_write(mace_private *lp, kio_addr_t ioaddr, int reg, int data)
 584 {
 585   unsigned long flags;
 586
 587   switch (reg >> 4) {
 588     case 0: /* register 0-15 */
 589       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
 590       break;
 591     case 1: /* register 16-31 */
 592       spin_lock_irqsave(&lp->bank_lock, flags);
 593       MACEBANK(1);
 594       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 595       MACEBANK(0);
 596       spin_unlock_irqrestore(&lp->bank_lock, flags);
 597       break;
 598   }
 599 } /* mace_write */
 600
 601 /* ----------------------------------------------------------------------------
 602 mace_init
 603         Resets the MACE chip.
 604 ---------------------------------------------------------------------------- */
 605 static int mace_init(mace_private *lp, kio_addr_t ioaddr, char *enet_addr)
 606 {
 607   int i;
 608   int ct = 0;
 609
 610   /* MACE Software reset */
 611   mace_write(lp, ioaddr, MACE_BIUCC, 1);
 612   while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
 613     /* Wait for reset bit to be cleared automatically after <= 200ns */;
 614     if(++ct > 500)
 615     {
 616         printk(KERN_ERR "mace: reset failed, card removed ?\n");
 617         return -1;
 618     }
 619     udelay(1);
 620   }
 621   mace_write(lp, ioaddr, MACE_BIUCC, 0);
 622
 623   /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
 624   mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
 625
 626   mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
 627   mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
 628
 629   /*
 630    * Bit 2-1 PORTSEL[1-0] Port Select.
 631    * 00 AUI/10Base-2
 632    * 01 10Base-T
 633    * 10 DAI Port (reserved in Am2150)
 634    * 11 GPSI
 635    * For this card, only the first two are valid.
 636    * So, PLSCC should be set to
 637    * 0x00 for 10Base-2
 638    * 0x02 for 10Base-T
 639    * Or just set ASEL in PHYCC below!
 640    */
 641   switch (if_port) {
 642     case 1:
 643       mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
 644       break;
 645     case 2:
 646       mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
 647       break;
 648     default:
 649       mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
 650       /* ASEL Auto Select.  When set, the PORTSEL[1-0] bits are overridden,
 651          and the MACE device will automatically select the operating media
 652          interface port. */
 653       break;
 654   }
 655
 656   mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
 657   /* Poll ADDRCHG bit */
 658   ct = 0;
 659   while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
 660   {
 661         if(++ ct > 500)
 662         {
 663                 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
 664                 return -1;
 665         }
 666   }
 667   /* Set PADR register */
 668   for (i = 0; i < ETHER_ADDR_LEN; i++)
 669     mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
 670
 671   /* MAC Configuration Control Register should be written last */
 672   /* Let set_multicast_list set this. */
 673   /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
 674   mace_write(lp, ioaddr, MACE_MACCC, 0x00);
 675   return 0;
 676 } /* mace_init */
 677
 678 /* ----------------------------------------------------------------------------
 679 nmclan_config
 680         This routine is scheduled to run after a CARD_INSERTION event
 681         is received, to configure the PCMCIA socket, and to make the
 682         ethernet device available to the system.
 683 ---------------------------------------------------------------------------- */
 684
 685 #define CS_CHECK(fn, ret) \
 686   do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
 687
 688 static void nmclan_config(dev_link_t *link)
 689 {
 690   client_handle_t handle = link->handle;
 691   struct net_device *dev = link->priv;
 692   mace_private *lp = netdev_priv(dev);
 693   tuple_t tuple;
 694   cisparse_t parse;
 695   u_char buf[64];
 696   int i, last_ret, last_fn;
 697   kio_addr_t ioaddr;
 698
 699   DEBUG(0, "nmclan_config(0x%p)\n", link);
 700
 701   tuple.Attributes = 0;
 702   tuple.TupleData = buf;
 703   tuple.TupleDataMax = 64;
 704   tuple.TupleOffset = 0;
 705   tuple.DesiredTuple = CISTPL_CONFIG;
 706   CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
 707   CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
 708   CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
 709   link->conf.ConfigBase = parse.config.base;
 710
 711   /* Configure card */
 712   link->state |= DEV_CONFIG;
 713
 714   CS_CHECK(RequestIO, pcmcia_request_io(handle, &link->io));
 715   CS_CHECK(RequestIRQ, pcmcia_request_irq(handle, &link->irq));
 716   CS_CHECK(RequestConfiguration, pcmcia_request_configuration(handle, &link->conf));
 717   dev->irq = link->irq.AssignedIRQ;
 718   dev->base_addr = link->io.BasePort1;
 719
 720   ioaddr = dev->base_addr;
 721
 722   /* Read the ethernet address from the CIS. */
 723   tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
 724   tuple.TupleData = buf;
 725   tuple.TupleDataMax = 64;
 726   tuple.TupleOffset = 0;
 727   CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
 728   CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
 729   memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
 730
 731   /* Verify configuration by reading the MACE ID. */
 732   {
 733     char sig[2];
 734
 735     sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
 736     sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
 737     if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
 738       DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
 739             sig[0], sig[1]);
 740     } else {
 741       printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
 742              " be 0x40 0x?9\n", sig[0], sig[1]);
 743       link->state &= ~DEV_CONFIG_PENDING;
 744       return;
 745     }
 746   }
 747
 748   if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
 749         goto failed;
 750
 751   /* The if_port symbol can be set when the module is loaded */
 752   if (if_port <= 2)
 753     dev->if_port = if_port;
 754   else
 755     printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
 756
 757   link->dev = &lp->node;
 758   link->state &= ~DEV_CONFIG_PENDING;
 759   SET_NETDEV_DEV(dev, &handle_to_dev(handle));
 760
 761   i = register_netdev(dev);
 762   if (i != 0) {
 763     printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
 764     link->dev = NULL;
 765     goto failed;
 766   }
 767
 768   strcpy(lp->node.dev_name, dev->name);
 769
 770   printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port, hw_addr ",
 771          dev->name, dev->base_addr, dev->irq, if_names[dev->if_port]);
 772   for (i = 0; i < 6; i++)
 773       printk("%02X%s", dev->dev_addr[i], ((i<5) ? ":" : "\n"));
 774   return;
 775
 776 cs_failed:
 777     cs_error(link->handle, last_fn, last_ret);
 778 failed:
 779     nmclan_release(link);
 780     return;
 781
 782 } /* nmclan_config */
 783
 784 /* ----------------------------------------------------------------------------
 785 nmclan_release
 786         After a card is removed, nmclan_release() will unregister the
 787         net device, and release the PCMCIA configuration.  If the device
 788         is still open, this will be postponed until it is closed.
 789 ---------------------------------------------------------------------------- */
 790 static void nmclan_release(dev_link_t *link)
 791 {
 792
 793   DEBUG(0, "nmclan_release(0x%p)\n", link);
 794
 795   pcmcia_release_configuration(link->handle);
 796   pcmcia_release_io(link->handle, &link->io);
 797   pcmcia_release_irq(link->handle, &link->irq);
 798
 799   link->state &= ~DEV_CONFIG;
 800 }
 801
 802 static int nmclan_suspend(struct pcmcia_device *p_dev)
 803 {
 804         dev_link_t *link = dev_to_instance(p_dev);
 805         struct net_device *dev = link->priv;
 806
 807         link->state |= DEV_SUSPEND;
 808         if (link->state & DEV_CONFIG) {
 809                 if (link->open)
 810                         netif_device_detach(dev);
 811                 pcmcia_release_configuration(link->handle);
 812         }
 813
 814
 815         return 0;
 816 }
 817
 818 static int nmclan_resume(struct pcmcia_device *p_dev)
 819 {
 820         dev_link_t *link = dev_to_instance(p_dev);
 821         struct net_device *dev = link->priv;
 822
 823         link->state &= ~DEV_SUSPEND;
 824         if (link->state & DEV_CONFIG) {
 825                 pcmcia_request_configuration(link->handle, &link->conf);
 826                 if (link->open) {
 827                         nmclan_reset(dev);
 828                         netif_device_attach(dev);
 829                 }
 830         }
 831
 832         return 0;
 833 }
 834
 835 /* ----------------------------------------------------------------------------
 836 nmclan_event
 837         The card status event handler.  Mostly, this schedules other
 838         stuff to run after an event is received.  A CARD_REMOVAL event
 839         also sets some flags to discourage the net drivers from trying
 840         to talk to the card any more.
 841 ---------------------------------------------------------------------------- */
 842 static int nmclan_event(event_t event, int priority,
 843                        event_callback_args_t *args)
 844 {
 845   dev_link_t *link = args->client_data;
 846
 847   DEBUG(1, "nmclan_event(0x%06x)\n", event);
 848
 849   switch (event) {
 850     case CS_EVENT_CARD_INSERTION:
 851       link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
 852       nmclan_config(link);
 853       break;
 854     case CS_EVENT_RESET_REQUEST:
 855       return 1;
 856       break;
 857   }
 858   return 0;
 859 } /* nmclan_event */
 860
 861 /* ----------------------------------------------------------------------------
 862 nmclan_reset
 863         Reset and restore all of the Xilinx and MACE registers.
 864 ---------------------------------------------------------------------------- */
 865 static void nmclan_reset(struct net_device *dev)
 866 {
 867   mace_private *lp = netdev_priv(dev);
 868
 869 #if RESET_XILINX
 870   dev_link_t *link = &lp->link;
 871   conf_reg_t reg;
 872   u_long OrigCorValue;
 873
 874   /* Save original COR value */
 875   reg.Function = 0;
 876   reg.Action = CS_READ;
 877   reg.Offset = CISREG_COR;
 878   reg.Value = 0;
 879   pcmcia_access_configuration_register(link->handle, &reg);
 880   OrigCorValue = reg.Value;
 881
 882   /* Reset Xilinx */
 883   reg.Action = CS_WRITE;
 884   reg.Offset = CISREG_COR;
 885   DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
 886         OrigCorValue);
 887   reg.Value = COR_SOFT_RESET;
 888   pcmcia_access_configuration_register(link->handle, &reg);
 889   /* Need to wait for 20 ms for PCMCIA to finish reset. */
 890
 891   /* Restore original COR configuration index */
 892   reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
 893   pcmcia_access_configuration_register(link->handle, &reg);
 894   /* Xilinx is now completely reset along with the MACE chip. */
 895   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 896
 897 #endif /* #if RESET_XILINX */
 898
 899   /* Xilinx is now completely reset along with the MACE chip. */
 900   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 901
 902   /* Reinitialize the MACE chip for operation. */
 903   mace_init(lp, dev->base_addr, dev->dev_addr);
 904   mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
 905
 906   /* Restore the multicast list and enable TX and RX. */
 907   restore_multicast_list(dev);
 908 } /* nmclan_reset */
 909
 910 /* ----------------------------------------------------------------------------
 911 mace_config
 912         [Someone tell me what this is supposed to do?  Is if_port a defined
 913         standard?  If so, there should be defines to indicate 1=10Base-T,
 914         2=10Base-2, etc. including limited automatic detection.]
 915 ---------------------------------------------------------------------------- */
 916 static int mace_config(struct net_device *dev, struct ifmap *map)
 917 {
 918   if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
 919     if (map->port <= 2) {
 920       dev->if_port = map->port;
 921       printk(KERN_INFO "%s: switched to %s port\n", dev->name,
 922              if_names[dev->if_port]);
 923     } else
 924       return -EINVAL;
 925   }
 926   return 0;
 927 } /* mace_config */
 928
 929 /* ----------------------------------------------------------------------------
 930 mace_open
 931         Open device driver.
 932 ---------------------------------------------------------------------------- */
 933 static int mace_open(struct net_device *dev)
 934 {
 935   kio_addr_t ioaddr = dev->base_addr;
 936   mace_private *lp = netdev_priv(dev);
 937   dev_link_t *link = &lp->link;
 938
 939   if (!DEV_OK(link))
 940     return -ENODEV;
 941
 942   link->open++;
 943
 944   MACEBANK(0);
 945
 946   netif_start_queue(dev);
 947   nmclan_reset(dev);
 948
 949   return 0; /* Always succeed */
 950 } /* mace_open */
 951
 952 /* ----------------------------------------------------------------------------
 953 mace_close
 954         Closes device driver.
 955 ---------------------------------------------------------------------------- */
 956 static int mace_close(struct net_device *dev)
 957 {
 958   kio_addr_t ioaddr = dev->base_addr;
 959   mace_private *lp = netdev_priv(dev);
 960   dev_link_t *link = &lp->link;
 961
 962   DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
 963
 964   /* Mask off all interrupts from the MACE chip. */
 965   outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
 966
 967   link->open--;
 968   netif_stop_queue(dev);
 969
 970   return 0;
 971 } /* mace_close */
 972
 973 static void netdev_get_drvinfo(struct net_device *dev,
 974                                struct ethtool_drvinfo *info)
 975 {
 976         strcpy(info->driver, DRV_NAME);
 977         strcpy(info->version, DRV_VERSION);
 978         sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
 979 }
 980
 981 #ifdef PCMCIA_DEBUG
 982 static u32 netdev_get_msglevel(struct net_device *dev)
 983 {
 984         return pc_debug;
 985 }
 986
 987 static void netdev_set_msglevel(struct net_device *dev, u32 level)
 988 {
 989         pc_debug = level;
 990 }
 991 #endif /* PCMCIA_DEBUG */
 992
 993 static struct ethtool_ops netdev_ethtool_ops = {
 994         .get_drvinfo            = netdev_get_drvinfo,
 995 #ifdef PCMCIA_DEBUG
 996         .get_msglevel           = netdev_get_msglevel,
 997         .set_msglevel           = netdev_set_msglevel,
 998 #endif /* PCMCIA_DEBUG */
 999 };
1000
1001 /* ----------------------------------------------------------------------------
1002 mace_start_xmit
1003         This routine begins the packet transmit function.  When completed,
1004         it will generate a transmit interrupt.
1005
1006         According to /usr/src/linux/net/inet/dev.c, if _start_xmit
1007         returns 0, the "packet is now solely the responsibility of the
1008         driver."  If _start_xmit returns non-zero, the "transmission
1009         failed, put skb back into a list."
1010 ---------------------------------------------------------------------------- */
1011
1012 static void mace_tx_timeout(struct net_device *dev)
1013 {
1014   mace_private *lp = netdev_priv(dev);
1015   dev_link_t *link = &lp->link;
1016
1017   printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
1018 #if RESET_ON_TIMEOUT
1019   printk("resetting card\n");
1020   pcmcia_reset_card(link->handle, NULL);
1021 #else /* #if RESET_ON_TIMEOUT */
1022   printk("NOT resetting card\n");
1023 #endif /* #if RESET_ON_TIMEOUT */
1024   dev->trans_start = jiffies;
1025   netif_wake_queue(dev);
1026 }
1027
1028 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
1029 {
1030   mace_private *lp = netdev_priv(dev);
1031   kio_addr_t ioaddr = dev->base_addr;
1032
1033   netif_stop_queue(dev);
1034
1035   DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
1036         dev->name, (long)skb->len);
1037
1038 #if (!TX_INTERRUPTABLE)
1039   /* Disable MACE TX interrupts. */
1040   outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
1041     ioaddr + AM2150_MACE_BASE + MACE_IMR);
1042   lp->tx_irq_disabled=1;
1043 #endif /* #if (!TX_INTERRUPTABLE) */
1044
1045   {
1046     /* This block must not be interrupted by another transmit request!
1047        mace_tx_timeout will take care of timer-based retransmissions from
1048        the upper layers.  The interrupt handler is guaranteed never to
1049        service a transmit interrupt while we are in here.
1050     */
1051
1052     lp->linux_stats.tx_bytes += skb->len;
1053     lp->tx_free_frames--;
1054
1055     /* WARNING: Write the _exact_ number of bytes written in the header! */
1056     /* Put out the word header [must be an outw()] . . . */
1057     outw(skb->len, ioaddr + AM2150_XMT);
1058     /* . . . and the packet [may be any combination of outw() and outb()] */
1059     outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
1060     if (skb->len & 1) {
1061       /* Odd byte transfer */
1062       outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
1063     }
1064
1065     dev->trans_start = jiffies;
1066
1067 #if MULTI_TX
1068     if (lp->tx_free_frames > 0)
1069       netif_start_queue(dev);
1070 #endif /* #if MULTI_TX */
1071   }
1072
1073 #if (!TX_INTERRUPTABLE)
1074   /* Re-enable MACE TX interrupts. */
1075   lp->tx_irq_disabled=0;
1076   outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
1077 #endif /* #if (!TX_INTERRUPTABLE) */
1078
1079   dev_kfree_skb(skb);
1080
1081   return 0;
1082 } /* mace_start_xmit */
1083
1084 /* ----------------------------------------------------------------------------
1085 mace_interrupt
1086         The interrupt handler.
1087 ---------------------------------------------------------------------------- */
1088 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1089 {
1090   struct net_device *dev = (struct net_device *) dev_id;
1091   mace_private *lp = netdev_priv(dev);
1092   kio_addr_t ioaddr = dev->base_addr;
1093   int status;
1094   int IntrCnt = MACE_MAX_IR_ITERATIONS;
1095
1096   if (dev == NULL) {
1097     DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1098           irq);
1099     return IRQ_NONE;
1100   }
1101
1102   if (lp->tx_irq_disabled) {
1103     printk(
1104       (lp->tx_irq_disabled?
1105        KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1106        "[isr=%02X, imr=%02X]\n":
1107        KERN_NOTICE "%s: Re-entering the interrupt handler "
1108        "[isr=%02X, imr=%02X]\n"),
1109       dev->name,
1110       inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1111       inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1112     );
1113     /* WARNING: MACE_IR has been read! */
1114     return IRQ_NONE;
1115   }
1116
1117   if (!netif_device_present(dev)) {
1118     DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1119     return IRQ_NONE;
1120   }
1121
1122   do {
1123     /* WARNING: MACE_IR is a READ/CLEAR port! */
1124     status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1125
1126     DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1127
1128     if (status & MACE_IR_RCVINT) {
1129       mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1130     }
1131
1132     if (status & MACE_IR_XMTINT) {
1133       unsigned char fifofc;
1134       unsigned char xmtrc;
1135       unsigned char xmtfs;
1136
1137       fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1138       if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1139         lp->linux_stats.tx_errors++;
1140         outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1141       }
1142
1143       /* Transmit Retry Count (XMTRC, reg 4) */
1144       xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1145       if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1146       lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1147
1148       if (
1149         (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1150         MACE_XMTFS_XMTSV /* Transmit Status Valid */
1151       ) {
1152         lp->mace_stats.xmtsv++;
1153
1154         if (xmtfs & ~MACE_XMTFS_XMTSV) {
1155           if (xmtfs & MACE_XMTFS_UFLO) {
1156             /* Underflow.  Indicates that the Transmit FIFO emptied before
1157                the end of frame was reached. */
1158             lp->mace_stats.uflo++;
1159           }
1160           if (xmtfs & MACE_XMTFS_LCOL) {
1161             /* Late Collision */
1162             lp->mace_stats.lcol++;
1163           }
1164           if (xmtfs & MACE_XMTFS_MORE) {
1165             /* MORE than one retry was needed */
1166             lp->mace_stats.more++;
1167           }
1168           if (xmtfs & MACE_XMTFS_ONE) {
1169             /* Exactly ONE retry occurred */
1170             lp->mace_stats.one++;
1171           }
1172           if (xmtfs & MACE_XMTFS_DEFER) {
1173             /* Transmission was defered */
1174             lp->mace_stats.defer++;
1175           }
1176           if (xmtfs & MACE_XMTFS_LCAR) {
1177             /* Loss of carrier */
1178             lp->mace_stats.lcar++;
1179           }
1180           if (xmtfs & MACE_XMTFS_RTRY) {
1181             /* Retry error: transmit aborted after 16 attempts */
1182             lp->mace_stats.rtry++;
1183           }
1184         } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1185
1186       } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1187
1188       lp->linux_stats.tx_packets++;
1189       lp->tx_free_frames++;
1190       netif_wake_queue(dev);
1191     } /* if (status & MACE_IR_XMTINT) */
1192
1193     if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1194       if (status & MACE_IR_JAB) {
1195         /* Jabber Error.  Excessive transmit duration (20-150ms). */
1196         lp->mace_stats.jab++;
1197       }
1198       if (status & MACE_IR_BABL) {
1199         /* Babble Error.  >1518 bytes transmitted. */
1200         lp->mace_stats.babl++;
1201       }
1202       if (status & MACE_IR_CERR) {
1203         /* Collision Error.  CERR indicates the absence of the
1204            Signal Quality Error Test message after a packet
1205            transmission. */
1206         lp->mace_stats.cerr++;
1207       }
1208       if (status & MACE_IR_RCVCCO) {
1209         /* Receive Collision Count Overflow; */
1210         lp->mace_stats.rcvcco++;
1211       }
1212       if (status & MACE_IR_RNTPCO) {
1213         /* Runt Packet Count Overflow */
1214         lp->mace_stats.rntpco++;
1215       }
1216       if (status & MACE_IR_MPCO) {
1217         /* Missed Packet Count Overflow */
1218         lp->mace_stats.mpco++;
1219       }
1220     } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1221
1222   } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1223
1224   return IRQ_HANDLED;
1225 } /* mace_interrupt */
1226
1227 /* ----------------------------------------------------------------------------
1228 mace_rx
1229         Receives packets.
1230 ---------------------------------------------------------------------------- */
1231 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1232 {
1233   mace_private *lp = netdev_priv(dev);
1234   kio_addr_t ioaddr = dev->base_addr;
1235   unsigned char rx_framecnt;
1236   unsigned short rx_status;
1237
1238   while (
1239     ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1240     (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1241     (RxCnt--)
1242   ) {
1243     rx_status = inw(ioaddr + AM2150_RCV);
1244
1245     DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1246           " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1247
1248     if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1249       lp->linux_stats.rx_errors++;
1250       if (rx_status & MACE_RCVFS_OFLO) {
1251         lp->mace_stats.oflo++;
1252       }
1253       if (rx_status & MACE_RCVFS_CLSN) {
1254         lp->mace_stats.clsn++;
1255       }
1256       if (rx_status & MACE_RCVFS_FRAM) {
1257         lp->mace_stats.fram++;
1258       }
1259       if (rx_status & MACE_RCVFS_FCS) {
1260         lp->mace_stats.fcs++;
1261       }
1262     } else {
1263       short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1264         /* Auto Strip is off, always subtract 4 */
1265       struct sk_buff *skb;
1266
1267       lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1268         /* runt packet count */
1269       lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1270         /* rcv collision count */
1271
1272       DEBUG(3, "    receiving packet size 0x%X rx_status"
1273             " 0x%X.\n", pkt_len, rx_status);
1274
1275       skb = dev_alloc_skb(pkt_len+2);
1276
1277       if (skb != NULL) {
1278         skb->dev = dev;
1279
1280         skb_reserve(skb, 2);
1281         insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1282         if (pkt_len & 1)
1283             *(skb->tail-1) = inb(ioaddr + AM2150_RCV);
1284         skb->protocol = eth_type_trans(skb, dev);
1285
1286         netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1287
1288         dev->last_rx = jiffies;
1289         lp->linux_stats.rx_packets++;
1290         lp->linux_stats.rx_bytes += skb->len;
1291         outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1292         continue;
1293       } else {
1294         DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1295               " %d.\n", dev->name, pkt_len);
1296         lp->linux_stats.rx_dropped++;
1297       }
1298     }
1299     outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1300   } /* while */
1301
1302   return 0;
1303 } /* mace_rx */
1304
1305 /* ----------------------------------------------------------------------------
1306 pr_linux_stats
1307 ---------------------------------------------------------------------------- */
1308 static void pr_linux_stats(struct net_device_stats *pstats)
1309 {
1310   DEBUG(2, "pr_linux_stats\n");
1311   DEBUG(2, " rx_packets=%-7ld        tx_packets=%ld\n",
1312         (long)pstats->rx_packets, (long)pstats->tx_packets);
1313   DEBUG(2, " rx_errors=%-7ld         tx_errors=%ld\n",
1314         (long)pstats->rx_errors, (long)pstats->tx_errors);
1315   DEBUG(2, " rx_dropped=%-7ld        tx_dropped=%ld\n",
1316         (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1317   DEBUG(2, " multicast=%-7ld         collisions=%ld\n",
1318         (long)pstats->multicast, (long)pstats->collisions);
1319
1320   DEBUG(2, " rx_length_errors=%-7ld  rx_over_errors=%ld\n",
1321         (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1322   DEBUG(2, " rx_crc_errors=%-7ld     rx_frame_errors=%ld\n",
1323         (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1324   DEBUG(2, " rx_fifo_errors=%-7ld    rx_missed_errors=%ld\n",
1325         (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1326
1327   DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1328         (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1329   DEBUG(2, " tx_fifo_errors=%-7ld    tx_heartbeat_errors=%ld\n",
1330         (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1331   DEBUG(2, " tx_window_errors=%ld\n",
1332         (long)pstats->tx_window_errors);
1333 } /* pr_linux_stats */
1334
1335 /* ----------------------------------------------------------------------------
1336 pr_mace_stats
1337 ---------------------------------------------------------------------------- */
1338 static void pr_mace_stats(mace_statistics *pstats)
1339 {
1340   DEBUG(2, "pr_mace_stats\n");
1341
1342   DEBUG(2, " xmtsv=%-7d             uflo=%d\n",
1343         pstats->xmtsv, pstats->uflo);
1344   DEBUG(2, " lcol=%-7d              more=%d\n",
1345         pstats->lcol, pstats->more);
1346   DEBUG(2, " one=%-7d               defer=%d\n",
1347         pstats->one, pstats->defer);
1348   DEBUG(2, " lcar=%-7d              rtry=%d\n",
1349         pstats->lcar, pstats->rtry);
1350
1351   /* MACE_XMTRC */
1352   DEBUG(2, " exdef=%-7d             xmtrc=%d\n",
1353         pstats->exdef, pstats->xmtrc);
1354
1355   /* RFS1--Receive Status (RCVSTS) */
1356   DEBUG(2, " oflo=%-7d              clsn=%d\n",
1357         pstats->oflo, pstats->clsn);
1358   DEBUG(2, " fram=%-7d              fcs=%d\n",
1359         pstats->fram, pstats->fcs);
1360
1361   /* RFS2--Runt Packet Count (RNTPC) */
1362   /* RFS3--Receive Collision Count (RCVCC) */
1363   DEBUG(2, " rfs_rntpc=%-7d         rfs_rcvcc=%d\n",
1364         pstats->rfs_rntpc, pstats->rfs_rcvcc);
1365
1366   /* MACE_IR */
1367   DEBUG(2, " jab=%-7d               babl=%d\n",
1368         pstats->jab, pstats->babl);
1369   DEBUG(2, " cerr=%-7d              rcvcco=%d\n",
1370         pstats->cerr, pstats->rcvcco);
1371   DEBUG(2, " rntpco=%-7d            mpco=%d\n",
1372         pstats->rntpco, pstats->mpco);
1373
1374   /* MACE_MPC */
1375   DEBUG(2, " mpc=%d\n", pstats->mpc);
1376
1377   /* MACE_RNTPC */
1378   DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1379
1380   /* MACE_RCVCC */
1381   DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1382
1383 } /* pr_mace_stats */
1384
1385 /* ----------------------------------------------------------------------------
1386 update_stats
1387         Update statistics.  We change to register window 1, so this
1388         should be run single-threaded if the device is active. This is
1389         expected to be a rare operation, and it's simpler for the rest
1390         of the driver to assume that window 0 is always valid rather
1391         than use a special window-state variable.
1392
1393         oflo & uflo should _never_ occur since it would mean the Xilinx
1394         was not able to transfer data between the MACE FIFO and the
1395         card's SRAM fast enough.  If this happens, something is
1396         seriously wrong with the hardware.
1397 ---------------------------------------------------------------------------- */
1398 static void update_stats(kio_addr_t ioaddr, struct net_device *dev)
1399 {
1400   mace_private *lp = netdev_priv(dev);
1401
1402   lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1403   lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1404   lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1405   /* At this point, mace_stats is fully updated for this call.
1406      We may now update the linux_stats. */
1407
1408   /* The MACE has no equivalent for linux_stats field which are commented
1409      out. */
1410
1411   /* lp->linux_stats.multicast; */
1412   lp->linux_stats.collisions =
1413     lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1414     /* Collision: The MACE may retry sending a packet 15 times
1415        before giving up.  The retry count is in XMTRC.
1416        Does each retry constitute a collision?
1417        If so, why doesn't the RCVCC record these collisions? */
1418
1419   /* detailed rx_errors: */
1420   lp->linux_stats.rx_length_errors =
1421     lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1422   /* lp->linux_stats.rx_over_errors */
1423   lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1424   lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1425   lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1426   lp->linux_stats.rx_missed_errors =
1427     lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1428
1429   /* detailed tx_errors */
1430   lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1431   lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1432     /* LCAR usually results from bad cabling. */
1433   lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1434   lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1435   /* lp->linux_stats.tx_window_errors; */
1436
1437   return;
1438 } /* update_stats */
1439
1440 /* ----------------------------------------------------------------------------
1441 mace_get_stats
1442         Gathers ethernet statistics from the MACE chip.
1443 ---------------------------------------------------------------------------- */
1444 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1445 {
1446   mace_private *lp = netdev_priv(dev);
1447
1448   update_stats(dev->base_addr, dev);
1449
1450   DEBUG(1, "%s: updating the statistics.\n", dev->name);
1451   pr_linux_stats(&lp->linux_stats);
1452   pr_mace_stats(&lp->mace_stats);
1453
1454   return &lp->linux_stats;
1455 } /* net_device_stats */
1456
1457 /* ----------------------------------------------------------------------------
1458 updateCRC
1459         Modified from Am79C90 data sheet.
1460 ---------------------------------------------------------------------------- */
1461
1462 #ifdef BROKEN_MULTICAST
1463
1464 static void updateCRC(int *CRC, int bit)
1465 {
1466   int poly[]={
1467     1,1,1,0, 1,1,0,1,
1468     1,0,1,1, 1,0,0,0,
1469     1,0,0,0, 0,0,1,1,
1470     0,0,1,0, 0,0,0,0
1471   }; /* CRC polynomial.  poly[n] = coefficient of the x**n term of the
1472         CRC generator polynomial. */
1473
1474   int j;
1475
1476   /* shift CRC and control bit (CRC[32]) */
1477   for (j = 32; j > 0; j--)
1478     CRC[j] = CRC[j-1];
1479   CRC[0] = 0;
1480
1481   /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1482   if (bit ^ CRC[32])
1483     for (j = 0; j < 32; j++)
1484       CRC[j] ^= poly[j];
1485 } /* updateCRC */
1486
1487 /* ----------------------------------------------------------------------------
1488 BuildLAF
1489         Build logical address filter.
1490         Modified from Am79C90 data sheet.
1491
1492 Input
1493         ladrf: logical address filter (contents initialized to 0)
1494         adr: ethernet address
1495 ---------------------------------------------------------------------------- */
1496 static void BuildLAF(int *ladrf, int *adr)
1497 {
1498   int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1499
1500   int i, byte; /* temporary array indices */
1501   int hashcode; /* the output object */
1502
1503   CRC[32]=0;
1504
1505   for (byte = 0; byte < 6; byte++)
1506     for (i = 0; i < 8; i++)
1507       updateCRC(CRC, (adr[byte] >> i) & 1);
1508
1509   hashcode = 0;
1510   for (i = 0; i < 6; i++)
1511     hashcode = (hashcode << 1) + CRC[i];
1512
1513   byte = hashcode >> 3;
1514   ladrf[byte] |= (1 << (hashcode & 7));
1515
1516 #ifdef PCMCIA_DEBUG
1517   if (pc_debug > 2) {
1518     printk(KERN_DEBUG "    adr =");
1519     for (i = 0; i < 6; i++)
1520       printk(" %02X", adr[i]);
1521     printk("\n" KERN_DEBUG "    hashcode = %d(decimal), ladrf[0:63]"
1522            " =", hashcode);
1523     for (i = 0; i < 8; i++)
1524       printk(" %02X", ladrf[i]);
1525     printk("\n");
1526   }
1527 #endif
1528 } /* BuildLAF */
1529
1530 /* ----------------------------------------------------------------------------
1531 restore_multicast_list
1532         Restores the multicast filter for MACE chip to the last
1533         set_multicast_list() call.
1534
1535 Input
1536         multicast_num_addrs
1537         multicast_ladrf[]
1538 ---------------------------------------------------------------------------- */
1539 static void restore_multicast_list(struct net_device *dev)
1540 {
1541   mace_private *lp = netdev_priv(dev);
1542   int num_addrs = lp->multicast_num_addrs;
1543   int *ladrf = lp->multicast_ladrf;
1544   kio_addr_t ioaddr = dev->base_addr;
1545   int i;
1546
1547   DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1548         dev->name, num_addrs);
1549
1550   if (num_addrs > 0) {
1551
1552     DEBUG(1, "Attempt to restore multicast list detected.\n");
1553
1554     mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1555     /* Poll ADDRCHG bit */
1556     while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1557       ;
1558     /* Set LADRF register */
1559     for (i = 0; i < MACE_LADRF_LEN; i++)
1560       mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1561
1562     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1563     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1564
1565   } else if (num_addrs < 0) {
1566
1567     /* Promiscuous mode: receive all packets */
1568     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1569     mace_write(lp, ioaddr, MACE_MACCC,
1570       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1571     );
1572
1573   } else {
1574
1575     /* Normal mode */
1576     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1577     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1578
1579   }
1580 } /* restore_multicast_list */
1581
1582 /* ----------------------------------------------------------------------------
1583 set_multicast_list
1584         Set or clear the multicast filter for this adaptor.
1585
1586 Input
1587         num_addrs == -1 Promiscuous mode, receive all packets
1588         num_addrs == 0  Normal mode, clear multicast list
1589         num_addrs > 0   Multicast mode, receive normal and MC packets, and do
1590                         best-effort filtering.
1591 Output
1592         multicast_num_addrs
1593         multicast_ladrf[]
1594 ---------------------------------------------------------------------------- */
1595
1596 static void set_multicast_list(struct net_device *dev)
1597 {
1598   mace_private *lp = netdev_priv(dev);
1599   int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1600   int i;
1601   struct dev_mc_list *dmi = dev->mc_list;
1602
1603 #ifdef PCMCIA_DEBUG
1604   if (pc_debug > 1) {
1605     static int old;
1606     if (dev->mc_count != old) {
1607       old = dev->mc_count;
1608       DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1609             dev->name, old);
1610     }
1611   }
1612 #endif
1613
1614   /* Set multicast_num_addrs. */
1615   lp->multicast_num_addrs = dev->mc_count;
1616
1617   /* Set multicast_ladrf. */
1618   if (num_addrs > 0) {
1619     /* Calculate multicast logical address filter */
1620     memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1621     for (i = 0; i < dev->mc_count; i++) {
1622       memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1623       dmi = dmi->next;
1624       BuildLAF(lp->multicast_ladrf, adr);
1625     }
1626   }
1627
1628   restore_multicast_list(dev);
1629
1630 } /* set_multicast_list */
1631
1632 #endif /* BROKEN_MULTICAST */
1633
1634 static void restore_multicast_list(struct net_device *dev)
1635 {
1636   kio_addr_t ioaddr = dev->base_addr;
1637   mace_private *lp = netdev_priv(dev);
1638
1639   DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1640         lp->multicast_num_addrs);
1641
1642   if (dev->flags & IFF_PROMISC) {
1643     /* Promiscuous mode: receive all packets */
1644     mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1645     mace_write(lp, ioaddr, MACE_MACCC,
1646       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1647     );
1648   } else {
1649     /* Normal mode */
1650     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1651     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1652   }
1653 } /* restore_multicast_list */
1654
1655 static void set_multicast_list(struct net_device *dev)
1656 {
1657   mace_private *lp = netdev_priv(dev);
1658
1659 #ifdef PCMCIA_DEBUG
1660   if (pc_debug > 1) {
1661     static int old;
1662     if (dev->mc_count != old) {
1663       old = dev->mc_count;
1664       DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1665             dev->name, old);
1666     }
1667   }
1668 #endif
1669
1670   lp->multicast_num_addrs = dev->mc_count;
1671   restore_multicast_list(dev);
1672
1673 } /* set_multicast_list */
1674
1675 static struct pcmcia_device_id nmclan_ids[] = {
1676         PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1677         PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1678         PCMCIA_DEVICE_NULL,
1679 };
1680 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1681
1682 static struct pcmcia_driver nmclan_cs_driver = {
1683         .owner          = THIS_MODULE,
1684         .drv            = {
1685                 .name   = "nmclan_cs",
1686         },
1687         .attach         = nmclan_attach,
1688         .event          = nmclan_event,
1689         .remove         = nmclan_detach,
1690         .id_table       = nmclan_ids,
1691         .suspend        = nmclan_suspend,
1692         .resume         = nmclan_resume,
1693 };
1694
1695 static int __init init_nmclan_cs(void)
1696 {
1697         return pcmcia_register_driver(&nmclan_cs_driver);
1698 }
1699
1700 static void __exit exit_nmclan_cs(void)
1701 {
1702         pcmcia_unregister_driver(&nmclan_cs_driver);
1703         BUG_ON(dev_list != NULL);
1704 }
1705
1706 module_init(init_nmclan_cs);
1707 module_exit(exit_nmclan_cs);