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[PATCH] pcmcia: unify detach, REMOVAL_EVENT handlers into one remove callback
[linux-2.6/kvm.git] / drivers / net / e100.c
blob22cd045567075d33f26356cac785866212362506
1 /*******************************************************************************
2
3
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Recieve
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * Under typical operation, the receive unit (RU) is start once,
110 * and the controller happily fills RFDs as frames arrive. If
111 * replacement RFDs cannot be allocated, or the RU goes non-active,
112 * the RU must be restarted. Frame arrival generates an interrupt,
113 * and Rx indication and re-allocation happen in the same context,
114 * therefore no locking is required. A software-generated interrupt
115 * is generated from the watchdog to recover from a failed allocation
116 * senario where all Rx resources have been indicated and none re-
117 * placed.
118 *
119 * V. Miscellaneous
120 *
121 * VLAN offloading of tagging, stripping and filtering is not
122 * supported, but driver will accommodate the extra 4-byte VLAN tag
123 * for processing by upper layers. Tx/Rx Checksum offloading is not
124 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
125 * not supported (hardware limitation).
126 *
127 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
128 *
129 * Thanks to JC (jchapman@katalix.com) for helping with
130 * testing/troubleshooting the development driver.
131 *
132 * TODO:
133 * o several entry points race with dev->close
134 * o check for tx-no-resources/stop Q races with tx clean/wake Q
135 */
136
137 #include <linux/config.h>
138 #include <linux/module.h>
139 #include <linux/moduleparam.h>
140 #include <linux/kernel.h>
141 #include <linux/types.h>
142 #include <linux/slab.h>
143 #include <linux/delay.h>
144 #include <linux/init.h>
145 #include <linux/pci.h>
146 #include <linux/dma-mapping.h>
147 #include <linux/netdevice.h>
148 #include <linux/etherdevice.h>
149 #include <linux/mii.h>
150 #include <linux/if_vlan.h>
151 #include <linux/skbuff.h>
152 #include <linux/ethtool.h>
153 #include <linux/string.h>
154 #include <asm/unaligned.h>
155
156
157 #define DRV_NAME "e100"
158 #define DRV_EXT "-NAPI"
159 #define DRV_VERSION "3.4.14-k4"DRV_EXT
160 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
161 #define DRV_COPYRIGHT "Copyright(c) 1999-2005 Intel Corporation"
162 #define PFX DRV_NAME ": "
163
164 #define E100_WATCHDOG_PERIOD (2 * HZ)
165 #define E100_NAPI_WEIGHT 16
166
167 MODULE_DESCRIPTION(DRV_DESCRIPTION);
168 MODULE_AUTHOR(DRV_COPYRIGHT);
169 MODULE_LICENSE("GPL");
170 MODULE_VERSION(DRV_VERSION);
171
172 static int debug = 3;
173 module_param(debug, int, 0);
174 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
175 #define DPRINTK(nlevel, klevel, fmt, args...) \
176 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
177 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
178 __FUNCTION__ , ## args))
179
180 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
181 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
182 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
183 static struct pci_device_id e100_id_table[] = {
184 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
185 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
186 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
187 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
188 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
189 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
191 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
192 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
193 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
194 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
197 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
198 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
199 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
200 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
205 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
206 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
207 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
208 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
209 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
213 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
214 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
215 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
216 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
217 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
218 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
219 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
220 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
221 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
222 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
223 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
224 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
225 { 0, }
226 };
227 MODULE_DEVICE_TABLE(pci, e100_id_table);
228
229 enum mac {
230 mac_82557_D100_A = 0,
231 mac_82557_D100_B = 1,
232 mac_82557_D100_C = 2,
233 mac_82558_D101_A4 = 4,
234 mac_82558_D101_B0 = 5,
235 mac_82559_D101M = 8,
236 mac_82559_D101S = 9,
237 mac_82550_D102 = 12,
238 mac_82550_D102_C = 13,
239 mac_82551_E = 14,
240 mac_82551_F = 15,
241 mac_82551_10 = 16,
242 mac_unknown = 0xFF,
243 };
244
245 enum phy {
246 phy_100a = 0x000003E0,
247 phy_100c = 0x035002A8,
248 phy_82555_tx = 0x015002A8,
249 phy_nsc_tx = 0x5C002000,
250 phy_82562_et = 0x033002A8,
251 phy_82562_em = 0x032002A8,
252 phy_82562_ek = 0x031002A8,
253 phy_82562_eh = 0x017002A8,
254 phy_unknown = 0xFFFFFFFF,
255 };
256
257 /* CSR (Control/Status Registers) */
258 struct csr {
259 struct {
260 u8 status;
261 u8 stat_ack;
262 u8 cmd_lo;
263 u8 cmd_hi;
264 u32 gen_ptr;
265 } scb;
266 u32 port;
267 u16 flash_ctrl;
268 u8 eeprom_ctrl_lo;
269 u8 eeprom_ctrl_hi;
270 u32 mdi_ctrl;
271 u32 rx_dma_count;
272 };
273
274 enum scb_status {
275 rus_ready = 0x10,
276 rus_mask = 0x3C,
277 };
278
279 enum ru_state {
280 RU_SUSPENDED = 0,
281 RU_RUNNING = 1,
282 RU_UNINITIALIZED = -1,
283 };
284
285 enum scb_stat_ack {
286 stat_ack_not_ours = 0x00,
287 stat_ack_sw_gen = 0x04,
288 stat_ack_rnr = 0x10,
289 stat_ack_cu_idle = 0x20,
290 stat_ack_frame_rx = 0x40,
291 stat_ack_cu_cmd_done = 0x80,
292 stat_ack_not_present = 0xFF,
293 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
294 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
295 };
296
297 enum scb_cmd_hi {
298 irq_mask_none = 0x00,
299 irq_mask_all = 0x01,
300 irq_sw_gen = 0x02,
301 };
302
303 enum scb_cmd_lo {
304 cuc_nop = 0x00,
305 ruc_start = 0x01,
306 ruc_load_base = 0x06,
307 cuc_start = 0x10,
308 cuc_resume = 0x20,
309 cuc_dump_addr = 0x40,
310 cuc_dump_stats = 0x50,
311 cuc_load_base = 0x60,
312 cuc_dump_reset = 0x70,
313 };
314
315 enum cuc_dump {
316 cuc_dump_complete = 0x0000A005,
317 cuc_dump_reset_complete = 0x0000A007,
318 };
319
320 enum port {
321 software_reset = 0x0000,
322 selftest = 0x0001,
323 selective_reset = 0x0002,
324 };
325
326 enum eeprom_ctrl_lo {
327 eesk = 0x01,
328 eecs = 0x02,
329 eedi = 0x04,
330 eedo = 0x08,
331 };
332
333 enum mdi_ctrl {
334 mdi_write = 0x04000000,
335 mdi_read = 0x08000000,
336 mdi_ready = 0x10000000,
337 };
338
339 enum eeprom_op {
340 op_write = 0x05,
341 op_read = 0x06,
342 op_ewds = 0x10,
343 op_ewen = 0x13,
344 };
345
346 enum eeprom_offsets {
347 eeprom_cnfg_mdix = 0x03,
348 eeprom_id = 0x0A,
349 eeprom_config_asf = 0x0D,
350 eeprom_smbus_addr = 0x90,
351 };
352
353 enum eeprom_cnfg_mdix {
354 eeprom_mdix_enabled = 0x0080,
355 };
356
357 enum eeprom_id {
358 eeprom_id_wol = 0x0020,
359 };
360
361 enum eeprom_config_asf {
362 eeprom_asf = 0x8000,
363 eeprom_gcl = 0x4000,
364 };
365
366 enum cb_status {
367 cb_complete = 0x8000,
368 cb_ok = 0x2000,
369 };
370
371 enum cb_command {
372 cb_nop = 0x0000,
373 cb_iaaddr = 0x0001,
374 cb_config = 0x0002,
375 cb_multi = 0x0003,
376 cb_tx = 0x0004,
377 cb_ucode = 0x0005,
378 cb_dump = 0x0006,
379 cb_tx_sf = 0x0008,
380 cb_cid = 0x1f00,
381 cb_i = 0x2000,
382 cb_s = 0x4000,
383 cb_el = 0x8000,
384 };
385
386 struct rfd {
387 u16 status;
388 u16 command;
389 u32 link;
390 u32 rbd;
391 u16 actual_size;
392 u16 size;
393 };
394
395 struct rx {
396 struct rx *next, *prev;
397 struct sk_buff *skb;
398 dma_addr_t dma_addr;
399 };
400
401 #if defined(__BIG_ENDIAN_BITFIELD)
402 #define X(a,b) b,a
403 #else
404 #define X(a,b) a,b
405 #endif
406 struct config {
407 /*0*/ u8 X(byte_count:6, pad0:2);
408 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
409 /*2*/ u8 adaptive_ifs;
410 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
411 term_write_cache_line:1), pad3:4);
412 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
413 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
414 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
415 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
416 rx_discard_overruns:1), rx_save_bad_frames:1);
417 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
418 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
419 tx_dynamic_tbd:1);
420 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
421 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
422 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
423 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
424 loopback:2);
425 /*11*/ u8 X(linear_priority:3, pad11:5);
426 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
427 /*13*/ u8 ip_addr_lo;
428 /*14*/ u8 ip_addr_hi;
429 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
430 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
431 pad15_2:1), crs_or_cdt:1);
432 /*16*/ u8 fc_delay_lo;
433 /*17*/ u8 fc_delay_hi;
434 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
435 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
436 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
437 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
438 full_duplex_force:1), full_duplex_pin:1);
439 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
440 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
441 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
442 u8 pad_d102[9];
443 };
444
445 #define E100_MAX_MULTICAST_ADDRS 64
446 struct multi {
447 u16 count;
448 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
449 };
450
451 /* Important: keep total struct u32-aligned */
452 #define UCODE_SIZE 134
453 struct cb {
454 u16 status;
455 u16 command;
456 u32 link;
457 union {
458 u8 iaaddr[ETH_ALEN];
459 u32 ucode[UCODE_SIZE];
460 struct config config;
461 struct multi multi;
462 struct {
463 u32 tbd_array;
464 u16 tcb_byte_count;
465 u8 threshold;
466 u8 tbd_count;
467 struct {
468 u32 buf_addr;
469 u16 size;
470 u16 eol;
471 } tbd;
472 } tcb;
473 u32 dump_buffer_addr;
474 } u;
475 struct cb *next, *prev;
476 dma_addr_t dma_addr;
477 struct sk_buff *skb;
478 };
479
480 enum loopback {
481 lb_none = 0, lb_mac = 1, lb_phy = 3,
482 };
483
484 struct stats {
485 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
486 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
487 tx_multiple_collisions, tx_total_collisions;
488 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
489 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
490 rx_short_frame_errors;
491 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
492 u16 xmt_tco_frames, rcv_tco_frames;
493 u32 complete;
494 };
495
496 struct mem {
497 struct {
498 u32 signature;
499 u32 result;
500 } selftest;
501 struct stats stats;
502 u8 dump_buf[596];
503 };
504
505 struct param_range {
506 u32 min;
507 u32 max;
508 u32 count;
509 };
510
511 struct params {
512 struct param_range rfds;
513 struct param_range cbs;
514 };
515
516 struct nic {
517 /* Begin: frequently used values: keep adjacent for cache effect */
518 u32 msg_enable ____cacheline_aligned;
519 struct net_device *netdev;
520 struct pci_dev *pdev;
521
522 struct rx *rxs ____cacheline_aligned;
523 struct rx *rx_to_use;
524 struct rx *rx_to_clean;
525 struct rfd blank_rfd;
526 enum ru_state ru_running;
527
528 spinlock_t cb_lock ____cacheline_aligned;
529 spinlock_t cmd_lock;
530 struct csr __iomem *csr;
531 enum scb_cmd_lo cuc_cmd;
532 unsigned int cbs_avail;
533 struct cb *cbs;
534 struct cb *cb_to_use;
535 struct cb *cb_to_send;
536 struct cb *cb_to_clean;
537 u16 tx_command;
538 /* End: frequently used values: keep adjacent for cache effect */
539
540 enum {
541 ich = (1 << 0),
542 promiscuous = (1 << 1),
543 multicast_all = (1 << 2),
544 wol_magic = (1 << 3),
545 ich_10h_workaround = (1 << 4),
546 } flags ____cacheline_aligned;
547
548 enum mac mac;
549 enum phy phy;
550 struct params params;
551 struct net_device_stats net_stats;
552 struct timer_list watchdog;
553 struct timer_list blink_timer;
554 struct mii_if_info mii;
555 struct work_struct tx_timeout_task;
556 enum loopback loopback;
557
558 struct mem *mem;
559 dma_addr_t dma_addr;
560
561 dma_addr_t cbs_dma_addr;
562 u8 adaptive_ifs;
563 u8 tx_threshold;
564 u32 tx_frames;
565 u32 tx_collisions;
566 u32 tx_deferred;
567 u32 tx_single_collisions;
568 u32 tx_multiple_collisions;
569 u32 tx_fc_pause;
570 u32 tx_tco_frames;
571
572 u32 rx_fc_pause;
573 u32 rx_fc_unsupported;
574 u32 rx_tco_frames;
575 u32 rx_over_length_errors;
576
577 u8 rev_id;
578 u16 leds;
579 u16 eeprom_wc;
580 u16 eeprom[256];
581 };
582
583 static inline void e100_write_flush(struct nic *nic)
584 {
585 /* Flush previous PCI writes through intermediate bridges
586 * by doing a benign read */
587 (void)readb(&nic->csr->scb.status);
588 }
589
590 static inline void e100_enable_irq(struct nic *nic)
591 {
592 unsigned long flags;
593
594 spin_lock_irqsave(&nic->cmd_lock, flags);
595 writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
596 spin_unlock_irqrestore(&nic->cmd_lock, flags);
597 e100_write_flush(nic);
598 }
599
600 static inline void e100_disable_irq(struct nic *nic)
601 {
602 unsigned long flags;
603
604 spin_lock_irqsave(&nic->cmd_lock, flags);
605 writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
606 spin_unlock_irqrestore(&nic->cmd_lock, flags);
607 e100_write_flush(nic);
608 }
609
610 static void e100_hw_reset(struct nic *nic)
611 {
612 /* Put CU and RU into idle with a selective reset to get
613 * device off of PCI bus */
614 writel(selective_reset, &nic->csr->port);
615 e100_write_flush(nic); udelay(20);
616
617 /* Now fully reset device */
618 writel(software_reset, &nic->csr->port);
619 e100_write_flush(nic); udelay(20);
620
621 /* Mask off our interrupt line - it's unmasked after reset */
622 e100_disable_irq(nic);
623 }
624
625 static int e100_self_test(struct nic *nic)
626 {
627 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
628
629 /* Passing the self-test is a pretty good indication
630 * that the device can DMA to/from host memory */
631
632 nic->mem->selftest.signature = 0;
633 nic->mem->selftest.result = 0xFFFFFFFF;
634
635 writel(selftest | dma_addr, &nic->csr->port);
636 e100_write_flush(nic);
637 /* Wait 10 msec for self-test to complete */
638 msleep(10);
639
640 /* Interrupts are enabled after self-test */
641 e100_disable_irq(nic);
642
643 /* Check results of self-test */
644 if(nic->mem->selftest.result != 0) {
645 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
646 nic->mem->selftest.result);
647 return -ETIMEDOUT;
648 }
649 if(nic->mem->selftest.signature == 0) {
650 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
651 return -ETIMEDOUT;
652 }
653
654 return 0;
655 }
656
657 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
658 {
659 u32 cmd_addr_data[3];
660 u8 ctrl;
661 int i, j;
662
663 /* Three cmds: write/erase enable, write data, write/erase disable */
664 cmd_addr_data[0] = op_ewen << (addr_len - 2);
665 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
666 cpu_to_le16(data);
667 cmd_addr_data[2] = op_ewds << (addr_len - 2);
668
669 /* Bit-bang cmds to write word to eeprom */
670 for(j = 0; j < 3; j++) {
671
672 /* Chip select */
673 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
674 e100_write_flush(nic); udelay(4);
675
676 for(i = 31; i >= 0; i--) {
677 ctrl = (cmd_addr_data[j] & (1 << i)) ?
678 eecs | eedi : eecs;
679 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
680 e100_write_flush(nic); udelay(4);
681
682 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
683 e100_write_flush(nic); udelay(4);
684 }
685 /* Wait 10 msec for cmd to complete */
686 msleep(10);
687
688 /* Chip deselect */
689 writeb(0, &nic->csr->eeprom_ctrl_lo);
690 e100_write_flush(nic); udelay(4);
691 }
692 };
693
694 /* General technique stolen from the eepro100 driver - very clever */
695 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
696 {
697 u32 cmd_addr_data;
698 u16 data = 0;
699 u8 ctrl;
700 int i;
701
702 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
703
704 /* Chip select */
705 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
706 e100_write_flush(nic); udelay(4);
707
708 /* Bit-bang to read word from eeprom */
709 for(i = 31; i >= 0; i--) {
710 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
711 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
712 e100_write_flush(nic); udelay(4);
713
714 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
715 e100_write_flush(nic); udelay(4);
716
717 /* Eeprom drives a dummy zero to EEDO after receiving
718 * complete address. Use this to adjust addr_len. */
719 ctrl = readb(&nic->csr->eeprom_ctrl_lo);
720 if(!(ctrl & eedo) && i > 16) {
721 *addr_len -= (i - 16);
722 i = 17;
723 }
724
725 data = (data << 1) | (ctrl & eedo ? 1 : 0);
726 }
727
728 /* Chip deselect */
729 writeb(0, &nic->csr->eeprom_ctrl_lo);
730 e100_write_flush(nic); udelay(4);
731
732 return le16_to_cpu(data);
733 };
734
735 /* Load entire EEPROM image into driver cache and validate checksum */
736 static int e100_eeprom_load(struct nic *nic)
737 {
738 u16 addr, addr_len = 8, checksum = 0;
739
740 /* Try reading with an 8-bit addr len to discover actual addr len */
741 e100_eeprom_read(nic, &addr_len, 0);
742 nic->eeprom_wc = 1 << addr_len;
743
744 for(addr = 0; addr < nic->eeprom_wc; addr++) {
745 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
746 if(addr < nic->eeprom_wc - 1)
747 checksum += cpu_to_le16(nic->eeprom[addr]);
748 }
749
750 /* The checksum, stored in the last word, is calculated such that
751 * the sum of words should be 0xBABA */
752 checksum = le16_to_cpu(0xBABA - checksum);
753 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
754 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
755 return -EAGAIN;
756 }
757
758 return 0;
759 }
760
761 /* Save (portion of) driver EEPROM cache to device and update checksum */
762 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
763 {
764 u16 addr, addr_len = 8, checksum = 0;
765
766 /* Try reading with an 8-bit addr len to discover actual addr len */
767 e100_eeprom_read(nic, &addr_len, 0);
768 nic->eeprom_wc = 1 << addr_len;
769
770 if(start + count >= nic->eeprom_wc)
771 return -EINVAL;
772
773 for(addr = start; addr < start + count; addr++)
774 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
775
776 /* The checksum, stored in the last word, is calculated such that
777 * the sum of words should be 0xBABA */
778 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
779 checksum += cpu_to_le16(nic->eeprom[addr]);
780 nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
781 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
782 nic->eeprom[nic->eeprom_wc - 1]);
783
784 return 0;
785 }
786
787 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
788 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */
789 static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
790 {
791 unsigned long flags;
792 unsigned int i;
793 int err = 0;
794
795 spin_lock_irqsave(&nic->cmd_lock, flags);
796
797 /* Previous command is accepted when SCB clears */
798 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
799 if(likely(!readb(&nic->csr->scb.cmd_lo)))
800 break;
801 cpu_relax();
802 if(unlikely(i > E100_WAIT_SCB_FAST))
803 udelay(5);
804 }
805 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
806 err = -EAGAIN;
807 goto err_unlock;
808 }
809
810 if(unlikely(cmd != cuc_resume))
811 writel(dma_addr, &nic->csr->scb.gen_ptr);
812 writeb(cmd, &nic->csr->scb.cmd_lo);
813
814 err_unlock:
815 spin_unlock_irqrestore(&nic->cmd_lock, flags);
816
817 return err;
818 }
819
820 static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
821 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
822 {
823 struct cb *cb;
824 unsigned long flags;
825 int err = 0;
826
827 spin_lock_irqsave(&nic->cb_lock, flags);
828
829 if(unlikely(!nic->cbs_avail)) {
830 err = -ENOMEM;
831 goto err_unlock;
832 }
833
834 cb = nic->cb_to_use;
835 nic->cb_to_use = cb->next;
836 nic->cbs_avail--;
837 cb->skb = skb;
838
839 if(unlikely(!nic->cbs_avail))
840 err = -ENOSPC;
841
842 cb_prepare(nic, cb, skb);
843
844 /* Order is important otherwise we'll be in a race with h/w:
845 * set S-bit in current first, then clear S-bit in previous. */
846 cb->command |= cpu_to_le16(cb_s);
847 wmb();
848 cb->prev->command &= cpu_to_le16(~cb_s);
849
850 while(nic->cb_to_send != nic->cb_to_use) {
851 if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
852 nic->cb_to_send->dma_addr))) {
853 /* Ok, here's where things get sticky. It's
854 * possible that we can't schedule the command
855 * because the controller is too busy, so
856 * let's just queue the command and try again
857 * when another command is scheduled. */
858 if(err == -ENOSPC) {
859 //request a reset
860 schedule_work(&nic->tx_timeout_task);
861 }
862 break;
863 } else {
864 nic->cuc_cmd = cuc_resume;
865 nic->cb_to_send = nic->cb_to_send->next;
866 }
867 }
868
869 err_unlock:
870 spin_unlock_irqrestore(&nic->cb_lock, flags);
871
872 return err;
873 }
874
875 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
876 {
877 u32 data_out = 0;
878 unsigned int i;
879
880 writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
881
882 for(i = 0; i < 100; i++) {
883 udelay(20);
884 if((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
885 break;
886 }
887
888 DPRINTK(HW, DEBUG,
889 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
890 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
891 return (u16)data_out;
892 }
893
894 static int mdio_read(struct net_device *netdev, int addr, int reg)
895 {
896 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
897 }
898
899 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
900 {
901 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
902 }
903
904 static void e100_get_defaults(struct nic *nic)
905 {
906 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
907 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
908
909 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
910 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
911 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
912 if(nic->mac == mac_unknown)
913 nic->mac = mac_82557_D100_A;
914
915 nic->params.rfds = rfds;
916 nic->params.cbs = cbs;
917
918 /* Quadwords to DMA into FIFO before starting frame transmit */
919 nic->tx_threshold = 0xE0;
920
921 /* no interrupt for every tx completion, delay = 256us if not 557*/
922 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
923 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
924
925 /* Template for a freshly allocated RFD */
926 nic->blank_rfd.command = cpu_to_le16(cb_el);
927 nic->blank_rfd.rbd = 0xFFFFFFFF;
928 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
929
930 /* MII setup */
931 nic->mii.phy_id_mask = 0x1F;
932 nic->mii.reg_num_mask = 0x1F;
933 nic->mii.dev = nic->netdev;
934 nic->mii.mdio_read = mdio_read;
935 nic->mii.mdio_write = mdio_write;
936 }
937
938 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
939 {
940 struct config *config = &cb->u.config;
941 u8 *c = (u8 *)config;
942
943 cb->command = cpu_to_le16(cb_config);
944
945 memset(config, 0, sizeof(struct config));
946
947 config->byte_count = 0x16; /* bytes in this struct */
948 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
949 config->direct_rx_dma = 0x1; /* reserved */
950 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
951 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
952 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
953 config->tx_underrun_retry = 0x3; /* # of underrun retries */
954 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
955 config->pad10 = 0x6;
956 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
957 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
958 config->ifs = 0x6; /* x16 = inter frame spacing */
959 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
960 config->pad15_1 = 0x1;
961 config->pad15_2 = 0x1;
962 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
963 config->fc_delay_hi = 0x40; /* time delay for fc frame */
964 config->tx_padding = 0x1; /* 1=pad short frames */
965 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
966 config->pad18 = 0x1;
967 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
968 config->pad20_1 = 0x1F;
969 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
970 config->pad21_1 = 0x5;
971
972 config->adaptive_ifs = nic->adaptive_ifs;
973 config->loopback = nic->loopback;
974
975 if(nic->mii.force_media && nic->mii.full_duplex)
976 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
977
978 if(nic->flags & promiscuous || nic->loopback) {
979 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
980 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
981 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
982 }
983
984 if(nic->flags & multicast_all)
985 config->multicast_all = 0x1; /* 1=accept, 0=no */
986
987 /* disable WoL when up */
988 if(netif_running(nic->netdev) || !(nic->flags & wol_magic))
989 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
990
991 if(nic->mac >= mac_82558_D101_A4) {
992 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
993 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
994 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
995 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
996 if(nic->mac >= mac_82559_D101M)
997 config->tno_intr = 0x1; /* TCO stats enable */
998 else
999 config->standard_stat_counter = 0x0;
1000 }
1001
1002 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1003 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1004 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1005 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1006 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1007 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1008 }
1009
1010 /********************************************************/
1011 /* Micro code for 8086:1229 Rev 8 */
1012 /********************************************************/
1013
1014 /* Parameter values for the D101M B-step */
1015 #define D101M_CPUSAVER_TIMER_DWORD 78
1016 #define D101M_CPUSAVER_BUNDLE_DWORD 65
1017 #define D101M_CPUSAVER_MIN_SIZE_DWORD 126
1018
1019 #define D101M_B_RCVBUNDLE_UCODE \
1020 {\
1021 0x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \
1022 0x000C0001, 0x00101312, 0x000C0008, 0x00380216, \
1023 0x0010009C, 0x00204056, 0x002380CC, 0x00380056, \
1024 0x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \
1025 0x00380438, 0x00000000, 0x00140000, 0x00380555, \
1026 0x00308000, 0x00100662, 0x00100561, 0x000E0408, \
1027 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
1028 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
1029 0x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \
1030 0x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \
1031 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1032 0x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \
1033 0x003A0437, 0x00044010, 0x0038078A, 0x00000000, \
1034 0x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \
1035 0x00130824, 0x000C0001, 0x00101213, 0x00260C75, \
1036 0x00041000, 0x00010004, 0x00130826, 0x000C0006, \
1037 0x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \
1038 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1039 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1040 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
1041 0x00101210, 0x00380C34, 0x00000000, 0x00000000, \
1042 0x0021155B, 0x00100099, 0x00206559, 0x0010009C, \
1043 0x00244559, 0x00130836, 0x000C0000, 0x00220C62, \
1044 0x000C0001, 0x00101B13, 0x00229C0E, 0x00210C0E, \
1045 0x00226C0E, 0x00216C0E, 0x0022FC0E, 0x00215C0E, \
1046 0x00214C0E, 0x00380555, 0x00010004, 0x00041000, \
1047 0x00278C67, 0x00040800, 0x00018100, 0x003A0437, \
1048 0x00130826, 0x000C0001, 0x00220559, 0x00101313, \
1049 0x00380559, 0x00000000, 0x00000000, 0x00000000, \
1050 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1051 0x00000000, 0x00130831, 0x0010090B, 0x00124813, \
1052 0x000CFF80, 0x002606AB, 0x00041000, 0x00010004, \
1053 0x003806A8, 0x00000000, 0x00000000, 0x00000000, \
1054 }
1055
1056 /********************************************************/
1057 /* Micro code for 8086:1229 Rev 9 */
1058 /********************************************************/
1059
1060 /* Parameter values for the D101S */
1061 #define D101S_CPUSAVER_TIMER_DWORD 78
1062 #define D101S_CPUSAVER_BUNDLE_DWORD 67
1063 #define D101S_CPUSAVER_MIN_SIZE_DWORD 128
1064
1065 #define D101S_RCVBUNDLE_UCODE \
1066 {\
1067 0x00550242, 0xFFFF047E, 0xFFFFFFFF, 0x06FF0818, 0xFFFFFFFF, 0x05A6FFFF, \
1068 0x000C0001, 0x00101312, 0x000C0008, 0x00380243, \
1069 0x0010009C, 0x00204056, 0x002380D0, 0x00380056, \
1070 0x0010009C, 0x00244F8B, 0x00000800, 0x00124818, \
1071 0x0038047F, 0x00000000, 0x00140000, 0x003805A3, \
1072 0x00308000, 0x00100610, 0x00100561, 0x000E0408, \
1073 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
1074 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
1075 0x000C007E, 0x00222FA1, 0x000C0002, 0x00103093, \
1076 0x00380F90, 0x00080000, 0x00103090, 0x00380F90, \
1077 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1078 0x0010009C, 0x00244FAD, 0x00010004, 0x00041000, \
1079 0x003A047E, 0x00044010, 0x00380819, 0x00000000, \
1080 0x00100099, 0x00206FFD, 0x0010009A, 0x0020AFFD, \
1081 0x0010009C, 0x00244FC8, 0x00130824, 0x000C0001, \
1082 0x00101213, 0x00260FF7, 0x00041000, 0x00010004, \
1083 0x00130826, 0x000C0006, 0x00220700, 0x0013C926, \
1084 0x00101313, 0x00380700, 0x00000000, 0x00000000, \
1085 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1086 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
1087 0x00101210, 0x00380FB6, 0x00000000, 0x00000000, \
1088 0x002115A9, 0x00100099, 0x002065A7, 0x0010009A, \
1089 0x0020A5A7, 0x0010009C, 0x002445A7, 0x00130836, \
1090 0x000C0000, 0x00220FE4, 0x000C0001, 0x00101B13, \
1091 0x00229F8E, 0x00210F8E, 0x00226F8E, 0x00216F8E, \
1092 0x0022FF8E, 0x00215F8E, 0x00214F8E, 0x003805A3, \
1093 0x00010004, 0x00041000, 0x00278FE9, 0x00040800, \
1094 0x00018100, 0x003A047E, 0x00130826, 0x000C0001, \
1095 0x002205A7, 0x00101313, 0x003805A7, 0x00000000, \
1096 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1097 0x00000000, 0x00000000, 0x00000000, 0x00130831, \
1098 0x0010090B, 0x00124813, 0x000CFF80, 0x00260703, \
1099 0x00041000, 0x00010004, 0x00380700 \
1100 }
1101
1102 /********************************************************/
1103 /* Micro code for the 8086:1229 Rev F/10 */
1104 /********************************************************/
1105
1106 /* Parameter values for the D102 E-step */
1107 #define D102_E_CPUSAVER_TIMER_DWORD 42
1108 #define D102_E_CPUSAVER_BUNDLE_DWORD 54
1109 #define D102_E_CPUSAVER_MIN_SIZE_DWORD 46
1110
1111 #define D102_E_RCVBUNDLE_UCODE \
1112 {\
1113 0x007D028F, 0x0E4204F9, 0x14ED0C85, 0x14FA14E9, 0x0EF70E36, 0x1FFF1FFF, \
1114 0x00E014B9, 0x00000000, 0x00000000, 0x00000000, \
1115 0x00E014BD, 0x00000000, 0x00000000, 0x00000000, \
1116 0x00E014D5, 0x00000000, 0x00000000, 0x00000000, \
1117 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1118 0x00E014C1, 0x00000000, 0x00000000, 0x00000000, \
1119 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1120 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1121 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1122 0x00E014C8, 0x00000000, 0x00000000, 0x00000000, \
1123 0x00200600, 0x00E014EE, 0x00000000, 0x00000000, \
1124 0x0030FF80, 0x00940E46, 0x00038200, 0x00102000, \
1125 0x00E00E43, 0x00000000, 0x00000000, 0x00000000, \
1126 0x00300006, 0x00E014FB, 0x00000000, 0x00000000, \
1127 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1128 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1129 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1130 0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000, \
1131 0x00906EFD, 0x00900EFD, 0x00E00EF8, 0x00000000, \
1132 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1133 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1134 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1135 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1136 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1137 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1138 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1139 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1140 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1141 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1142 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1143 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1144 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1145 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1146 }
1147
1148 static void e100_load_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1149 {
1150 /* *INDENT-OFF* */
1151 static struct {
1152 u32 ucode[UCODE_SIZE + 1];
1153 u8 mac;
1154 u8 timer_dword;
1155 u8 bundle_dword;
1156 u8 min_size_dword;
1157 } ucode_opts[] = {
1158 { D101M_B_RCVBUNDLE_UCODE,
1159 mac_82559_D101M,
1160 D101M_CPUSAVER_TIMER_DWORD,
1161 D101M_CPUSAVER_BUNDLE_DWORD,
1162 D101M_CPUSAVER_MIN_SIZE_DWORD },
1163 { D101S_RCVBUNDLE_UCODE,
1164 mac_82559_D101S,
1165 D101S_CPUSAVER_TIMER_DWORD,
1166 D101S_CPUSAVER_BUNDLE_DWORD,
1167 D101S_CPUSAVER_MIN_SIZE_DWORD },
1168 { D102_E_RCVBUNDLE_UCODE,
1169 mac_82551_F,
1170 D102_E_CPUSAVER_TIMER_DWORD,
1171 D102_E_CPUSAVER_BUNDLE_DWORD,
1172 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1173 { D102_E_RCVBUNDLE_UCODE,
1174 mac_82551_10,
1175 D102_E_CPUSAVER_TIMER_DWORD,
1176 D102_E_CPUSAVER_BUNDLE_DWORD,
1177 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1178 { {0}, 0, 0, 0, 0}
1179 }, *opts;
1180 /* *INDENT-ON* */
1181
1182 /*************************************************************************
1183 * CPUSaver parameters
1184 *
1185 * All CPUSaver parameters are 16-bit literals that are part of a
1186 * "move immediate value" instruction. By changing the value of
1187 * the literal in the instruction before the code is loaded, the
1188 * driver can change the algorithm.
1189 *
1190 * INTDELAY - This loads the dead-man timer with its inital value.
1191 * When this timer expires the interrupt is asserted, and the
1192 * timer is reset each time a new packet is received. (see
1193 * BUNDLEMAX below to set the limit on number of chained packets)
1194 * The current default is 0x600 or 1536. Experiments show that
1195 * the value should probably stay within the 0x200 - 0x1000.
1196 *
1197 * BUNDLEMAX -
1198 * This sets the maximum number of frames that will be bundled. In
1199 * some situations, such as the TCP windowing algorithm, it may be
1200 * better to limit the growth of the bundle size than let it go as
1201 * high as it can, because that could cause too much added latency.
1202 * The default is six, because this is the number of packets in the
1203 * default TCP window size. A value of 1 would make CPUSaver indicate
1204 * an interrupt for every frame received. If you do not want to put
1205 * a limit on the bundle size, set this value to xFFFF.
1206 *
1207 * BUNDLESMALL -
1208 * This contains a bit-mask describing the minimum size frame that
1209 * will be bundled. The default masks the lower 7 bits, which means
1210 * that any frame less than 128 bytes in length will not be bundled,
1211 * but will instead immediately generate an interrupt. This does
1212 * not affect the current bundle in any way. Any frame that is 128
1213 * bytes or large will be bundled normally. This feature is meant
1214 * to provide immediate indication of ACK frames in a TCP environment.
1215 * Customers were seeing poor performance when a machine with CPUSaver
1216 * enabled was sending but not receiving. The delay introduced when
1217 * the ACKs were received was enough to reduce total throughput, because
1218 * the sender would sit idle until the ACK was finally seen.
1219 *
1220 * The current default is 0xFF80, which masks out the lower 7 bits.
1221 * This means that any frame which is x7F (127) bytes or smaller
1222 * will cause an immediate interrupt. Because this value must be a
1223 * bit mask, there are only a few valid values that can be used. To
1224 * turn this feature off, the driver can write the value xFFFF to the
1225 * lower word of this instruction (in the same way that the other
1226 * parameters are used). Likewise, a value of 0xF800 (2047) would
1227 * cause an interrupt to be generated for every frame, because all
1228 * standard Ethernet frames are <= 2047 bytes in length.
1229 *************************************************************************/
1230
1231 /* if you wish to disable the ucode functionality, while maintaining the
1232 * workarounds it provides, set the following defines to:
1233 * BUNDLESMALL 0
1234 * BUNDLEMAX 1
1235 * INTDELAY 1
1236 */
1237 #define BUNDLESMALL 1
1238 #define BUNDLEMAX (u16)6
1239 #define INTDELAY (u16)1536 /* 0x600 */
1240
1241 /* do not load u-code for ICH devices */
1242 if (nic->flags & ich)
1243 goto noloaducode;
1244
1245 /* Search for ucode match against h/w rev_id */
1246 for (opts = ucode_opts; opts->mac; opts++) {
1247 int i;
1248 u32 *ucode = opts->ucode;
1249 if (nic->mac != opts->mac)
1250 continue;
1251
1252 /* Insert user-tunable settings */
1253 ucode[opts->timer_dword] &= 0xFFFF0000;
1254 ucode[opts->timer_dword] |= INTDELAY;
1255 ucode[opts->bundle_dword] &= 0xFFFF0000;
1256 ucode[opts->bundle_dword] |= BUNDLEMAX;
1257 ucode[opts->min_size_dword] &= 0xFFFF0000;
1258 ucode[opts->min_size_dword] |= (BUNDLESMALL) ? 0xFFFF : 0xFF80;
1259
1260 for (i = 0; i < UCODE_SIZE; i++)
1261 cb->u.ucode[i] = cpu_to_le32(ucode[i]);
1262 cb->command = cpu_to_le16(cb_ucode);
1263 return;
1264 }
1265
1266 noloaducode:
1267 cb->command = cpu_to_le16(cb_nop);
1268 }
1269
1270 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1271 struct sk_buff *skb)
1272 {
1273 cb->command = cpu_to_le16(cb_iaaddr);
1274 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1275 }
1276
1277 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1278 {
1279 cb->command = cpu_to_le16(cb_dump);
1280 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1281 offsetof(struct mem, dump_buf));
1282 }
1283
1284 #define NCONFIG_AUTO_SWITCH 0x0080
1285 #define MII_NSC_CONG MII_RESV1
1286 #define NSC_CONG_ENABLE 0x0100
1287 #define NSC_CONG_TXREADY 0x0400
1288 #define ADVERTISE_FC_SUPPORTED 0x0400
1289 static int e100_phy_init(struct nic *nic)
1290 {
1291 struct net_device *netdev = nic->netdev;
1292 u32 addr;
1293 u16 bmcr, stat, id_lo, id_hi, cong;
1294
1295 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1296 for(addr = 0; addr < 32; addr++) {
1297 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1298 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1299 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1300 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1301 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1302 break;
1303 }
1304 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1305 if(addr == 32)
1306 return -EAGAIN;
1307
1308 /* Selected the phy and isolate the rest */
1309 for(addr = 0; addr < 32; addr++) {
1310 if(addr != nic->mii.phy_id) {
1311 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1312 } else {
1313 bmcr = mdio_read(netdev, addr, MII_BMCR);
1314 mdio_write(netdev, addr, MII_BMCR,
1315 bmcr & ~BMCR_ISOLATE);
1316 }
1317 }
1318
1319 /* Get phy ID */
1320 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1321 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1322 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1323 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1324
1325 /* Handle National tx phys */
1326 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1327 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1328 /* Disable congestion control */
1329 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1330 cong |= NSC_CONG_TXREADY;
1331 cong &= ~NSC_CONG_ENABLE;
1332 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1333 }
1334
1335 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1336 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000))) {
1337 /* enable/disable MDI/MDI-X auto-switching.
1338 MDI/MDI-X auto-switching is disabled for 82551ER/QM chips */
1339 if((nic->mac == mac_82551_E) || (nic->mac == mac_82551_F) ||
1340 (nic->mac == mac_82551_10) || (nic->mii.force_media) ||
1341 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))
1342 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, 0);
1343 else
1344 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, NCONFIG_AUTO_SWITCH);
1345 }
1346
1347 return 0;
1348 }
1349
1350 static int e100_hw_init(struct nic *nic)
1351 {
1352 int err;
1353
1354 e100_hw_reset(nic);
1355
1356 DPRINTK(HW, ERR, "e100_hw_init\n");
1357 if(!in_interrupt() && (err = e100_self_test(nic)))
1358 return err;
1359
1360 if((err = e100_phy_init(nic)))
1361 return err;
1362 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1363 return err;
1364 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1365 return err;
1366 if((err = e100_exec_cb(nic, NULL, e100_load_ucode)))
1367 return err;
1368 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1369 return err;
1370 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1371 return err;
1372 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1373 nic->dma_addr + offsetof(struct mem, stats))))
1374 return err;
1375 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1376 return err;
1377
1378 e100_disable_irq(nic);
1379
1380 return 0;
1381 }
1382
1383 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1384 {
1385 struct net_device *netdev = nic->netdev;
1386 struct dev_mc_list *list = netdev->mc_list;
1387 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1388
1389 cb->command = cpu_to_le16(cb_multi);
1390 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1391 for(i = 0; list && i < count; i++, list = list->next)
1392 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1393 ETH_ALEN);
1394 }
1395
1396 static void e100_set_multicast_list(struct net_device *netdev)
1397 {
1398 struct nic *nic = netdev_priv(netdev);
1399
1400 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1401 netdev->mc_count, netdev->flags);
1402
1403 if(netdev->flags & IFF_PROMISC)
1404 nic->flags |= promiscuous;
1405 else
1406 nic->flags &= ~promiscuous;
1407
1408 if(netdev->flags & IFF_ALLMULTI ||
1409 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1410 nic->flags |= multicast_all;
1411 else
1412 nic->flags &= ~multicast_all;
1413
1414 e100_exec_cb(nic, NULL, e100_configure);
1415 e100_exec_cb(nic, NULL, e100_multi);
1416 }
1417
1418 static void e100_update_stats(struct nic *nic)
1419 {
1420 struct net_device_stats *ns = &nic->net_stats;
1421 struct stats *s = &nic->mem->stats;
1422 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1423 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1424 &s->complete;
1425
1426 /* Device's stats reporting may take several microseconds to
1427 * complete, so where always waiting for results of the
1428 * previous command. */
1429
1430 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1431 *complete = 0;
1432 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1433 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1434 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1435 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1436 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1437 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1438 ns->collisions += nic->tx_collisions;
1439 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1440 le32_to_cpu(s->tx_lost_crs);
1441 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1442 nic->rx_over_length_errors;
1443 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1444 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1445 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1446 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1447 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1448 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1449 le32_to_cpu(s->rx_alignment_errors) +
1450 le32_to_cpu(s->rx_short_frame_errors) +
1451 le32_to_cpu(s->rx_cdt_errors);
1452 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1453 nic->tx_single_collisions +=
1454 le32_to_cpu(s->tx_single_collisions);
1455 nic->tx_multiple_collisions +=
1456 le32_to_cpu(s->tx_multiple_collisions);
1457 if(nic->mac >= mac_82558_D101_A4) {
1458 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1459 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1460 nic->rx_fc_unsupported +=
1461 le32_to_cpu(s->fc_rcv_unsupported);
1462 if(nic->mac >= mac_82559_D101M) {
1463 nic->tx_tco_frames +=
1464 le16_to_cpu(s->xmt_tco_frames);
1465 nic->rx_tco_frames +=
1466 le16_to_cpu(s->rcv_tco_frames);
1467 }
1468 }
1469 }
1470
1471
1472 if(e100_exec_cmd(nic, cuc_dump_reset, 0))
1473 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1474 }
1475
1476 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1477 {
1478 /* Adjust inter-frame-spacing (IFS) between two transmits if
1479 * we're getting collisions on a half-duplex connection. */
1480
1481 if(duplex == DUPLEX_HALF) {
1482 u32 prev = nic->adaptive_ifs;
1483 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1484
1485 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1486 (nic->tx_frames > min_frames)) {
1487 if(nic->adaptive_ifs < 60)
1488 nic->adaptive_ifs += 5;
1489 } else if (nic->tx_frames < min_frames) {
1490 if(nic->adaptive_ifs >= 5)
1491 nic->adaptive_ifs -= 5;
1492 }
1493 if(nic->adaptive_ifs != prev)
1494 e100_exec_cb(nic, NULL, e100_configure);
1495 }
1496 }
1497
1498 static void e100_watchdog(unsigned long data)
1499 {
1500 struct nic *nic = (struct nic *)data;
1501 struct ethtool_cmd cmd;
1502
1503 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1504
1505 /* mii library handles link maintenance tasks */
1506
1507 mii_ethtool_gset(&nic->mii, &cmd);
1508
1509 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1510 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1511 cmd.speed == SPEED_100 ? "100" : "10",
1512 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1513 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1514 DPRINTK(LINK, INFO, "link down\n");
1515 }
1516
1517 mii_check_link(&nic->mii);
1518
1519 /* Software generated interrupt to recover from (rare) Rx
1520 * allocation failure.
1521 * Unfortunately have to use a spinlock to not re-enable interrupts
1522 * accidentally, due to hardware that shares a register between the
1523 * interrupt mask bit and the SW Interrupt generation bit */
1524 spin_lock_irq(&nic->cmd_lock);
1525 writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1526 spin_unlock_irq(&nic->cmd_lock);
1527 e100_write_flush(nic);
1528
1529 e100_update_stats(nic);
1530 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1531
1532 if(nic->mac <= mac_82557_D100_C)
1533 /* Issue a multicast command to workaround a 557 lock up */
1534 e100_set_multicast_list(nic->netdev);
1535
1536 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1537 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1538 nic->flags |= ich_10h_workaround;
1539 else
1540 nic->flags &= ~ich_10h_workaround;
1541
1542 mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
1543 }
1544
1545 static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1546 struct sk_buff *skb)
1547 {
1548 cb->command = nic->tx_command;
1549 /* interrupt every 16 packets regardless of delay */
1550 if((nic->cbs_avail & ~15) == nic->cbs_avail)
1551 cb->command |= cpu_to_le16(cb_i);
1552 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1553 cb->u.tcb.tcb_byte_count = 0;
1554 cb->u.tcb.threshold = nic->tx_threshold;
1555 cb->u.tcb.tbd_count = 1;
1556 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1557 skb->data, skb->len, PCI_DMA_TODEVICE));
1558 /* check for mapping failure? */
1559 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1560 }
1561
1562 static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1563 {
1564 struct nic *nic = netdev_priv(netdev);
1565 int err;
1566
1567 if(nic->flags & ich_10h_workaround) {
1568 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1569 Issue a NOP command followed by a 1us delay before
1570 issuing the Tx command. */
1571 if(e100_exec_cmd(nic, cuc_nop, 0))
1572 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1573 udelay(1);
1574 }
1575
1576 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1577
1578 switch(err) {
1579 case -ENOSPC:
1580 /* We queued the skb, but now we're out of space. */
1581 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1582 netif_stop_queue(netdev);
1583 break;
1584 case -ENOMEM:
1585 /* This is a hard error - log it. */
1586 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1587 netif_stop_queue(netdev);
1588 return 1;
1589 }
1590
1591 netdev->trans_start = jiffies;
1592 return 0;
1593 }
1594
1595 static inline int e100_tx_clean(struct nic *nic)
1596 {
1597 struct cb *cb;
1598 int tx_cleaned = 0;
1599
1600 spin_lock(&nic->cb_lock);
1601
1602 DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
1603 nic->cb_to_clean->status);
1604
1605 /* Clean CBs marked complete */
1606 for(cb = nic->cb_to_clean;
1607 cb->status & cpu_to_le16(cb_complete);
1608 cb = nic->cb_to_clean = cb->next) {
1609 if(likely(cb->skb != NULL)) {
1610 nic->net_stats.tx_packets++;
1611 nic->net_stats.tx_bytes += cb->skb->len;
1612
1613 pci_unmap_single(nic->pdev,
1614 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1615 le16_to_cpu(cb->u.tcb.tbd.size),
1616 PCI_DMA_TODEVICE);
1617 dev_kfree_skb_any(cb->skb);
1618 cb->skb = NULL;
1619 tx_cleaned = 1;
1620 }
1621 cb->status = 0;
1622 nic->cbs_avail++;
1623 }
1624
1625 spin_unlock(&nic->cb_lock);
1626
1627 /* Recover from running out of Tx resources in xmit_frame */
1628 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1629 netif_wake_queue(nic->netdev);
1630
1631 return tx_cleaned;
1632 }
1633
1634 static void e100_clean_cbs(struct nic *nic)
1635 {
1636 if(nic->cbs) {
1637 while(nic->cbs_avail != nic->params.cbs.count) {
1638 struct cb *cb = nic->cb_to_clean;
1639 if(cb->skb) {
1640 pci_unmap_single(nic->pdev,
1641 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1642 le16_to_cpu(cb->u.tcb.tbd.size),
1643 PCI_DMA_TODEVICE);
1644 dev_kfree_skb(cb->skb);
1645 }
1646 nic->cb_to_clean = nic->cb_to_clean->next;
1647 nic->cbs_avail++;
1648 }
1649 pci_free_consistent(nic->pdev,
1650 sizeof(struct cb) * nic->params.cbs.count,
1651 nic->cbs, nic->cbs_dma_addr);
1652 nic->cbs = NULL;
1653 nic->cbs_avail = 0;
1654 }
1655 nic->cuc_cmd = cuc_start;
1656 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1657 nic->cbs;
1658 }
1659
1660 static int e100_alloc_cbs(struct nic *nic)
1661 {
1662 struct cb *cb;
1663 unsigned int i, count = nic->params.cbs.count;
1664
1665 nic->cuc_cmd = cuc_start;
1666 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1667 nic->cbs_avail = 0;
1668
1669 nic->cbs = pci_alloc_consistent(nic->pdev,
1670 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1671 if(!nic->cbs)
1672 return -ENOMEM;
1673
1674 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1675 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1676 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1677
1678 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1679 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1680 ((i+1) % count) * sizeof(struct cb));
1681 cb->skb = NULL;
1682 }
1683
1684 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1685 nic->cbs_avail = count;
1686
1687 return 0;
1688 }
1689
1690 static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1691 {
1692 if(!nic->rxs) return;
1693 if(RU_SUSPENDED != nic->ru_running) return;
1694
1695 /* handle init time starts */
1696 if(!rx) rx = nic->rxs;
1697
1698 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1699 if(rx->skb) {
1700 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1701 nic->ru_running = RU_RUNNING;
1702 }
1703 }
1704
1705 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1706 static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1707 {
1708 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + NET_IP_ALIGN)))
1709 return -ENOMEM;
1710
1711 /* Align, init, and map the RFD. */
1712 rx->skb->dev = nic->netdev;
1713 skb_reserve(rx->skb, NET_IP_ALIGN);
1714 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1715 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1716 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1717
1718 if(pci_dma_mapping_error(rx->dma_addr)) {
1719 dev_kfree_skb_any(rx->skb);
1720 rx->skb = NULL;
1721 rx->dma_addr = 0;
1722 return -ENOMEM;
1723 }
1724
1725 /* Link the RFD to end of RFA by linking previous RFD to
1726 * this one, and clearing EL bit of previous. */
1727 if(rx->prev->skb) {
1728 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1729 put_unaligned(cpu_to_le32(rx->dma_addr),
1730 (u32 *)&prev_rfd->link);
1731 wmb();
1732 prev_rfd->command &= ~cpu_to_le16(cb_el);
1733 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1734 sizeof(struct rfd), PCI_DMA_TODEVICE);
1735 }
1736
1737 return 0;
1738 }
1739
1740 static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
1741 unsigned int *work_done, unsigned int work_to_do)
1742 {
1743 struct sk_buff *skb = rx->skb;
1744 struct rfd *rfd = (struct rfd *)skb->data;
1745 u16 rfd_status, actual_size;
1746
1747 if(unlikely(work_done && *work_done >= work_to_do))
1748 return -EAGAIN;
1749
1750 /* Need to sync before taking a peek at cb_complete bit */
1751 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1752 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1753 rfd_status = le16_to_cpu(rfd->status);
1754
1755 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1756
1757 /* If data isn't ready, nothing to indicate */
1758 if(unlikely(!(rfd_status & cb_complete)))
1759 return -ENODATA;
1760
1761 /* Get actual data size */
1762 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1763 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1764 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1765
1766 /* Get data */
1767 pci_unmap_single(nic->pdev, rx->dma_addr,
1768 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1769
1770 /* this allows for a fast restart without re-enabling interrupts */
1771 if(le16_to_cpu(rfd->command) & cb_el)
1772 nic->ru_running = RU_SUSPENDED;
1773
1774 /* Pull off the RFD and put the actual data (minus eth hdr) */
1775 skb_reserve(skb, sizeof(struct rfd));
1776 skb_put(skb, actual_size);
1777 skb->protocol = eth_type_trans(skb, nic->netdev);
1778
1779 if(unlikely(!(rfd_status & cb_ok))) {
1780 /* Don't indicate if hardware indicates errors */
1781 dev_kfree_skb_any(skb);
1782 } else if(actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1783 /* Don't indicate oversized frames */
1784 nic->rx_over_length_errors++;
1785 dev_kfree_skb_any(skb);
1786 } else {
1787 nic->net_stats.rx_packets++;
1788 nic->net_stats.rx_bytes += actual_size;
1789 nic->netdev->last_rx = jiffies;
1790 netif_receive_skb(skb);
1791 if(work_done)
1792 (*work_done)++;
1793 }
1794
1795 rx->skb = NULL;
1796
1797 return 0;
1798 }
1799
1800 static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1801 unsigned int work_to_do)
1802 {
1803 struct rx *rx;
1804 int restart_required = 0;
1805 struct rx *rx_to_start = NULL;
1806
1807 /* are we already rnr? then pay attention!!! this ensures that
1808 * the state machine progression never allows a start with a
1809 * partially cleaned list, avoiding a race between hardware
1810 * and rx_to_clean when in NAPI mode */
1811 if(RU_SUSPENDED == nic->ru_running)
1812 restart_required = 1;
1813
1814 /* Indicate newly arrived packets */
1815 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1816 int err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1817 if(-EAGAIN == err) {
1818 /* hit quota so have more work to do, restart once
1819 * cleanup is complete */
1820 restart_required = 0;
1821 break;
1822 } else if(-ENODATA == err)
1823 break; /* No more to clean */
1824 }
1825
1826 /* save our starting point as the place we'll restart the receiver */
1827 if(restart_required)
1828 rx_to_start = nic->rx_to_clean;
1829
1830 /* Alloc new skbs to refill list */
1831 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1832 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1833 break; /* Better luck next time (see watchdog) */
1834 }
1835
1836 if(restart_required) {
1837 // ack the rnr?
1838 writeb(stat_ack_rnr, &nic->csr->scb.stat_ack);
1839 e100_start_receiver(nic, rx_to_start);
1840 if(work_done)
1841 (*work_done)++;
1842 }
1843 }
1844
1845 static void e100_rx_clean_list(struct nic *nic)
1846 {
1847 struct rx *rx;
1848 unsigned int i, count = nic->params.rfds.count;
1849
1850 nic->ru_running = RU_UNINITIALIZED;
1851
1852 if(nic->rxs) {
1853 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1854 if(rx->skb) {
1855 pci_unmap_single(nic->pdev, rx->dma_addr,
1856 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1857 dev_kfree_skb(rx->skb);
1858 }
1859 }
1860 kfree(nic->rxs);
1861 nic->rxs = NULL;
1862 }
1863
1864 nic->rx_to_use = nic->rx_to_clean = NULL;
1865 }
1866
1867 static int e100_rx_alloc_list(struct nic *nic)
1868 {
1869 struct rx *rx;
1870 unsigned int i, count = nic->params.rfds.count;
1871
1872 nic->rx_to_use = nic->rx_to_clean = NULL;
1873 nic->ru_running = RU_UNINITIALIZED;
1874
1875 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1876 return -ENOMEM;
1877 memset(nic->rxs, 0, sizeof(struct rx) * count);
1878
1879 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1880 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1881 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1882 if(e100_rx_alloc_skb(nic, rx)) {
1883 e100_rx_clean_list(nic);
1884 return -ENOMEM;
1885 }
1886 }
1887
1888 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1889 nic->ru_running = RU_SUSPENDED;
1890
1891 return 0;
1892 }
1893
1894 static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1895 {
1896 struct net_device *netdev = dev_id;
1897 struct nic *nic = netdev_priv(netdev);
1898 u8 stat_ack = readb(&nic->csr->scb.stat_ack);
1899
1900 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1901
1902 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
1903 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1904 return IRQ_NONE;
1905
1906 /* Ack interrupt(s) */
1907 writeb(stat_ack, &nic->csr->scb.stat_ack);
1908
1909 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1910 if(stat_ack & stat_ack_rnr)
1911 nic->ru_running = RU_SUSPENDED;
1912
1913 if(likely(netif_rx_schedule_prep(netdev))) {
1914 e100_disable_irq(nic);
1915 __netif_rx_schedule(netdev);
1916 }
1917
1918 return IRQ_HANDLED;
1919 }
1920
1921 static int e100_poll(struct net_device *netdev, int *budget)
1922 {
1923 struct nic *nic = netdev_priv(netdev);
1924 unsigned int work_to_do = min(netdev->quota, *budget);
1925 unsigned int work_done = 0;
1926 int tx_cleaned;
1927
1928 e100_rx_clean(nic, &work_done, work_to_do);
1929 tx_cleaned = e100_tx_clean(nic);
1930
1931 /* If no Rx and Tx cleanup work was done, exit polling mode. */
1932 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
1933 netif_rx_complete(netdev);
1934 e100_enable_irq(nic);
1935 return 0;
1936 }
1937
1938 *budget -= work_done;
1939 netdev->quota -= work_done;
1940
1941 return 1;
1942 }
1943
1944 #ifdef CONFIG_NET_POLL_CONTROLLER
1945 static void e100_netpoll(struct net_device *netdev)
1946 {
1947 struct nic *nic = netdev_priv(netdev);
1948
1949 e100_disable_irq(nic);
1950 e100_intr(nic->pdev->irq, netdev, NULL);
1951 e100_tx_clean(nic);
1952 e100_enable_irq(nic);
1953 }
1954 #endif
1955
1956 static struct net_device_stats *e100_get_stats(struct net_device *netdev)
1957 {
1958 struct nic *nic = netdev_priv(netdev);
1959 return &nic->net_stats;
1960 }
1961
1962 static int e100_set_mac_address(struct net_device *netdev, void *p)
1963 {
1964 struct nic *nic = netdev_priv(netdev);
1965 struct sockaddr *addr = p;
1966
1967 if (!is_valid_ether_addr(addr->sa_data))
1968 return -EADDRNOTAVAIL;
1969
1970 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1971 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
1972
1973 return 0;
1974 }
1975
1976 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
1977 {
1978 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
1979 return -EINVAL;
1980 netdev->mtu = new_mtu;
1981 return 0;
1982 }
1983
1984 #ifdef CONFIG_PM
1985 static int e100_asf(struct nic *nic)
1986 {
1987 /* ASF can be enabled from eeprom */
1988 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
1989 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
1990 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
1991 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
1992 }
1993 #endif
1994
1995 static int e100_up(struct nic *nic)
1996 {
1997 int err;
1998
1999 if((err = e100_rx_alloc_list(nic)))
2000 return err;
2001 if((err = e100_alloc_cbs(nic)))
2002 goto err_rx_clean_list;
2003 if((err = e100_hw_init(nic)))
2004 goto err_clean_cbs;
2005 e100_set_multicast_list(nic->netdev);
2006 e100_start_receiver(nic, NULL);
2007 mod_timer(&nic->watchdog, jiffies);
2008 if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
2009 nic->netdev->name, nic->netdev)))
2010 goto err_no_irq;
2011 netif_wake_queue(nic->netdev);
2012 netif_poll_enable(nic->netdev);
2013 /* enable ints _after_ enabling poll, preventing a race between
2014 * disable ints+schedule */
2015 e100_enable_irq(nic);
2016 return 0;
2017
2018 err_no_irq:
2019 del_timer_sync(&nic->watchdog);
2020 err_clean_cbs:
2021 e100_clean_cbs(nic);
2022 err_rx_clean_list:
2023 e100_rx_clean_list(nic);
2024 return err;
2025 }
2026
2027 static void e100_down(struct nic *nic)
2028 {
2029 /* wait here for poll to complete */
2030 netif_poll_disable(nic->netdev);
2031 netif_stop_queue(nic->netdev);
2032 e100_hw_reset(nic);
2033 free_irq(nic->pdev->irq, nic->netdev);
2034 del_timer_sync(&nic->watchdog);
2035 netif_carrier_off(nic->netdev);
2036 e100_clean_cbs(nic);
2037 e100_rx_clean_list(nic);
2038 }
2039
2040 static void e100_tx_timeout(struct net_device *netdev)
2041 {
2042 struct nic *nic = netdev_priv(netdev);
2043
2044 /* Reset outside of interrupt context, to avoid request_irq
2045 * in interrupt context */
2046 schedule_work(&nic->tx_timeout_task);
2047 }
2048
2049 static void e100_tx_timeout_task(struct net_device *netdev)
2050 {
2051 struct nic *nic = netdev_priv(netdev);
2052
2053 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2054 readb(&nic->csr->scb.status));
2055 e100_down(netdev_priv(netdev));
2056 e100_up(netdev_priv(netdev));
2057 }
2058
2059 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2060 {
2061 int err;
2062 struct sk_buff *skb;
2063
2064 /* Use driver resources to perform internal MAC or PHY
2065 * loopback test. A single packet is prepared and transmitted
2066 * in loopback mode, and the test passes if the received
2067 * packet compares byte-for-byte to the transmitted packet. */
2068
2069 if((err = e100_rx_alloc_list(nic)))
2070 return err;
2071 if((err = e100_alloc_cbs(nic)))
2072 goto err_clean_rx;
2073
2074 /* ICH PHY loopback is broken so do MAC loopback instead */
2075 if(nic->flags & ich && loopback_mode == lb_phy)
2076 loopback_mode = lb_mac;
2077
2078 nic->loopback = loopback_mode;
2079 if((err = e100_hw_init(nic)))
2080 goto err_loopback_none;
2081
2082 if(loopback_mode == lb_phy)
2083 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2084 BMCR_LOOPBACK);
2085
2086 e100_start_receiver(nic, NULL);
2087
2088 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
2089 err = -ENOMEM;
2090 goto err_loopback_none;
2091 }
2092 skb_put(skb, ETH_DATA_LEN);
2093 memset(skb->data, 0xFF, ETH_DATA_LEN);
2094 e100_xmit_frame(skb, nic->netdev);
2095
2096 msleep(10);
2097
2098 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2099 skb->data, ETH_DATA_LEN))
2100 err = -EAGAIN;
2101
2102 err_loopback_none:
2103 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2104 nic->loopback = lb_none;
2105 e100_hw_init(nic);
2106 e100_clean_cbs(nic);
2107 err_clean_rx:
2108 e100_rx_clean_list(nic);
2109 return err;
2110 }
2111
2112 #define MII_LED_CONTROL 0x1B
2113 static void e100_blink_led(unsigned long data)
2114 {
2115 struct nic *nic = (struct nic *)data;
2116 enum led_state {
2117 led_on = 0x01,
2118 led_off = 0x04,
2119 led_on_559 = 0x05,
2120 led_on_557 = 0x07,
2121 };
2122
2123 nic->leds = (nic->leds & led_on) ? led_off :
2124 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2125 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
2126 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2127 }
2128
2129 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2130 {
2131 struct nic *nic = netdev_priv(netdev);
2132 return mii_ethtool_gset(&nic->mii, cmd);
2133 }
2134
2135 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2136 {
2137 struct nic *nic = netdev_priv(netdev);
2138 int err;
2139
2140 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2141 err = mii_ethtool_sset(&nic->mii, cmd);
2142 e100_exec_cb(nic, NULL, e100_configure);
2143
2144 return err;
2145 }
2146
2147 static void e100_get_drvinfo(struct net_device *netdev,
2148 struct ethtool_drvinfo *info)
2149 {
2150 struct nic *nic = netdev_priv(netdev);
2151 strcpy(info->driver, DRV_NAME);
2152 strcpy(info->version, DRV_VERSION);
2153 strcpy(info->fw_version, "N/A");
2154 strcpy(info->bus_info, pci_name(nic->pdev));
2155 }
2156
2157 static int e100_get_regs_len(struct net_device *netdev)
2158 {
2159 struct nic *nic = netdev_priv(netdev);
2160 #define E100_PHY_REGS 0x1C
2161 #define E100_REGS_LEN 1 + E100_PHY_REGS + \
2162 sizeof(nic->mem->dump_buf) / sizeof(u32)
2163 return E100_REGS_LEN * sizeof(u32);
2164 }
2165
2166 static void e100_get_regs(struct net_device *netdev,
2167 struct ethtool_regs *regs, void *p)
2168 {
2169 struct nic *nic = netdev_priv(netdev);
2170 u32 *buff = p;
2171 int i;
2172
2173 regs->version = (1 << 24) | nic->rev_id;
2174 buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
2175 readb(&nic->csr->scb.cmd_lo) << 16 |
2176 readw(&nic->csr->scb.status);
2177 for(i = E100_PHY_REGS; i >= 0; i--)
2178 buff[1 + E100_PHY_REGS - i] =
2179 mdio_read(netdev, nic->mii.phy_id, i);
2180 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2181 e100_exec_cb(nic, NULL, e100_dump);
2182 msleep(10);
2183 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2184 sizeof(nic->mem->dump_buf));
2185 }
2186
2187 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2188 {
2189 struct nic *nic = netdev_priv(netdev);
2190 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2191 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2192 }
2193
2194 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2195 {
2196 struct nic *nic = netdev_priv(netdev);
2197
2198 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2199 return -EOPNOTSUPP;
2200
2201 if(wol->wolopts)
2202 nic->flags |= wol_magic;
2203 else
2204 nic->flags &= ~wol_magic;
2205
2206 e100_exec_cb(nic, NULL, e100_configure);
2207
2208 return 0;
2209 }
2210
2211 static u32 e100_get_msglevel(struct net_device *netdev)
2212 {
2213 struct nic *nic = netdev_priv(netdev);
2214 return nic->msg_enable;
2215 }
2216
2217 static void e100_set_msglevel(struct net_device *netdev, u32 value)
2218 {
2219 struct nic *nic = netdev_priv(netdev);
2220 nic->msg_enable = value;
2221 }
2222
2223 static int e100_nway_reset(struct net_device *netdev)
2224 {
2225 struct nic *nic = netdev_priv(netdev);
2226 return mii_nway_restart(&nic->mii);
2227 }
2228
2229 static u32 e100_get_link(struct net_device *netdev)
2230 {
2231 struct nic *nic = netdev_priv(netdev);
2232 return mii_link_ok(&nic->mii);
2233 }
2234
2235 static int e100_get_eeprom_len(struct net_device *netdev)
2236 {
2237 struct nic *nic = netdev_priv(netdev);
2238 return nic->eeprom_wc << 1;
2239 }
2240
2241 #define E100_EEPROM_MAGIC 0x1234
2242 static int e100_get_eeprom(struct net_device *netdev,
2243 struct ethtool_eeprom *eeprom, u8 *bytes)
2244 {
2245 struct nic *nic = netdev_priv(netdev);
2246
2247 eeprom->magic = E100_EEPROM_MAGIC;
2248 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2249
2250 return 0;
2251 }
2252
2253 static int e100_set_eeprom(struct net_device *netdev,
2254 struct ethtool_eeprom *eeprom, u8 *bytes)
2255 {
2256 struct nic *nic = netdev_priv(netdev);
2257
2258 if(eeprom->magic != E100_EEPROM_MAGIC)
2259 return -EINVAL;
2260
2261 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2262
2263 return e100_eeprom_save(nic, eeprom->offset >> 1,
2264 (eeprom->len >> 1) + 1);
2265 }
2266
2267 static void e100_get_ringparam(struct net_device *netdev,
2268 struct ethtool_ringparam *ring)
2269 {
2270 struct nic *nic = netdev_priv(netdev);
2271 struct param_range *rfds = &nic->params.rfds;
2272 struct param_range *cbs = &nic->params.cbs;
2273
2274 ring->rx_max_pending = rfds->max;
2275 ring->tx_max_pending = cbs->max;
2276 ring->rx_mini_max_pending = 0;
2277 ring->rx_jumbo_max_pending = 0;
2278 ring->rx_pending = rfds->count;
2279 ring->tx_pending = cbs->count;
2280 ring->rx_mini_pending = 0;
2281 ring->rx_jumbo_pending = 0;
2282 }
2283
2284 static int e100_set_ringparam(struct net_device *netdev,
2285 struct ethtool_ringparam *ring)
2286 {
2287 struct nic *nic = netdev_priv(netdev);
2288 struct param_range *rfds = &nic->params.rfds;
2289 struct param_range *cbs = &nic->params.cbs;
2290
2291 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2292 return -EINVAL;
2293
2294 if(netif_running(netdev))
2295 e100_down(nic);
2296 rfds->count = max(ring->rx_pending, rfds->min);
2297 rfds->count = min(rfds->count, rfds->max);
2298 cbs->count = max(ring->tx_pending, cbs->min);
2299 cbs->count = min(cbs->count, cbs->max);
2300 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2301 rfds->count, cbs->count);
2302 if(netif_running(netdev))
2303 e100_up(nic);
2304
2305 return 0;
2306 }
2307
2308 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2309 "Link test (on/offline)",
2310 "Eeprom test (on/offline)",
2311 "Self test (offline)",
2312 "Mac loopback (offline)",
2313 "Phy loopback (offline)",
2314 };
2315 #define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
2316
2317 static int e100_diag_test_count(struct net_device *netdev)
2318 {
2319 return E100_TEST_LEN;
2320 }
2321
2322 static void e100_diag_test(struct net_device *netdev,
2323 struct ethtool_test *test, u64 *data)
2324 {
2325 struct ethtool_cmd cmd;
2326 struct nic *nic = netdev_priv(netdev);
2327 int i, err;
2328
2329 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2330 data[0] = !mii_link_ok(&nic->mii);
2331 data[1] = e100_eeprom_load(nic);
2332 if(test->flags & ETH_TEST_FL_OFFLINE) {
2333
2334 /* save speed, duplex & autoneg settings */
2335 err = mii_ethtool_gset(&nic->mii, &cmd);
2336
2337 if(netif_running(netdev))
2338 e100_down(nic);
2339 data[2] = e100_self_test(nic);
2340 data[3] = e100_loopback_test(nic, lb_mac);
2341 data[4] = e100_loopback_test(nic, lb_phy);
2342
2343 /* restore speed, duplex & autoneg settings */
2344 err = mii_ethtool_sset(&nic->mii, &cmd);
2345
2346 if(netif_running(netdev))
2347 e100_up(nic);
2348 }
2349 for(i = 0; i < E100_TEST_LEN; i++)
2350 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2351
2352 msleep_interruptible(4 * 1000);
2353 }
2354
2355 static int e100_phys_id(struct net_device *netdev, u32 data)
2356 {
2357 struct nic *nic = netdev_priv(netdev);
2358
2359 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2360 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2361 mod_timer(&nic->blink_timer, jiffies);
2362 msleep_interruptible(data * 1000);
2363 del_timer_sync(&nic->blink_timer);
2364 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
2365
2366 return 0;
2367 }
2368
2369 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2370 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2371 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2372 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2373 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2374 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2375 "tx_heartbeat_errors", "tx_window_errors",
2376 /* device-specific stats */
2377 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2378 "tx_flow_control_pause", "rx_flow_control_pause",
2379 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2380 };
2381 #define E100_NET_STATS_LEN 21
2382 #define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
2383
2384 static int e100_get_stats_count(struct net_device *netdev)
2385 {
2386 return E100_STATS_LEN;
2387 }
2388
2389 static void e100_get_ethtool_stats(struct net_device *netdev,
2390 struct ethtool_stats *stats, u64 *data)
2391 {
2392 struct nic *nic = netdev_priv(netdev);
2393 int i;
2394
2395 for(i = 0; i < E100_NET_STATS_LEN; i++)
2396 data[i] = ((unsigned long *)&nic->net_stats)[i];
2397
2398 data[i++] = nic->tx_deferred;
2399 data[i++] = nic->tx_single_collisions;
2400 data[i++] = nic->tx_multiple_collisions;
2401 data[i++] = nic->tx_fc_pause;
2402 data[i++] = nic->rx_fc_pause;
2403 data[i++] = nic->rx_fc_unsupported;
2404 data[i++] = nic->tx_tco_frames;
2405 data[i++] = nic->rx_tco_frames;
2406 }
2407
2408 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2409 {
2410 switch(stringset) {
2411 case ETH_SS_TEST:
2412 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2413 break;
2414 case ETH_SS_STATS:
2415 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2416 break;
2417 }
2418 }
2419
2420 static struct ethtool_ops e100_ethtool_ops = {
2421 .get_settings = e100_get_settings,
2422 .set_settings = e100_set_settings,
2423 .get_drvinfo = e100_get_drvinfo,
2424 .get_regs_len = e100_get_regs_len,
2425 .get_regs = e100_get_regs,
2426 .get_wol = e100_get_wol,
2427 .set_wol = e100_set_wol,
2428 .get_msglevel = e100_get_msglevel,
2429 .set_msglevel = e100_set_msglevel,
2430 .nway_reset = e100_nway_reset,
2431 .get_link = e100_get_link,
2432 .get_eeprom_len = e100_get_eeprom_len,
2433 .get_eeprom = e100_get_eeprom,
2434 .set_eeprom = e100_set_eeprom,
2435 .get_ringparam = e100_get_ringparam,
2436 .set_ringparam = e100_set_ringparam,
2437 .self_test_count = e100_diag_test_count,
2438 .self_test = e100_diag_test,
2439 .get_strings = e100_get_strings,
2440 .phys_id = e100_phys_id,
2441 .get_stats_count = e100_get_stats_count,
2442 .get_ethtool_stats = e100_get_ethtool_stats,
2443 .get_perm_addr = ethtool_op_get_perm_addr,
2444 };
2445
2446 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2447 {
2448 struct nic *nic = netdev_priv(netdev);
2449
2450 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2451 }
2452
2453 static int e100_alloc(struct nic *nic)
2454 {
2455 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2456 &nic->dma_addr);
2457 return nic->mem ? 0 : -ENOMEM;
2458 }
2459
2460 static void e100_free(struct nic *nic)
2461 {
2462 if(nic->mem) {
2463 pci_free_consistent(nic->pdev, sizeof(struct mem),
2464 nic->mem, nic->dma_addr);
2465 nic->mem = NULL;
2466 }
2467 }
2468
2469 static int e100_open(struct net_device *netdev)
2470 {
2471 struct nic *nic = netdev_priv(netdev);
2472 int err = 0;
2473
2474 netif_carrier_off(netdev);
2475 if((err = e100_up(nic)))
2476 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2477 return err;
2478 }
2479
2480 static int e100_close(struct net_device *netdev)
2481 {
2482 e100_down(netdev_priv(netdev));
2483 return 0;
2484 }
2485
2486 static int __devinit e100_probe(struct pci_dev *pdev,
2487 const struct pci_device_id *ent)
2488 {
2489 struct net_device *netdev;
2490 struct nic *nic;
2491 int err;
2492
2493 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2494 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2495 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2496 return -ENOMEM;
2497 }
2498
2499 netdev->open = e100_open;
2500 netdev->stop = e100_close;
2501 netdev->hard_start_xmit = e100_xmit_frame;
2502 netdev->get_stats = e100_get_stats;
2503 netdev->set_multicast_list = e100_set_multicast_list;
2504 netdev->set_mac_address = e100_set_mac_address;
2505 netdev->change_mtu = e100_change_mtu;
2506 netdev->do_ioctl = e100_do_ioctl;
2507 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2508 netdev->tx_timeout = e100_tx_timeout;
2509 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2510 netdev->poll = e100_poll;
2511 netdev->weight = E100_NAPI_WEIGHT;
2512 #ifdef CONFIG_NET_POLL_CONTROLLER
2513 netdev->poll_controller = e100_netpoll;
2514 #endif
2515 strcpy(netdev->name, pci_name(pdev));
2516
2517 nic = netdev_priv(netdev);
2518 nic->netdev = netdev;
2519 nic->pdev = pdev;
2520 nic->msg_enable = (1 << debug) - 1;
2521 pci_set_drvdata(pdev, netdev);
2522
2523 if((err = pci_enable_device(pdev))) {
2524 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2525 goto err_out_free_dev;
2526 }
2527
2528 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2529 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2530 "base address, aborting.\n");
2531 err = -ENODEV;
2532 goto err_out_disable_pdev;
2533 }
2534
2535 if((err = pci_request_regions(pdev, DRV_NAME))) {
2536 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2537 goto err_out_disable_pdev;
2538 }
2539
2540 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
2541 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2542 goto err_out_free_res;
2543 }
2544
2545 SET_MODULE_OWNER(netdev);
2546 SET_NETDEV_DEV(netdev, &pdev->dev);
2547
2548 nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
2549 if(!nic->csr) {
2550 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2551 err = -ENOMEM;
2552 goto err_out_free_res;
2553 }
2554
2555 if(ent->driver_data)
2556 nic->flags |= ich;
2557 else
2558 nic->flags &= ~ich;
2559
2560 e100_get_defaults(nic);
2561
2562 /* locks must be initialized before calling hw_reset */
2563 spin_lock_init(&nic->cb_lock);
2564 spin_lock_init(&nic->cmd_lock);
2565
2566 /* Reset the device before pci_set_master() in case device is in some
2567 * funky state and has an interrupt pending - hint: we don't have the
2568 * interrupt handler registered yet. */
2569 e100_hw_reset(nic);
2570
2571 pci_set_master(pdev);
2572
2573 init_timer(&nic->watchdog);
2574 nic->watchdog.function = e100_watchdog;
2575 nic->watchdog.data = (unsigned long)nic;
2576 init_timer(&nic->blink_timer);
2577 nic->blink_timer.function = e100_blink_led;
2578 nic->blink_timer.data = (unsigned long)nic;
2579
2580 INIT_WORK(&nic->tx_timeout_task,
2581 (void (*)(void *))e100_tx_timeout_task, netdev);
2582
2583 if((err = e100_alloc(nic))) {
2584 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2585 goto err_out_iounmap;
2586 }
2587
2588 if((err = e100_eeprom_load(nic)))
2589 goto err_out_free;
2590
2591 e100_phy_init(nic);
2592
2593 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2594 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2595 if(!is_valid_ether_addr(netdev->perm_addr)) {
2596 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2597 "EEPROM, aborting.\n");
2598 err = -EAGAIN;
2599 goto err_out_free;
2600 }
2601
2602 /* Wol magic packet can be enabled from eeprom */
2603 if((nic->mac >= mac_82558_D101_A4) &&
2604 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2605 nic->flags |= wol_magic;
2606
2607 /* ack any pending wake events, disable PME */
2608 pci_enable_wake(pdev, 0, 0);
2609
2610 strcpy(netdev->name, "eth%d");
2611 if((err = register_netdev(netdev))) {
2612 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2613 goto err_out_free;
2614 }
2615
2616 DPRINTK(PROBE, INFO, "addr 0x%lx, irq %d, "
2617 "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
2618 pci_resource_start(pdev, 0), pdev->irq,
2619 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2620 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2621
2622 return 0;
2623
2624 err_out_free:
2625 e100_free(nic);
2626 err_out_iounmap:
2627 iounmap(nic->csr);
2628 err_out_free_res:
2629 pci_release_regions(pdev);
2630 err_out_disable_pdev:
2631 pci_disable_device(pdev);
2632 err_out_free_dev:
2633 pci_set_drvdata(pdev, NULL);
2634 free_netdev(netdev);
2635 return err;
2636 }
2637
2638 static void __devexit e100_remove(struct pci_dev *pdev)
2639 {
2640 struct net_device *netdev = pci_get_drvdata(pdev);
2641
2642 if(netdev) {
2643 struct nic *nic = netdev_priv(netdev);
2644 unregister_netdev(netdev);
2645 e100_free(nic);
2646 iounmap(nic->csr);
2647 free_netdev(netdev);
2648 pci_release_regions(pdev);
2649 pci_disable_device(pdev);
2650 pci_set_drvdata(pdev, NULL);
2651 }
2652 }
2653
2654 #ifdef CONFIG_PM
2655 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2656 {
2657 struct net_device *netdev = pci_get_drvdata(pdev);
2658 struct nic *nic = netdev_priv(netdev);
2659
2660 if(netif_running(netdev))
2661 e100_down(nic);
2662 e100_hw_reset(nic);
2663 netif_device_detach(netdev);
2664
2665 pci_save_state(pdev);
2666 pci_enable_wake(pdev, pci_choose_state(pdev, state), nic->flags & (wol_magic | e100_asf(nic)));
2667 pci_disable_device(pdev);
2668 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2669
2670 return 0;
2671 }
2672
2673 static int e100_resume(struct pci_dev *pdev)
2674 {
2675 struct net_device *netdev = pci_get_drvdata(pdev);
2676 struct nic *nic = netdev_priv(netdev);
2677
2678 pci_set_power_state(pdev, PCI_D0);
2679 pci_restore_state(pdev);
2680 /* ack any pending wake events, disable PME */
2681 pci_enable_wake(pdev, 0, 0);
2682 if(e100_hw_init(nic))
2683 DPRINTK(HW, ERR, "e100_hw_init failed\n");
2684
2685 netif_device_attach(netdev);
2686 if(netif_running(netdev))
2687 e100_up(nic);
2688
2689 return 0;
2690 }
2691 #endif
2692
2693
2694 static void e100_shutdown(struct pci_dev *pdev)
2695 {
2696 struct net_device *netdev = pci_get_drvdata(pdev);
2697 struct nic *nic = netdev_priv(netdev);
2698
2699 #ifdef CONFIG_PM
2700 pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
2701 #else
2702 pci_enable_wake(pdev, 0, nic->flags & (wol_magic));
2703 #endif
2704 }
2705
2706
2707 static struct pci_driver e100_driver = {
2708 .name = DRV_NAME,
2709 .id_table = e100_id_table,
2710 .probe = e100_probe,
2711 .remove = __devexit_p(e100_remove),
2712 #ifdef CONFIG_PM
2713 .suspend = e100_suspend,
2714 .resume = e100_resume,
2715 #endif
2716 .shutdown = e100_shutdown,
2717 };
2718
2719 static int __init e100_init_module(void)
2720 {
2721 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2722 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2723 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2724 }
2725 return pci_module_init(&e100_driver);
2726 }
2727
2728 static void __exit e100_cleanup_module(void)
2729 {
2730 pci_unregister_driver(&e100_driver);
2731 }
2732
2733 module_init(e100_init_module);
2734 module_exit(e100_cleanup_module);
kernel-based virtual machine