?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mips: fix bitops
[linux-2.6/kvm.git] / include / asm-mips / bitops.h
blob5478d947e28902d581e1c50998b23800b13aacde
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (c) 1999, 2000 Silicon Graphics, Inc.
8 */
9 #ifndef _ASM_BITOPS_H
10 #define _ASM_BITOPS_H
11
12 #include <linux/compiler.h>
13 #include <linux/irqflags.h>
14 #include <linux/types.h>
15 #include <asm/barrier.h>
16 #include <asm/bug.h>
17 #include <asm/byteorder.h> /* sigh ... */
18 #include <asm/cpu-features.h>
19 #include <asm/sgidefs.h>
20 #include <asm/war.h>
21
22 #if _MIPS_SZLONG == 32
23 #define SZLONG_LOG 5
24 #define SZLONG_MASK 31UL
25 #define __LL "ll "
26 #define __SC "sc "
27 #define __INS "ins "
28 #define __EXT "ext "
29 #elif _MIPS_SZLONG == 64
30 #define SZLONG_LOG 6
31 #define SZLONG_MASK 63UL
32 #define __LL "lld "
33 #define __SC "scd "
34 #define __INS "dins "
35 #define __EXT "dext "
36 #endif
37
38 /*
39 * clear_bit() doesn't provide any barrier for the compiler.
40 */
41 #define smp_mb__before_clear_bit() smp_llsc_mb()
42 #define smp_mb__after_clear_bit() smp_llsc_mb()
43
44 /*
45 * set_bit - Atomically set a bit in memory
46 * @nr: the bit to set
47 * @addr: the address to start counting from
48 *
49 * This function is atomic and may not be reordered. See __set_bit()
50 * if you do not require the atomic guarantees.
51 * Note that @nr may be almost arbitrarily large; this function is not
52 * restricted to acting on a single-word quantity.
53 */
54 static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
55 {
56 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
57 unsigned short bit = nr & SZLONG_MASK;
58 unsigned long temp;
59
60 if (cpu_has_llsc && R10000_LLSC_WAR) {
61 __asm__ __volatile__(
62 " .set mips3 \n"
63 "1: " __LL "%0, %1 # set_bit \n"
64 " or %0, %2 \n"
65 " " __SC "%0, %1 \n"
66 " beqzl %0, 1b \n"
67 " .set mips0 \n"
68 : "=&r" (temp), "=m" (*m)
69 : "ir" (1UL << bit), "m" (*m));
70 #ifdef CONFIG_CPU_MIPSR2
71 } else if (__builtin_constant_p(bit)) {
72 __asm__ __volatile__(
73 "1: " __LL "%0, %1 # set_bit \n"
74 " " __INS "%0, %4, %2, 1 \n"
75 " " __SC "%0, %1 \n"
76 " beqz %0, 2f \n"
77 " .subsection 2 \n"
78 "2: b 1b \n"
79 " .previous \n"
80 : "=&r" (temp), "=m" (*m)
81 : "ir" (bit), "m" (*m), "r" (~0));
82 #endif /* CONFIG_CPU_MIPSR2 */
83 } else if (cpu_has_llsc) {
84 __asm__ __volatile__(
85 " .set mips3 \n"
86 "1: " __LL "%0, %1 # set_bit \n"
87 " or %0, %2 \n"
88 " " __SC "%0, %1 \n"
89 " beqz %0, 2f \n"
90 " .subsection 2 \n"
91 "2: b 1b \n"
92 " .previous \n"
93 " .set mips0 \n"
94 : "=&r" (temp), "=m" (*m)
95 : "ir" (1UL << bit), "m" (*m));
96 } else {
97 volatile unsigned long *a = addr;
98 unsigned long mask;
99 unsigned long flags;
100
101 a += nr >> SZLONG_LOG;
102 mask = 1UL << bit;
103 raw_local_irq_save(flags);
104 *a |= mask;
105 raw_local_irq_restore(flags);
106 }
107 }
108
109 /*
110 * clear_bit - Clears a bit in memory
111 * @nr: Bit to clear
112 * @addr: Address to start counting from
113 *
114 * clear_bit() is atomic and may not be reordered. However, it does
115 * not contain a memory barrier, so if it is used for locking purposes,
116 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
117 * in order to ensure changes are visible on other processors.
118 */
119 static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
120 {
121 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
122 unsigned short bit = nr & SZLONG_MASK;
123 unsigned long temp;
124
125 if (cpu_has_llsc && R10000_LLSC_WAR) {
126 __asm__ __volatile__(
127 " .set mips3 \n"
128 "1: " __LL "%0, %1 # clear_bit \n"
129 " and %0, %2 \n"
130 " " __SC "%0, %1 \n"
131 " beqzl %0, 1b \n"
132 " .set mips0 \n"
133 : "=&r" (temp), "=m" (*m)
134 : "ir" (~(1UL << bit)), "m" (*m));
135 #ifdef CONFIG_CPU_MIPSR2
136 } else if (__builtin_constant_p(bit)) {
137 __asm__ __volatile__(
138 "1: " __LL "%0, %1 # clear_bit \n"
139 " " __INS "%0, $0, %2, 1 \n"
140 " " __SC "%0, %1 \n"
141 " beqz %0, 2f \n"
142 " .subsection 2 \n"
143 "2: b 1b \n"
144 " .previous \n"
145 : "=&r" (temp), "=m" (*m)
146 : "ir" (bit), "m" (*m));
147 #endif /* CONFIG_CPU_MIPSR2 */
148 } else if (cpu_has_llsc) {
149 __asm__ __volatile__(
150 " .set mips3 \n"
151 "1: " __LL "%0, %1 # clear_bit \n"
152 " and %0, %2 \n"
153 " " __SC "%0, %1 \n"
154 " beqz %0, 2f \n"
155 " .subsection 2 \n"
156 "2: b 1b \n"
157 " .previous \n"
158 " .set mips0 \n"
159 : "=&r" (temp), "=m" (*m)
160 : "ir" (~(1UL << bit)), "m" (*m));
161 } else {
162 volatile unsigned long *a = addr;
163 unsigned long mask;
164 unsigned long flags;
165
166 a += nr >> SZLONG_LOG;
167 mask = 1UL << bit;
168 raw_local_irq_save(flags);
169 *a &= ~mask;
170 raw_local_irq_restore(flags);
171 }
172 }
173
174 /*
175 * change_bit - Toggle a bit in memory
176 * @nr: Bit to change
177 * @addr: Address to start counting from
178 *
179 * change_bit() is atomic and may not be reordered.
180 * Note that @nr may be almost arbitrarily large; this function is not
181 * restricted to acting on a single-word quantity.
182 */
183 static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
184 {
185 unsigned short bit = nr & SZLONG_MASK;
186
187 if (cpu_has_llsc && R10000_LLSC_WAR) {
188 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
189 unsigned long temp;
190
191 __asm__ __volatile__(
192 " .set mips3 \n"
193 "1: " __LL "%0, %1 # change_bit \n"
194 " xor %0, %2 \n"
195 " " __SC "%0, %1 \n"
196 " beqzl %0, 1b \n"
197 " .set mips0 \n"
198 : "=&r" (temp), "=m" (*m)
199 : "ir" (1UL << bit), "m" (*m));
200 } else if (cpu_has_llsc) {
201 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
202 unsigned long temp;
203
204 __asm__ __volatile__(
205 " .set mips3 \n"
206 "1: " __LL "%0, %1 # change_bit \n"
207 " xor %0, %2 \n"
208 " " __SC "%0, %1 \n"
209 " beqz %0, 2f \n"
210 " .subsection 2 \n"
211 "2: b 1b \n"
212 " .previous \n"
213 " .set mips0 \n"
214 : "=&r" (temp), "=m" (*m)
215 : "ir" (1UL << bit), "m" (*m));
216 } else {
217 volatile unsigned long *a = addr;
218 unsigned long mask;
219 unsigned long flags;
220
221 a += nr >> SZLONG_LOG;
222 mask = 1UL << bit;
223 raw_local_irq_save(flags);
224 *a ^= mask;
225 raw_local_irq_restore(flags);
226 }
227 }
228
229 /*
230 * test_and_set_bit - Set a bit and return its old value
231 * @nr: Bit to set
232 * @addr: Address to count from
233 *
234 * This operation is atomic and cannot be reordered.
235 * It also implies a memory barrier.
236 */
237 static inline int test_and_set_bit(unsigned long nr,
238 volatile unsigned long *addr)
239 {
240 unsigned short bit = nr & SZLONG_MASK;
241 unsigned long res;
242
243 smp_llsc_mb();
244
245 if (cpu_has_llsc && R10000_LLSC_WAR) {
246 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
247 unsigned long temp;
248
249 __asm__ __volatile__(
250 " .set mips3 \n"
251 "1: " __LL "%0, %1 # test_and_set_bit \n"
252 " or %2, %0, %3 \n"
253 " " __SC "%2, %1 \n"
254 " beqzl %2, 1b \n"
255 " and %2, %0, %3 \n"
256 " .set mips0 \n"
257 : "=&r" (temp), "=m" (*m), "=&r" (res)
258 : "r" (1UL << bit), "m" (*m)
259 : "memory");
260 } else if (cpu_has_llsc) {
261 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
262 unsigned long temp;
263
264 __asm__ __volatile__(
265 " .set push \n"
266 " .set noreorder \n"
267 " .set mips3 \n"
268 "1: " __LL "%0, %1 # test_and_set_bit \n"
269 " or %2, %0, %3 \n"
270 " " __SC "%2, %1 \n"
271 " beqz %2, 2f \n"
272 " and %2, %0, %3 \n"
273 " .subsection 2 \n"
274 "2: b 1b \n"
275 " nop \n"
276 " .previous \n"
277 " .set pop \n"
278 : "=&r" (temp), "=m" (*m), "=&r" (res)
279 : "r" (1UL << bit), "m" (*m)
280 : "memory");
281 } else {
282 volatile unsigned long *a = addr;
283 unsigned long mask;
284 unsigned long flags;
285
286 a += nr >> SZLONG_LOG;
287 mask = 1UL << bit;
288 raw_local_irq_save(flags);
289 res = (mask & *a);
290 *a |= mask;
291 raw_local_irq_restore(flags);
292 }
293
294 smp_llsc_mb();
295
296 return res != 0;
297 }
298
299 /*
300 * test_and_clear_bit - Clear a bit and return its old value
301 * @nr: Bit to clear
302 * @addr: Address to count from
303 *
304 * This operation is atomic and cannot be reordered.
305 * It also implies a memory barrier.
306 */
307 static inline int test_and_clear_bit(unsigned long nr,
308 volatile unsigned long *addr)
309 {
310 unsigned short bit = nr & SZLONG_MASK;
311 unsigned long res;
312
313 smp_llsc_mb();
314
315 if (cpu_has_llsc && R10000_LLSC_WAR) {
316 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
317 unsigned long temp;
318
319 __asm__ __volatile__(
320 " .set mips3 \n"
321 "1: " __LL "%0, %1 # test_and_clear_bit \n"
322 " or %2, %0, %3 \n"
323 " xor %2, %3 \n"
324 " " __SC "%2, %1 \n"
325 " beqzl %2, 1b \n"
326 " and %2, %0, %3 \n"
327 " .set mips0 \n"
328 : "=&r" (temp), "=m" (*m), "=&r" (res)
329 : "r" (1UL << bit), "m" (*m)
330 : "memory");
331 #ifdef CONFIG_CPU_MIPSR2
332 } else if (__builtin_constant_p(nr)) {
333 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
334 unsigned long temp;
335
336 __asm__ __volatile__(
337 "1: " __LL "%0, %1 # test_and_clear_bit \n"
338 " " __EXT "%2, %0, %3, 1 \n"
339 " " __INS "%0, $0, %3, 1 \n"
340 " " __SC "%0, %1 \n"
341 " beqz %0, 2f \n"
342 " .subsection 2 \n"
343 "2: b 1b \n"
344 " .previous \n"
345 : "=&r" (temp), "=m" (*m), "=&r" (res)
346 : "ri" (bit), "m" (*m)
347 : "memory");
348 #endif
349 } else if (cpu_has_llsc) {
350 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
351 unsigned long temp;
352
353 __asm__ __volatile__(
354 " .set push \n"
355 " .set noreorder \n"
356 " .set mips3 \n"
357 "1: " __LL "%0, %1 # test_and_clear_bit \n"
358 " or %2, %0, %3 \n"
359 " xor %2, %3 \n"
360 " " __SC "%2, %1 \n"
361 " beqz %2, 2f \n"
362 " and %2, %0, %3 \n"
363 " .subsection 2 \n"
364 "2: b 1b \n"
365 " nop \n"
366 " .previous \n"
367 " .set pop \n"
368 : "=&r" (temp), "=m" (*m), "=&r" (res)
369 : "r" (1UL << bit), "m" (*m)
370 : "memory");
371 } else {
372 volatile unsigned long *a = addr;
373 unsigned long mask;
374 unsigned long flags;
375
376 a += nr >> SZLONG_LOG;
377 mask = 1UL << bit;
378 raw_local_irq_save(flags);
379 res = (mask & *a);
380 *a &= ~mask;
381 raw_local_irq_restore(flags);
382 }
383
384 smp_llsc_mb();
385
386 return res != 0;
387 }
388
389 /*
390 * test_and_change_bit - Change a bit and return its old value
391 * @nr: Bit to change
392 * @addr: Address to count from
393 *
394 * This operation is atomic and cannot be reordered.
395 * It also implies a memory barrier.
396 */
397 static inline int test_and_change_bit(unsigned long nr,
398 volatile unsigned long *addr)
399 {
400 unsigned short bit = nr & SZLONG_MASK;
401 unsigned long res;
402
403 smp_llsc_mb();
404
405 if (cpu_has_llsc && R10000_LLSC_WAR) {
406 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
407 unsigned long temp;
408
409 __asm__ __volatile__(
410 " .set mips3 \n"
411 "1: " __LL "%0, %1 # test_and_change_bit \n"
412 " xor %2, %0, %3 \n"
413 " " __SC "%2, %1 \n"
414 " beqzl %2, 1b \n"
415 " and %2, %0, %3 \n"
416 " .set mips0 \n"
417 : "=&r" (temp), "=m" (*m), "=&r" (res)
418 : "r" (1UL << bit), "m" (*m)
419 : "memory");
420 } else if (cpu_has_llsc) {
421 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
422 unsigned long temp;
423
424 __asm__ __volatile__(
425 " .set push \n"
426 " .set noreorder \n"
427 " .set mips3 \n"
428 "1: " __LL "%0, %1 # test_and_change_bit \n"
429 " xor %2, %0, %3 \n"
430 " " __SC "\t%2, %1 \n"
431 " beqz %2, 2f \n"
432 " and %2, %0, %3 \n"
433 " .subsection 2 \n"
434 "2: b 1b \n"
435 " nop \n"
436 " .previous \n"
437 " .set pop \n"
438 : "=&r" (temp), "=m" (*m), "=&r" (res)
439 : "r" (1UL << bit), "m" (*m)
440 : "memory");
441 } else {
442 volatile unsigned long *a = addr;
443 unsigned long mask;
444 unsigned long flags;
445
446 a += nr >> SZLONG_LOG;
447 mask = 1UL << bit;
448 raw_local_irq_save(flags);
449 res = (mask & *a);
450 *a ^= mask;
451 raw_local_irq_restore(flags);
452 }
453
454 smp_llsc_mb();
455
456 return res != 0;
457 }
458
459 #include <asm-generic/bitops/non-atomic.h>
460
461 /*
462 * Return the bit position (0..63) of the most significant 1 bit in a word
463 * Returns -1 if no 1 bit exists
464 */
465 static inline int __ilog2(unsigned long x)
466 {
467 int lz;
468
469 if (sizeof(x) == 4) {
470 __asm__(
471 " .set push \n"
472 " .set mips32 \n"
473 " clz %0, %1 \n"
474 " .set pop \n"
475 : "=r" (lz)
476 : "r" (x));
477
478 return 31 - lz;
479 }
480
481 BUG_ON(sizeof(x) != 8);
482
483 __asm__(
484 " .set push \n"
485 " .set mips64 \n"
486 " dclz %0, %1 \n"
487 " .set pop \n"
488 : "=r" (lz)
489 : "r" (x));
490
491 return 63 - lz;
492 }
493
494 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
495
496 /*
497 * __ffs - find first bit in word.
498 * @word: The word to search
499 *
500 * Returns 0..SZLONG-1
501 * Undefined if no bit exists, so code should check against 0 first.
502 */
503 static inline unsigned long __ffs(unsigned long word)
504 {
505 return __ilog2(word & -word);
506 }
507
508 /*
509 * fls - find last bit set.
510 * @word: The word to search
511 *
512 * This is defined the same way as ffs.
513 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
514 */
515 static inline int fls(int word)
516 {
517 __asm__("clz %0, %1" : "=r" (word) : "r" (word));
518
519 return 32 - word;
520 }
521
522 #if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
523 static inline int fls64(__u64 word)
524 {
525 __asm__("dclz %0, %1" : "=r" (word) : "r" (word));
526
527 return 64 - word;
528 }
529 #else
530 #include <asm-generic/bitops/fls64.h>
531 #endif
532
533 /*
534 * ffs - find first bit set.
535 * @word: The word to search
536 *
537 * This is defined the same way as
538 * the libc and compiler builtin ffs routines, therefore
539 * differs in spirit from the above ffz (man ffs).
540 */
541 static inline int ffs(int word)
542 {
543 if (!word)
544 return 0;
545
546 return fls(word & -word);
547 }
548
549 #else
550
551 #include <asm-generic/bitops/__ffs.h>
552 #include <asm-generic/bitops/ffs.h>
553 #include <asm-generic/bitops/fls.h>
554 #include <asm-generic/bitops/fls64.h>
555
556 #endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
557
558 #include <asm-generic/bitops/ffz.h>
559 #include <asm-generic/bitops/find.h>
560
561 #ifdef __KERNEL__
562
563 #include <asm-generic/bitops/sched.h>
564 #include <asm-generic/bitops/hweight.h>
565 #include <asm-generic/bitops/lock.h>
566 #include <asm-generic/bitops/ext2-non-atomic.h>
567 #include <asm-generic/bitops/ext2-atomic.h>
568 #include <asm-generic/bitops/minix.h>
569
570 #endif /* __KERNEL__ */
571
572 #endif /* _ASM_BITOPS_H */
kernel-based virtual machine