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igb: add support for 82576 quad copper adapter
[linux-2.6/kvm.git] / drivers / net / igb / igb_main.c
blob7124f59fb99fdb59527da0be1fc0776b1c04f6ef
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/pci-aspm.h>
43 #include <linux/delay.h>
44 #include <linux/interrupt.h>
45 #include <linux/if_ether.h>
46 #include <linux/aer.h>
47 #ifdef CONFIG_IGB_DCA
48 #include <linux/dca.h>
49 #endif
50 #include "igb.h"
51
52 #define DRV_VERSION "1.3.16-k2"
53 char igb_driver_name[] = "igb";
54 char igb_driver_version[] = DRV_VERSION;
55 static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
58
59 static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61 };
62
63 static struct pci_device_id igb_pci_tbl[] = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
72 /* required last entry */
73 {0, }
74 };
75
76 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
77
78 void igb_reset(struct igb_adapter *);
79 static int igb_setup_all_tx_resources(struct igb_adapter *);
80 static int igb_setup_all_rx_resources(struct igb_adapter *);
81 static void igb_free_all_tx_resources(struct igb_adapter *);
82 static void igb_free_all_rx_resources(struct igb_adapter *);
83 void igb_update_stats(struct igb_adapter *);
84 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
85 static void __devexit igb_remove(struct pci_dev *pdev);
86 static int igb_sw_init(struct igb_adapter *);
87 static int igb_open(struct net_device *);
88 static int igb_close(struct net_device *);
89 static void igb_configure_tx(struct igb_adapter *);
90 static void igb_configure_rx(struct igb_adapter *);
91 static void igb_setup_rctl(struct igb_adapter *);
92 static void igb_clean_all_tx_rings(struct igb_adapter *);
93 static void igb_clean_all_rx_rings(struct igb_adapter *);
94 static void igb_clean_tx_ring(struct igb_ring *);
95 static void igb_clean_rx_ring(struct igb_ring *);
96 static void igb_set_multi(struct net_device *);
97 static void igb_update_phy_info(unsigned long);
98 static void igb_watchdog(unsigned long);
99 static void igb_watchdog_task(struct work_struct *);
100 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
101 struct igb_ring *);
102 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
103 static struct net_device_stats *igb_get_stats(struct net_device *);
104 static int igb_change_mtu(struct net_device *, int);
105 static int igb_set_mac(struct net_device *, void *);
106 static irqreturn_t igb_intr(int irq, void *);
107 static irqreturn_t igb_intr_msi(int irq, void *);
108 static irqreturn_t igb_msix_other(int irq, void *);
109 static irqreturn_t igb_msix_rx(int irq, void *);
110 static irqreturn_t igb_msix_tx(int irq, void *);
111 #ifdef CONFIG_IGB_DCA
112 static void igb_update_rx_dca(struct igb_ring *);
113 static void igb_update_tx_dca(struct igb_ring *);
114 static void igb_setup_dca(struct igb_adapter *);
115 #endif /* CONFIG_IGB_DCA */
116 static bool igb_clean_tx_irq(struct igb_ring *);
117 static int igb_poll(struct napi_struct *, int);
118 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
119 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
120 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
121 static void igb_tx_timeout(struct net_device *);
122 static void igb_reset_task(struct work_struct *);
123 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
124 static void igb_vlan_rx_add_vid(struct net_device *, u16);
125 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
126 static void igb_restore_vlan(struct igb_adapter *);
127 static void igb_ping_all_vfs(struct igb_adapter *);
128 static void igb_msg_task(struct igb_adapter *);
129 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
130 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
131 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
132 static void igb_vmm_control(struct igb_adapter *);
133 static inline void igb_set_vmolr(struct e1000_hw *, int);
134 static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
137
138 static int igb_suspend(struct pci_dev *, pm_message_t);
139 #ifdef CONFIG_PM
140 static int igb_resume(struct pci_dev *);
141 #endif
142 static void igb_shutdown(struct pci_dev *);
143 #ifdef CONFIG_IGB_DCA
144 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
145 static struct notifier_block dca_notifier = {
146 .notifier_call = igb_notify_dca,
147 .next = NULL,
148 .priority = 0
149 };
150 #endif
151 #ifdef CONFIG_NET_POLL_CONTROLLER
152 /* for netdump / net console */
153 static void igb_netpoll(struct net_device *);
154 #endif
155
156 #ifdef CONFIG_PCI_IOV
157 static ssize_t igb_set_num_vfs(struct device *, struct device_attribute *,
158 const char *, size_t);
159 static ssize_t igb_show_num_vfs(struct device *, struct device_attribute *,
160 char *);
161 DEVICE_ATTR(num_vfs, S_IRUGO | S_IWUSR, igb_show_num_vfs, igb_set_num_vfs);
162 #endif
163 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
164 pci_channel_state_t);
165 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
166 static void igb_io_resume(struct pci_dev *);
167
168 static struct pci_error_handlers igb_err_handler = {
169 .error_detected = igb_io_error_detected,
170 .slot_reset = igb_io_slot_reset,
171 .resume = igb_io_resume,
172 };
173
174
175 static struct pci_driver igb_driver = {
176 .name = igb_driver_name,
177 .id_table = igb_pci_tbl,
178 .probe = igb_probe,
179 .remove = __devexit_p(igb_remove),
180 #ifdef CONFIG_PM
181 /* Power Managment Hooks */
182 .suspend = igb_suspend,
183 .resume = igb_resume,
184 #endif
185 .shutdown = igb_shutdown,
186 .err_handler = &igb_err_handler
187 };
188
189 static int global_quad_port_a; /* global quad port a indication */
190
191 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
192 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
193 MODULE_LICENSE("GPL");
194 MODULE_VERSION(DRV_VERSION);
195
196 /**
197 * Scale the NIC clock cycle by a large factor so that
198 * relatively small clock corrections can be added or
199 * substracted at each clock tick. The drawbacks of a
200 * large factor are a) that the clock register overflows
201 * more quickly (not such a big deal) and b) that the
202 * increment per tick has to fit into 24 bits.
203 *
204 * Note that
205 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
206 * IGB_TSYNC_SCALE
207 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
208 *
209 * The base scale factor is intentionally a power of two
210 * so that the division in %struct timecounter can be done with
211 * a shift.
212 */
213 #define IGB_TSYNC_SHIFT (19)
214 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
215
216 /**
217 * The duration of one clock cycle of the NIC.
218 *
219 * @todo This hard-coded value is part of the specification and might change
220 * in future hardware revisions. Add revision check.
221 */
222 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
223
224 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
225 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
226 #endif
227
228 /**
229 * igb_read_clock - read raw cycle counter (to be used by time counter)
230 */
231 static cycle_t igb_read_clock(const struct cyclecounter *tc)
232 {
233 struct igb_adapter *adapter =
234 container_of(tc, struct igb_adapter, cycles);
235 struct e1000_hw *hw = &adapter->hw;
236 u64 stamp;
237
238 stamp = rd32(E1000_SYSTIML);
239 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
240
241 return stamp;
242 }
243
244 #ifdef DEBUG
245 /**
246 * igb_get_hw_dev_name - return device name string
247 * used by hardware layer to print debugging information
248 **/
249 char *igb_get_hw_dev_name(struct e1000_hw *hw)
250 {
251 struct igb_adapter *adapter = hw->back;
252 return adapter->netdev->name;
253 }
254
255 /**
256 * igb_get_time_str - format current NIC and system time as string
257 */
258 static char *igb_get_time_str(struct igb_adapter *adapter,
259 char buffer[160])
260 {
261 cycle_t hw = adapter->cycles.read(&adapter->cycles);
262 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
263 struct timespec sys;
264 struct timespec delta;
265 getnstimeofday(&sys);
266
267 delta = timespec_sub(nic, sys);
268
269 sprintf(buffer,
270 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
271 hw,
272 (long)nic.tv_sec, nic.tv_nsec,
273 (long)sys.tv_sec, sys.tv_nsec,
274 (long)delta.tv_sec, delta.tv_nsec);
275
276 return buffer;
277 }
278 #endif
279
280 /**
281 * igb_init_module - Driver Registration Routine
282 *
283 * igb_init_module is the first routine called when the driver is
284 * loaded. All it does is register with the PCI subsystem.
285 **/
286 static int __init igb_init_module(void)
287 {
288 int ret;
289 printk(KERN_INFO "%s - version %s\n",
290 igb_driver_string, igb_driver_version);
291
292 printk(KERN_INFO "%s\n", igb_copyright);
293
294 global_quad_port_a = 0;
295
296 #ifdef CONFIG_IGB_DCA
297 dca_register_notify(&dca_notifier);
298 #endif
299
300 ret = pci_register_driver(&igb_driver);
301 return ret;
302 }
303
304 module_init(igb_init_module);
305
306 /**
307 * igb_exit_module - Driver Exit Cleanup Routine
308 *
309 * igb_exit_module is called just before the driver is removed
310 * from memory.
311 **/
312 static void __exit igb_exit_module(void)
313 {
314 #ifdef CONFIG_IGB_DCA
315 dca_unregister_notify(&dca_notifier);
316 #endif
317 pci_unregister_driver(&igb_driver);
318 }
319
320 module_exit(igb_exit_module);
321
322 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
323 /**
324 * igb_cache_ring_register - Descriptor ring to register mapping
325 * @adapter: board private structure to initialize
326 *
327 * Once we know the feature-set enabled for the device, we'll cache
328 * the register offset the descriptor ring is assigned to.
329 **/
330 static void igb_cache_ring_register(struct igb_adapter *adapter)
331 {
332 int i;
333 unsigned int rbase_offset = adapter->vfs_allocated_count;
334
335 switch (adapter->hw.mac.type) {
336 case e1000_82576:
337 /* The queues are allocated for virtualization such that VF 0
338 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
339 * In order to avoid collision we start at the first free queue
340 * and continue consuming queues in the same sequence
341 */
342 for (i = 0; i < adapter->num_rx_queues; i++)
343 adapter->rx_ring[i].reg_idx = rbase_offset +
344 Q_IDX_82576(i);
345 for (i = 0; i < adapter->num_tx_queues; i++)
346 adapter->tx_ring[i].reg_idx = rbase_offset +
347 Q_IDX_82576(i);
348 break;
349 case e1000_82575:
350 default:
351 for (i = 0; i < adapter->num_rx_queues; i++)
352 adapter->rx_ring[i].reg_idx = i;
353 for (i = 0; i < adapter->num_tx_queues; i++)
354 adapter->tx_ring[i].reg_idx = i;
355 break;
356 }
357 }
358
359 /**
360 * igb_alloc_queues - Allocate memory for all rings
361 * @adapter: board private structure to initialize
362 *
363 * We allocate one ring per queue at run-time since we don't know the
364 * number of queues at compile-time.
365 **/
366 static int igb_alloc_queues(struct igb_adapter *adapter)
367 {
368 int i;
369
370 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
371 sizeof(struct igb_ring), GFP_KERNEL);
372 if (!adapter->tx_ring)
373 return -ENOMEM;
374
375 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
376 sizeof(struct igb_ring), GFP_KERNEL);
377 if (!adapter->rx_ring) {
378 kfree(adapter->tx_ring);
379 return -ENOMEM;
380 }
381
382 adapter->rx_ring->buddy = adapter->tx_ring;
383
384 for (i = 0; i < adapter->num_tx_queues; i++) {
385 struct igb_ring *ring = &(adapter->tx_ring[i]);
386 ring->count = adapter->tx_ring_count;
387 ring->adapter = adapter;
388 ring->queue_index = i;
389 }
390 for (i = 0; i < adapter->num_rx_queues; i++) {
391 struct igb_ring *ring = &(adapter->rx_ring[i]);
392 ring->count = adapter->rx_ring_count;
393 ring->adapter = adapter;
394 ring->queue_index = i;
395 ring->itr_register = E1000_ITR;
396
397 /* set a default napi handler for each rx_ring */
398 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
399 }
400
401 igb_cache_ring_register(adapter);
402 return 0;
403 }
404
405 static void igb_free_queues(struct igb_adapter *adapter)
406 {
407 int i;
408
409 for (i = 0; i < adapter->num_rx_queues; i++)
410 netif_napi_del(&adapter->rx_ring[i].napi);
411
412 kfree(adapter->tx_ring);
413 kfree(adapter->rx_ring);
414 }
415
416 #define IGB_N0_QUEUE -1
417 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
418 int tx_queue, int msix_vector)
419 {
420 u32 msixbm = 0;
421 struct e1000_hw *hw = &adapter->hw;
422 u32 ivar, index;
423
424 switch (hw->mac.type) {
425 case e1000_82575:
426 /* The 82575 assigns vectors using a bitmask, which matches the
427 bitmask for the EICR/EIMS/EIMC registers. To assign one
428 or more queues to a vector, we write the appropriate bits
429 into the MSIXBM register for that vector. */
430 if (rx_queue > IGB_N0_QUEUE) {
431 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
432 adapter->rx_ring[rx_queue].eims_value = msixbm;
433 }
434 if (tx_queue > IGB_N0_QUEUE) {
435 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
436 adapter->tx_ring[tx_queue].eims_value =
437 E1000_EICR_TX_QUEUE0 << tx_queue;
438 }
439 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
440 break;
441 case e1000_82576:
442 /* 82576 uses a table-based method for assigning vectors.
443 Each queue has a single entry in the table to which we write
444 a vector number along with a "valid" bit. Sadly, the layout
445 of the table is somewhat counterintuitive. */
446 if (rx_queue > IGB_N0_QUEUE) {
447 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
448 ivar = array_rd32(E1000_IVAR0, index);
449 if (rx_queue & 0x1) {
450 /* vector goes into third byte of register */
451 ivar = ivar & 0xFF00FFFF;
452 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
453 } else {
454 /* vector goes into low byte of register */
455 ivar = ivar & 0xFFFFFF00;
456 ivar |= msix_vector | E1000_IVAR_VALID;
457 }
458 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
459 array_wr32(E1000_IVAR0, index, ivar);
460 }
461 if (tx_queue > IGB_N0_QUEUE) {
462 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
463 ivar = array_rd32(E1000_IVAR0, index);
464 if (tx_queue & 0x1) {
465 /* vector goes into high byte of register */
466 ivar = ivar & 0x00FFFFFF;
467 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
468 } else {
469 /* vector goes into second byte of register */
470 ivar = ivar & 0xFFFF00FF;
471 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
472 }
473 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
474 array_wr32(E1000_IVAR0, index, ivar);
475 }
476 break;
477 default:
478 BUG();
479 break;
480 }
481 }
482
483 /**
484 * igb_configure_msix - Configure MSI-X hardware
485 *
486 * igb_configure_msix sets up the hardware to properly
487 * generate MSI-X interrupts.
488 **/
489 static void igb_configure_msix(struct igb_adapter *adapter)
490 {
491 u32 tmp;
492 int i, vector = 0;
493 struct e1000_hw *hw = &adapter->hw;
494
495 adapter->eims_enable_mask = 0;
496 if (hw->mac.type == e1000_82576)
497 /* Turn on MSI-X capability first, or our settings
498 * won't stick. And it will take days to debug. */
499 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
500 E1000_GPIE_PBA | E1000_GPIE_EIAME |
501 E1000_GPIE_NSICR);
502
503 for (i = 0; i < adapter->num_tx_queues; i++) {
504 struct igb_ring *tx_ring = &adapter->tx_ring[i];
505 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
506 adapter->eims_enable_mask |= tx_ring->eims_value;
507 if (tx_ring->itr_val)
508 writel(tx_ring->itr_val,
509 hw->hw_addr + tx_ring->itr_register);
510 else
511 writel(1, hw->hw_addr + tx_ring->itr_register);
512 }
513
514 for (i = 0; i < adapter->num_rx_queues; i++) {
515 struct igb_ring *rx_ring = &adapter->rx_ring[i];
516 rx_ring->buddy = NULL;
517 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
518 adapter->eims_enable_mask |= rx_ring->eims_value;
519 if (rx_ring->itr_val)
520 writel(rx_ring->itr_val,
521 hw->hw_addr + rx_ring->itr_register);
522 else
523 writel(1, hw->hw_addr + rx_ring->itr_register);
524 }
525
526
527 /* set vector for other causes, i.e. link changes */
528 switch (hw->mac.type) {
529 case e1000_82575:
530 array_wr32(E1000_MSIXBM(0), vector++,
531 E1000_EIMS_OTHER);
532
533 tmp = rd32(E1000_CTRL_EXT);
534 /* enable MSI-X PBA support*/
535 tmp |= E1000_CTRL_EXT_PBA_CLR;
536
537 /* Auto-Mask interrupts upon ICR read. */
538 tmp |= E1000_CTRL_EXT_EIAME;
539 tmp |= E1000_CTRL_EXT_IRCA;
540
541 wr32(E1000_CTRL_EXT, tmp);
542 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
543 adapter->eims_other = E1000_EIMS_OTHER;
544
545 break;
546
547 case e1000_82576:
548 tmp = (vector++ | E1000_IVAR_VALID) << 8;
549 wr32(E1000_IVAR_MISC, tmp);
550
551 adapter->eims_enable_mask = (1 << (vector)) - 1;
552 adapter->eims_other = 1 << (vector - 1);
553 break;
554 default:
555 /* do nothing, since nothing else supports MSI-X */
556 break;
557 } /* switch (hw->mac.type) */
558 wrfl();
559 }
560
561 /**
562 * igb_request_msix - Initialize MSI-X interrupts
563 *
564 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
565 * kernel.
566 **/
567 static int igb_request_msix(struct igb_adapter *adapter)
568 {
569 struct net_device *netdev = adapter->netdev;
570 int i, err = 0, vector = 0;
571
572 vector = 0;
573
574 for (i = 0; i < adapter->num_tx_queues; i++) {
575 struct igb_ring *ring = &(adapter->tx_ring[i]);
576 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
577 err = request_irq(adapter->msix_entries[vector].vector,
578 &igb_msix_tx, 0, ring->name,
579 &(adapter->tx_ring[i]));
580 if (err)
581 goto out;
582 ring->itr_register = E1000_EITR(0) + (vector << 2);
583 ring->itr_val = 976; /* ~4000 ints/sec */
584 vector++;
585 }
586 for (i = 0; i < adapter->num_rx_queues; i++) {
587 struct igb_ring *ring = &(adapter->rx_ring[i]);
588 if (strlen(netdev->name) < (IFNAMSIZ - 5))
589 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
590 else
591 memcpy(ring->name, netdev->name, IFNAMSIZ);
592 err = request_irq(adapter->msix_entries[vector].vector,
593 &igb_msix_rx, 0, ring->name,
594 &(adapter->rx_ring[i]));
595 if (err)
596 goto out;
597 ring->itr_register = E1000_EITR(0) + (vector << 2);
598 ring->itr_val = adapter->itr;
599 vector++;
600 }
601
602 err = request_irq(adapter->msix_entries[vector].vector,
603 &igb_msix_other, 0, netdev->name, netdev);
604 if (err)
605 goto out;
606
607 igb_configure_msix(adapter);
608 return 0;
609 out:
610 return err;
611 }
612
613 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
614 {
615 if (adapter->msix_entries) {
616 pci_disable_msix(adapter->pdev);
617 kfree(adapter->msix_entries);
618 adapter->msix_entries = NULL;
619 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
620 pci_disable_msi(adapter->pdev);
621 return;
622 }
623
624
625 /**
626 * igb_set_interrupt_capability - set MSI or MSI-X if supported
627 *
628 * Attempt to configure interrupts using the best available
629 * capabilities of the hardware and kernel.
630 **/
631 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
632 {
633 int err;
634 int numvecs, i;
635
636 /* Number of supported queues. */
637 /* Having more queues than CPUs doesn't make sense. */
638 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
639 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
640
641 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
642 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
643 GFP_KERNEL);
644 if (!adapter->msix_entries)
645 goto msi_only;
646
647 for (i = 0; i < numvecs; i++)
648 adapter->msix_entries[i].entry = i;
649
650 err = pci_enable_msix(adapter->pdev,
651 adapter->msix_entries,
652 numvecs);
653 if (err == 0)
654 goto out;
655
656 igb_reset_interrupt_capability(adapter);
657
658 /* If we can't do MSI-X, try MSI */
659 msi_only:
660 adapter->num_rx_queues = 1;
661 adapter->num_tx_queues = 1;
662 if (!pci_enable_msi(adapter->pdev))
663 adapter->flags |= IGB_FLAG_HAS_MSI;
664 out:
665 /* Notify the stack of the (possibly) reduced Tx Queue count. */
666 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
667 return;
668 }
669
670 /**
671 * igb_request_irq - initialize interrupts
672 *
673 * Attempts to configure interrupts using the best available
674 * capabilities of the hardware and kernel.
675 **/
676 static int igb_request_irq(struct igb_adapter *adapter)
677 {
678 struct net_device *netdev = adapter->netdev;
679 struct e1000_hw *hw = &adapter->hw;
680 int err = 0;
681
682 if (adapter->msix_entries) {
683 err = igb_request_msix(adapter);
684 if (!err)
685 goto request_done;
686 /* fall back to MSI */
687 igb_reset_interrupt_capability(adapter);
688 if (!pci_enable_msi(adapter->pdev))
689 adapter->flags |= IGB_FLAG_HAS_MSI;
690 igb_free_all_tx_resources(adapter);
691 igb_free_all_rx_resources(adapter);
692 adapter->num_rx_queues = 1;
693 igb_alloc_queues(adapter);
694 } else {
695 switch (hw->mac.type) {
696 case e1000_82575:
697 wr32(E1000_MSIXBM(0),
698 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
699 break;
700 case e1000_82576:
701 wr32(E1000_IVAR0, E1000_IVAR_VALID);
702 break;
703 default:
704 break;
705 }
706 }
707
708 if (adapter->flags & IGB_FLAG_HAS_MSI) {
709 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
710 netdev->name, netdev);
711 if (!err)
712 goto request_done;
713 /* fall back to legacy interrupts */
714 igb_reset_interrupt_capability(adapter);
715 adapter->flags &= ~IGB_FLAG_HAS_MSI;
716 }
717
718 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
719 netdev->name, netdev);
720
721 if (err)
722 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
723 err);
724
725 request_done:
726 return err;
727 }
728
729 static void igb_free_irq(struct igb_adapter *adapter)
730 {
731 struct net_device *netdev = adapter->netdev;
732
733 if (adapter->msix_entries) {
734 int vector = 0, i;
735
736 for (i = 0; i < adapter->num_tx_queues; i++)
737 free_irq(adapter->msix_entries[vector++].vector,
738 &(adapter->tx_ring[i]));
739 for (i = 0; i < adapter->num_rx_queues; i++)
740 free_irq(adapter->msix_entries[vector++].vector,
741 &(adapter->rx_ring[i]));
742
743 free_irq(adapter->msix_entries[vector++].vector, netdev);
744 return;
745 }
746
747 free_irq(adapter->pdev->irq, netdev);
748 }
749
750 /**
751 * igb_irq_disable - Mask off interrupt generation on the NIC
752 * @adapter: board private structure
753 **/
754 static void igb_irq_disable(struct igb_adapter *adapter)
755 {
756 struct e1000_hw *hw = &adapter->hw;
757
758 if (adapter->msix_entries) {
759 wr32(E1000_EIAM, 0);
760 wr32(E1000_EIMC, ~0);
761 wr32(E1000_EIAC, 0);
762 }
763
764 wr32(E1000_IAM, 0);
765 wr32(E1000_IMC, ~0);
766 wrfl();
767 synchronize_irq(adapter->pdev->irq);
768 }
769
770 /**
771 * igb_irq_enable - Enable default interrupt generation settings
772 * @adapter: board private structure
773 **/
774 static void igb_irq_enable(struct igb_adapter *adapter)
775 {
776 struct e1000_hw *hw = &adapter->hw;
777
778 if (adapter->msix_entries) {
779 wr32(E1000_EIAC, adapter->eims_enable_mask);
780 wr32(E1000_EIAM, adapter->eims_enable_mask);
781 wr32(E1000_EIMS, adapter->eims_enable_mask);
782 if (adapter->vfs_allocated_count)
783 wr32(E1000_MBVFIMR, 0xFF);
784 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
785 E1000_IMS_DOUTSYNC));
786 } else {
787 wr32(E1000_IMS, IMS_ENABLE_MASK);
788 wr32(E1000_IAM, IMS_ENABLE_MASK);
789 }
790 }
791
792 static void igb_update_mng_vlan(struct igb_adapter *adapter)
793 {
794 struct net_device *netdev = adapter->netdev;
795 u16 vid = adapter->hw.mng_cookie.vlan_id;
796 u16 old_vid = adapter->mng_vlan_id;
797 if (adapter->vlgrp) {
798 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
799 if (adapter->hw.mng_cookie.status &
800 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
801 igb_vlan_rx_add_vid(netdev, vid);
802 adapter->mng_vlan_id = vid;
803 } else
804 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
805
806 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
807 (vid != old_vid) &&
808 !vlan_group_get_device(adapter->vlgrp, old_vid))
809 igb_vlan_rx_kill_vid(netdev, old_vid);
810 } else
811 adapter->mng_vlan_id = vid;
812 }
813 }
814
815 /**
816 * igb_release_hw_control - release control of the h/w to f/w
817 * @adapter: address of board private structure
818 *
819 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
820 * For ASF and Pass Through versions of f/w this means that the
821 * driver is no longer loaded.
822 *
823 **/
824 static void igb_release_hw_control(struct igb_adapter *adapter)
825 {
826 struct e1000_hw *hw = &adapter->hw;
827 u32 ctrl_ext;
828
829 /* Let firmware take over control of h/w */
830 ctrl_ext = rd32(E1000_CTRL_EXT);
831 wr32(E1000_CTRL_EXT,
832 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
833 }
834
835
836 /**
837 * igb_get_hw_control - get control of the h/w from f/w
838 * @adapter: address of board private structure
839 *
840 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
841 * For ASF and Pass Through versions of f/w this means that
842 * the driver is loaded.
843 *
844 **/
845 static void igb_get_hw_control(struct igb_adapter *adapter)
846 {
847 struct e1000_hw *hw = &adapter->hw;
848 u32 ctrl_ext;
849
850 /* Let firmware know the driver has taken over */
851 ctrl_ext = rd32(E1000_CTRL_EXT);
852 wr32(E1000_CTRL_EXT,
853 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
854 }
855
856 /**
857 * igb_configure - configure the hardware for RX and TX
858 * @adapter: private board structure
859 **/
860 static void igb_configure(struct igb_adapter *adapter)
861 {
862 struct net_device *netdev = adapter->netdev;
863 int i;
864
865 igb_get_hw_control(adapter);
866 igb_set_multi(netdev);
867
868 igb_restore_vlan(adapter);
869
870 igb_configure_tx(adapter);
871 igb_setup_rctl(adapter);
872 igb_configure_rx(adapter);
873
874 igb_rx_fifo_flush_82575(&adapter->hw);
875
876 /* call IGB_DESC_UNUSED which always leaves
877 * at least 1 descriptor unused to make sure
878 * next_to_use != next_to_clean */
879 for (i = 0; i < adapter->num_rx_queues; i++) {
880 struct igb_ring *ring = &adapter->rx_ring[i];
881 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
882 }
883
884
885 adapter->tx_queue_len = netdev->tx_queue_len;
886 }
887
888
889 /**
890 * igb_up - Open the interface and prepare it to handle traffic
891 * @adapter: board private structure
892 **/
893
894 int igb_up(struct igb_adapter *adapter)
895 {
896 struct e1000_hw *hw = &adapter->hw;
897 int i;
898
899 /* hardware has been reset, we need to reload some things */
900 igb_configure(adapter);
901
902 clear_bit(__IGB_DOWN, &adapter->state);
903
904 for (i = 0; i < adapter->num_rx_queues; i++)
905 napi_enable(&adapter->rx_ring[i].napi);
906 if (adapter->msix_entries)
907 igb_configure_msix(adapter);
908
909 igb_vmm_control(adapter);
910 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
911 igb_set_vmolr(hw, adapter->vfs_allocated_count);
912
913 /* Clear any pending interrupts. */
914 rd32(E1000_ICR);
915 igb_irq_enable(adapter);
916
917 /* Fire a link change interrupt to start the watchdog. */
918 wr32(E1000_ICS, E1000_ICS_LSC);
919 return 0;
920 }
921
922 void igb_down(struct igb_adapter *adapter)
923 {
924 struct e1000_hw *hw = &adapter->hw;
925 struct net_device *netdev = adapter->netdev;
926 u32 tctl, rctl;
927 int i;
928
929 /* signal that we're down so the interrupt handler does not
930 * reschedule our watchdog timer */
931 set_bit(__IGB_DOWN, &adapter->state);
932
933 /* disable receives in the hardware */
934 rctl = rd32(E1000_RCTL);
935 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
936 /* flush and sleep below */
937
938 netif_tx_stop_all_queues(netdev);
939
940 /* disable transmits in the hardware */
941 tctl = rd32(E1000_TCTL);
942 tctl &= ~E1000_TCTL_EN;
943 wr32(E1000_TCTL, tctl);
944 /* flush both disables and wait for them to finish */
945 wrfl();
946 msleep(10);
947
948 for (i = 0; i < adapter->num_rx_queues; i++)
949 napi_disable(&adapter->rx_ring[i].napi);
950
951 igb_irq_disable(adapter);
952
953 del_timer_sync(&adapter->watchdog_timer);
954 del_timer_sync(&adapter->phy_info_timer);
955
956 netdev->tx_queue_len = adapter->tx_queue_len;
957 netif_carrier_off(netdev);
958
959 /* record the stats before reset*/
960 igb_update_stats(adapter);
961
962 adapter->link_speed = 0;
963 adapter->link_duplex = 0;
964
965 if (!pci_channel_offline(adapter->pdev))
966 igb_reset(adapter);
967 igb_clean_all_tx_rings(adapter);
968 igb_clean_all_rx_rings(adapter);
969 }
970
971 void igb_reinit_locked(struct igb_adapter *adapter)
972 {
973 WARN_ON(in_interrupt());
974 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
975 msleep(1);
976 igb_down(adapter);
977 igb_up(adapter);
978 clear_bit(__IGB_RESETTING, &adapter->state);
979 }
980
981 void igb_reset(struct igb_adapter *adapter)
982 {
983 struct e1000_hw *hw = &adapter->hw;
984 struct e1000_mac_info *mac = &hw->mac;
985 struct e1000_fc_info *fc = &hw->fc;
986 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
987 u16 hwm;
988
989 /* Repartition Pba for greater than 9k mtu
990 * To take effect CTRL.RST is required.
991 */
992 switch (mac->type) {
993 case e1000_82576:
994 pba = E1000_PBA_64K;
995 break;
996 case e1000_82575:
997 default:
998 pba = E1000_PBA_34K;
999 break;
1000 }
1001
1002 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1003 (mac->type < e1000_82576)) {
1004 /* adjust PBA for jumbo frames */
1005 wr32(E1000_PBA, pba);
1006
1007 /* To maintain wire speed transmits, the Tx FIFO should be
1008 * large enough to accommodate two full transmit packets,
1009 * rounded up to the next 1KB and expressed in KB. Likewise,
1010 * the Rx FIFO should be large enough to accommodate at least
1011 * one full receive packet and is similarly rounded up and
1012 * expressed in KB. */
1013 pba = rd32(E1000_PBA);
1014 /* upper 16 bits has Tx packet buffer allocation size in KB */
1015 tx_space = pba >> 16;
1016 /* lower 16 bits has Rx packet buffer allocation size in KB */
1017 pba &= 0xffff;
1018 /* the tx fifo also stores 16 bytes of information about the tx
1019 * but don't include ethernet FCS because hardware appends it */
1020 min_tx_space = (adapter->max_frame_size +
1021 sizeof(union e1000_adv_tx_desc) -
1022 ETH_FCS_LEN) * 2;
1023 min_tx_space = ALIGN(min_tx_space, 1024);
1024 min_tx_space >>= 10;
1025 /* software strips receive CRC, so leave room for it */
1026 min_rx_space = adapter->max_frame_size;
1027 min_rx_space = ALIGN(min_rx_space, 1024);
1028 min_rx_space >>= 10;
1029
1030 /* If current Tx allocation is less than the min Tx FIFO size,
1031 * and the min Tx FIFO size is less than the current Rx FIFO
1032 * allocation, take space away from current Rx allocation */
1033 if (tx_space < min_tx_space &&
1034 ((min_tx_space - tx_space) < pba)) {
1035 pba = pba - (min_tx_space - tx_space);
1036
1037 /* if short on rx space, rx wins and must trump tx
1038 * adjustment */
1039 if (pba < min_rx_space)
1040 pba = min_rx_space;
1041 }
1042 wr32(E1000_PBA, pba);
1043 }
1044
1045 /* flow control settings */
1046 /* The high water mark must be low enough to fit one full frame
1047 * (or the size used for early receive) above it in the Rx FIFO.
1048 * Set it to the lower of:
1049 * - 90% of the Rx FIFO size, or
1050 * - the full Rx FIFO size minus one full frame */
1051 hwm = min(((pba << 10) * 9 / 10),
1052 ((pba << 10) - 2 * adapter->max_frame_size));
1053
1054 if (mac->type < e1000_82576) {
1055 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1056 fc->low_water = fc->high_water - 8;
1057 } else {
1058 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1059 fc->low_water = fc->high_water - 16;
1060 }
1061 fc->pause_time = 0xFFFF;
1062 fc->send_xon = 1;
1063 fc->type = fc->original_type;
1064
1065 /* disable receive for all VFs and wait one second */
1066 if (adapter->vfs_allocated_count) {
1067 int i;
1068 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1069 adapter->vf_data[i].clear_to_send = false;
1070
1071 /* ping all the active vfs to let them know we are going down */
1072 igb_ping_all_vfs(adapter);
1073
1074 /* disable transmits and receives */
1075 wr32(E1000_VFRE, 0);
1076 wr32(E1000_VFTE, 0);
1077 }
1078
1079 /* Allow time for pending master requests to run */
1080 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1081 wr32(E1000_WUC, 0);
1082
1083 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1084 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1085
1086 igb_update_mng_vlan(adapter);
1087
1088 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1089 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1090
1091 igb_reset_adaptive(&adapter->hw);
1092 igb_get_phy_info(&adapter->hw);
1093 }
1094
1095 static const struct net_device_ops igb_netdev_ops = {
1096 .ndo_open = igb_open,
1097 .ndo_stop = igb_close,
1098 .ndo_start_xmit = igb_xmit_frame_adv,
1099 .ndo_get_stats = igb_get_stats,
1100 .ndo_set_multicast_list = igb_set_multi,
1101 .ndo_set_mac_address = igb_set_mac,
1102 .ndo_change_mtu = igb_change_mtu,
1103 .ndo_do_ioctl = igb_ioctl,
1104 .ndo_tx_timeout = igb_tx_timeout,
1105 .ndo_validate_addr = eth_validate_addr,
1106 .ndo_vlan_rx_register = igb_vlan_rx_register,
1107 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1108 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1109 #ifdef CONFIG_NET_POLL_CONTROLLER
1110 .ndo_poll_controller = igb_netpoll,
1111 #endif
1112 };
1113
1114 /**
1115 * igb_probe - Device Initialization Routine
1116 * @pdev: PCI device information struct
1117 * @ent: entry in igb_pci_tbl
1118 *
1119 * Returns 0 on success, negative on failure
1120 *
1121 * igb_probe initializes an adapter identified by a pci_dev structure.
1122 * The OS initialization, configuring of the adapter private structure,
1123 * and a hardware reset occur.
1124 **/
1125 static int __devinit igb_probe(struct pci_dev *pdev,
1126 const struct pci_device_id *ent)
1127 {
1128 struct net_device *netdev;
1129 struct igb_adapter *adapter;
1130 struct e1000_hw *hw;
1131 struct pci_dev *us_dev;
1132 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1133 unsigned long mmio_start, mmio_len;
1134 int err, pci_using_dac, pos;
1135 u16 eeprom_data = 0, state = 0;
1136 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1137 u32 part_num;
1138
1139 err = pci_enable_device_mem(pdev);
1140 if (err)
1141 return err;
1142
1143 pci_using_dac = 0;
1144 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1145 if (!err) {
1146 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1147 if (!err)
1148 pci_using_dac = 1;
1149 } else {
1150 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1151 if (err) {
1152 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1153 if (err) {
1154 dev_err(&pdev->dev, "No usable DMA "
1155 "configuration, aborting\n");
1156 goto err_dma;
1157 }
1158 }
1159 }
1160
1161 /* 82575 requires that the pci-e link partner disable the L0s state */
1162 switch (pdev->device) {
1163 case E1000_DEV_ID_82575EB_COPPER:
1164 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1165 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1166 us_dev = pdev->bus->self;
1167 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1168 if (pos) {
1169 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1170 &state);
1171 state &= ~PCIE_LINK_STATE_L0S;
1172 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1173 state);
1174 dev_info(&pdev->dev,
1175 "Disabling ASPM L0s upstream switch port %s\n",
1176 pci_name(us_dev));
1177 }
1178 default:
1179 break;
1180 }
1181
1182 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1183 IORESOURCE_MEM),
1184 igb_driver_name);
1185 if (err)
1186 goto err_pci_reg;
1187
1188 err = pci_enable_pcie_error_reporting(pdev);
1189 if (err) {
1190 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1191 "0x%x\n", err);
1192 /* non-fatal, continue */
1193 }
1194
1195 pci_set_master(pdev);
1196 pci_save_state(pdev);
1197
1198 err = -ENOMEM;
1199 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1200 IGB_ABS_MAX_TX_QUEUES);
1201 if (!netdev)
1202 goto err_alloc_etherdev;
1203
1204 SET_NETDEV_DEV(netdev, &pdev->dev);
1205
1206 pci_set_drvdata(pdev, netdev);
1207 adapter = netdev_priv(netdev);
1208 adapter->netdev = netdev;
1209 adapter->pdev = pdev;
1210 hw = &adapter->hw;
1211 hw->back = adapter;
1212 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1213
1214 mmio_start = pci_resource_start(pdev, 0);
1215 mmio_len = pci_resource_len(pdev, 0);
1216
1217 err = -EIO;
1218 hw->hw_addr = ioremap(mmio_start, mmio_len);
1219 if (!hw->hw_addr)
1220 goto err_ioremap;
1221
1222 netdev->netdev_ops = &igb_netdev_ops;
1223 igb_set_ethtool_ops(netdev);
1224 netdev->watchdog_timeo = 5 * HZ;
1225
1226 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1227
1228 netdev->mem_start = mmio_start;
1229 netdev->mem_end = mmio_start + mmio_len;
1230
1231 /* PCI config space info */
1232 hw->vendor_id = pdev->vendor;
1233 hw->device_id = pdev->device;
1234 hw->revision_id = pdev->revision;
1235 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1236 hw->subsystem_device_id = pdev->subsystem_device;
1237
1238 /* setup the private structure */
1239 hw->back = adapter;
1240 /* Copy the default MAC, PHY and NVM function pointers */
1241 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1242 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1243 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1244 /* Initialize skew-specific constants */
1245 err = ei->get_invariants(hw);
1246 if (err)
1247 goto err_sw_init;
1248
1249 /* setup the private structure */
1250 err = igb_sw_init(adapter);
1251 if (err)
1252 goto err_sw_init;
1253
1254 igb_get_bus_info_pcie(hw);
1255
1256 /* set flags */
1257 switch (hw->mac.type) {
1258 case e1000_82575:
1259 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1260 break;
1261 case e1000_82576:
1262 default:
1263 break;
1264 }
1265
1266 hw->phy.autoneg_wait_to_complete = false;
1267 hw->mac.adaptive_ifs = true;
1268
1269 /* Copper options */
1270 if (hw->phy.media_type == e1000_media_type_copper) {
1271 hw->phy.mdix = AUTO_ALL_MODES;
1272 hw->phy.disable_polarity_correction = false;
1273 hw->phy.ms_type = e1000_ms_hw_default;
1274 }
1275
1276 if (igb_check_reset_block(hw))
1277 dev_info(&pdev->dev,
1278 "PHY reset is blocked due to SOL/IDER session.\n");
1279
1280 netdev->features = NETIF_F_SG |
1281 NETIF_F_IP_CSUM |
1282 NETIF_F_HW_VLAN_TX |
1283 NETIF_F_HW_VLAN_RX |
1284 NETIF_F_HW_VLAN_FILTER;
1285
1286 netdev->features |= NETIF_F_IPV6_CSUM;
1287 netdev->features |= NETIF_F_TSO;
1288 netdev->features |= NETIF_F_TSO6;
1289
1290 netdev->features |= NETIF_F_GRO;
1291
1292 netdev->vlan_features |= NETIF_F_TSO;
1293 netdev->vlan_features |= NETIF_F_TSO6;
1294 netdev->vlan_features |= NETIF_F_IP_CSUM;
1295 netdev->vlan_features |= NETIF_F_SG;
1296
1297 if (pci_using_dac)
1298 netdev->features |= NETIF_F_HIGHDMA;
1299
1300 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1301
1302 /* before reading the NVM, reset the controller to put the device in a
1303 * known good starting state */
1304 hw->mac.ops.reset_hw(hw);
1305
1306 /* make sure the NVM is good */
1307 if (igb_validate_nvm_checksum(hw) < 0) {
1308 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1309 err = -EIO;
1310 goto err_eeprom;
1311 }
1312
1313 /* copy the MAC address out of the NVM */
1314 if (hw->mac.ops.read_mac_addr(hw))
1315 dev_err(&pdev->dev, "NVM Read Error\n");
1316
1317 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1318 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1319
1320 if (!is_valid_ether_addr(netdev->perm_addr)) {
1321 dev_err(&pdev->dev, "Invalid MAC Address\n");
1322 err = -EIO;
1323 goto err_eeprom;
1324 }
1325
1326 init_timer(&adapter->watchdog_timer);
1327 adapter->watchdog_timer.function = &igb_watchdog;
1328 adapter->watchdog_timer.data = (unsigned long) adapter;
1329
1330 init_timer(&adapter->phy_info_timer);
1331 adapter->phy_info_timer.function = &igb_update_phy_info;
1332 adapter->phy_info_timer.data = (unsigned long) adapter;
1333
1334 INIT_WORK(&adapter->reset_task, igb_reset_task);
1335 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1336
1337 /* Initialize link properties that are user-changeable */
1338 adapter->fc_autoneg = true;
1339 hw->mac.autoneg = true;
1340 hw->phy.autoneg_advertised = 0x2f;
1341
1342 hw->fc.original_type = e1000_fc_default;
1343 hw->fc.type = e1000_fc_default;
1344
1345 adapter->itr_setting = IGB_DEFAULT_ITR;
1346 adapter->itr = IGB_START_ITR;
1347
1348 igb_validate_mdi_setting(hw);
1349
1350 adapter->rx_csum = 1;
1351
1352 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1353 * enable the ACPI Magic Packet filter
1354 */
1355
1356 if (hw->bus.func == 0)
1357 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1358 else if (hw->bus.func == 1)
1359 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1360
1361 if (eeprom_data & eeprom_apme_mask)
1362 adapter->eeprom_wol |= E1000_WUFC_MAG;
1363
1364 /* now that we have the eeprom settings, apply the special cases where
1365 * the eeprom may be wrong or the board simply won't support wake on
1366 * lan on a particular port */
1367 switch (pdev->device) {
1368 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1369 adapter->eeprom_wol = 0;
1370 break;
1371 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1372 case E1000_DEV_ID_82576_FIBER:
1373 case E1000_DEV_ID_82576_SERDES:
1374 /* Wake events only supported on port A for dual fiber
1375 * regardless of eeprom setting */
1376 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1377 adapter->eeprom_wol = 0;
1378 break;
1379 case E1000_DEV_ID_82576_QUAD_COPPER:
1380 /* if quad port adapter, disable WoL on all but port A */
1381 if (global_quad_port_a != 0)
1382 adapter->eeprom_wol = 0;
1383 else
1384 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1385 /* Reset for multiple quad port adapters */
1386 if (++global_quad_port_a == 4)
1387 global_quad_port_a = 0;
1388 break;
1389 }
1390
1391 /* initialize the wol settings based on the eeprom settings */
1392 adapter->wol = adapter->eeprom_wol;
1393 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1394
1395 /* reset the hardware with the new settings */
1396 igb_reset(adapter);
1397
1398 /* let the f/w know that the h/w is now under the control of the
1399 * driver. */
1400 igb_get_hw_control(adapter);
1401
1402 /* tell the stack to leave us alone until igb_open() is called */
1403 netif_carrier_off(netdev);
1404 netif_tx_stop_all_queues(netdev);
1405
1406 strcpy(netdev->name, "eth%d");
1407 err = register_netdev(netdev);
1408 if (err)
1409 goto err_register;
1410
1411 #ifdef CONFIG_PCI_IOV
1412 /* since iov functionality isn't critical to base device function we
1413 * can accept failure. If it fails we don't allow iov to be enabled */
1414 if (hw->mac.type == e1000_82576) {
1415 err = pci_enable_sriov(pdev, 0);
1416 if (!err)
1417 err = device_create_file(&netdev->dev,
1418 &dev_attr_num_vfs);
1419 if (err)
1420 dev_err(&pdev->dev, "Failed to initialize IOV\n");
1421 }
1422
1423 #endif
1424 #ifdef CONFIG_IGB_DCA
1425 if (dca_add_requester(&pdev->dev) == 0) {
1426 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1427 dev_info(&pdev->dev, "DCA enabled\n");
1428 /* Always use CB2 mode, difference is masked
1429 * in the CB driver. */
1430 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
1431 igb_setup_dca(adapter);
1432 }
1433 #endif
1434
1435 /*
1436 * Initialize hardware timer: we keep it running just in case
1437 * that some program needs it later on.
1438 */
1439 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1440 adapter->cycles.read = igb_read_clock;
1441 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1442 adapter->cycles.mult = 1;
1443 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1444 wr32(E1000_TIMINCA,
1445 (1<<24) |
1446 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1447 #if 0
1448 /*
1449 * Avoid rollover while we initialize by resetting the time counter.
1450 */
1451 wr32(E1000_SYSTIML, 0x00000000);
1452 wr32(E1000_SYSTIMH, 0x00000000);
1453 #else
1454 /*
1455 * Set registers so that rollover occurs soon to test this.
1456 */
1457 wr32(E1000_SYSTIML, 0x00000000);
1458 wr32(E1000_SYSTIMH, 0xFF800000);
1459 #endif
1460 wrfl();
1461 timecounter_init(&adapter->clock,
1462 &adapter->cycles,
1463 ktime_to_ns(ktime_get_real()));
1464
1465 /*
1466 * Synchronize our NIC clock against system wall clock. NIC
1467 * time stamp reading requires ~3us per sample, each sample
1468 * was pretty stable even under load => only require 10
1469 * samples for each offset comparison.
1470 */
1471 memset(&adapter->compare, 0, sizeof(adapter->compare));
1472 adapter->compare.source = &adapter->clock;
1473 adapter->compare.target = ktime_get_real;
1474 adapter->compare.num_samples = 10;
1475 timecompare_update(&adapter->compare, 0);
1476
1477 #ifdef DEBUG
1478 {
1479 char buffer[160];
1480 printk(KERN_DEBUG
1481 "igb: %s: hw %p initialized timer\n",
1482 igb_get_time_str(adapter, buffer),
1483 &adapter->hw);
1484 }
1485 #endif
1486
1487 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1488 /* print bus type/speed/width info */
1489 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1490 netdev->name,
1491 ((hw->bus.speed == e1000_bus_speed_2500)
1492 ? "2.5Gb/s" : "unknown"),
1493 ((hw->bus.width == e1000_bus_width_pcie_x4)
1494 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1495 ? "Width x1" : "unknown"),
1496 netdev->dev_addr);
1497
1498 igb_read_part_num(hw, &part_num);
1499 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1500 (part_num >> 8), (part_num & 0xff));
1501
1502 dev_info(&pdev->dev,
1503 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1504 adapter->msix_entries ? "MSI-X" :
1505 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1506 adapter->num_rx_queues, adapter->num_tx_queues);
1507
1508 return 0;
1509
1510 err_register:
1511 igb_release_hw_control(adapter);
1512 err_eeprom:
1513 if (!igb_check_reset_block(hw))
1514 igb_reset_phy(hw);
1515
1516 if (hw->flash_address)
1517 iounmap(hw->flash_address);
1518
1519 igb_free_queues(adapter);
1520 err_sw_init:
1521 iounmap(hw->hw_addr);
1522 err_ioremap:
1523 free_netdev(netdev);
1524 err_alloc_etherdev:
1525 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1526 IORESOURCE_MEM));
1527 err_pci_reg:
1528 err_dma:
1529 pci_disable_device(pdev);
1530 return err;
1531 }
1532
1533 /**
1534 * igb_remove - Device Removal Routine
1535 * @pdev: PCI device information struct
1536 *
1537 * igb_remove is called by the PCI subsystem to alert the driver
1538 * that it should release a PCI device. The could be caused by a
1539 * Hot-Plug event, or because the driver is going to be removed from
1540 * memory.
1541 **/
1542 static void __devexit igb_remove(struct pci_dev *pdev)
1543 {
1544 struct net_device *netdev = pci_get_drvdata(pdev);
1545 struct igb_adapter *adapter = netdev_priv(netdev);
1546 struct e1000_hw *hw = &adapter->hw;
1547 int err;
1548
1549 /* flush_scheduled work may reschedule our watchdog task, so
1550 * explicitly disable watchdog tasks from being rescheduled */
1551 set_bit(__IGB_DOWN, &adapter->state);
1552 del_timer_sync(&adapter->watchdog_timer);
1553 del_timer_sync(&adapter->phy_info_timer);
1554
1555 flush_scheduled_work();
1556
1557 #ifdef CONFIG_IGB_DCA
1558 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1559 dev_info(&pdev->dev, "DCA disabled\n");
1560 dca_remove_requester(&pdev->dev);
1561 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1562 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1563 }
1564 #endif
1565
1566 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1567 * would have already happened in close and is redundant. */
1568 igb_release_hw_control(adapter);
1569
1570 unregister_netdev(netdev);
1571
1572 if (!igb_check_reset_block(&adapter->hw))
1573 igb_reset_phy(&adapter->hw);
1574
1575 igb_reset_interrupt_capability(adapter);
1576
1577 igb_free_queues(adapter);
1578
1579 #ifdef CONFIG_PCI_IOV
1580 /* reclaim resources allocated to VFs */
1581 if (adapter->vf_data) {
1582 /* disable iov and allow time for transactions to clear */
1583 pci_disable_sriov(pdev);
1584 msleep(500);
1585
1586 kfree(adapter->vf_data);
1587 adapter->vf_data = NULL;
1588 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1589 msleep(100);
1590 dev_info(&pdev->dev, "IOV Disabled\n");
1591 }
1592 #endif
1593 iounmap(hw->hw_addr);
1594 if (hw->flash_address)
1595 iounmap(hw->flash_address);
1596 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1597 IORESOURCE_MEM));
1598
1599 free_netdev(netdev);
1600
1601 err = pci_disable_pcie_error_reporting(pdev);
1602 if (err)
1603 dev_err(&pdev->dev,
1604 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1605
1606 pci_disable_device(pdev);
1607 }
1608
1609 /**
1610 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1611 * @adapter: board private structure to initialize
1612 *
1613 * igb_sw_init initializes the Adapter private data structure.
1614 * Fields are initialized based on PCI device information and
1615 * OS network device settings (MTU size).
1616 **/
1617 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1618 {
1619 struct e1000_hw *hw = &adapter->hw;
1620 struct net_device *netdev = adapter->netdev;
1621 struct pci_dev *pdev = adapter->pdev;
1622
1623 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1624
1625 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1626 adapter->rx_ring_count = IGB_DEFAULT_RXD;
1627 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1628 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1629 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1630 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1631
1632 /* This call may decrease the number of queues depending on
1633 * interrupt mode. */
1634 igb_set_interrupt_capability(adapter);
1635
1636 if (igb_alloc_queues(adapter)) {
1637 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1638 return -ENOMEM;
1639 }
1640
1641 /* Explicitly disable IRQ since the NIC can be in any state. */
1642 igb_irq_disable(adapter);
1643
1644 set_bit(__IGB_DOWN, &adapter->state);
1645 return 0;
1646 }
1647
1648 /**
1649 * igb_open - Called when a network interface is made active
1650 * @netdev: network interface device structure
1651 *
1652 * Returns 0 on success, negative value on failure
1653 *
1654 * The open entry point is called when a network interface is made
1655 * active by the system (IFF_UP). At this point all resources needed
1656 * for transmit and receive operations are allocated, the interrupt
1657 * handler is registered with the OS, the watchdog timer is started,
1658 * and the stack is notified that the interface is ready.
1659 **/
1660 static int igb_open(struct net_device *netdev)
1661 {
1662 struct igb_adapter *adapter = netdev_priv(netdev);
1663 struct e1000_hw *hw = &adapter->hw;
1664 int err;
1665 int i;
1666
1667 /* disallow open during test */
1668 if (test_bit(__IGB_TESTING, &adapter->state))
1669 return -EBUSY;
1670
1671 /* allocate transmit descriptors */
1672 err = igb_setup_all_tx_resources(adapter);
1673 if (err)
1674 goto err_setup_tx;
1675
1676 /* allocate receive descriptors */
1677 err = igb_setup_all_rx_resources(adapter);
1678 if (err)
1679 goto err_setup_rx;
1680
1681 /* e1000_power_up_phy(adapter); */
1682
1683 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1684 if ((adapter->hw.mng_cookie.status &
1685 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1686 igb_update_mng_vlan(adapter);
1687
1688 /* before we allocate an interrupt, we must be ready to handle it.
1689 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1690 * as soon as we call pci_request_irq, so we have to setup our
1691 * clean_rx handler before we do so. */
1692 igb_configure(adapter);
1693
1694 igb_vmm_control(adapter);
1695 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1696 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1697
1698 err = igb_request_irq(adapter);
1699 if (err)
1700 goto err_req_irq;
1701
1702 /* From here on the code is the same as igb_up() */
1703 clear_bit(__IGB_DOWN, &adapter->state);
1704
1705 for (i = 0; i < adapter->num_rx_queues; i++)
1706 napi_enable(&adapter->rx_ring[i].napi);
1707
1708 /* Clear any pending interrupts. */
1709 rd32(E1000_ICR);
1710
1711 igb_irq_enable(adapter);
1712
1713 netif_tx_start_all_queues(netdev);
1714
1715 /* Fire a link status change interrupt to start the watchdog. */
1716 wr32(E1000_ICS, E1000_ICS_LSC);
1717
1718 return 0;
1719
1720 err_req_irq:
1721 igb_release_hw_control(adapter);
1722 /* e1000_power_down_phy(adapter); */
1723 igb_free_all_rx_resources(adapter);
1724 err_setup_rx:
1725 igb_free_all_tx_resources(adapter);
1726 err_setup_tx:
1727 igb_reset(adapter);
1728
1729 return err;
1730 }
1731
1732 /**
1733 * igb_close - Disables a network interface
1734 * @netdev: network interface device structure
1735 *
1736 * Returns 0, this is not allowed to fail
1737 *
1738 * The close entry point is called when an interface is de-activated
1739 * by the OS. The hardware is still under the driver's control, but
1740 * needs to be disabled. A global MAC reset is issued to stop the
1741 * hardware, and all transmit and receive resources are freed.
1742 **/
1743 static int igb_close(struct net_device *netdev)
1744 {
1745 struct igb_adapter *adapter = netdev_priv(netdev);
1746
1747 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1748 igb_down(adapter);
1749
1750 igb_free_irq(adapter);
1751
1752 igb_free_all_tx_resources(adapter);
1753 igb_free_all_rx_resources(adapter);
1754
1755 /* kill manageability vlan ID if supported, but not if a vlan with
1756 * the same ID is registered on the host OS (let 8021q kill it) */
1757 if ((adapter->hw.mng_cookie.status &
1758 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1759 !(adapter->vlgrp &&
1760 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1761 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1762
1763 return 0;
1764 }
1765
1766 /**
1767 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1768 * @adapter: board private structure
1769 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1770 *
1771 * Return 0 on success, negative on failure
1772 **/
1773 int igb_setup_tx_resources(struct igb_adapter *adapter,
1774 struct igb_ring *tx_ring)
1775 {
1776 struct pci_dev *pdev = adapter->pdev;
1777 int size;
1778
1779 size = sizeof(struct igb_buffer) * tx_ring->count;
1780 tx_ring->buffer_info = vmalloc(size);
1781 if (!tx_ring->buffer_info)
1782 goto err;
1783 memset(tx_ring->buffer_info, 0, size);
1784
1785 /* round up to nearest 4K */
1786 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1787 tx_ring->size = ALIGN(tx_ring->size, 4096);
1788
1789 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1790 &tx_ring->dma);
1791
1792 if (!tx_ring->desc)
1793 goto err;
1794
1795 tx_ring->adapter = adapter;
1796 tx_ring->next_to_use = 0;
1797 tx_ring->next_to_clean = 0;
1798 return 0;
1799
1800 err:
1801 vfree(tx_ring->buffer_info);
1802 dev_err(&adapter->pdev->dev,
1803 "Unable to allocate memory for the transmit descriptor ring\n");
1804 return -ENOMEM;
1805 }
1806
1807 /**
1808 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1809 * (Descriptors) for all queues
1810 * @adapter: board private structure
1811 *
1812 * Return 0 on success, negative on failure
1813 **/
1814 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1815 {
1816 int i, err = 0;
1817 int r_idx;
1818
1819 for (i = 0; i < adapter->num_tx_queues; i++) {
1820 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1821 if (err) {
1822 dev_err(&adapter->pdev->dev,
1823 "Allocation for Tx Queue %u failed\n", i);
1824 for (i--; i >= 0; i--)
1825 igb_free_tx_resources(&adapter->tx_ring[i]);
1826 break;
1827 }
1828 }
1829
1830 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1831 r_idx = i % adapter->num_tx_queues;
1832 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1833 }
1834 return err;
1835 }
1836
1837 /**
1838 * igb_configure_tx - Configure transmit Unit after Reset
1839 * @adapter: board private structure
1840 *
1841 * Configure the Tx unit of the MAC after a reset.
1842 **/
1843 static void igb_configure_tx(struct igb_adapter *adapter)
1844 {
1845 u64 tdba;
1846 struct e1000_hw *hw = &adapter->hw;
1847 u32 tctl;
1848 u32 txdctl, txctrl;
1849 int i, j;
1850
1851 for (i = 0; i < adapter->num_tx_queues; i++) {
1852 struct igb_ring *ring = &adapter->tx_ring[i];
1853 j = ring->reg_idx;
1854 wr32(E1000_TDLEN(j),
1855 ring->count * sizeof(union e1000_adv_tx_desc));
1856 tdba = ring->dma;
1857 wr32(E1000_TDBAL(j),
1858 tdba & 0x00000000ffffffffULL);
1859 wr32(E1000_TDBAH(j), tdba >> 32);
1860
1861 ring->head = E1000_TDH(j);
1862 ring->tail = E1000_TDT(j);
1863 writel(0, hw->hw_addr + ring->tail);
1864 writel(0, hw->hw_addr + ring->head);
1865 txdctl = rd32(E1000_TXDCTL(j));
1866 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1867 wr32(E1000_TXDCTL(j), txdctl);
1868
1869 /* Turn off Relaxed Ordering on head write-backs. The
1870 * writebacks MUST be delivered in order or it will
1871 * completely screw up our bookeeping.
1872 */
1873 txctrl = rd32(E1000_DCA_TXCTRL(j));
1874 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1875 wr32(E1000_DCA_TXCTRL(j), txctrl);
1876 }
1877
1878 /* disable queue 0 to prevent tail bump w/o re-configuration */
1879 if (adapter->vfs_allocated_count)
1880 wr32(E1000_TXDCTL(0), 0);
1881
1882 /* Program the Transmit Control Register */
1883 tctl = rd32(E1000_TCTL);
1884 tctl &= ~E1000_TCTL_CT;
1885 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1886 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1887
1888 igb_config_collision_dist(hw);
1889
1890 /* Setup Transmit Descriptor Settings for eop descriptor */
1891 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1892
1893 /* Enable transmits */
1894 tctl |= E1000_TCTL_EN;
1895
1896 wr32(E1000_TCTL, tctl);
1897 }
1898
1899 /**
1900 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1901 * @adapter: board private structure
1902 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1903 *
1904 * Returns 0 on success, negative on failure
1905 **/
1906 int igb_setup_rx_resources(struct igb_adapter *adapter,
1907 struct igb_ring *rx_ring)
1908 {
1909 struct pci_dev *pdev = adapter->pdev;
1910 int size, desc_len;
1911
1912 size = sizeof(struct igb_buffer) * rx_ring->count;
1913 rx_ring->buffer_info = vmalloc(size);
1914 if (!rx_ring->buffer_info)
1915 goto err;
1916 memset(rx_ring->buffer_info, 0, size);
1917
1918 desc_len = sizeof(union e1000_adv_rx_desc);
1919
1920 /* Round up to nearest 4K */
1921 rx_ring->size = rx_ring->count * desc_len;
1922 rx_ring->size = ALIGN(rx_ring->size, 4096);
1923
1924 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1925 &rx_ring->dma);
1926
1927 if (!rx_ring->desc)
1928 goto err;
1929
1930 rx_ring->next_to_clean = 0;
1931 rx_ring->next_to_use = 0;
1932
1933 rx_ring->adapter = adapter;
1934
1935 return 0;
1936
1937 err:
1938 vfree(rx_ring->buffer_info);
1939 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1940 "the receive descriptor ring\n");
1941 return -ENOMEM;
1942 }
1943
1944 /**
1945 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1946 * (Descriptors) for all queues
1947 * @adapter: board private structure
1948 *
1949 * Return 0 on success, negative on failure
1950 **/
1951 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1952 {
1953 int i, err = 0;
1954
1955 for (i = 0; i < adapter->num_rx_queues; i++) {
1956 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1957 if (err) {
1958 dev_err(&adapter->pdev->dev,
1959 "Allocation for Rx Queue %u failed\n", i);
1960 for (i--; i >= 0; i--)
1961 igb_free_rx_resources(&adapter->rx_ring[i]);
1962 break;
1963 }
1964 }
1965
1966 return err;
1967 }
1968
1969 /**
1970 * igb_setup_rctl - configure the receive control registers
1971 * @adapter: Board private structure
1972 **/
1973 static void igb_setup_rctl(struct igb_adapter *adapter)
1974 {
1975 struct e1000_hw *hw = &adapter->hw;
1976 u32 rctl;
1977 u32 srrctl = 0;
1978 int i, j;
1979
1980 rctl = rd32(E1000_RCTL);
1981
1982 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1983 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1984
1985 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1986 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1987
1988 /*
1989 * enable stripping of CRC. It's unlikely this will break BMC
1990 * redirection as it did with e1000. Newer features require
1991 * that the HW strips the CRC.
1992 */
1993 rctl |= E1000_RCTL_SECRC;
1994
1995 /*
1996 * disable store bad packets and clear size bits.
1997 */
1998 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
1999
2000 /* enable LPE when to prevent packets larger than max_frame_size */
2001 rctl |= E1000_RCTL_LPE;
2002
2003 /* Setup buffer sizes */
2004 switch (adapter->rx_buffer_len) {
2005 case IGB_RXBUFFER_256:
2006 rctl |= E1000_RCTL_SZ_256;
2007 break;
2008 case IGB_RXBUFFER_512:
2009 rctl |= E1000_RCTL_SZ_512;
2010 break;
2011 default:
2012 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2013 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2014 break;
2015 }
2016
2017 /* 82575 and greater support packet-split where the protocol
2018 * header is placed in skb->data and the packet data is
2019 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2020 * In the case of a non-split, skb->data is linearly filled,
2021 * followed by the page buffers. Therefore, skb->data is
2022 * sized to hold the largest protocol header.
2023 */
2024 /* allocations using alloc_page take too long for regular MTU
2025 * so only enable packet split for jumbo frames */
2026 if (adapter->netdev->mtu > ETH_DATA_LEN) {
2027 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2028 srrctl |= adapter->rx_ps_hdr_size <<
2029 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2030 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2031 } else {
2032 adapter->rx_ps_hdr_size = 0;
2033 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2034 }
2035
2036 /* Attention!!! For SR-IOV PF driver operations you must enable
2037 * queue drop for all VF and PF queues to prevent head of line blocking
2038 * if an un-trusted VF does not provide descriptors to hardware.
2039 */
2040 if (adapter->vfs_allocated_count) {
2041 u32 vmolr;
2042
2043 j = adapter->rx_ring[0].reg_idx;
2044
2045 /* set all queue drop enable bits */
2046 wr32(E1000_QDE, ALL_QUEUES);
2047 srrctl |= E1000_SRRCTL_DROP_EN;
2048
2049 /* disable queue 0 to prevent tail write w/o re-config */
2050 wr32(E1000_RXDCTL(0), 0);
2051
2052 vmolr = rd32(E1000_VMOLR(j));
2053 if (rctl & E1000_RCTL_LPE)
2054 vmolr |= E1000_VMOLR_LPE;
2055 if (adapter->num_rx_queues > 0)
2056 vmolr |= E1000_VMOLR_RSSE;
2057 wr32(E1000_VMOLR(j), vmolr);
2058 }
2059
2060 for (i = 0; i < adapter->num_rx_queues; i++) {
2061 j = adapter->rx_ring[i].reg_idx;
2062 wr32(E1000_SRRCTL(j), srrctl);
2063 }
2064
2065 wr32(E1000_RCTL, rctl);
2066 }
2067
2068 /**
2069 * igb_rlpml_set - set maximum receive packet size
2070 * @adapter: board private structure
2071 *
2072 * Configure maximum receivable packet size.
2073 **/
2074 static void igb_rlpml_set(struct igb_adapter *adapter)
2075 {
2076 u32 max_frame_size = adapter->max_frame_size;
2077 struct e1000_hw *hw = &adapter->hw;
2078 u16 pf_id = adapter->vfs_allocated_count;
2079
2080 if (adapter->vlgrp)
2081 max_frame_size += VLAN_TAG_SIZE;
2082
2083 /* if vfs are enabled we set RLPML to the largest possible request
2084 * size and set the VMOLR RLPML to the size we need */
2085 if (pf_id) {
2086 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2087 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2088 }
2089
2090 wr32(E1000_RLPML, max_frame_size);
2091 }
2092
2093 /**
2094 * igb_configure_vt_default_pool - Configure VT default pool
2095 * @adapter: board private structure
2096 *
2097 * Configure the default pool
2098 **/
2099 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2100 {
2101 struct e1000_hw *hw = &adapter->hw;
2102 u16 pf_id = adapter->vfs_allocated_count;
2103 u32 vtctl;
2104
2105 /* not in sr-iov mode - do nothing */
2106 if (!pf_id)
2107 return;
2108
2109 vtctl = rd32(E1000_VT_CTL);
2110 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2111 E1000_VT_CTL_DISABLE_DEF_POOL);
2112 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2113 wr32(E1000_VT_CTL, vtctl);
2114 }
2115
2116 /**
2117 * igb_configure_rx - Configure receive Unit after Reset
2118 * @adapter: board private structure
2119 *
2120 * Configure the Rx unit of the MAC after a reset.
2121 **/
2122 static void igb_configure_rx(struct igb_adapter *adapter)
2123 {
2124 u64 rdba;
2125 struct e1000_hw *hw = &adapter->hw;
2126 u32 rctl, rxcsum;
2127 u32 rxdctl;
2128 int i;
2129
2130 /* disable receives while setting up the descriptors */
2131 rctl = rd32(E1000_RCTL);
2132 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2133 wrfl();
2134 mdelay(10);
2135
2136 if (adapter->itr_setting > 3)
2137 wr32(E1000_ITR, adapter->itr);
2138
2139 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2140 * the Base and Length of the Rx Descriptor Ring */
2141 for (i = 0; i < adapter->num_rx_queues; i++) {
2142 struct igb_ring *ring = &adapter->rx_ring[i];
2143 int j = ring->reg_idx;
2144 rdba = ring->dma;
2145 wr32(E1000_RDBAL(j),
2146 rdba & 0x00000000ffffffffULL);
2147 wr32(E1000_RDBAH(j), rdba >> 32);
2148 wr32(E1000_RDLEN(j),
2149 ring->count * sizeof(union e1000_adv_rx_desc));
2150
2151 ring->head = E1000_RDH(j);
2152 ring->tail = E1000_RDT(j);
2153 writel(0, hw->hw_addr + ring->tail);
2154 writel(0, hw->hw_addr + ring->head);
2155
2156 rxdctl = rd32(E1000_RXDCTL(j));
2157 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2158 rxdctl &= 0xFFF00000;
2159 rxdctl |= IGB_RX_PTHRESH;
2160 rxdctl |= IGB_RX_HTHRESH << 8;
2161 rxdctl |= IGB_RX_WTHRESH << 16;
2162 wr32(E1000_RXDCTL(j), rxdctl);
2163 }
2164
2165 if (adapter->num_rx_queues > 1) {
2166 u32 random[10];
2167 u32 mrqc;
2168 u32 j, shift;
2169 union e1000_reta {
2170 u32 dword;
2171 u8 bytes[4];
2172 } reta;
2173
2174 get_random_bytes(&random[0], 40);
2175
2176 if (hw->mac.type >= e1000_82576)
2177 shift = 0;
2178 else
2179 shift = 6;
2180 for (j = 0; j < (32 * 4); j++) {
2181 reta.bytes[j & 3] =
2182 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2183 if ((j & 3) == 3)
2184 writel(reta.dword,
2185 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2186 }
2187 if (adapter->vfs_allocated_count)
2188 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2189 else
2190 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2191
2192 /* Fill out hash function seeds */
2193 for (j = 0; j < 10; j++)
2194 array_wr32(E1000_RSSRK(0), j, random[j]);
2195
2196 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2197 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2198 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2199 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2200 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2201 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2202 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2203 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2204
2205
2206 wr32(E1000_MRQC, mrqc);
2207
2208 /* Multiqueue and raw packet checksumming are mutually
2209 * exclusive. Note that this not the same as TCP/IP
2210 * checksumming, which works fine. */
2211 rxcsum = rd32(E1000_RXCSUM);
2212 rxcsum |= E1000_RXCSUM_PCSD;
2213 wr32(E1000_RXCSUM, rxcsum);
2214 } else {
2215 /* Enable multi-queue for sr-iov */
2216 if (adapter->vfs_allocated_count)
2217 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2218 /* Enable Receive Checksum Offload for TCP and UDP */
2219 rxcsum = rd32(E1000_RXCSUM);
2220 if (adapter->rx_csum)
2221 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2222 else
2223 rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2224
2225 wr32(E1000_RXCSUM, rxcsum);
2226 }
2227
2228 /* Set the default pool for the PF's first queue */
2229 igb_configure_vt_default_pool(adapter);
2230
2231 igb_rlpml_set(adapter);
2232
2233 /* Enable Receives */
2234 wr32(E1000_RCTL, rctl);
2235 }
2236
2237 /**
2238 * igb_free_tx_resources - Free Tx Resources per Queue
2239 * @tx_ring: Tx descriptor ring for a specific queue
2240 *
2241 * Free all transmit software resources
2242 **/
2243 void igb_free_tx_resources(struct igb_ring *tx_ring)
2244 {
2245 struct pci_dev *pdev = tx_ring->adapter->pdev;
2246
2247 igb_clean_tx_ring(tx_ring);
2248
2249 vfree(tx_ring->buffer_info);
2250 tx_ring->buffer_info = NULL;
2251
2252 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2253
2254 tx_ring->desc = NULL;
2255 }
2256
2257 /**
2258 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2259 * @adapter: board private structure
2260 *
2261 * Free all transmit software resources
2262 **/
2263 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2264 {
2265 int i;
2266
2267 for (i = 0; i < adapter->num_tx_queues; i++)
2268 igb_free_tx_resources(&adapter->tx_ring[i]);
2269 }
2270
2271 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2272 struct igb_buffer *buffer_info)
2273 {
2274 if (buffer_info->dma) {
2275 pci_unmap_page(adapter->pdev,
2276 buffer_info->dma,
2277 buffer_info->length,
2278 PCI_DMA_TODEVICE);
2279 buffer_info->dma = 0;
2280 }
2281 if (buffer_info->skb) {
2282 dev_kfree_skb_any(buffer_info->skb);
2283 buffer_info->skb = NULL;
2284 }
2285 buffer_info->time_stamp = 0;
2286 buffer_info->next_to_watch = 0;
2287 /* buffer_info must be completely set up in the transmit path */
2288 }
2289
2290 /**
2291 * igb_clean_tx_ring - Free Tx Buffers
2292 * @tx_ring: ring to be cleaned
2293 **/
2294 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2295 {
2296 struct igb_adapter *adapter = tx_ring->adapter;
2297 struct igb_buffer *buffer_info;
2298 unsigned long size;
2299 unsigned int i;
2300
2301 if (!tx_ring->buffer_info)
2302 return;
2303 /* Free all the Tx ring sk_buffs */
2304
2305 for (i = 0; i < tx_ring->count; i++) {
2306 buffer_info = &tx_ring->buffer_info[i];
2307 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2308 }
2309
2310 size = sizeof(struct igb_buffer) * tx_ring->count;
2311 memset(tx_ring->buffer_info, 0, size);
2312
2313 /* Zero out the descriptor ring */
2314
2315 memset(tx_ring->desc, 0, tx_ring->size);
2316
2317 tx_ring->next_to_use = 0;
2318 tx_ring->next_to_clean = 0;
2319
2320 writel(0, adapter->hw.hw_addr + tx_ring->head);
2321 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2322 }
2323
2324 /**
2325 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2326 * @adapter: board private structure
2327 **/
2328 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2329 {
2330 int i;
2331
2332 for (i = 0; i < adapter->num_tx_queues; i++)
2333 igb_clean_tx_ring(&adapter->tx_ring[i]);
2334 }
2335
2336 /**
2337 * igb_free_rx_resources - Free Rx Resources
2338 * @rx_ring: ring to clean the resources from
2339 *
2340 * Free all receive software resources
2341 **/
2342 void igb_free_rx_resources(struct igb_ring *rx_ring)
2343 {
2344 struct pci_dev *pdev = rx_ring->adapter->pdev;
2345
2346 igb_clean_rx_ring(rx_ring);
2347
2348 vfree(rx_ring->buffer_info);
2349 rx_ring->buffer_info = NULL;
2350
2351 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2352
2353 rx_ring->desc = NULL;
2354 }
2355
2356 /**
2357 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2358 * @adapter: board private structure
2359 *
2360 * Free all receive software resources
2361 **/
2362 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2363 {
2364 int i;
2365
2366 for (i = 0; i < adapter->num_rx_queues; i++)
2367 igb_free_rx_resources(&adapter->rx_ring[i]);
2368 }
2369
2370 /**
2371 * igb_clean_rx_ring - Free Rx Buffers per Queue
2372 * @rx_ring: ring to free buffers from
2373 **/
2374 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2375 {
2376 struct igb_adapter *adapter = rx_ring->adapter;
2377 struct igb_buffer *buffer_info;
2378 struct pci_dev *pdev = adapter->pdev;
2379 unsigned long size;
2380 unsigned int i;
2381
2382 if (!rx_ring->buffer_info)
2383 return;
2384 /* Free all the Rx ring sk_buffs */
2385 for (i = 0; i < rx_ring->count; i++) {
2386 buffer_info = &rx_ring->buffer_info[i];
2387 if (buffer_info->dma) {
2388 if (adapter->rx_ps_hdr_size)
2389 pci_unmap_single(pdev, buffer_info->dma,
2390 adapter->rx_ps_hdr_size,
2391 PCI_DMA_FROMDEVICE);
2392 else
2393 pci_unmap_single(pdev, buffer_info->dma,
2394 adapter->rx_buffer_len,
2395 PCI_DMA_FROMDEVICE);
2396 buffer_info->dma = 0;
2397 }
2398
2399 if (buffer_info->skb) {
2400 dev_kfree_skb(buffer_info->skb);
2401 buffer_info->skb = NULL;
2402 }
2403 if (buffer_info->page) {
2404 if (buffer_info->page_dma)
2405 pci_unmap_page(pdev, buffer_info->page_dma,
2406 PAGE_SIZE / 2,
2407 PCI_DMA_FROMDEVICE);
2408 put_page(buffer_info->page);
2409 buffer_info->page = NULL;
2410 buffer_info->page_dma = 0;
2411 buffer_info->page_offset = 0;
2412 }
2413 }
2414
2415 size = sizeof(struct igb_buffer) * rx_ring->count;
2416 memset(rx_ring->buffer_info, 0, size);
2417
2418 /* Zero out the descriptor ring */
2419 memset(rx_ring->desc, 0, rx_ring->size);
2420
2421 rx_ring->next_to_clean = 0;
2422 rx_ring->next_to_use = 0;
2423
2424 writel(0, adapter->hw.hw_addr + rx_ring->head);
2425 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2426 }
2427
2428 /**
2429 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2430 * @adapter: board private structure
2431 **/
2432 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2433 {
2434 int i;
2435
2436 for (i = 0; i < adapter->num_rx_queues; i++)
2437 igb_clean_rx_ring(&adapter->rx_ring[i]);
2438 }
2439
2440 /**
2441 * igb_set_mac - Change the Ethernet Address of the NIC
2442 * @netdev: network interface device structure
2443 * @p: pointer to an address structure
2444 *
2445 * Returns 0 on success, negative on failure
2446 **/
2447 static int igb_set_mac(struct net_device *netdev, void *p)
2448 {
2449 struct igb_adapter *adapter = netdev_priv(netdev);
2450 struct e1000_hw *hw = &adapter->hw;
2451 struct sockaddr *addr = p;
2452
2453 if (!is_valid_ether_addr(addr->sa_data))
2454 return -EADDRNOTAVAIL;
2455
2456 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2457 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2458
2459 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2460
2461 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2462
2463 return 0;
2464 }
2465
2466 /**
2467 * igb_set_multi - Multicast and Promiscuous mode set
2468 * @netdev: network interface device structure
2469 *
2470 * The set_multi entry point is called whenever the multicast address
2471 * list or the network interface flags are updated. This routine is
2472 * responsible for configuring the hardware for proper multicast,
2473 * promiscuous mode, and all-multi behavior.
2474 **/
2475 static void igb_set_multi(struct net_device *netdev)
2476 {
2477 struct igb_adapter *adapter = netdev_priv(netdev);
2478 struct e1000_hw *hw = &adapter->hw;
2479 struct e1000_mac_info *mac = &hw->mac;
2480 struct dev_mc_list *mc_ptr;
2481 u8 *mta_list;
2482 u32 rctl;
2483 int i;
2484
2485 /* Check for Promiscuous and All Multicast modes */
2486
2487 rctl = rd32(E1000_RCTL);
2488
2489 if (netdev->flags & IFF_PROMISC) {
2490 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2491 rctl &= ~E1000_RCTL_VFE;
2492 } else {
2493 if (netdev->flags & IFF_ALLMULTI) {
2494 rctl |= E1000_RCTL_MPE;
2495 rctl &= ~E1000_RCTL_UPE;
2496 } else
2497 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2498 rctl |= E1000_RCTL_VFE;
2499 }
2500 wr32(E1000_RCTL, rctl);
2501
2502 if (!netdev->mc_count) {
2503 /* nothing to program, so clear mc list */
2504 igb_update_mc_addr_list(hw, NULL, 0, 1,
2505 mac->rar_entry_count);
2506 return;
2507 }
2508
2509 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2510 if (!mta_list)
2511 return;
2512
2513 /* The shared function expects a packed array of only addresses. */
2514 mc_ptr = netdev->mc_list;
2515
2516 for (i = 0; i < netdev->mc_count; i++) {
2517 if (!mc_ptr)
2518 break;
2519 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2520 mc_ptr = mc_ptr->next;
2521 }
2522 igb_update_mc_addr_list(hw, mta_list, i,
2523 adapter->vfs_allocated_count + 1,
2524 mac->rar_entry_count);
2525
2526 igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2527 igb_restore_vf_multicasts(adapter);
2528
2529 kfree(mta_list);
2530 }
2531
2532 /* Need to wait a few seconds after link up to get diagnostic information from
2533 * the phy */
2534 static void igb_update_phy_info(unsigned long data)
2535 {
2536 struct igb_adapter *adapter = (struct igb_adapter *) data;
2537 igb_get_phy_info(&adapter->hw);
2538 }
2539
2540 /**
2541 * igb_has_link - check shared code for link and determine up/down
2542 * @adapter: pointer to driver private info
2543 **/
2544 static bool igb_has_link(struct igb_adapter *adapter)
2545 {
2546 struct e1000_hw *hw = &adapter->hw;
2547 bool link_active = false;
2548 s32 ret_val = 0;
2549
2550 /* get_link_status is set on LSC (link status) interrupt or
2551 * rx sequence error interrupt. get_link_status will stay
2552 * false until the e1000_check_for_link establishes link
2553 * for copper adapters ONLY
2554 */
2555 switch (hw->phy.media_type) {
2556 case e1000_media_type_copper:
2557 if (hw->mac.get_link_status) {
2558 ret_val = hw->mac.ops.check_for_link(hw);
2559 link_active = !hw->mac.get_link_status;
2560 } else {
2561 link_active = true;
2562 }
2563 break;
2564 case e1000_media_type_fiber:
2565 ret_val = hw->mac.ops.check_for_link(hw);
2566 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2567 break;
2568 case e1000_media_type_internal_serdes:
2569 ret_val = hw->mac.ops.check_for_link(hw);
2570 link_active = hw->mac.serdes_has_link;
2571 break;
2572 default:
2573 case e1000_media_type_unknown:
2574 break;
2575 }
2576
2577 return link_active;
2578 }
2579
2580 /**
2581 * igb_watchdog - Timer Call-back
2582 * @data: pointer to adapter cast into an unsigned long
2583 **/
2584 static void igb_watchdog(unsigned long data)
2585 {
2586 struct igb_adapter *adapter = (struct igb_adapter *)data;
2587 /* Do the rest outside of interrupt context */
2588 schedule_work(&adapter->watchdog_task);
2589 }
2590
2591 static void igb_watchdog_task(struct work_struct *work)
2592 {
2593 struct igb_adapter *adapter = container_of(work,
2594 struct igb_adapter, watchdog_task);
2595 struct e1000_hw *hw = &adapter->hw;
2596 struct net_device *netdev = adapter->netdev;
2597 struct igb_ring *tx_ring = adapter->tx_ring;
2598 u32 link;
2599 u32 eics = 0;
2600 int i;
2601
2602 link = igb_has_link(adapter);
2603 if ((netif_carrier_ok(netdev)) && link)
2604 goto link_up;
2605
2606 if (link) {
2607 if (!netif_carrier_ok(netdev)) {
2608 u32 ctrl;
2609 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2610 &adapter->link_speed,
2611 &adapter->link_duplex);
2612
2613 ctrl = rd32(E1000_CTRL);
2614 /* Links status message must follow this format */
2615 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2616 "Flow Control: %s\n",
2617 netdev->name,
2618 adapter->link_speed,
2619 adapter->link_duplex == FULL_DUPLEX ?
2620 "Full Duplex" : "Half Duplex",
2621 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2622 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2623 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2624 E1000_CTRL_TFCE) ? "TX" : "None")));
2625
2626 /* tweak tx_queue_len according to speed/duplex and
2627 * adjust the timeout factor */
2628 netdev->tx_queue_len = adapter->tx_queue_len;
2629 adapter->tx_timeout_factor = 1;
2630 switch (adapter->link_speed) {
2631 case SPEED_10:
2632 netdev->tx_queue_len = 10;
2633 adapter->tx_timeout_factor = 14;
2634 break;
2635 case SPEED_100:
2636 netdev->tx_queue_len = 100;
2637 /* maybe add some timeout factor ? */
2638 break;
2639 }
2640
2641 netif_carrier_on(netdev);
2642 netif_tx_wake_all_queues(netdev);
2643
2644 igb_ping_all_vfs(adapter);
2645
2646 /* link state has changed, schedule phy info update */
2647 if (!test_bit(__IGB_DOWN, &adapter->state))
2648 mod_timer(&adapter->phy_info_timer,
2649 round_jiffies(jiffies + 2 * HZ));
2650 }
2651 } else {
2652 if (netif_carrier_ok(netdev)) {
2653 adapter->link_speed = 0;
2654 adapter->link_duplex = 0;
2655 /* Links status message must follow this format */
2656 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2657 netdev->name);
2658 netif_carrier_off(netdev);
2659 netif_tx_stop_all_queues(netdev);
2660
2661 igb_ping_all_vfs(adapter);
2662
2663 /* link state has changed, schedule phy info update */
2664 if (!test_bit(__IGB_DOWN, &adapter->state))
2665 mod_timer(&adapter->phy_info_timer,
2666 round_jiffies(jiffies + 2 * HZ));
2667 }
2668 }
2669
2670 link_up:
2671 igb_update_stats(adapter);
2672
2673 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2674 adapter->tpt_old = adapter->stats.tpt;
2675 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2676 adapter->colc_old = adapter->stats.colc;
2677
2678 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2679 adapter->gorc_old = adapter->stats.gorc;
2680 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2681 adapter->gotc_old = adapter->stats.gotc;
2682
2683 igb_update_adaptive(&adapter->hw);
2684
2685 if (!netif_carrier_ok(netdev)) {
2686 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2687 /* We've lost link, so the controller stops DMA,
2688 * but we've got queued Tx work that's never going
2689 * to get done, so reset controller to flush Tx.
2690 * (Do the reset outside of interrupt context). */
2691 adapter->tx_timeout_count++;
2692 schedule_work(&adapter->reset_task);
2693 }
2694 }
2695
2696 /* Cause software interrupt to ensure rx ring is cleaned */
2697 if (adapter->msix_entries) {
2698 for (i = 0; i < adapter->num_rx_queues; i++)
2699 eics |= adapter->rx_ring[i].eims_value;
2700 wr32(E1000_EICS, eics);
2701 } else {
2702 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2703 }
2704
2705 /* Force detection of hung controller every watchdog period */
2706 tx_ring->detect_tx_hung = true;
2707
2708 /* Reset the timer */
2709 if (!test_bit(__IGB_DOWN, &adapter->state))
2710 mod_timer(&adapter->watchdog_timer,
2711 round_jiffies(jiffies + 2 * HZ));
2712 }
2713
2714 enum latency_range {
2715 lowest_latency = 0,
2716 low_latency = 1,
2717 bulk_latency = 2,
2718 latency_invalid = 255
2719 };
2720
2721
2722 /**
2723 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2724 *
2725 * Stores a new ITR value based on strictly on packet size. This
2726 * algorithm is less sophisticated than that used in igb_update_itr,
2727 * due to the difficulty of synchronizing statistics across multiple
2728 * receive rings. The divisors and thresholds used by this fuction
2729 * were determined based on theoretical maximum wire speed and testing
2730 * data, in order to minimize response time while increasing bulk
2731 * throughput.
2732 * This functionality is controlled by the InterruptThrottleRate module
2733 * parameter (see igb_param.c)
2734 * NOTE: This function is called only when operating in a multiqueue
2735 * receive environment.
2736 * @rx_ring: pointer to ring
2737 **/
2738 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2739 {
2740 int new_val = rx_ring->itr_val;
2741 int avg_wire_size = 0;
2742 struct igb_adapter *adapter = rx_ring->adapter;
2743
2744 if (!rx_ring->total_packets)
2745 goto clear_counts; /* no packets, so don't do anything */
2746
2747 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2748 * ints/sec - ITR timer value of 120 ticks.
2749 */
2750 if (adapter->link_speed != SPEED_1000) {
2751 new_val = 120;
2752 goto set_itr_val;
2753 }
2754 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2755
2756 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2757 avg_wire_size += 24;
2758
2759 /* Don't starve jumbo frames */
2760 avg_wire_size = min(avg_wire_size, 3000);
2761
2762 /* Give a little boost to mid-size frames */
2763 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2764 new_val = avg_wire_size / 3;
2765 else
2766 new_val = avg_wire_size / 2;
2767
2768 set_itr_val:
2769 if (new_val != rx_ring->itr_val) {
2770 rx_ring->itr_val = new_val;
2771 rx_ring->set_itr = 1;
2772 }
2773 clear_counts:
2774 rx_ring->total_bytes = 0;
2775 rx_ring->total_packets = 0;
2776 }
2777
2778 /**
2779 * igb_update_itr - update the dynamic ITR value based on statistics
2780 * Stores a new ITR value based on packets and byte
2781 * counts during the last interrupt. The advantage of per interrupt
2782 * computation is faster updates and more accurate ITR for the current
2783 * traffic pattern. Constants in this function were computed
2784 * based on theoretical maximum wire speed and thresholds were set based
2785 * on testing data as well as attempting to minimize response time
2786 * while increasing bulk throughput.
2787 * this functionality is controlled by the InterruptThrottleRate module
2788 * parameter (see igb_param.c)
2789 * NOTE: These calculations are only valid when operating in a single-
2790 * queue environment.
2791 * @adapter: pointer to adapter
2792 * @itr_setting: current adapter->itr
2793 * @packets: the number of packets during this measurement interval
2794 * @bytes: the number of bytes during this measurement interval
2795 **/
2796 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2797 int packets, int bytes)
2798 {
2799 unsigned int retval = itr_setting;
2800
2801 if (packets == 0)
2802 goto update_itr_done;
2803
2804 switch (itr_setting) {
2805 case lowest_latency:
2806 /* handle TSO and jumbo frames */
2807 if (bytes/packets > 8000)
2808 retval = bulk_latency;
2809 else if ((packets < 5) && (bytes > 512))
2810 retval = low_latency;
2811 break;
2812 case low_latency: /* 50 usec aka 20000 ints/s */
2813 if (bytes > 10000) {
2814 /* this if handles the TSO accounting */
2815 if (bytes/packets > 8000) {
2816 retval = bulk_latency;
2817 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2818 retval = bulk_latency;
2819 } else if ((packets > 35)) {
2820 retval = lowest_latency;
2821 }
2822 } else if (bytes/packets > 2000) {
2823 retval = bulk_latency;
2824 } else if (packets <= 2 && bytes < 512) {
2825 retval = lowest_latency;
2826 }
2827 break;
2828 case bulk_latency: /* 250 usec aka 4000 ints/s */
2829 if (bytes > 25000) {
2830 if (packets > 35)
2831 retval = low_latency;
2832 } else if (bytes < 1500) {
2833 retval = low_latency;
2834 }
2835 break;
2836 }
2837
2838 update_itr_done:
2839 return retval;
2840 }
2841
2842 static void igb_set_itr(struct igb_adapter *adapter)
2843 {
2844 u16 current_itr;
2845 u32 new_itr = adapter->itr;
2846
2847 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2848 if (adapter->link_speed != SPEED_1000) {
2849 current_itr = 0;
2850 new_itr = 4000;
2851 goto set_itr_now;
2852 }
2853
2854 adapter->rx_itr = igb_update_itr(adapter,
2855 adapter->rx_itr,
2856 adapter->rx_ring->total_packets,
2857 adapter->rx_ring->total_bytes);
2858
2859 if (adapter->rx_ring->buddy) {
2860 adapter->tx_itr = igb_update_itr(adapter,
2861 adapter->tx_itr,
2862 adapter->tx_ring->total_packets,
2863 adapter->tx_ring->total_bytes);
2864 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2865 } else {
2866 current_itr = adapter->rx_itr;
2867 }
2868
2869 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2870 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2871 current_itr = low_latency;
2872
2873 switch (current_itr) {
2874 /* counts and packets in update_itr are dependent on these numbers */
2875 case lowest_latency:
2876 new_itr = 70000;
2877 break;
2878 case low_latency:
2879 new_itr = 20000; /* aka hwitr = ~200 */
2880 break;
2881 case bulk_latency:
2882 new_itr = 4000;
2883 break;
2884 default:
2885 break;
2886 }
2887
2888 set_itr_now:
2889 adapter->rx_ring->total_bytes = 0;
2890 adapter->rx_ring->total_packets = 0;
2891 if (adapter->rx_ring->buddy) {
2892 adapter->rx_ring->buddy->total_bytes = 0;
2893 adapter->rx_ring->buddy->total_packets = 0;
2894 }
2895
2896 if (new_itr != adapter->itr) {
2897 /* this attempts to bias the interrupt rate towards Bulk
2898 * by adding intermediate steps when interrupt rate is
2899 * increasing */
2900 new_itr = new_itr > adapter->itr ?
2901 min(adapter->itr + (new_itr >> 2), new_itr) :
2902 new_itr;
2903 /* Don't write the value here; it resets the adapter's
2904 * internal timer, and causes us to delay far longer than
2905 * we should between interrupts. Instead, we write the ITR
2906 * value at the beginning of the next interrupt so the timing
2907 * ends up being correct.
2908 */
2909 adapter->itr = new_itr;
2910 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2911 adapter->rx_ring->set_itr = 1;
2912 }
2913
2914 return;
2915 }
2916
2917
2918 #define IGB_TX_FLAGS_CSUM 0x00000001
2919 #define IGB_TX_FLAGS_VLAN 0x00000002
2920 #define IGB_TX_FLAGS_TSO 0x00000004
2921 #define IGB_TX_FLAGS_IPV4 0x00000008
2922 #define IGB_TX_FLAGS_TSTAMP 0x00000010
2923 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2924 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2925
2926 static inline int igb_tso_adv(struct igb_adapter *adapter,
2927 struct igb_ring *tx_ring,
2928 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2929 {
2930 struct e1000_adv_tx_context_desc *context_desc;
2931 unsigned int i;
2932 int err;
2933 struct igb_buffer *buffer_info;
2934 u32 info = 0, tu_cmd = 0;
2935 u32 mss_l4len_idx, l4len;
2936 *hdr_len = 0;
2937
2938 if (skb_header_cloned(skb)) {
2939 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2940 if (err)
2941 return err;
2942 }
2943
2944 l4len = tcp_hdrlen(skb);
2945 *hdr_len += l4len;
2946
2947 if (skb->protocol == htons(ETH_P_IP)) {
2948 struct iphdr *iph = ip_hdr(skb);
2949 iph->tot_len = 0;
2950 iph->check = 0;
2951 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2952 iph->daddr, 0,
2953 IPPROTO_TCP,
2954 0);
2955 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2956 ipv6_hdr(skb)->payload_len = 0;
2957 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2958 &ipv6_hdr(skb)->daddr,
2959 0, IPPROTO_TCP, 0);
2960 }
2961
2962 i = tx_ring->next_to_use;
2963
2964 buffer_info = &tx_ring->buffer_info[i];
2965 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2966 /* VLAN MACLEN IPLEN */
2967 if (tx_flags & IGB_TX_FLAGS_VLAN)
2968 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2969 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2970 *hdr_len += skb_network_offset(skb);
2971 info |= skb_network_header_len(skb);
2972 *hdr_len += skb_network_header_len(skb);
2973 context_desc->vlan_macip_lens = cpu_to_le32(info);
2974
2975 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2976 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2977
2978 if (skb->protocol == htons(ETH_P_IP))
2979 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2980 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2981
2982 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2983
2984 /* MSS L4LEN IDX */
2985 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2986 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2987
2988 /* For 82575, context index must be unique per ring. */
2989 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2990 mss_l4len_idx |= tx_ring->queue_index << 4;
2991
2992 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2993 context_desc->seqnum_seed = 0;
2994
2995 buffer_info->time_stamp = jiffies;
2996 buffer_info->next_to_watch = i;
2997 buffer_info->dma = 0;
2998 i++;
2999 if (i == tx_ring->count)
3000 i = 0;
3001
3002 tx_ring->next_to_use = i;
3003
3004 return true;
3005 }
3006
3007 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3008 struct igb_ring *tx_ring,
3009 struct sk_buff *skb, u32 tx_flags)
3010 {
3011 struct e1000_adv_tx_context_desc *context_desc;
3012 unsigned int i;
3013 struct igb_buffer *buffer_info;
3014 u32 info = 0, tu_cmd = 0;
3015
3016 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3017 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3018 i = tx_ring->next_to_use;
3019 buffer_info = &tx_ring->buffer_info[i];
3020 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3021
3022 if (tx_flags & IGB_TX_FLAGS_VLAN)
3023 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3024 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3025 if (skb->ip_summed == CHECKSUM_PARTIAL)
3026 info |= skb_network_header_len(skb);
3027
3028 context_desc->vlan_macip_lens = cpu_to_le32(info);
3029
3030 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3031
3032 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3033 switch (skb->protocol) {
3034 case cpu_to_be16(ETH_P_IP):
3035 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3036 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3037 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3038 break;
3039 case cpu_to_be16(ETH_P_IPV6):
3040 /* XXX what about other V6 headers?? */
3041 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3042 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3043 break;
3044 default:
3045 if (unlikely(net_ratelimit()))
3046 dev_warn(&adapter->pdev->dev,
3047 "partial checksum but proto=%x!\n",
3048 skb->protocol);
3049 break;
3050 }
3051 }
3052
3053 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3054 context_desc->seqnum_seed = 0;
3055 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3056 context_desc->mss_l4len_idx =
3057 cpu_to_le32(tx_ring->queue_index << 4);
3058 else
3059 context_desc->mss_l4len_idx = 0;
3060
3061 buffer_info->time_stamp = jiffies;
3062 buffer_info->next_to_watch = i;
3063 buffer_info->dma = 0;
3064
3065 i++;
3066 if (i == tx_ring->count)
3067 i = 0;
3068 tx_ring->next_to_use = i;
3069
3070 return true;
3071 }
3072 return false;
3073 }
3074
3075 #define IGB_MAX_TXD_PWR 16
3076 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3077
3078 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3079 struct igb_ring *tx_ring, struct sk_buff *skb,
3080 unsigned int first)
3081 {
3082 struct igb_buffer *buffer_info;
3083 unsigned int len = skb_headlen(skb);
3084 unsigned int count = 0, i;
3085 unsigned int f;
3086
3087 i = tx_ring->next_to_use;
3088
3089 buffer_info = &tx_ring->buffer_info[i];
3090 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3091 buffer_info->length = len;
3092 /* set time_stamp *before* dma to help avoid a possible race */
3093 buffer_info->time_stamp = jiffies;
3094 buffer_info->next_to_watch = i;
3095 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
3096 PCI_DMA_TODEVICE);
3097 count++;
3098 i++;
3099 if (i == tx_ring->count)
3100 i = 0;
3101
3102 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3103 struct skb_frag_struct *frag;
3104
3105 frag = &skb_shinfo(skb)->frags[f];
3106 len = frag->size;
3107
3108 buffer_info = &tx_ring->buffer_info[i];
3109 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3110 buffer_info->length = len;
3111 buffer_info->time_stamp = jiffies;
3112 buffer_info->next_to_watch = i;
3113 buffer_info->dma = pci_map_page(adapter->pdev,
3114 frag->page,
3115 frag->page_offset,
3116 len,
3117 PCI_DMA_TODEVICE);
3118
3119 count++;
3120 i++;
3121 if (i == tx_ring->count)
3122 i = 0;
3123 }
3124
3125 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
3126 tx_ring->buffer_info[i].skb = skb;
3127 tx_ring->buffer_info[first].next_to_watch = i;
3128
3129 return count;
3130 }
3131
3132 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3133 struct igb_ring *tx_ring,
3134 int tx_flags, int count, u32 paylen,
3135 u8 hdr_len)
3136 {
3137 union e1000_adv_tx_desc *tx_desc = NULL;
3138 struct igb_buffer *buffer_info;
3139 u32 olinfo_status = 0, cmd_type_len;
3140 unsigned int i;
3141
3142 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3143 E1000_ADVTXD_DCMD_DEXT);
3144
3145 if (tx_flags & IGB_TX_FLAGS_VLAN)
3146 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3147
3148 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3149 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3150
3151 if (tx_flags & IGB_TX_FLAGS_TSO) {
3152 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3153
3154 /* insert tcp checksum */
3155 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3156
3157 /* insert ip checksum */
3158 if (tx_flags & IGB_TX_FLAGS_IPV4)
3159 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3160
3161 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3162 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3163 }
3164
3165 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3166 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3167 IGB_TX_FLAGS_VLAN)))
3168 olinfo_status |= tx_ring->queue_index << 4;
3169
3170 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3171
3172 i = tx_ring->next_to_use;
3173 while (count--) {
3174 buffer_info = &tx_ring->buffer_info[i];
3175 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3176 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3177 tx_desc->read.cmd_type_len =
3178 cpu_to_le32(cmd_type_len | buffer_info->length);
3179 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3180 i++;
3181 if (i == tx_ring->count)
3182 i = 0;
3183 }
3184
3185 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3186 /* Force memory writes to complete before letting h/w
3187 * know there are new descriptors to fetch. (Only
3188 * applicable for weak-ordered memory model archs,
3189 * such as IA-64). */
3190 wmb();
3191
3192 tx_ring->next_to_use = i;
3193 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3194 /* we need this if more than one processor can write to our tail
3195 * at a time, it syncronizes IO on IA64/Altix systems */
3196 mmiowb();
3197 }
3198
3199 static int __igb_maybe_stop_tx(struct net_device *netdev,
3200 struct igb_ring *tx_ring, int size)
3201 {
3202 struct igb_adapter *adapter = netdev_priv(netdev);
3203
3204 netif_stop_subqueue(netdev, tx_ring->queue_index);
3205
3206 /* Herbert's original patch had:
3207 * smp_mb__after_netif_stop_queue();
3208 * but since that doesn't exist yet, just open code it. */
3209 smp_mb();
3210
3211 /* We need to check again in a case another CPU has just
3212 * made room available. */
3213 if (IGB_DESC_UNUSED(tx_ring) < size)
3214 return -EBUSY;
3215
3216 /* A reprieve! */
3217 netif_wake_subqueue(netdev, tx_ring->queue_index);
3218 ++adapter->restart_queue;
3219 return 0;
3220 }
3221
3222 static int igb_maybe_stop_tx(struct net_device *netdev,
3223 struct igb_ring *tx_ring, int size)
3224 {
3225 if (IGB_DESC_UNUSED(tx_ring) >= size)
3226 return 0;
3227 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3228 }
3229
3230 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3231 struct net_device *netdev,
3232 struct igb_ring *tx_ring)
3233 {
3234 struct igb_adapter *adapter = netdev_priv(netdev);
3235 unsigned int first;
3236 unsigned int tx_flags = 0;
3237 u8 hdr_len = 0;
3238 int tso = 0;
3239 union skb_shared_tx *shtx;
3240
3241 if (test_bit(__IGB_DOWN, &adapter->state)) {
3242 dev_kfree_skb_any(skb);
3243 return NETDEV_TX_OK;
3244 }
3245
3246 if (skb->len <= 0) {
3247 dev_kfree_skb_any(skb);
3248 return NETDEV_TX_OK;
3249 }
3250
3251 /* need: 1 descriptor per page,
3252 * + 2 desc gap to keep tail from touching head,
3253 * + 1 desc for skb->data,
3254 * + 1 desc for context descriptor,
3255 * otherwise try next time */
3256 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3257 /* this is a hard error */
3258 return NETDEV_TX_BUSY;
3259 }
3260
3261 /*
3262 * TODO: check that there currently is no other packet with
3263 * time stamping in the queue
3264 *
3265 * When doing time stamping, keep the connection to the socket
3266 * a while longer: it is still needed by skb_hwtstamp_tx(),
3267 * called either in igb_tx_hwtstamp() or by our caller when
3268 * doing software time stamping.
3269 */
3270 shtx = skb_tx(skb);
3271 if (unlikely(shtx->hardware)) {
3272 shtx->in_progress = 1;
3273 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3274 }
3275
3276 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3277 tx_flags |= IGB_TX_FLAGS_VLAN;
3278 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3279 }
3280
3281 if (skb->protocol == htons(ETH_P_IP))
3282 tx_flags |= IGB_TX_FLAGS_IPV4;
3283
3284 first = tx_ring->next_to_use;
3285 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3286 &hdr_len) : 0;
3287
3288 if (tso < 0) {
3289 dev_kfree_skb_any(skb);
3290 return NETDEV_TX_OK;
3291 }
3292
3293 if (tso)
3294 tx_flags |= IGB_TX_FLAGS_TSO;
3295 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3296 (skb->ip_summed == CHECKSUM_PARTIAL))
3297 tx_flags |= IGB_TX_FLAGS_CSUM;
3298
3299 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
3300 igb_tx_map_adv(adapter, tx_ring, skb, first),
3301 skb->len, hdr_len);
3302
3303 netdev->trans_start = jiffies;
3304
3305 /* Make sure there is space in the ring for the next send. */
3306 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3307
3308 return NETDEV_TX_OK;
3309 }
3310
3311 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3312 {
3313 struct igb_adapter *adapter = netdev_priv(netdev);
3314 struct igb_ring *tx_ring;
3315
3316 int r_idx = 0;
3317 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3318 tx_ring = adapter->multi_tx_table[r_idx];
3319
3320 /* This goes back to the question of how to logically map a tx queue
3321 * to a flow. Right now, performance is impacted slightly negatively
3322 * if using multiple tx queues. If the stack breaks away from a
3323 * single qdisc implementation, we can look at this again. */
3324 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3325 }
3326
3327 /**
3328 * igb_tx_timeout - Respond to a Tx Hang
3329 * @netdev: network interface device structure
3330 **/
3331 static void igb_tx_timeout(struct net_device *netdev)
3332 {
3333 struct igb_adapter *adapter = netdev_priv(netdev);
3334 struct e1000_hw *hw = &adapter->hw;
3335
3336 /* Do the reset outside of interrupt context */
3337 adapter->tx_timeout_count++;
3338 schedule_work(&adapter->reset_task);
3339 wr32(E1000_EICS,
3340 (adapter->eims_enable_mask & ~adapter->eims_other));
3341 }
3342
3343 static void igb_reset_task(struct work_struct *work)
3344 {
3345 struct igb_adapter *adapter;
3346 adapter = container_of(work, struct igb_adapter, reset_task);
3347
3348 igb_reinit_locked(adapter);
3349 }
3350
3351 /**
3352 * igb_get_stats - Get System Network Statistics
3353 * @netdev: network interface device structure
3354 *
3355 * Returns the address of the device statistics structure.
3356 * The statistics are actually updated from the timer callback.
3357 **/
3358 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3359 {
3360 struct igb_adapter *adapter = netdev_priv(netdev);
3361
3362 /* only return the current stats */
3363 return &adapter->net_stats;
3364 }
3365
3366 /**
3367 * igb_change_mtu - Change the Maximum Transfer Unit
3368 * @netdev: network interface device structure
3369 * @new_mtu: new value for maximum frame size
3370 *
3371 * Returns 0 on success, negative on failure
3372 **/
3373 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3374 {
3375 struct igb_adapter *adapter = netdev_priv(netdev);
3376 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3377
3378 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3379 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3380 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3381 return -EINVAL;
3382 }
3383
3384 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3385 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3386 return -EINVAL;
3387 }
3388
3389 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3390 msleep(1);
3391
3392 /* igb_down has a dependency on max_frame_size */
3393 adapter->max_frame_size = max_frame;
3394 if (netif_running(netdev))
3395 igb_down(adapter);
3396
3397 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3398 * means we reserve 2 more, this pushes us to allocate from the next
3399 * larger slab size.
3400 * i.e. RXBUFFER_2048 --> size-4096 slab
3401 */
3402
3403 if (max_frame <= IGB_RXBUFFER_256)
3404 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3405 else if (max_frame <= IGB_RXBUFFER_512)
3406 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3407 else if (max_frame <= IGB_RXBUFFER_1024)
3408 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3409 else if (max_frame <= IGB_RXBUFFER_2048)
3410 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3411 else
3412 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3413 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3414 #else
3415 adapter->rx_buffer_len = PAGE_SIZE / 2;
3416 #endif
3417
3418 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3419 if (adapter->vfs_allocated_count &&
3420 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3421 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3422
3423 /* adjust allocation if LPE protects us, and we aren't using SBP */
3424 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3425 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3426 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3427
3428 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3429 netdev->mtu, new_mtu);
3430 netdev->mtu = new_mtu;
3431
3432 if (netif_running(netdev))
3433 igb_up(adapter);
3434 else
3435 igb_reset(adapter);
3436
3437 clear_bit(__IGB_RESETTING, &adapter->state);
3438
3439 return 0;
3440 }
3441
3442 /**
3443 * igb_update_stats - Update the board statistics counters
3444 * @adapter: board private structure
3445 **/
3446
3447 void igb_update_stats(struct igb_adapter *adapter)
3448 {
3449 struct e1000_hw *hw = &adapter->hw;
3450 struct pci_dev *pdev = adapter->pdev;
3451 u16 phy_tmp;
3452
3453 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3454
3455 /*
3456 * Prevent stats update while adapter is being reset, or if the pci
3457 * connection is down.
3458 */
3459 if (adapter->link_speed == 0)
3460 return;
3461 if (pci_channel_offline(pdev))
3462 return;
3463
3464 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3465 adapter->stats.gprc += rd32(E1000_GPRC);
3466 adapter->stats.gorc += rd32(E1000_GORCL);
3467 rd32(E1000_GORCH); /* clear GORCL */
3468 adapter->stats.bprc += rd32(E1000_BPRC);
3469 adapter->stats.mprc += rd32(E1000_MPRC);
3470 adapter->stats.roc += rd32(E1000_ROC);
3471
3472 adapter->stats.prc64 += rd32(E1000_PRC64);
3473 adapter->stats.prc127 += rd32(E1000_PRC127);
3474 adapter->stats.prc255 += rd32(E1000_PRC255);
3475 adapter->stats.prc511 += rd32(E1000_PRC511);
3476 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3477 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3478 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3479 adapter->stats.sec += rd32(E1000_SEC);
3480
3481 adapter->stats.mpc += rd32(E1000_MPC);
3482 adapter->stats.scc += rd32(E1000_SCC);
3483 adapter->stats.ecol += rd32(E1000_ECOL);
3484 adapter->stats.mcc += rd32(E1000_MCC);
3485 adapter->stats.latecol += rd32(E1000_LATECOL);
3486 adapter->stats.dc += rd32(E1000_DC);
3487 adapter->stats.rlec += rd32(E1000_RLEC);
3488 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3489 adapter->stats.xontxc += rd32(E1000_XONTXC);
3490 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3491 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3492 adapter->stats.fcruc += rd32(E1000_FCRUC);
3493 adapter->stats.gptc += rd32(E1000_GPTC);
3494 adapter->stats.gotc += rd32(E1000_GOTCL);
3495 rd32(E1000_GOTCH); /* clear GOTCL */
3496 adapter->stats.rnbc += rd32(E1000_RNBC);
3497 adapter->stats.ruc += rd32(E1000_RUC);
3498 adapter->stats.rfc += rd32(E1000_RFC);
3499 adapter->stats.rjc += rd32(E1000_RJC);
3500 adapter->stats.tor += rd32(E1000_TORH);
3501 adapter->stats.tot += rd32(E1000_TOTH);
3502 adapter->stats.tpr += rd32(E1000_TPR);
3503
3504 adapter->stats.ptc64 += rd32(E1000_PTC64);
3505 adapter->stats.ptc127 += rd32(E1000_PTC127);
3506 adapter->stats.ptc255 += rd32(E1000_PTC255);
3507 adapter->stats.ptc511 += rd32(E1000_PTC511);
3508 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3509 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3510
3511 adapter->stats.mptc += rd32(E1000_MPTC);
3512 adapter->stats.bptc += rd32(E1000_BPTC);
3513
3514 /* used for adaptive IFS */
3515
3516 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3517 adapter->stats.tpt += hw->mac.tx_packet_delta;
3518 hw->mac.collision_delta = rd32(E1000_COLC);
3519 adapter->stats.colc += hw->mac.collision_delta;
3520
3521 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3522 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3523 adapter->stats.tncrs += rd32(E1000_TNCRS);
3524 adapter->stats.tsctc += rd32(E1000_TSCTC);
3525 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3526
3527 adapter->stats.iac += rd32(E1000_IAC);
3528 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3529 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3530 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3531 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3532 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3533 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3534 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3535 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3536
3537 /* Fill out the OS statistics structure */
3538 adapter->net_stats.multicast = adapter->stats.mprc;
3539 adapter->net_stats.collisions = adapter->stats.colc;
3540
3541 /* Rx Errors */
3542
3543 /* RLEC on some newer hardware can be incorrect so build
3544 * our own version based on RUC and ROC */
3545 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3546 adapter->stats.crcerrs + adapter->stats.algnerrc +
3547 adapter->stats.ruc + adapter->stats.roc +
3548 adapter->stats.cexterr;
3549 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3550 adapter->stats.roc;
3551 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3552 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3553 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3554
3555 /* Tx Errors */
3556 adapter->net_stats.tx_errors = adapter->stats.ecol +
3557 adapter->stats.latecol;
3558 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3559 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3560 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3561
3562 /* Tx Dropped needs to be maintained elsewhere */
3563
3564 /* Phy Stats */
3565 if (hw->phy.media_type == e1000_media_type_copper) {
3566 if ((adapter->link_speed == SPEED_1000) &&
3567 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3568 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3569 adapter->phy_stats.idle_errors += phy_tmp;
3570 }
3571 }
3572
3573 /* Management Stats */
3574 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3575 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3576 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3577 }
3578
3579 static irqreturn_t igb_msix_other(int irq, void *data)
3580 {
3581 struct net_device *netdev = data;
3582 struct igb_adapter *adapter = netdev_priv(netdev);
3583 struct e1000_hw *hw = &adapter->hw;
3584 u32 icr = rd32(E1000_ICR);
3585
3586 /* reading ICR causes bit 31 of EICR to be cleared */
3587
3588 if(icr & E1000_ICR_DOUTSYNC) {
3589 /* HW is reporting DMA is out of sync */
3590 adapter->stats.doosync++;
3591 }
3592
3593 /* Check for a mailbox event */
3594 if (icr & E1000_ICR_VMMB)
3595 igb_msg_task(adapter);
3596
3597 if (icr & E1000_ICR_LSC) {
3598 hw->mac.get_link_status = 1;
3599 /* guard against interrupt when we're going down */
3600 if (!test_bit(__IGB_DOWN, &adapter->state))
3601 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3602 }
3603
3604 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3605 wr32(E1000_EIMS, adapter->eims_other);
3606
3607 return IRQ_HANDLED;
3608 }
3609
3610 static irqreturn_t igb_msix_tx(int irq, void *data)
3611 {
3612 struct igb_ring *tx_ring = data;
3613 struct igb_adapter *adapter = tx_ring->adapter;
3614 struct e1000_hw *hw = &adapter->hw;
3615
3616 #ifdef CONFIG_IGB_DCA
3617 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3618 igb_update_tx_dca(tx_ring);
3619 #endif
3620
3621 tx_ring->total_bytes = 0;
3622 tx_ring->total_packets = 0;
3623
3624 /* auto mask will automatically reenable the interrupt when we write
3625 * EICS */
3626 if (!igb_clean_tx_irq(tx_ring))
3627 /* Ring was not completely cleaned, so fire another interrupt */
3628 wr32(E1000_EICS, tx_ring->eims_value);
3629 else
3630 wr32(E1000_EIMS, tx_ring->eims_value);
3631
3632 return IRQ_HANDLED;
3633 }
3634
3635 static void igb_write_itr(struct igb_ring *ring)
3636 {
3637 struct e1000_hw *hw = &ring->adapter->hw;
3638 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3639 switch (hw->mac.type) {
3640 case e1000_82576:
3641 wr32(ring->itr_register, ring->itr_val |
3642 0x80000000);
3643 break;
3644 default:
3645 wr32(ring->itr_register, ring->itr_val |
3646 (ring->itr_val << 16));
3647 break;
3648 }
3649 ring->set_itr = 0;
3650 }
3651 }
3652
3653 static irqreturn_t igb_msix_rx(int irq, void *data)
3654 {
3655 struct igb_ring *rx_ring = data;
3656
3657 /* Write the ITR value calculated at the end of the
3658 * previous interrupt.
3659 */
3660
3661 igb_write_itr(rx_ring);
3662
3663 if (napi_schedule_prep(&rx_ring->napi))
3664 __napi_schedule(&rx_ring->napi);
3665
3666 #ifdef CONFIG_IGB_DCA
3667 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3668 igb_update_rx_dca(rx_ring);
3669 #endif
3670 return IRQ_HANDLED;
3671 }
3672
3673 #ifdef CONFIG_IGB_DCA
3674 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3675 {
3676 u32 dca_rxctrl;
3677 struct igb_adapter *adapter = rx_ring->adapter;
3678 struct e1000_hw *hw = &adapter->hw;
3679 int cpu = get_cpu();
3680 int q = rx_ring->reg_idx;
3681
3682 if (rx_ring->cpu != cpu) {
3683 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3684 if (hw->mac.type == e1000_82576) {
3685 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3686 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3687 E1000_DCA_RXCTRL_CPUID_SHIFT;
3688 } else {
3689 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3690 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3691 }
3692 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3693 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3694 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3695 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3696 rx_ring->cpu = cpu;
3697 }
3698 put_cpu();
3699 }
3700
3701 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3702 {
3703 u32 dca_txctrl;
3704 struct igb_adapter *adapter = tx_ring->adapter;
3705 struct e1000_hw *hw = &adapter->hw;
3706 int cpu = get_cpu();
3707 int q = tx_ring->reg_idx;
3708
3709 if (tx_ring->cpu != cpu) {
3710 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3711 if (hw->mac.type == e1000_82576) {
3712 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3713 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3714 E1000_DCA_TXCTRL_CPUID_SHIFT;
3715 } else {
3716 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3717 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3718 }
3719 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3720 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3721 tx_ring->cpu = cpu;
3722 }
3723 put_cpu();
3724 }
3725
3726 static void igb_setup_dca(struct igb_adapter *adapter)
3727 {
3728 int i;
3729
3730 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3731 return;
3732
3733 for (i = 0; i < adapter->num_tx_queues; i++) {
3734 adapter->tx_ring[i].cpu = -1;
3735 igb_update_tx_dca(&adapter->tx_ring[i]);
3736 }
3737 for (i = 0; i < adapter->num_rx_queues; i++) {
3738 adapter->rx_ring[i].cpu = -1;
3739 igb_update_rx_dca(&adapter->rx_ring[i]);
3740 }
3741 }
3742
3743 static int __igb_notify_dca(struct device *dev, void *data)
3744 {
3745 struct net_device *netdev = dev_get_drvdata(dev);
3746 struct igb_adapter *adapter = netdev_priv(netdev);
3747 struct e1000_hw *hw = &adapter->hw;
3748 unsigned long event = *(unsigned long *)data;
3749
3750 switch (event) {
3751 case DCA_PROVIDER_ADD:
3752 /* if already enabled, don't do it again */
3753 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3754 break;
3755 /* Always use CB2 mode, difference is masked
3756 * in the CB driver. */
3757 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3758 if (dca_add_requester(dev) == 0) {
3759 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3760 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3761 igb_setup_dca(adapter);
3762 break;
3763 }
3764 /* Fall Through since DCA is disabled. */
3765 case DCA_PROVIDER_REMOVE:
3766 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3767 /* without this a class_device is left
3768 * hanging around in the sysfs model */
3769 dca_remove_requester(dev);
3770 dev_info(&adapter->pdev->dev, "DCA disabled\n");
3771 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3772 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3773 }
3774 break;
3775 }
3776
3777 return 0;
3778 }
3779
3780 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3781 void *p)
3782 {
3783 int ret_val;
3784
3785 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3786 __igb_notify_dca);
3787
3788 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3789 }
3790 #endif /* CONFIG_IGB_DCA */
3791
3792 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3793 {
3794 struct e1000_hw *hw = &adapter->hw;
3795 u32 ping;
3796 int i;
3797
3798 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3799 ping = E1000_PF_CONTROL_MSG;
3800 if (adapter->vf_data[i].clear_to_send)
3801 ping |= E1000_VT_MSGTYPE_CTS;
3802 igb_write_mbx(hw, &ping, 1, i);
3803 }
3804 }
3805
3806 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3807 u32 *msgbuf, u32 vf)
3808 {
3809 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3810 u16 *hash_list = (u16 *)&msgbuf[1];
3811 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3812 int i;
3813
3814 /* only up to 30 hash values supported */
3815 if (n > 30)
3816 n = 30;
3817
3818 /* salt away the number of multi cast addresses assigned
3819 * to this VF for later use to restore when the PF multi cast
3820 * list changes
3821 */
3822 vf_data->num_vf_mc_hashes = n;
3823
3824 /* VFs are limited to using the MTA hash table for their multicast
3825 * addresses */
3826 for (i = 0; i < n; i++)
3827 vf_data->vf_mc_hashes[i] = hash_list[i];;
3828
3829 /* Flush and reset the mta with the new values */
3830 igb_set_multi(adapter->netdev);
3831
3832 return 0;
3833 }
3834
3835 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3836 {
3837 struct e1000_hw *hw = &adapter->hw;
3838 struct vf_data_storage *vf_data;
3839 int i, j;
3840
3841 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3842 vf_data = &adapter->vf_data[i];
3843 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3844 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3845 }
3846 }
3847
3848 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3849 {
3850 struct e1000_hw *hw = &adapter->hw;
3851 u32 pool_mask, reg, vid;
3852 int i;
3853
3854 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3855
3856 /* Find the vlan filter for this id */
3857 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3858 reg = rd32(E1000_VLVF(i));
3859
3860 /* remove the vf from the pool */
3861 reg &= ~pool_mask;
3862
3863 /* if pool is empty then remove entry from vfta */
3864 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3865 (reg & E1000_VLVF_VLANID_ENABLE)) {
3866 reg = 0;
3867 vid = reg & E1000_VLVF_VLANID_MASK;
3868 igb_vfta_set(hw, vid, false);
3869 }
3870
3871 wr32(E1000_VLVF(i), reg);
3872 }
3873 }
3874
3875 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3876 {
3877 struct e1000_hw *hw = &adapter->hw;
3878 u32 reg, i;
3879
3880 /* It is an error to call this function when VFs are not enabled */
3881 if (!adapter->vfs_allocated_count)
3882 return -1;
3883
3884 /* Find the vlan filter for this id */
3885 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3886 reg = rd32(E1000_VLVF(i));
3887 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3888 vid == (reg & E1000_VLVF_VLANID_MASK))
3889 break;
3890 }
3891
3892 if (add) {
3893 if (i == E1000_VLVF_ARRAY_SIZE) {
3894 /* Did not find a matching VLAN ID entry that was
3895 * enabled. Search for a free filter entry, i.e.
3896 * one without the enable bit set
3897 */
3898 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3899 reg = rd32(E1000_VLVF(i));
3900 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3901 break;
3902 }
3903 }
3904 if (i < E1000_VLVF_ARRAY_SIZE) {
3905 /* Found an enabled/available entry */
3906 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3907
3908 /* if !enabled we need to set this up in vfta */
3909 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3910 /* add VID to filter table, if bit already set
3911 * PF must have added it outside of table */
3912 if (igb_vfta_set(hw, vid, true))
3913 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
3914 adapter->vfs_allocated_count);
3915 reg |= E1000_VLVF_VLANID_ENABLE;
3916 }
3917 reg &= ~E1000_VLVF_VLANID_MASK;
3918 reg |= vid;
3919
3920 wr32(E1000_VLVF(i), reg);
3921 return 0;
3922 }
3923 } else {
3924 if (i < E1000_VLVF_ARRAY_SIZE) {
3925 /* remove vf from the pool */
3926 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3927 /* if pool is empty then remove entry from vfta */
3928 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3929 reg = 0;
3930 igb_vfta_set(hw, vid, false);
3931 }
3932 wr32(E1000_VLVF(i), reg);
3933 return 0;
3934 }
3935 }
3936 return -1;
3937 }
3938
3939 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3940 {
3941 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3942 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3943
3944 return igb_vlvf_set(adapter, vid, add, vf);
3945 }
3946
3947 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3948 {
3949 struct e1000_hw *hw = &adapter->hw;
3950
3951 /* disable mailbox functionality for vf */
3952 adapter->vf_data[vf].clear_to_send = false;
3953
3954 /* reset offloads to defaults */
3955 igb_set_vmolr(hw, vf);
3956
3957 /* reset vlans for device */
3958 igb_clear_vf_vfta(adapter, vf);
3959
3960 /* reset multicast table array for vf */
3961 adapter->vf_data[vf].num_vf_mc_hashes = 0;
3962
3963 /* Flush and reset the mta with the new values */
3964 igb_set_multi(adapter->netdev);
3965 }
3966
3967 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
3968 {
3969 struct e1000_hw *hw = &adapter->hw;
3970 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
3971 u32 reg, msgbuf[3];
3972 u8 *addr = (u8 *)(&msgbuf[1]);
3973
3974 /* process all the same items cleared in a function level reset */
3975 igb_vf_reset_event(adapter, vf);
3976
3977 /* set vf mac address */
3978 igb_rar_set(hw, vf_mac, vf + 1);
3979 igb_set_rah_pool(hw, vf, vf + 1);
3980
3981 /* enable transmit and receive for vf */
3982 reg = rd32(E1000_VFTE);
3983 wr32(E1000_VFTE, reg | (1 << vf));
3984 reg = rd32(E1000_VFRE);
3985 wr32(E1000_VFRE, reg | (1 << vf));
3986
3987 /* enable mailbox functionality for vf */
3988 adapter->vf_data[vf].clear_to_send = true;
3989
3990 /* reply to reset with ack and vf mac address */
3991 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
3992 memcpy(addr, vf_mac, 6);
3993 igb_write_mbx(hw, msgbuf, 3, vf);
3994 }
3995
3996 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
3997 {
3998 unsigned char *addr = (char *)&msg[1];
3999 int err = -1;
4000
4001 if (is_valid_ether_addr(addr))
4002 err = igb_set_vf_mac(adapter, vf, addr);
4003
4004 return err;
4005
4006 }
4007
4008 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4009 {
4010 struct e1000_hw *hw = &adapter->hw;
4011 u32 msg = E1000_VT_MSGTYPE_NACK;
4012
4013 /* if device isn't clear to send it shouldn't be reading either */
4014 if (!adapter->vf_data[vf].clear_to_send)
4015 igb_write_mbx(hw, &msg, 1, vf);
4016 }
4017
4018
4019 static void igb_msg_task(struct igb_adapter *adapter)
4020 {
4021 struct e1000_hw *hw = &adapter->hw;
4022 u32 vf;
4023
4024 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4025 /* process any reset requests */
4026 if (!igb_check_for_rst(hw, vf)) {
4027 adapter->vf_data[vf].clear_to_send = false;
4028 igb_vf_reset_event(adapter, vf);
4029 }
4030
4031 /* process any messages pending */
4032 if (!igb_check_for_msg(hw, vf))
4033 igb_rcv_msg_from_vf(adapter, vf);
4034
4035 /* process any acks */
4036 if (!igb_check_for_ack(hw, vf))
4037 igb_rcv_ack_from_vf(adapter, vf);
4038
4039 }
4040 }
4041
4042 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4043 {
4044 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4045 u32 msgbuf[mbx_size];
4046 struct e1000_hw *hw = &adapter->hw;
4047 s32 retval;
4048
4049 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4050
4051 if (retval)
4052 dev_err(&adapter->pdev->dev,
4053 "Error receiving message from VF\n");
4054
4055 /* this is a message we already processed, do nothing */
4056 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4057 return retval;
4058
4059 /*
4060 * until the vf completes a reset it should not be
4061 * allowed to start any configuration.
4062 */
4063
4064 if (msgbuf[0] == E1000_VF_RESET) {
4065 igb_vf_reset_msg(adapter, vf);
4066
4067 return retval;
4068 }
4069
4070 if (!adapter->vf_data[vf].clear_to_send) {
4071 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4072 igb_write_mbx(hw, msgbuf, 1, vf);
4073 return retval;
4074 }
4075
4076 switch ((msgbuf[0] & 0xFFFF)) {
4077 case E1000_VF_SET_MAC_ADDR:
4078 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4079 break;
4080 case E1000_VF_SET_MULTICAST:
4081 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4082 break;
4083 case E1000_VF_SET_LPE:
4084 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4085 break;
4086 case E1000_VF_SET_VLAN:
4087 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4088 break;
4089 default:
4090 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4091 retval = -1;
4092 break;
4093 }
4094
4095 /* notify the VF of the results of what it sent us */
4096 if (retval)
4097 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4098 else
4099 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4100
4101 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4102
4103 igb_write_mbx(hw, msgbuf, 1, vf);
4104
4105 return retval;
4106 }
4107
4108 /**
4109 * igb_intr_msi - Interrupt Handler
4110 * @irq: interrupt number
4111 * @data: pointer to a network interface device structure
4112 **/
4113 static irqreturn_t igb_intr_msi(int irq, void *data)
4114 {
4115 struct net_device *netdev = data;
4116 struct igb_adapter *adapter = netdev_priv(netdev);
4117 struct e1000_hw *hw = &adapter->hw;
4118 /* read ICR disables interrupts using IAM */
4119 u32 icr = rd32(E1000_ICR);
4120
4121 igb_write_itr(adapter->rx_ring);
4122
4123 if(icr & E1000_ICR_DOUTSYNC) {
4124 /* HW is reporting DMA is out of sync */
4125 adapter->stats.doosync++;
4126 }
4127
4128 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4129 hw->mac.get_link_status = 1;
4130 if (!test_bit(__IGB_DOWN, &adapter->state))
4131 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4132 }
4133
4134 napi_schedule(&adapter->rx_ring[0].napi);
4135
4136 return IRQ_HANDLED;
4137 }
4138
4139 /**
4140 * igb_intr - Legacy Interrupt Handler
4141 * @irq: interrupt number
4142 * @data: pointer to a network interface device structure
4143 **/
4144 static irqreturn_t igb_intr(int irq, void *data)
4145 {
4146 struct net_device *netdev = data;
4147 struct igb_adapter *adapter = netdev_priv(netdev);
4148 struct e1000_hw *hw = &adapter->hw;
4149 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4150 * need for the IMC write */
4151 u32 icr = rd32(E1000_ICR);
4152 if (!icr)
4153 return IRQ_NONE; /* Not our interrupt */
4154
4155 igb_write_itr(adapter->rx_ring);
4156
4157 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4158 * not set, then the adapter didn't send an interrupt */
4159 if (!(icr & E1000_ICR_INT_ASSERTED))
4160 return IRQ_NONE;
4161
4162 if(icr & E1000_ICR_DOUTSYNC) {
4163 /* HW is reporting DMA is out of sync */
4164 adapter->stats.doosync++;
4165 }
4166
4167 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4168 hw->mac.get_link_status = 1;
4169 /* guard against interrupt when we're going down */
4170 if (!test_bit(__IGB_DOWN, &adapter->state))
4171 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4172 }
4173
4174 napi_schedule(&adapter->rx_ring[0].napi);
4175
4176 return IRQ_HANDLED;
4177 }
4178
4179 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4180 {
4181 struct igb_adapter *adapter = rx_ring->adapter;
4182 struct e1000_hw *hw = &adapter->hw;
4183
4184 if (adapter->itr_setting & 3) {
4185 if (adapter->num_rx_queues == 1)
4186 igb_set_itr(adapter);
4187 else
4188 igb_update_ring_itr(rx_ring);
4189 }
4190
4191 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4192 if (adapter->msix_entries)
4193 wr32(E1000_EIMS, rx_ring->eims_value);
4194 else
4195 igb_irq_enable(adapter);
4196 }
4197 }
4198
4199 /**
4200 * igb_poll - NAPI Rx polling callback
4201 * @napi: napi polling structure
4202 * @budget: count of how many packets we should handle
4203 **/
4204 static int igb_poll(struct napi_struct *napi, int budget)
4205 {
4206 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4207 int work_done = 0;
4208
4209 #ifdef CONFIG_IGB_DCA
4210 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4211 igb_update_rx_dca(rx_ring);
4212 #endif
4213 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4214
4215 if (rx_ring->buddy) {
4216 #ifdef CONFIG_IGB_DCA
4217 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4218 igb_update_tx_dca(rx_ring->buddy);
4219 #endif
4220 if (!igb_clean_tx_irq(rx_ring->buddy))
4221 work_done = budget;
4222 }
4223
4224 /* If not enough Rx work done, exit the polling mode */
4225 if (work_done < budget) {
4226 napi_complete(napi);
4227 igb_rx_irq_enable(rx_ring);
4228 }
4229
4230 return work_done;
4231 }
4232
4233 /**
4234 * igb_hwtstamp - utility function which checks for TX time stamp
4235 * @adapter: board private structure
4236 * @skb: packet that was just sent
4237 *
4238 * If we were asked to do hardware stamping and such a time stamp is
4239 * available, then it must have been for this skb here because we only
4240 * allow only one such packet into the queue.
4241 */
4242 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4243 {
4244 union skb_shared_tx *shtx = skb_tx(skb);
4245 struct e1000_hw *hw = &adapter->hw;
4246
4247 if (unlikely(shtx->hardware)) {
4248 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4249 if (valid) {
4250 u64 regval = rd32(E1000_TXSTMPL);
4251 u64 ns;
4252 struct skb_shared_hwtstamps shhwtstamps;
4253
4254 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4255 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4256 ns = timecounter_cyc2time(&adapter->clock,
4257 regval);
4258 timecompare_update(&adapter->compare, ns);
4259 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4260 shhwtstamps.syststamp =
4261 timecompare_transform(&adapter->compare, ns);
4262 skb_tstamp_tx(skb, &shhwtstamps);
4263 }
4264 }
4265 }
4266
4267 /**
4268 * igb_clean_tx_irq - Reclaim resources after transmit completes
4269 * @adapter: board private structure
4270 * returns true if ring is completely cleaned
4271 **/
4272 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4273 {
4274 struct igb_adapter *adapter = tx_ring->adapter;
4275 struct net_device *netdev = adapter->netdev;
4276 struct e1000_hw *hw = &adapter->hw;
4277 struct igb_buffer *buffer_info;
4278 struct sk_buff *skb;
4279 union e1000_adv_tx_desc *tx_desc, *eop_desc;
4280 unsigned int total_bytes = 0, total_packets = 0;
4281 unsigned int i, eop, count = 0;
4282 bool cleaned = false;
4283
4284 i = tx_ring->next_to_clean;
4285 eop = tx_ring->buffer_info[i].next_to_watch;
4286 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4287
4288 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4289 (count < tx_ring->count)) {
4290 for (cleaned = false; !cleaned; count++) {
4291 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4292 buffer_info = &tx_ring->buffer_info[i];
4293 cleaned = (i == eop);
4294 skb = buffer_info->skb;
4295
4296 if (skb) {
4297 unsigned int segs, bytecount;
4298 /* gso_segs is currently only valid for tcp */
4299 segs = skb_shinfo(skb)->gso_segs ?: 1;
4300 /* multiply data chunks by size of headers */
4301 bytecount = ((segs - 1) * skb_headlen(skb)) +
4302 skb->len;
4303 total_packets += segs;
4304 total_bytes += bytecount;
4305
4306 igb_tx_hwtstamp(adapter, skb);
4307 }
4308
4309 igb_unmap_and_free_tx_resource(adapter, buffer_info);
4310 tx_desc->wb.status = 0;
4311
4312 i++;
4313 if (i == tx_ring->count)
4314 i = 0;
4315 }
4316 eop = tx_ring->buffer_info[i].next_to_watch;
4317 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4318 }
4319
4320 tx_ring->next_to_clean = i;
4321
4322 if (unlikely(count &&
4323 netif_carrier_ok(netdev) &&
4324 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4325 /* Make sure that anybody stopping the queue after this
4326 * sees the new next_to_clean.
4327 */
4328 smp_mb();
4329 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4330 !(test_bit(__IGB_DOWN, &adapter->state))) {
4331 netif_wake_subqueue(netdev, tx_ring->queue_index);
4332 ++adapter->restart_queue;
4333 }
4334 }
4335
4336 if (tx_ring->detect_tx_hung) {
4337 /* Detect a transmit hang in hardware, this serializes the
4338 * check with the clearing of time_stamp and movement of i */
4339 tx_ring->detect_tx_hung = false;
4340 if (tx_ring->buffer_info[i].time_stamp &&
4341 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4342 (adapter->tx_timeout_factor * HZ))
4343 && !(rd32(E1000_STATUS) &
4344 E1000_STATUS_TXOFF)) {
4345
4346 /* detected Tx unit hang */
4347 dev_err(&adapter->pdev->dev,
4348 "Detected Tx Unit Hang\n"
4349 " Tx Queue <%d>\n"
4350 " TDH <%x>\n"
4351 " TDT <%x>\n"
4352 " next_to_use <%x>\n"
4353 " next_to_clean <%x>\n"
4354 "buffer_info[next_to_clean]\n"
4355 " time_stamp <%lx>\n"
4356 " next_to_watch <%x>\n"
4357 " jiffies <%lx>\n"
4358 " desc.status <%x>\n",
4359 tx_ring->queue_index,
4360 readl(adapter->hw.hw_addr + tx_ring->head),
4361 readl(adapter->hw.hw_addr + tx_ring->tail),
4362 tx_ring->next_to_use,
4363 tx_ring->next_to_clean,
4364 tx_ring->buffer_info[i].time_stamp,
4365 eop,
4366 jiffies,
4367 eop_desc->wb.status);
4368 netif_stop_subqueue(netdev, tx_ring->queue_index);
4369 }
4370 }
4371 tx_ring->total_bytes += total_bytes;
4372 tx_ring->total_packets += total_packets;
4373 tx_ring->tx_stats.bytes += total_bytes;
4374 tx_ring->tx_stats.packets += total_packets;
4375 adapter->net_stats.tx_bytes += total_bytes;
4376 adapter->net_stats.tx_packets += total_packets;
4377 return (count < tx_ring->count);
4378 }
4379
4380 /**
4381 * igb_receive_skb - helper function to handle rx indications
4382 * @ring: pointer to receive ring receving this packet
4383 * @status: descriptor status field as written by hardware
4384 * @rx_desc: receive descriptor containing vlan and type information.
4385 * @skb: pointer to sk_buff to be indicated to stack
4386 **/
4387 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4388 union e1000_adv_rx_desc * rx_desc,
4389 struct sk_buff *skb)
4390 {
4391 struct igb_adapter * adapter = ring->adapter;
4392 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4393
4394 skb_record_rx_queue(skb, ring->queue_index);
4395 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
4396 if (vlan_extracted)
4397 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4398 le16_to_cpu(rx_desc->wb.upper.vlan),
4399 skb);
4400 else
4401 napi_gro_receive(&ring->napi, skb);
4402 } else {
4403 if (vlan_extracted)
4404 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4405 le16_to_cpu(rx_desc->wb.upper.vlan));
4406 else
4407 netif_receive_skb(skb);
4408 }
4409 }
4410
4411 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4412 u32 status_err, struct sk_buff *skb)
4413 {
4414 skb->ip_summed = CHECKSUM_NONE;
4415
4416 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4417 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4418 return;
4419 /* TCP/UDP checksum error bit is set */
4420 if (status_err &
4421 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4422 /* let the stack verify checksum errors */
4423 adapter->hw_csum_err++;
4424 return;
4425 }
4426 /* It must be a TCP or UDP packet with a valid checksum */
4427 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4428 skb->ip_summed = CHECKSUM_UNNECESSARY;
4429
4430 adapter->hw_csum_good++;
4431 }
4432
4433 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4434 int *work_done, int budget)
4435 {
4436 struct igb_adapter *adapter = rx_ring->adapter;
4437 struct net_device *netdev = adapter->netdev;
4438 struct e1000_hw *hw = &adapter->hw;
4439 struct pci_dev *pdev = adapter->pdev;
4440 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4441 struct igb_buffer *buffer_info , *next_buffer;
4442 struct sk_buff *skb;
4443 bool cleaned = false;
4444 int cleaned_count = 0;
4445 unsigned int total_bytes = 0, total_packets = 0;
4446 unsigned int i;
4447 u32 length, hlen, staterr;
4448
4449 i = rx_ring->next_to_clean;
4450 buffer_info = &rx_ring->buffer_info[i];
4451 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4452 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4453
4454 while (staterr & E1000_RXD_STAT_DD) {
4455 if (*work_done >= budget)
4456 break;
4457 (*work_done)++;
4458
4459 skb = buffer_info->skb;
4460 prefetch(skb->data - NET_IP_ALIGN);
4461 buffer_info->skb = NULL;
4462
4463 i++;
4464 if (i == rx_ring->count)
4465 i = 0;
4466 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4467 prefetch(next_rxd);
4468 next_buffer = &rx_ring->buffer_info[i];
4469
4470 length = le16_to_cpu(rx_desc->wb.upper.length);
4471 cleaned = true;
4472 cleaned_count++;
4473
4474 if (!adapter->rx_ps_hdr_size) {
4475 pci_unmap_single(pdev, buffer_info->dma,
4476 adapter->rx_buffer_len +
4477 NET_IP_ALIGN,
4478 PCI_DMA_FROMDEVICE);
4479 skb_put(skb, length);
4480 goto send_up;
4481 }
4482
4483 /* HW will not DMA in data larger than the given buffer, even
4484 * if it parses the (NFS, of course) header to be larger. In
4485 * that case, it fills the header buffer and spills the rest
4486 * into the page.
4487 */
4488 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4489 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4490 if (hlen > adapter->rx_ps_hdr_size)
4491 hlen = adapter->rx_ps_hdr_size;
4492
4493 if (!skb_shinfo(skb)->nr_frags) {
4494 pci_unmap_single(pdev, buffer_info->dma,
4495 adapter->rx_ps_hdr_size + NET_IP_ALIGN,
4496 PCI_DMA_FROMDEVICE);
4497 skb_put(skb, hlen);
4498 }
4499
4500 if (length) {
4501 pci_unmap_page(pdev, buffer_info->page_dma,
4502 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4503 buffer_info->page_dma = 0;
4504
4505 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4506 buffer_info->page,
4507 buffer_info->page_offset,
4508 length);
4509
4510 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4511 (page_count(buffer_info->page) != 1))
4512 buffer_info->page = NULL;
4513 else
4514 get_page(buffer_info->page);
4515
4516 skb->len += length;
4517 skb->data_len += length;
4518
4519 skb->truesize += length;
4520 }
4521
4522 if (!(staterr & E1000_RXD_STAT_EOP)) {
4523 buffer_info->skb = next_buffer->skb;
4524 buffer_info->dma = next_buffer->dma;
4525 next_buffer->skb = skb;
4526 next_buffer->dma = 0;
4527 goto next_desc;
4528 }
4529 send_up:
4530 /*
4531 * If this bit is set, then the RX registers contain
4532 * the time stamp. No other packet will be time
4533 * stamped until we read these registers, so read the
4534 * registers to make them available again. Because
4535 * only one packet can be time stamped at a time, we
4536 * know that the register values must belong to this
4537 * one here and therefore we don't need to compare
4538 * any of the additional attributes stored for it.
4539 *
4540 * If nothing went wrong, then it should have a
4541 * skb_shared_tx that we can turn into a
4542 * skb_shared_hwtstamps.
4543 *
4544 * TODO: can time stamping be triggered (thus locking
4545 * the registers) without the packet reaching this point
4546 * here? In that case RX time stamping would get stuck.
4547 *
4548 * TODO: in "time stamp all packets" mode this bit is
4549 * not set. Need a global flag for this mode and then
4550 * always read the registers. Cannot be done without
4551 * a race condition.
4552 */
4553 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4554 u64 regval;
4555 u64 ns;
4556 struct skb_shared_hwtstamps *shhwtstamps =
4557 skb_hwtstamps(skb);
4558
4559 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4560 "igb: no RX time stamp available for time stamped packet");
4561 regval = rd32(E1000_RXSTMPL);
4562 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4563 ns = timecounter_cyc2time(&adapter->clock, regval);
4564 timecompare_update(&adapter->compare, ns);
4565 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4566 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4567 shhwtstamps->syststamp =
4568 timecompare_transform(&adapter->compare, ns);
4569 }
4570
4571 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4572 dev_kfree_skb_irq(skb);
4573 goto next_desc;
4574 }
4575
4576 total_bytes += skb->len;
4577 total_packets++;
4578
4579 igb_rx_checksum_adv(adapter, staterr, skb);
4580
4581 skb->protocol = eth_type_trans(skb, netdev);
4582
4583 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4584
4585 next_desc:
4586 rx_desc->wb.upper.status_error = 0;
4587
4588 /* return some buffers to hardware, one at a time is too slow */
4589 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4590 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4591 cleaned_count = 0;
4592 }
4593
4594 /* use prefetched values */
4595 rx_desc = next_rxd;
4596 buffer_info = next_buffer;
4597 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4598 }
4599
4600 rx_ring->next_to_clean = i;
4601 cleaned_count = IGB_DESC_UNUSED(rx_ring);
4602
4603 if (cleaned_count)
4604 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4605
4606 rx_ring->total_packets += total_packets;
4607 rx_ring->total_bytes += total_bytes;
4608 rx_ring->rx_stats.packets += total_packets;
4609 rx_ring->rx_stats.bytes += total_bytes;
4610 adapter->net_stats.rx_bytes += total_bytes;
4611 adapter->net_stats.rx_packets += total_packets;
4612 return cleaned;
4613 }
4614
4615 /**
4616 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4617 * @adapter: address of board private structure
4618 **/
4619 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4620 int cleaned_count)
4621 {
4622 struct igb_adapter *adapter = rx_ring->adapter;
4623 struct net_device *netdev = adapter->netdev;
4624 struct pci_dev *pdev = adapter->pdev;
4625 union e1000_adv_rx_desc *rx_desc;
4626 struct igb_buffer *buffer_info;
4627 struct sk_buff *skb;
4628 unsigned int i;
4629 int bufsz;
4630
4631 i = rx_ring->next_to_use;
4632 buffer_info = &rx_ring->buffer_info[i];
4633
4634 if (adapter->rx_ps_hdr_size)
4635 bufsz = adapter->rx_ps_hdr_size;
4636 else
4637 bufsz = adapter->rx_buffer_len;
4638 bufsz += NET_IP_ALIGN;
4639
4640 while (cleaned_count--) {
4641 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4642
4643 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4644 if (!buffer_info->page) {
4645 buffer_info->page = alloc_page(GFP_ATOMIC);
4646 if (!buffer_info->page) {
4647 adapter->alloc_rx_buff_failed++;
4648 goto no_buffers;
4649 }
4650 buffer_info->page_offset = 0;
4651 } else {
4652 buffer_info->page_offset ^= PAGE_SIZE / 2;
4653 }
4654 buffer_info->page_dma =
4655 pci_map_page(pdev, buffer_info->page,
4656 buffer_info->page_offset,
4657 PAGE_SIZE / 2,
4658 PCI_DMA_FROMDEVICE);
4659 }
4660
4661 if (!buffer_info->skb) {
4662 skb = netdev_alloc_skb(netdev, bufsz);
4663 if (!skb) {
4664 adapter->alloc_rx_buff_failed++;
4665 goto no_buffers;
4666 }
4667
4668 /* Make buffer alignment 2 beyond a 16 byte boundary
4669 * this will result in a 16 byte aligned IP header after
4670 * the 14 byte MAC header is removed
4671 */
4672 skb_reserve(skb, NET_IP_ALIGN);
4673
4674 buffer_info->skb = skb;
4675 buffer_info->dma = pci_map_single(pdev, skb->data,
4676 bufsz,
4677 PCI_DMA_FROMDEVICE);
4678 }
4679 /* Refresh the desc even if buffer_addrs didn't change because
4680 * each write-back erases this info. */
4681 if (adapter->rx_ps_hdr_size) {
4682 rx_desc->read.pkt_addr =
4683 cpu_to_le64(buffer_info->page_dma);
4684 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4685 } else {
4686 rx_desc->read.pkt_addr =
4687 cpu_to_le64(buffer_info->dma);
4688 rx_desc->read.hdr_addr = 0;
4689 }
4690
4691 i++;
4692 if (i == rx_ring->count)
4693 i = 0;
4694 buffer_info = &rx_ring->buffer_info[i];
4695 }
4696
4697 no_buffers:
4698 if (rx_ring->next_to_use != i) {
4699 rx_ring->next_to_use = i;
4700 if (i == 0)
4701 i = (rx_ring->count - 1);
4702 else
4703 i--;
4704
4705 /* Force memory writes to complete before letting h/w
4706 * know there are new descriptors to fetch. (Only
4707 * applicable for weak-ordered memory model archs,
4708 * such as IA-64). */
4709 wmb();
4710 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4711 }
4712 }
4713
4714 /**
4715 * igb_mii_ioctl -
4716 * @netdev:
4717 * @ifreq:
4718 * @cmd:
4719 **/
4720 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4721 {
4722 struct igb_adapter *adapter = netdev_priv(netdev);
4723 struct mii_ioctl_data *data = if_mii(ifr);
4724
4725 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4726 return -EOPNOTSUPP;
4727
4728 switch (cmd) {
4729 case SIOCGMIIPHY:
4730 data->phy_id = adapter->hw.phy.addr;
4731 break;
4732 case SIOCGMIIREG:
4733 if (!capable(CAP_NET_ADMIN))
4734 return -EPERM;
4735 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4736 &data->val_out))
4737 return -EIO;
4738 break;
4739 case SIOCSMIIREG:
4740 default:
4741 return -EOPNOTSUPP;
4742 }
4743 return 0;
4744 }
4745
4746 /**
4747 * igb_hwtstamp_ioctl - control hardware time stamping
4748 * @netdev:
4749 * @ifreq:
4750 * @cmd:
4751 *
4752 * Outgoing time stamping can be enabled and disabled. Play nice and
4753 * disable it when requested, although it shouldn't case any overhead
4754 * when no packet needs it. At most one packet in the queue may be
4755 * marked for time stamping, otherwise it would be impossible to tell
4756 * for sure to which packet the hardware time stamp belongs.
4757 *
4758 * Incoming time stamping has to be configured via the hardware
4759 * filters. Not all combinations are supported, in particular event
4760 * type has to be specified. Matching the kind of event packet is
4761 * not supported, with the exception of "all V2 events regardless of
4762 * level 2 or 4".
4763 *
4764 **/
4765 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4766 struct ifreq *ifr, int cmd)
4767 {
4768 struct igb_adapter *adapter = netdev_priv(netdev);
4769 struct e1000_hw *hw = &adapter->hw;
4770 struct hwtstamp_config config;
4771 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4772 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4773 u32 tsync_rx_ctl_type = 0;
4774 u32 tsync_rx_cfg = 0;
4775 int is_l4 = 0;
4776 int is_l2 = 0;
4777 short port = 319; /* PTP */
4778 u32 regval;
4779
4780 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4781 return -EFAULT;
4782
4783 /* reserved for future extensions */
4784 if (config.flags)
4785 return -EINVAL;
4786
4787 switch (config.tx_type) {
4788 case HWTSTAMP_TX_OFF:
4789 tsync_tx_ctl_bit = 0;
4790 break;
4791 case HWTSTAMP_TX_ON:
4792 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4793 break;
4794 default:
4795 return -ERANGE;
4796 }
4797
4798 switch (config.rx_filter) {
4799 case HWTSTAMP_FILTER_NONE:
4800 tsync_rx_ctl_bit = 0;
4801 break;
4802 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4803 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4804 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4805 case HWTSTAMP_FILTER_ALL:
4806 /*
4807 * register TSYNCRXCFG must be set, therefore it is not
4808 * possible to time stamp both Sync and Delay_Req messages
4809 * => fall back to time stamping all packets
4810 */
4811 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4812 config.rx_filter = HWTSTAMP_FILTER_ALL;
4813 break;
4814 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4815 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4816 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4817 is_l4 = 1;
4818 break;
4819 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4820 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4821 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4822 is_l4 = 1;
4823 break;
4824 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4825 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4826 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4827 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4828 is_l2 = 1;
4829 is_l4 = 1;
4830 config.rx_filter = HWTSTAMP_FILTER_SOME;
4831 break;
4832 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4833 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4834 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4835 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4836 is_l2 = 1;
4837 is_l4 = 1;
4838 config.rx_filter = HWTSTAMP_FILTER_SOME;
4839 break;
4840 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4841 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4842 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4843 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4844 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4845 is_l2 = 1;
4846 break;
4847 default:
4848 return -ERANGE;
4849 }
4850
4851 /* enable/disable TX */
4852 regval = rd32(E1000_TSYNCTXCTL);
4853 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4854 wr32(E1000_TSYNCTXCTL, regval);
4855
4856 /* enable/disable RX, define which PTP packets are time stamped */
4857 regval = rd32(E1000_TSYNCRXCTL);
4858 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4859 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4860 wr32(E1000_TSYNCRXCTL, regval);
4861 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4862
4863 /*
4864 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4865 * (Ethertype to filter on)
4866 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4867 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4868 */
4869 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4870
4871 /* L4 Queue Filter[0]: only filter by source and destination port */
4872 wr32(E1000_SPQF0, htons(port));
4873 wr32(E1000_IMIREXT(0), is_l4 ?
4874 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4875 wr32(E1000_IMIR(0), is_l4 ?
4876 (htons(port)
4877 | (0<<16) /* immediate interrupt disabled */
4878 | 0 /* (1<<17) bit cleared: do not bypass
4879 destination port check */)
4880 : 0);
4881 wr32(E1000_FTQF0, is_l4 ?
4882 (0x11 /* UDP */
4883 | (1<<15) /* VF not compared */
4884 | (1<<27) /* Enable Timestamping */
4885 | (7<<28) /* only source port filter enabled,
4886 source/target address and protocol
4887 masked */)
4888 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4889 enabled */));
4890
4891 wrfl();
4892
4893 adapter->hwtstamp_config = config;
4894
4895 /* clear TX/RX time stamp registers, just to be sure */
4896 regval = rd32(E1000_TXSTMPH);
4897 regval = rd32(E1000_RXSTMPH);
4898
4899 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4900 -EFAULT : 0;
4901 }
4902
4903 /**
4904 * igb_ioctl -
4905 * @netdev:
4906 * @ifreq:
4907 * @cmd:
4908 **/
4909 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4910 {
4911 switch (cmd) {
4912 case SIOCGMIIPHY:
4913 case SIOCGMIIREG:
4914 case SIOCSMIIREG:
4915 return igb_mii_ioctl(netdev, ifr, cmd);
4916 case SIOCSHWTSTAMP:
4917 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
4918 default:
4919 return -EOPNOTSUPP;
4920 }
4921 }
4922
4923 static void igb_vlan_rx_register(struct net_device *netdev,
4924 struct vlan_group *grp)
4925 {
4926 struct igb_adapter *adapter = netdev_priv(netdev);
4927 struct e1000_hw *hw = &adapter->hw;
4928 u32 ctrl, rctl;
4929
4930 igb_irq_disable(adapter);
4931 adapter->vlgrp = grp;
4932
4933 if (grp) {
4934 /* enable VLAN tag insert/strip */
4935 ctrl = rd32(E1000_CTRL);
4936 ctrl |= E1000_CTRL_VME;
4937 wr32(E1000_CTRL, ctrl);
4938
4939 /* enable VLAN receive filtering */
4940 rctl = rd32(E1000_RCTL);
4941 rctl &= ~E1000_RCTL_CFIEN;
4942 wr32(E1000_RCTL, rctl);
4943 igb_update_mng_vlan(adapter);
4944 } else {
4945 /* disable VLAN tag insert/strip */
4946 ctrl = rd32(E1000_CTRL);
4947 ctrl &= ~E1000_CTRL_VME;
4948 wr32(E1000_CTRL, ctrl);
4949
4950 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4951 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4952 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4953 }
4954 }
4955
4956 igb_rlpml_set(adapter);
4957
4958 if (!test_bit(__IGB_DOWN, &adapter->state))
4959 igb_irq_enable(adapter);
4960 }
4961
4962 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4963 {
4964 struct igb_adapter *adapter = netdev_priv(netdev);
4965 struct e1000_hw *hw = &adapter->hw;
4966 int pf_id = adapter->vfs_allocated_count;
4967
4968 if ((hw->mng_cookie.status &
4969 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4970 (vid == adapter->mng_vlan_id))
4971 return;
4972
4973 /* add vid to vlvf if sr-iov is enabled,
4974 * if that fails add directly to filter table */
4975 if (igb_vlvf_set(adapter, vid, true, pf_id))
4976 igb_vfta_set(hw, vid, true);
4977
4978 }
4979
4980 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4981 {
4982 struct igb_adapter *adapter = netdev_priv(netdev);
4983 struct e1000_hw *hw = &adapter->hw;
4984 int pf_id = adapter->vfs_allocated_count;
4985
4986 igb_irq_disable(adapter);
4987 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4988
4989 if (!test_bit(__IGB_DOWN, &adapter->state))
4990 igb_irq_enable(adapter);
4991
4992 if ((adapter->hw.mng_cookie.status &
4993 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4994 (vid == adapter->mng_vlan_id)) {
4995 /* release control to f/w */
4996 igb_release_hw_control(adapter);
4997 return;
4998 }
4999
5000 /* remove vid from vlvf if sr-iov is enabled,
5001 * if not in vlvf remove from vfta */
5002 if (igb_vlvf_set(adapter, vid, false, pf_id))
5003 igb_vfta_set(hw, vid, false);
5004 }
5005
5006 static void igb_restore_vlan(struct igb_adapter *adapter)
5007 {
5008 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5009
5010 if (adapter->vlgrp) {
5011 u16 vid;
5012 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5013 if (!vlan_group_get_device(adapter->vlgrp, vid))
5014 continue;
5015 igb_vlan_rx_add_vid(adapter->netdev, vid);
5016 }
5017 }
5018 }
5019
5020 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5021 {
5022 struct e1000_mac_info *mac = &adapter->hw.mac;
5023
5024 mac->autoneg = 0;
5025
5026 /* Fiber NICs only allow 1000 gbps Full duplex */
5027 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5028 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5029 dev_err(&adapter->pdev->dev,
5030 "Unsupported Speed/Duplex configuration\n");
5031 return -EINVAL;
5032 }
5033
5034 switch (spddplx) {
5035 case SPEED_10 + DUPLEX_HALF:
5036 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5037 break;
5038 case SPEED_10 + DUPLEX_FULL:
5039 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5040 break;
5041 case SPEED_100 + DUPLEX_HALF:
5042 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5043 break;
5044 case SPEED_100 + DUPLEX_FULL:
5045 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5046 break;
5047 case SPEED_1000 + DUPLEX_FULL:
5048 mac->autoneg = 1;
5049 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5050 break;
5051 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5052 default:
5053 dev_err(&adapter->pdev->dev,
5054 "Unsupported Speed/Duplex configuration\n");
5055 return -EINVAL;
5056 }
5057 return 0;
5058 }
5059
5060 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5061 {
5062 struct net_device *netdev = pci_get_drvdata(pdev);
5063 struct igb_adapter *adapter = netdev_priv(netdev);
5064 struct e1000_hw *hw = &adapter->hw;
5065 u32 ctrl, rctl, status;
5066 u32 wufc = adapter->wol;
5067 #ifdef CONFIG_PM
5068 int retval = 0;
5069 #endif
5070
5071 netif_device_detach(netdev);
5072
5073 if (netif_running(netdev))
5074 igb_close(netdev);
5075
5076 igb_reset_interrupt_capability(adapter);
5077
5078 igb_free_queues(adapter);
5079
5080 #ifdef CONFIG_PM
5081 retval = pci_save_state(pdev);
5082 if (retval)
5083 return retval;
5084 #endif
5085
5086 status = rd32(E1000_STATUS);
5087 if (status & E1000_STATUS_LU)
5088 wufc &= ~E1000_WUFC_LNKC;
5089
5090 if (wufc) {
5091 igb_setup_rctl(adapter);
5092 igb_set_multi(netdev);
5093
5094 /* turn on all-multi mode if wake on multicast is enabled */
5095 if (wufc & E1000_WUFC_MC) {
5096 rctl = rd32(E1000_RCTL);
5097 rctl |= E1000_RCTL_MPE;
5098 wr32(E1000_RCTL, rctl);
5099 }
5100
5101 ctrl = rd32(E1000_CTRL);
5102 /* advertise wake from D3Cold */
5103 #define E1000_CTRL_ADVD3WUC 0x00100000
5104 /* phy power management enable */
5105 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5106 ctrl |= E1000_CTRL_ADVD3WUC;
5107 wr32(E1000_CTRL, ctrl);
5108
5109 /* Allow time for pending master requests to run */
5110 igb_disable_pcie_master(&adapter->hw);
5111
5112 wr32(E1000_WUC, E1000_WUC_PME_EN);
5113 wr32(E1000_WUFC, wufc);
5114 } else {
5115 wr32(E1000_WUC, 0);
5116 wr32(E1000_WUFC, 0);
5117 }
5118
5119 /* make sure adapter isn't asleep if manageability/wol is enabled */
5120 if (wufc || adapter->en_mng_pt) {
5121 pci_enable_wake(pdev, PCI_D3hot, 1);
5122 pci_enable_wake(pdev, PCI_D3cold, 1);
5123 } else {
5124 igb_shutdown_fiber_serdes_link_82575(hw);
5125 pci_enable_wake(pdev, PCI_D3hot, 0);
5126 pci_enable_wake(pdev, PCI_D3cold, 0);
5127 }
5128
5129 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5130 * would have already happened in close and is redundant. */
5131 igb_release_hw_control(adapter);
5132
5133 pci_disable_device(pdev);
5134
5135 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5136
5137 return 0;
5138 }
5139
5140 #ifdef CONFIG_PM
5141 static int igb_resume(struct pci_dev *pdev)
5142 {
5143 struct net_device *netdev = pci_get_drvdata(pdev);
5144 struct igb_adapter *adapter = netdev_priv(netdev);
5145 struct e1000_hw *hw = &adapter->hw;
5146 u32 err;
5147
5148 pci_set_power_state(pdev, PCI_D0);
5149 pci_restore_state(pdev);
5150
5151 err = pci_enable_device_mem(pdev);
5152 if (err) {
5153 dev_err(&pdev->dev,
5154 "igb: Cannot enable PCI device from suspend\n");
5155 return err;
5156 }
5157 pci_set_master(pdev);
5158
5159 pci_enable_wake(pdev, PCI_D3hot, 0);
5160 pci_enable_wake(pdev, PCI_D3cold, 0);
5161
5162 igb_set_interrupt_capability(adapter);
5163
5164 if (igb_alloc_queues(adapter)) {
5165 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5166 return -ENOMEM;
5167 }
5168
5169 /* e1000_power_up_phy(adapter); */
5170
5171 igb_reset(adapter);
5172
5173 /* let the f/w know that the h/w is now under the control of the
5174 * driver. */
5175 igb_get_hw_control(adapter);
5176
5177 wr32(E1000_WUS, ~0);
5178
5179 if (netif_running(netdev)) {
5180 err = igb_open(netdev);
5181 if (err)
5182 return err;
5183 }
5184
5185 netif_device_attach(netdev);
5186
5187 return 0;
5188 }
5189 #endif
5190
5191 static void igb_shutdown(struct pci_dev *pdev)
5192 {
5193 igb_suspend(pdev, PMSG_SUSPEND);
5194 }
5195
5196 #ifdef CONFIG_NET_POLL_CONTROLLER
5197 /*
5198 * Polling 'interrupt' - used by things like netconsole to send skbs
5199 * without having to re-enable interrupts. It's not called while
5200 * the interrupt routine is executing.
5201 */
5202 static void igb_netpoll(struct net_device *netdev)
5203 {
5204 struct igb_adapter *adapter = netdev_priv(netdev);
5205 struct e1000_hw *hw = &adapter->hw;
5206 int i;
5207
5208 if (!adapter->msix_entries) {
5209 igb_irq_disable(adapter);
5210 napi_schedule(&adapter->rx_ring[0].napi);
5211 return;
5212 }
5213
5214 for (i = 0; i < adapter->num_tx_queues; i++) {
5215 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5216 wr32(E1000_EIMC, tx_ring->eims_value);
5217 igb_clean_tx_irq(tx_ring);
5218 wr32(E1000_EIMS, tx_ring->eims_value);
5219 }
5220
5221 for (i = 0; i < adapter->num_rx_queues; i++) {
5222 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5223 wr32(E1000_EIMC, rx_ring->eims_value);
5224 napi_schedule(&rx_ring->napi);
5225 }
5226 }
5227 #endif /* CONFIG_NET_POLL_CONTROLLER */
5228
5229 /**
5230 * igb_io_error_detected - called when PCI error is detected
5231 * @pdev: Pointer to PCI device
5232 * @state: The current pci connection state
5233 *
5234 * This function is called after a PCI bus error affecting
5235 * this device has been detected.
5236 */
5237 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5238 pci_channel_state_t state)
5239 {
5240 struct net_device *netdev = pci_get_drvdata(pdev);
5241 struct igb_adapter *adapter = netdev_priv(netdev);
5242
5243 netif_device_detach(netdev);
5244
5245 if (netif_running(netdev))
5246 igb_down(adapter);
5247 pci_disable_device(pdev);
5248
5249 /* Request a slot slot reset. */
5250 return PCI_ERS_RESULT_NEED_RESET;
5251 }
5252
5253 /**
5254 * igb_io_slot_reset - called after the pci bus has been reset.
5255 * @pdev: Pointer to PCI device
5256 *
5257 * Restart the card from scratch, as if from a cold-boot. Implementation
5258 * resembles the first-half of the igb_resume routine.
5259 */
5260 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5261 {
5262 struct net_device *netdev = pci_get_drvdata(pdev);
5263 struct igb_adapter *adapter = netdev_priv(netdev);
5264 struct e1000_hw *hw = &adapter->hw;
5265 pci_ers_result_t result;
5266 int err;
5267
5268 if (pci_enable_device_mem(pdev)) {
5269 dev_err(&pdev->dev,
5270 "Cannot re-enable PCI device after reset.\n");
5271 result = PCI_ERS_RESULT_DISCONNECT;
5272 } else {
5273 pci_set_master(pdev);
5274 pci_restore_state(pdev);
5275
5276 pci_enable_wake(pdev, PCI_D3hot, 0);
5277 pci_enable_wake(pdev, PCI_D3cold, 0);
5278
5279 igb_reset(adapter);
5280 wr32(E1000_WUS, ~0);
5281 result = PCI_ERS_RESULT_RECOVERED;
5282 }
5283
5284 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5285 if (err) {
5286 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5287 "failed 0x%0x\n", err);
5288 /* non-fatal, continue */
5289 }
5290
5291 return result;
5292 }
5293
5294 /**
5295 * igb_io_resume - called when traffic can start flowing again.
5296 * @pdev: Pointer to PCI device
5297 *
5298 * This callback is called when the error recovery driver tells us that
5299 * its OK to resume normal operation. Implementation resembles the
5300 * second-half of the igb_resume routine.
5301 */
5302 static void igb_io_resume(struct pci_dev *pdev)
5303 {
5304 struct net_device *netdev = pci_get_drvdata(pdev);
5305 struct igb_adapter *adapter = netdev_priv(netdev);
5306
5307 if (netif_running(netdev)) {
5308 if (igb_up(adapter)) {
5309 dev_err(&pdev->dev, "igb_up failed after reset\n");
5310 return;
5311 }
5312 }
5313
5314 netif_device_attach(netdev);
5315
5316 /* let the f/w know that the h/w is now under the control of the
5317 * driver. */
5318 igb_get_hw_control(adapter);
5319 }
5320
5321 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5322 {
5323 u32 reg_data;
5324
5325 reg_data = rd32(E1000_VMOLR(vfn));
5326 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
5327 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
5328 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
5329 E1000_VMOLR_AUPE | /* Accept untagged packets */
5330 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5331 wr32(E1000_VMOLR(vfn), reg_data);
5332 }
5333
5334 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5335 int vfn)
5336 {
5337 struct e1000_hw *hw = &adapter->hw;
5338 u32 vmolr;
5339
5340 vmolr = rd32(E1000_VMOLR(vfn));
5341 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5342 vmolr |= size | E1000_VMOLR_LPE;
5343 wr32(E1000_VMOLR(vfn), vmolr);
5344
5345 return 0;
5346 }
5347
5348 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5349 {
5350 u32 reg_data;
5351
5352 reg_data = rd32(E1000_RAH(entry));
5353 reg_data &= ~E1000_RAH_POOL_MASK;
5354 reg_data |= E1000_RAH_POOL_1 << pool;;
5355 wr32(E1000_RAH(entry), reg_data);
5356 }
5357
5358 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5359 int entry_count, u16 total_rar_filters)
5360 {
5361 struct e1000_hw *hw = &adapter->hw;
5362 int i = adapter->vfs_allocated_count + 1;
5363
5364 if ((i + entry_count) < total_rar_filters)
5365 total_rar_filters = i + entry_count;
5366
5367 for (; i < total_rar_filters; i++)
5368 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5369 }
5370
5371 static int igb_set_vf_mac(struct igb_adapter *adapter,
5372 int vf, unsigned char *mac_addr)
5373 {
5374 struct e1000_hw *hw = &adapter->hw;
5375 int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5376
5377 igb_rar_set(hw, mac_addr, rar_entry);
5378
5379 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5380
5381 igb_set_rah_pool(hw, vf, rar_entry);
5382
5383 return 0;
5384 }
5385
5386 static void igb_vmm_control(struct igb_adapter *adapter)
5387 {
5388 struct e1000_hw *hw = &adapter->hw;
5389 u32 reg_data;
5390
5391 if (!adapter->vfs_allocated_count)
5392 return;
5393
5394 /* VF's need PF reset indication before they
5395 * can send/receive mail */
5396 reg_data = rd32(E1000_CTRL_EXT);
5397 reg_data |= E1000_CTRL_EXT_PFRSTD;
5398 wr32(E1000_CTRL_EXT, reg_data);
5399
5400 igb_vmdq_set_loopback_pf(hw, true);
5401 igb_vmdq_set_replication_pf(hw, true);
5402 }
5403
5404 #ifdef CONFIG_PCI_IOV
5405 static ssize_t igb_show_num_vfs(struct device *dev,
5406 struct device_attribute *attr, char *buf)
5407 {
5408 struct igb_adapter *adapter = netdev_priv(to_net_dev(dev));
5409
5410 return sprintf(buf, "%d\n", adapter->vfs_allocated_count);
5411 }
5412
5413 static ssize_t igb_set_num_vfs(struct device *dev,
5414 struct device_attribute *attr,
5415 const char *buf, size_t count)
5416 {
5417 struct net_device *netdev = to_net_dev(dev);
5418 struct igb_adapter *adapter = netdev_priv(netdev);
5419 struct e1000_hw *hw = &adapter->hw;
5420 struct pci_dev *pdev = adapter->pdev;
5421 unsigned int num_vfs, i;
5422 unsigned char mac_addr[ETH_ALEN];
5423 int err;
5424
5425 sscanf(buf, "%u", &num_vfs);
5426
5427 if (num_vfs > 7)
5428 num_vfs = 7;
5429
5430 /* value unchanged do nothing */
5431 if (num_vfs == adapter->vfs_allocated_count)
5432 return count;
5433
5434 if (netdev->flags & IFF_UP)
5435 igb_close(netdev);
5436
5437 igb_reset_interrupt_capability(adapter);
5438 igb_free_queues(adapter);
5439 adapter->tx_ring = NULL;
5440 adapter->rx_ring = NULL;
5441 adapter->vfs_allocated_count = 0;
5442
5443 /* reclaim resources allocated to VFs since we are changing count */
5444 if (adapter->vf_data) {
5445 /* disable iov and allow time for transactions to clear */
5446 pci_disable_sriov(pdev);
5447 msleep(500);
5448
5449 kfree(adapter->vf_data);
5450 adapter->vf_data = NULL;
5451 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
5452 msleep(100);
5453 dev_info(&pdev->dev, "IOV Disabled\n");
5454 }
5455
5456 if (num_vfs) {
5457 adapter->vf_data = kcalloc(num_vfs,
5458 sizeof(struct vf_data_storage),
5459 GFP_KERNEL);
5460 if (!adapter->vf_data) {
5461 dev_err(&pdev->dev, "Could not allocate VF private "
5462 "data - IOV enable failed\n");
5463 } else {
5464 err = pci_enable_sriov(pdev, num_vfs);
5465 if (!err) {
5466 adapter->vfs_allocated_count = num_vfs;
5467 dev_info(&pdev->dev, "%d vfs allocated\n", num_vfs);
5468 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5469 random_ether_addr(mac_addr);
5470 igb_set_vf_mac(adapter, i, mac_addr);
5471 }
5472 } else {
5473 kfree(adapter->vf_data);
5474 adapter->vf_data = NULL;
5475 }
5476 }
5477 }
5478
5479 igb_set_interrupt_capability(adapter);
5480 igb_alloc_queues(adapter);
5481 igb_reset(adapter);
5482
5483 if (netdev->flags & IFF_UP)
5484 igb_open(netdev);
5485
5486 return count;
5487 }
5488 #endif /* CONFIG_PCI_IOV */
5489 /* igb_main.c */
kernel-based virtual machine