1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/init.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/netdevice.h>
11 #include <linux/ethtool.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/mii.h>
17 #include <linux/if_ether.h>
18 #include <linux/if_vlan.h>
21 #include <linux/ipv6.h>
22 #include <linux/log2.h>
23 #include <linux/jiffies.h>
24 #include <linux/crc32.h>
29 #include <linux/of_device.h>
34 #define DRV_MODULE_NAME "niu"
35 #define PFX DRV_MODULE_NAME ": "
36 #define DRV_MODULE_VERSION "0.8"
37 #define DRV_MODULE_RELDATE "April 24, 2008"
39 static char version
[] __devinitdata
=
40 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION
);
47 #ifndef DMA_44BIT_MASK
48 #define DMA_44BIT_MASK 0x00000fffffffffffULL
52 static u64
readq(void __iomem
*reg
)
54 return (((u64
)readl(reg
+ 0x4UL
) << 32) |
58 static void writeq(u64 val
, void __iomem
*reg
)
60 writel(val
& 0xffffffff, reg
);
61 writel(val
>> 32, reg
+ 0x4UL
);
65 static struct pci_device_id niu_pci_tbl
[] = {
66 {PCI_DEVICE(PCI_VENDOR_ID_SUN
, 0xabcd)},
70 MODULE_DEVICE_TABLE(pci
, niu_pci_tbl
);
72 #define NIU_TX_TIMEOUT (5 * HZ)
74 #define nr64(reg) readq(np->regs + (reg))
75 #define nw64(reg, val) writeq((val), np->regs + (reg))
77 #define nr64_mac(reg) readq(np->mac_regs + (reg))
78 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
80 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
81 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
83 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
84 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
86 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
87 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
89 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
92 static int debug
= -1;
93 module_param(debug
, int, 0);
94 MODULE_PARM_DESC(debug
, "NIU debug level");
96 #define niudbg(TYPE, f, a...) \
97 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
98 printk(KERN_DEBUG PFX f, ## a); \
101 #define niuinfo(TYPE, f, a...) \
102 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
103 printk(KERN_INFO PFX f, ## a); \
106 #define niuwarn(TYPE, f, a...) \
107 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
108 printk(KERN_WARNING PFX f, ## a); \
111 #define niu_lock_parent(np, flags) \
112 spin_lock_irqsave(&np->parent->lock, flags)
113 #define niu_unlock_parent(np, flags) \
114 spin_unlock_irqrestore(&np->parent->lock, flags)
116 static int serdes_init_10g_serdes(struct niu
*np
);
118 static int __niu_wait_bits_clear_mac(struct niu
*np
, unsigned long reg
,
119 u64 bits
, int limit
, int delay
)
121 while (--limit
>= 0) {
122 u64 val
= nr64_mac(reg
);
133 static int __niu_set_and_wait_clear_mac(struct niu
*np
, unsigned long reg
,
134 u64 bits
, int limit
, int delay
,
135 const char *reg_name
)
140 err
= __niu_wait_bits_clear_mac(np
, reg
, bits
, limit
, delay
);
142 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
143 "would not clear, val[%llx]\n",
144 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
145 (unsigned long long) nr64_mac(reg
));
149 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
150 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
151 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
154 static int __niu_wait_bits_clear_ipp(struct niu
*np
, unsigned long reg
,
155 u64 bits
, int limit
, int delay
)
157 while (--limit
>= 0) {
158 u64 val
= nr64_ipp(reg
);
169 static int __niu_set_and_wait_clear_ipp(struct niu
*np
, unsigned long reg
,
170 u64 bits
, int limit
, int delay
,
171 const char *reg_name
)
180 err
= __niu_wait_bits_clear_ipp(np
, reg
, bits
, limit
, delay
);
182 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
183 "would not clear, val[%llx]\n",
184 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
185 (unsigned long long) nr64_ipp(reg
));
189 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
191 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
194 static int __niu_wait_bits_clear(struct niu
*np
, unsigned long reg
,
195 u64 bits
, int limit
, int delay
)
197 while (--limit
>= 0) {
209 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
211 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
214 static int __niu_set_and_wait_clear(struct niu
*np
, unsigned long reg
,
215 u64 bits
, int limit
, int delay
,
216 const char *reg_name
)
221 err
= __niu_wait_bits_clear(np
, reg
, bits
, limit
, delay
);
223 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
224 "would not clear, val[%llx]\n",
225 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
226 (unsigned long long) nr64(reg
));
230 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
231 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
232 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
235 static void niu_ldg_rearm(struct niu
*np
, struct niu_ldg
*lp
, int on
)
237 u64 val
= (u64
) lp
->timer
;
240 val
|= LDG_IMGMT_ARM
;
242 nw64(LDG_IMGMT(lp
->ldg_num
), val
);
245 static int niu_ldn_irq_enable(struct niu
*np
, int ldn
, int on
)
247 unsigned long mask_reg
, bits
;
250 if (ldn
< 0 || ldn
> LDN_MAX
)
254 mask_reg
= LD_IM0(ldn
);
257 mask_reg
= LD_IM1(ldn
- 64);
261 val
= nr64(mask_reg
);
271 static int niu_enable_ldn_in_ldg(struct niu
*np
, struct niu_ldg
*lp
, int on
)
273 struct niu_parent
*parent
= np
->parent
;
276 for (i
= 0; i
<= LDN_MAX
; i
++) {
279 if (parent
->ldg_map
[i
] != lp
->ldg_num
)
282 err
= niu_ldn_irq_enable(np
, i
, on
);
289 static int niu_enable_interrupts(struct niu
*np
, int on
)
293 for (i
= 0; i
< np
->num_ldg
; i
++) {
294 struct niu_ldg
*lp
= &np
->ldg
[i
];
297 err
= niu_enable_ldn_in_ldg(np
, lp
, on
);
301 for (i
= 0; i
< np
->num_ldg
; i
++)
302 niu_ldg_rearm(np
, &np
->ldg
[i
], on
);
307 static u32
phy_encode(u32 type
, int port
)
309 return (type
<< (port
* 2));
312 static u32
phy_decode(u32 val
, int port
)
314 return (val
>> (port
* 2)) & PORT_TYPE_MASK
;
317 static int mdio_wait(struct niu
*np
)
322 while (--limit
> 0) {
323 val
= nr64(MIF_FRAME_OUTPUT
);
324 if ((val
>> MIF_FRAME_OUTPUT_TA_SHIFT
) & 0x1)
325 return val
& MIF_FRAME_OUTPUT_DATA
;
333 static int mdio_read(struct niu
*np
, int port
, int dev
, int reg
)
337 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
342 nw64(MIF_FRAME_OUTPUT
, MDIO_READ_OP(port
, dev
));
343 return mdio_wait(np
);
346 static int mdio_write(struct niu
*np
, int port
, int dev
, int reg
, int data
)
350 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
355 nw64(MIF_FRAME_OUTPUT
, MDIO_WRITE_OP(port
, dev
, data
));
363 static int mii_read(struct niu
*np
, int port
, int reg
)
365 nw64(MIF_FRAME_OUTPUT
, MII_READ_OP(port
, reg
));
366 return mdio_wait(np
);
369 static int mii_write(struct niu
*np
, int port
, int reg
, int data
)
373 nw64(MIF_FRAME_OUTPUT
, MII_WRITE_OP(port
, reg
, data
));
381 static int esr2_set_tx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
385 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
386 ESR2_TI_PLL_TX_CFG_L(channel
),
389 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
390 ESR2_TI_PLL_TX_CFG_H(channel
),
395 static int esr2_set_rx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
399 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
400 ESR2_TI_PLL_RX_CFG_L(channel
),
403 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
404 ESR2_TI_PLL_RX_CFG_H(channel
),
409 /* Mode is always 10G fiber. */
410 static int serdes_init_niu(struct niu
*np
)
412 struct niu_link_config
*lp
= &np
->link_config
;
416 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
417 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
418 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
419 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
421 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
422 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
424 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
425 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
427 tx_cfg
|= PLL_TX_CFG_ENTEST
;
428 rx_cfg
|= PLL_RX_CFG_ENTEST
;
431 /* Initialize all 4 lanes of the SERDES. */
432 for (i
= 0; i
< 4; i
++) {
433 int err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
438 for (i
= 0; i
< 4; i
++) {
439 int err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
447 static int esr_read_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32
*val
)
451 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
, ESR_RXTX_CTRL_L(chan
));
453 *val
= (err
& 0xffff);
454 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
455 ESR_RXTX_CTRL_H(chan
));
457 *val
|= ((err
& 0xffff) << 16);
463 static int esr_read_glue0(struct niu
*np
, unsigned long chan
, u32
*val
)
467 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
468 ESR_GLUE_CTRL0_L(chan
));
470 *val
= (err
& 0xffff);
471 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
472 ESR_GLUE_CTRL0_H(chan
));
474 *val
|= ((err
& 0xffff) << 16);
481 static int esr_read_reset(struct niu
*np
, u32
*val
)
485 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
486 ESR_RXTX_RESET_CTRL_L
);
488 *val
= (err
& 0xffff);
489 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
490 ESR_RXTX_RESET_CTRL_H
);
492 *val
|= ((err
& 0xffff) << 16);
499 static int esr_write_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32 val
)
503 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
504 ESR_RXTX_CTRL_L(chan
), val
& 0xffff);
506 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
507 ESR_RXTX_CTRL_H(chan
), (val
>> 16));
511 static int esr_write_glue0(struct niu
*np
, unsigned long chan
, u32 val
)
515 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
516 ESR_GLUE_CTRL0_L(chan
), val
& 0xffff);
518 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
519 ESR_GLUE_CTRL0_H(chan
), (val
>> 16));
523 static int esr_reset(struct niu
*np
)
528 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
529 ESR_RXTX_RESET_CTRL_L
, 0x0000);
532 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
533 ESR_RXTX_RESET_CTRL_H
, 0xffff);
538 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
539 ESR_RXTX_RESET_CTRL_L
, 0xffff);
544 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
545 ESR_RXTX_RESET_CTRL_H
, 0x0000);
550 err
= esr_read_reset(np
, &reset
);
554 dev_err(np
->device
, PFX
"Port %u ESR_RESET "
555 "did not clear [%08x]\n",
563 static int serdes_init_10g(struct niu
*np
)
565 struct niu_link_config
*lp
= &np
->link_config
;
566 unsigned long ctrl_reg
, test_cfg_reg
, i
;
567 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
572 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
573 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
576 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
577 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
583 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
584 ENET_SERDES_CTRL_SDET_1
|
585 ENET_SERDES_CTRL_SDET_2
|
586 ENET_SERDES_CTRL_SDET_3
|
587 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
588 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
589 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
590 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
591 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
592 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
593 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
594 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
597 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
598 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
599 ENET_SERDES_TEST_MD_0_SHIFT
) |
600 (ENET_TEST_MD_PAD_LOOPBACK
<<
601 ENET_SERDES_TEST_MD_1_SHIFT
) |
602 (ENET_TEST_MD_PAD_LOOPBACK
<<
603 ENET_SERDES_TEST_MD_2_SHIFT
) |
604 (ENET_TEST_MD_PAD_LOOPBACK
<<
605 ENET_SERDES_TEST_MD_3_SHIFT
));
608 nw64(ctrl_reg
, ctrl_val
);
609 nw64(test_cfg_reg
, test_cfg_val
);
611 /* Initialize all 4 lanes of the SERDES. */
612 for (i
= 0; i
< 4; i
++) {
613 u32 rxtx_ctrl
, glue0
;
615 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
618 err
= esr_read_glue0(np
, i
, &glue0
);
622 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
623 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
624 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
626 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
627 ESR_GLUE_CTRL0_THCNT
|
628 ESR_GLUE_CTRL0_BLTIME
);
629 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
630 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
631 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
632 (BLTIME_300_CYCLES
<<
633 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
635 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
638 err
= esr_write_glue0(np
, i
, glue0
);
647 sig
= nr64(ESR_INT_SIGNALS
);
650 mask
= ESR_INT_SIGNALS_P0_BITS
;
651 val
= (ESR_INT_SRDY0_P0
|
661 mask
= ESR_INT_SIGNALS_P1_BITS
;
662 val
= (ESR_INT_SRDY0_P1
|
675 if ((sig
& mask
) != val
) {
676 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
677 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
680 dev_err(np
->device
, PFX
"Port %u signal bits [%08x] are not "
681 "[%08x]\n", np
->port
, (int) (sig
& mask
), (int) val
);
684 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
)
685 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
689 static int serdes_init_1g(struct niu
*np
)
693 val
= nr64(ENET_SERDES_1_PLL_CFG
);
694 val
&= ~ENET_SERDES_PLL_FBDIV2
;
697 val
|= ENET_SERDES_PLL_HRATE0
;
700 val
|= ENET_SERDES_PLL_HRATE1
;
703 val
|= ENET_SERDES_PLL_HRATE2
;
706 val
|= ENET_SERDES_PLL_HRATE3
;
711 nw64(ENET_SERDES_1_PLL_CFG
, val
);
716 static int serdes_init_1g_serdes(struct niu
*np
)
718 struct niu_link_config
*lp
= &np
->link_config
;
719 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
720 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
722 u64 reset_val
, val_rd
;
724 val
= ENET_SERDES_PLL_HRATE0
| ENET_SERDES_PLL_HRATE1
|
725 ENET_SERDES_PLL_HRATE2
| ENET_SERDES_PLL_HRATE3
|
726 ENET_SERDES_PLL_FBDIV0
;
729 reset_val
= ENET_SERDES_RESET_0
;
730 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
731 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
732 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
735 reset_val
= ENET_SERDES_RESET_1
;
736 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
737 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
738 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
744 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
745 ENET_SERDES_CTRL_SDET_1
|
746 ENET_SERDES_CTRL_SDET_2
|
747 ENET_SERDES_CTRL_SDET_3
|
748 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
749 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
750 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
751 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
752 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
753 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
754 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
755 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
758 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
759 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
760 ENET_SERDES_TEST_MD_0_SHIFT
) |
761 (ENET_TEST_MD_PAD_LOOPBACK
<<
762 ENET_SERDES_TEST_MD_1_SHIFT
) |
763 (ENET_TEST_MD_PAD_LOOPBACK
<<
764 ENET_SERDES_TEST_MD_2_SHIFT
) |
765 (ENET_TEST_MD_PAD_LOOPBACK
<<
766 ENET_SERDES_TEST_MD_3_SHIFT
));
769 nw64(ENET_SERDES_RESET
, reset_val
);
771 val_rd
= nr64(ENET_SERDES_RESET
);
772 val_rd
&= ~reset_val
;
774 nw64(ctrl_reg
, ctrl_val
);
775 nw64(test_cfg_reg
, test_cfg_val
);
776 nw64(ENET_SERDES_RESET
, val_rd
);
779 /* Initialize all 4 lanes of the SERDES. */
780 for (i
= 0; i
< 4; i
++) {
781 u32 rxtx_ctrl
, glue0
;
783 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
786 err
= esr_read_glue0(np
, i
, &glue0
);
790 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
791 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
792 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
794 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
795 ESR_GLUE_CTRL0_THCNT
|
796 ESR_GLUE_CTRL0_BLTIME
);
797 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
798 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
799 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
800 (BLTIME_300_CYCLES
<<
801 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
803 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
806 err
= esr_write_glue0(np
, i
, glue0
);
812 sig
= nr64(ESR_INT_SIGNALS
);
815 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
820 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
828 if ((sig
& mask
) != val
) {
829 dev_err(np
->device
, PFX
"Port %u signal bits [%08x] are not "
830 "[%08x]\n", np
->port
, (int) (sig
& mask
), (int) val
);
837 static int link_status_1g_serdes(struct niu
*np
, int *link_up_p
)
839 struct niu_link_config
*lp
= &np
->link_config
;
847 current_speed
= SPEED_INVALID
;
848 current_duplex
= DUPLEX_INVALID
;
850 spin_lock_irqsave(&np
->lock
, flags
);
852 val
= nr64_pcs(PCS_MII_STAT
);
854 if (val
& PCS_MII_STAT_LINK_STATUS
) {
856 current_speed
= SPEED_1000
;
857 current_duplex
= DUPLEX_FULL
;
860 lp
->active_speed
= current_speed
;
861 lp
->active_duplex
= current_duplex
;
862 spin_unlock_irqrestore(&np
->lock
, flags
);
864 *link_up_p
= link_up
;
869 static int link_status_10g_serdes(struct niu
*np
, int *link_up_p
)
872 struct niu_link_config
*lp
= &np
->link_config
;
879 if (!(np
->flags
& NIU_FLAGS_10G
))
880 return link_status_1g_serdes(np
, link_up_p
);
882 current_speed
= SPEED_INVALID
;
883 current_duplex
= DUPLEX_INVALID
;
884 spin_lock_irqsave(&np
->lock
, flags
);
886 val
= nr64_xpcs(XPCS_STATUS(0));
887 val2
= nr64_mac(XMAC_INTER2
);
888 if (val2
& 0x01000000)
891 if ((val
& 0x1000ULL
) && link_ok
) {
893 current_speed
= SPEED_10000
;
894 current_duplex
= DUPLEX_FULL
;
896 lp
->active_speed
= current_speed
;
897 lp
->active_duplex
= current_duplex
;
898 spin_unlock_irqrestore(&np
->lock
, flags
);
899 *link_up_p
= link_up
;
904 static int link_status_1g_rgmii(struct niu
*np
, int *link_up_p
)
906 struct niu_link_config
*lp
= &np
->link_config
;
907 u16 current_speed
, bmsr
;
913 current_speed
= SPEED_INVALID
;
914 current_duplex
= DUPLEX_INVALID
;
916 spin_lock_irqsave(&np
->lock
, flags
);
920 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
925 if (bmsr
& BMSR_LSTATUS
) {
926 u16 adv
, lpa
, common
, estat
;
928 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
933 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
940 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
945 current_speed
= SPEED_1000
;
946 current_duplex
= DUPLEX_FULL
;
949 lp
->active_speed
= current_speed
;
950 lp
->active_duplex
= current_duplex
;
954 spin_unlock_irqrestore(&np
->lock
, flags
);
956 *link_up_p
= link_up
;
961 static int bcm8704_reset(struct niu
*np
)
965 err
= mdio_read(np
, np
->phy_addr
,
966 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
970 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
976 while (--limit
>= 0) {
977 err
= mdio_read(np
, np
->phy_addr
,
978 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
981 if (!(err
& BMCR_RESET
))
985 dev_err(np
->device
, PFX
"Port %u PHY will not reset "
986 "(bmcr=%04x)\n", np
->port
, (err
& 0xffff));
992 /* When written, certain PHY registers need to be read back twice
993 * in order for the bits to settle properly.
995 static int bcm8704_user_dev3_readback(struct niu
*np
, int reg
)
997 int err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1000 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1006 static int bcm8706_init_user_dev3(struct niu
*np
)
1011 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1012 BCM8704_USER_OPT_DIGITAL_CTRL
);
1015 err
&= ~USER_ODIG_CTRL_GPIOS
;
1016 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1017 err
|= USER_ODIG_CTRL_RESV2
;
1018 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1019 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1028 static int bcm8704_init_user_dev3(struct niu
*np
)
1032 err
= mdio_write(np
, np
->phy_addr
,
1033 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_CONTROL
,
1034 (USER_CONTROL_OPTXRST_LVL
|
1035 USER_CONTROL_OPBIASFLT_LVL
|
1036 USER_CONTROL_OBTMPFLT_LVL
|
1037 USER_CONTROL_OPPRFLT_LVL
|
1038 USER_CONTROL_OPTXFLT_LVL
|
1039 USER_CONTROL_OPRXLOS_LVL
|
1040 USER_CONTROL_OPRXFLT_LVL
|
1041 USER_CONTROL_OPTXON_LVL
|
1042 (0x3f << USER_CONTROL_RES1_SHIFT
)));
1046 err
= mdio_write(np
, np
->phy_addr
,
1047 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_PMD_TX_CONTROL
,
1048 (USER_PMD_TX_CTL_XFP_CLKEN
|
1049 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH
) |
1050 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH
) |
1051 USER_PMD_TX_CTL_TSCK_LPWREN
));
1055 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_CONTROL
);
1058 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_PMD_TX_CONTROL
);
1062 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1063 BCM8704_USER_OPT_DIGITAL_CTRL
);
1066 err
&= ~USER_ODIG_CTRL_GPIOS
;
1067 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1068 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1069 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1078 static int mrvl88x2011_act_led(struct niu
*np
, int val
)
1082 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1083 MRVL88X2011_LED_8_TO_11_CTL
);
1087 err
&= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT
,MRVL88X2011_LED_CTL_MASK
);
1088 err
|= MRVL88X2011_LED(MRVL88X2011_LED_ACT
,val
);
1090 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1091 MRVL88X2011_LED_8_TO_11_CTL
, err
);
1094 static int mrvl88x2011_led_blink_rate(struct niu
*np
, int rate
)
1098 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1099 MRVL88X2011_LED_BLINK_CTL
);
1101 err
&= ~MRVL88X2011_LED_BLKRATE_MASK
;
1104 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1105 MRVL88X2011_LED_BLINK_CTL
, err
);
1111 static int xcvr_init_10g_mrvl88x2011(struct niu
*np
)
1115 /* Set LED functions */
1116 err
= mrvl88x2011_led_blink_rate(np
, MRVL88X2011_LED_BLKRATE_134MS
);
1121 err
= mrvl88x2011_act_led(np
, MRVL88X2011_LED_CTL_OFF
);
1125 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1126 MRVL88X2011_GENERAL_CTL
);
1130 err
|= MRVL88X2011_ENA_XFPREFCLK
;
1132 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1133 MRVL88X2011_GENERAL_CTL
, err
);
1137 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1138 MRVL88X2011_PMA_PMD_CTL_1
);
1142 if (np
->link_config
.loopback_mode
== LOOPBACK_MAC
)
1143 err
|= MRVL88X2011_LOOPBACK
;
1145 err
&= ~MRVL88X2011_LOOPBACK
;
1147 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1148 MRVL88X2011_PMA_PMD_CTL_1
, err
);
1153 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1154 MRVL88X2011_10G_PMD_TX_DIS
, MRVL88X2011_ENA_PMDTX
);
1158 static int xcvr_diag_bcm870x(struct niu
*np
)
1160 u16 analog_stat0
, tx_alarm_status
;
1164 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1168 pr_info(PFX
"Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1171 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, 0x20);
1174 pr_info(PFX
"Port %u USER_DEV3(0x20) [%04x]\n",
1177 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1181 pr_info(PFX
"Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1185 /* XXX dig this out it might not be so useful XXX */
1186 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1187 BCM8704_USER_ANALOG_STATUS0
);
1190 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1191 BCM8704_USER_ANALOG_STATUS0
);
1196 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1197 BCM8704_USER_TX_ALARM_STATUS
);
1200 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1201 BCM8704_USER_TX_ALARM_STATUS
);
1204 tx_alarm_status
= err
;
1206 if (analog_stat0
!= 0x03fc) {
1207 if ((analog_stat0
== 0x43bc) && (tx_alarm_status
!= 0)) {
1208 pr_info(PFX
"Port %u cable not connected "
1209 "or bad cable.\n", np
->port
);
1210 } else if (analog_stat0
== 0x639c) {
1211 pr_info(PFX
"Port %u optical module is bad "
1212 "or missing.\n", np
->port
);
1219 static int xcvr_10g_set_lb_bcm870x(struct niu
*np
)
1221 struct niu_link_config
*lp
= &np
->link_config
;
1224 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1229 err
&= ~BMCR_LOOPBACK
;
1231 if (lp
->loopback_mode
== LOOPBACK_MAC
)
1232 err
|= BMCR_LOOPBACK
;
1234 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1242 static int xcvr_init_10g_bcm8706(struct niu
*np
)
1247 if ((np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) &&
1248 (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) == 0)
1251 val
= nr64_mac(XMAC_CONFIG
);
1252 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1253 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1254 nw64_mac(XMAC_CONFIG
, val
);
1256 val
= nr64(MIF_CONFIG
);
1257 val
|= MIF_CONFIG_INDIRECT_MODE
;
1258 nw64(MIF_CONFIG
, val
);
1260 err
= bcm8704_reset(np
);
1264 err
= xcvr_10g_set_lb_bcm870x(np
);
1268 err
= bcm8706_init_user_dev3(np
);
1272 err
= xcvr_diag_bcm870x(np
);
1279 static int xcvr_init_10g_bcm8704(struct niu
*np
)
1283 err
= bcm8704_reset(np
);
1287 err
= bcm8704_init_user_dev3(np
);
1291 err
= xcvr_10g_set_lb_bcm870x(np
);
1295 err
= xcvr_diag_bcm870x(np
);
1302 static int xcvr_init_10g(struct niu
*np
)
1307 val
= nr64_mac(XMAC_CONFIG
);
1308 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1309 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1310 nw64_mac(XMAC_CONFIG
, val
);
1312 /* XXX shared resource, lock parent XXX */
1313 val
= nr64(MIF_CONFIG
);
1314 val
|= MIF_CONFIG_INDIRECT_MODE
;
1315 nw64(MIF_CONFIG
, val
);
1317 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
1318 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
1320 /* handle different phy types */
1321 switch (phy_id
& NIU_PHY_ID_MASK
) {
1322 case NIU_PHY_ID_MRVL88X2011
:
1323 err
= xcvr_init_10g_mrvl88x2011(np
);
1326 default: /* bcom 8704 */
1327 err
= xcvr_init_10g_bcm8704(np
);
1334 static int mii_reset(struct niu
*np
)
1338 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, BMCR_RESET
);
1343 while (--limit
>= 0) {
1345 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1348 if (!(err
& BMCR_RESET
))
1352 dev_err(np
->device
, PFX
"Port %u MII would not reset, "
1353 "bmcr[%04x]\n", np
->port
, err
);
1362 static int xcvr_init_1g_rgmii(struct niu
*np
)
1366 u16 bmcr
, bmsr
, estat
;
1368 val
= nr64(MIF_CONFIG
);
1369 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1370 nw64(MIF_CONFIG
, val
);
1372 err
= mii_reset(np
);
1376 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1382 if (bmsr
& BMSR_ESTATEN
) {
1383 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1390 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1394 if (bmsr
& BMSR_ESTATEN
) {
1397 if (estat
& ESTATUS_1000_TFULL
)
1398 ctrl1000
|= ADVERTISE_1000FULL
;
1399 err
= mii_write(np
, np
->phy_addr
, MII_CTRL1000
, ctrl1000
);
1404 bmcr
= (BMCR_SPEED1000
| BMCR_FULLDPLX
);
1406 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1410 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1413 bmcr
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1415 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1423 static int mii_init_common(struct niu
*np
)
1425 struct niu_link_config
*lp
= &np
->link_config
;
1426 u16 bmcr
, bmsr
, adv
, estat
;
1429 err
= mii_reset(np
);
1433 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1439 if (bmsr
& BMSR_ESTATEN
) {
1440 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1447 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1451 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
1452 bmcr
|= BMCR_LOOPBACK
;
1453 if (lp
->active_speed
== SPEED_1000
)
1454 bmcr
|= BMCR_SPEED1000
;
1455 if (lp
->active_duplex
== DUPLEX_FULL
)
1456 bmcr
|= BMCR_FULLDPLX
;
1459 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
1462 aux
= (BCM5464R_AUX_CTL_EXT_LB
|
1463 BCM5464R_AUX_CTL_WRITE_1
);
1464 err
= mii_write(np
, np
->phy_addr
, BCM5464R_AUX_CTL
, aux
);
1469 /* XXX configurable XXX */
1470 /* XXX for now don't advertise half-duplex or asym pause... XXX */
1471 adv
= ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
;
1472 if (bmsr
& BMSR_10FULL
)
1473 adv
|= ADVERTISE_10FULL
;
1474 if (bmsr
& BMSR_100FULL
)
1475 adv
|= ADVERTISE_100FULL
;
1476 err
= mii_write(np
, np
->phy_addr
, MII_ADVERTISE
, adv
);
1480 if (bmsr
& BMSR_ESTATEN
) {
1483 if (estat
& ESTATUS_1000_TFULL
)
1484 ctrl1000
|= ADVERTISE_1000FULL
;
1485 err
= mii_write(np
, np
->phy_addr
, MII_CTRL1000
, ctrl1000
);
1489 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1491 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1495 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1498 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1502 pr_info(PFX
"Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1503 np
->port
, bmcr
, bmsr
);
1509 static int xcvr_init_1g(struct niu
*np
)
1513 /* XXX shared resource, lock parent XXX */
1514 val
= nr64(MIF_CONFIG
);
1515 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1516 nw64(MIF_CONFIG
, val
);
1518 return mii_init_common(np
);
1521 static int niu_xcvr_init(struct niu
*np
)
1523 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1528 err
= ops
->xcvr_init(np
);
1533 static int niu_serdes_init(struct niu
*np
)
1535 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1539 if (ops
->serdes_init
)
1540 err
= ops
->serdes_init(np
);
1545 static void niu_init_xif(struct niu
*);
1546 static void niu_handle_led(struct niu
*, int status
);
1548 static int niu_link_status_common(struct niu
*np
, int link_up
)
1550 struct niu_link_config
*lp
= &np
->link_config
;
1551 struct net_device
*dev
= np
->dev
;
1552 unsigned long flags
;
1554 if (!netif_carrier_ok(dev
) && link_up
) {
1555 niuinfo(LINK
, "%s: Link is up at %s, %s duplex\n",
1557 (lp
->active_speed
== SPEED_10000
?
1559 (lp
->active_speed
== SPEED_1000
?
1561 (lp
->active_speed
== SPEED_100
?
1562 "100Mbit/sec" : "10Mbit/sec"))),
1563 (lp
->active_duplex
== DUPLEX_FULL
?
1566 spin_lock_irqsave(&np
->lock
, flags
);
1568 niu_handle_led(np
, 1);
1569 spin_unlock_irqrestore(&np
->lock
, flags
);
1571 netif_carrier_on(dev
);
1572 } else if (netif_carrier_ok(dev
) && !link_up
) {
1573 niuwarn(LINK
, "%s: Link is down\n", dev
->name
);
1574 spin_lock_irqsave(&np
->lock
, flags
);
1575 niu_handle_led(np
, 0);
1576 spin_unlock_irqrestore(&np
->lock
, flags
);
1577 netif_carrier_off(dev
);
1583 static int link_status_10g_mrvl(struct niu
*np
, int *link_up_p
)
1585 int err
, link_up
, pma_status
, pcs_status
;
1589 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1590 MRVL88X2011_10G_PMD_STATUS_2
);
1594 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1595 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1596 MRVL88X2011_PMA_PMD_STATUS_1
);
1600 pma_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
1602 /* Check PMC Register : 3.0001.2 == 1: read twice */
1603 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1604 MRVL88X2011_PMA_PMD_STATUS_1
);
1608 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1609 MRVL88X2011_PMA_PMD_STATUS_1
);
1613 pcs_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
1615 /* Check XGXS Register : 4.0018.[0-3,12] */
1616 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV4_ADDR
,
1617 MRVL88X2011_10G_XGXS_LANE_STAT
);
1621 if (err
== (PHYXS_XGXS_LANE_STAT_ALINGED
| PHYXS_XGXS_LANE_STAT_LANE3
|
1622 PHYXS_XGXS_LANE_STAT_LANE2
| PHYXS_XGXS_LANE_STAT_LANE1
|
1623 PHYXS_XGXS_LANE_STAT_LANE0
| PHYXS_XGXS_LANE_STAT_MAGIC
|
1625 link_up
= (pma_status
&& pcs_status
) ? 1 : 0;
1627 np
->link_config
.active_speed
= SPEED_10000
;
1628 np
->link_config
.active_duplex
= DUPLEX_FULL
;
1631 mrvl88x2011_act_led(np
, (link_up
?
1632 MRVL88X2011_LED_CTL_PCS_ACT
:
1633 MRVL88X2011_LED_CTL_OFF
));
1635 *link_up_p
= link_up
;
1639 static int link_status_10g_bcm8706(struct niu
*np
, int *link_up_p
)
1644 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1645 BCM8704_PMD_RCV_SIGDET
);
1648 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
1653 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1654 BCM8704_PCS_10G_R_STATUS
);
1658 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
1663 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1664 BCM8704_PHYXS_XGXS_LANE_STAT
);
1667 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
1668 PHYXS_XGXS_LANE_STAT_MAGIC
|
1669 PHYXS_XGXS_LANE_STAT_PATTEST
|
1670 PHYXS_XGXS_LANE_STAT_LANE3
|
1671 PHYXS_XGXS_LANE_STAT_LANE2
|
1672 PHYXS_XGXS_LANE_STAT_LANE1
|
1673 PHYXS_XGXS_LANE_STAT_LANE0
)) {
1675 np
->link_config
.active_speed
= SPEED_INVALID
;
1676 np
->link_config
.active_duplex
= DUPLEX_INVALID
;
1681 np
->link_config
.active_speed
= SPEED_10000
;
1682 np
->link_config
.active_duplex
= DUPLEX_FULL
;
1686 *link_up_p
= link_up
;
1687 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
)
1692 static int link_status_10g_bcom(struct niu
*np
, int *link_up_p
)
1698 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1699 BCM8704_PMD_RCV_SIGDET
);
1702 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
1707 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1708 BCM8704_PCS_10G_R_STATUS
);
1711 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
1716 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1717 BCM8704_PHYXS_XGXS_LANE_STAT
);
1721 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
1722 PHYXS_XGXS_LANE_STAT_MAGIC
|
1723 PHYXS_XGXS_LANE_STAT_LANE3
|
1724 PHYXS_XGXS_LANE_STAT_LANE2
|
1725 PHYXS_XGXS_LANE_STAT_LANE1
|
1726 PHYXS_XGXS_LANE_STAT_LANE0
)) {
1732 np
->link_config
.active_speed
= SPEED_10000
;
1733 np
->link_config
.active_duplex
= DUPLEX_FULL
;
1737 *link_up_p
= link_up
;
1741 static int link_status_10g(struct niu
*np
, int *link_up_p
)
1743 unsigned long flags
;
1746 spin_lock_irqsave(&np
->lock
, flags
);
1748 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
1751 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
1752 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
1754 /* handle different phy types */
1755 switch (phy_id
& NIU_PHY_ID_MASK
) {
1756 case NIU_PHY_ID_MRVL88X2011
:
1757 err
= link_status_10g_mrvl(np
, link_up_p
);
1760 default: /* bcom 8704 */
1761 err
= link_status_10g_bcom(np
, link_up_p
);
1766 spin_unlock_irqrestore(&np
->lock
, flags
);
1771 static int niu_10g_phy_present(struct niu
*np
)
1775 sig
= nr64(ESR_INT_SIGNALS
);
1778 mask
= ESR_INT_SIGNALS_P0_BITS
;
1779 val
= (ESR_INT_SRDY0_P0
|
1782 ESR_INT_XDP_P0_CH3
|
1783 ESR_INT_XDP_P0_CH2
|
1784 ESR_INT_XDP_P0_CH1
|
1785 ESR_INT_XDP_P0_CH0
);
1789 mask
= ESR_INT_SIGNALS_P1_BITS
;
1790 val
= (ESR_INT_SRDY0_P1
|
1793 ESR_INT_XDP_P1_CH3
|
1794 ESR_INT_XDP_P1_CH2
|
1795 ESR_INT_XDP_P1_CH1
|
1796 ESR_INT_XDP_P1_CH0
);
1803 if ((sig
& mask
) != val
)
1808 static int link_status_10g_hotplug(struct niu
*np
, int *link_up_p
)
1810 unsigned long flags
;
1813 int phy_present_prev
;
1815 spin_lock_irqsave(&np
->lock
, flags
);
1817 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
1818 phy_present_prev
= (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) ?
1820 phy_present
= niu_10g_phy_present(np
);
1821 if (phy_present
!= phy_present_prev
) {
1824 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
1825 if (np
->phy_ops
->xcvr_init
)
1826 err
= np
->phy_ops
->xcvr_init(np
);
1829 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
1832 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
1834 niuwarn(LINK
, "%s: Hotplug PHY Removed\n",
1838 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
)
1839 err
= link_status_10g_bcm8706(np
, link_up_p
);
1842 spin_unlock_irqrestore(&np
->lock
, flags
);
1847 static int link_status_1g(struct niu
*np
, int *link_up_p
)
1849 struct niu_link_config
*lp
= &np
->link_config
;
1850 u16 current_speed
, bmsr
;
1851 unsigned long flags
;
1856 current_speed
= SPEED_INVALID
;
1857 current_duplex
= DUPLEX_INVALID
;
1859 spin_lock_irqsave(&np
->lock
, flags
);
1862 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
1865 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1870 if (bmsr
& BMSR_LSTATUS
) {
1871 u16 adv
, lpa
, common
, estat
;
1873 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1878 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1885 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1891 if (estat
& (ESTATUS_1000_TFULL
| ESTATUS_1000_THALF
)) {
1892 current_speed
= SPEED_1000
;
1893 if (estat
& ESTATUS_1000_TFULL
)
1894 current_duplex
= DUPLEX_FULL
;
1896 current_duplex
= DUPLEX_HALF
;
1898 if (common
& ADVERTISE_100BASE4
) {
1899 current_speed
= SPEED_100
;
1900 current_duplex
= DUPLEX_HALF
;
1901 } else if (common
& ADVERTISE_100FULL
) {
1902 current_speed
= SPEED_100
;
1903 current_duplex
= DUPLEX_FULL
;
1904 } else if (common
& ADVERTISE_100HALF
) {
1905 current_speed
= SPEED_100
;
1906 current_duplex
= DUPLEX_HALF
;
1907 } else if (common
& ADVERTISE_10FULL
) {
1908 current_speed
= SPEED_10
;
1909 current_duplex
= DUPLEX_FULL
;
1910 } else if (common
& ADVERTISE_10HALF
) {
1911 current_speed
= SPEED_10
;
1912 current_duplex
= DUPLEX_HALF
;
1917 lp
->active_speed
= current_speed
;
1918 lp
->active_duplex
= current_duplex
;
1922 spin_unlock_irqrestore(&np
->lock
, flags
);
1924 *link_up_p
= link_up
;
1928 static int niu_link_status(struct niu
*np
, int *link_up_p
)
1930 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1934 if (ops
->link_status
)
1935 err
= ops
->link_status(np
, link_up_p
);
1940 static void niu_timer(unsigned long __opaque
)
1942 struct niu
*np
= (struct niu
*) __opaque
;
1946 err
= niu_link_status(np
, &link_up
);
1948 niu_link_status_common(np
, link_up
);
1950 if (netif_carrier_ok(np
->dev
))
1954 np
->timer
.expires
= jiffies
+ off
;
1956 add_timer(&np
->timer
);
1959 static const struct niu_phy_ops phy_ops_10g_serdes
= {
1960 .serdes_init
= serdes_init_10g_serdes
,
1961 .link_status
= link_status_10g_serdes
,
1964 static const struct niu_phy_ops phy_ops_1g_rgmii
= {
1965 .xcvr_init
= xcvr_init_1g_rgmii
,
1966 .link_status
= link_status_1g_rgmii
,
1969 static const struct niu_phy_ops phy_ops_10g_fiber_niu
= {
1970 .serdes_init
= serdes_init_niu
,
1971 .xcvr_init
= xcvr_init_10g
,
1972 .link_status
= link_status_10g
,
1975 static const struct niu_phy_ops phy_ops_10g_fiber
= {
1976 .serdes_init
= serdes_init_10g
,
1977 .xcvr_init
= xcvr_init_10g
,
1978 .link_status
= link_status_10g
,
1981 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug
= {
1982 .serdes_init
= serdes_init_10g
,
1983 .xcvr_init
= xcvr_init_10g_bcm8706
,
1984 .link_status
= link_status_10g_hotplug
,
1987 static const struct niu_phy_ops phy_ops_10g_copper
= {
1988 .serdes_init
= serdes_init_10g
,
1989 .link_status
= link_status_10g
, /* XXX */
1992 static const struct niu_phy_ops phy_ops_1g_fiber
= {
1993 .serdes_init
= serdes_init_1g
,
1994 .xcvr_init
= xcvr_init_1g
,
1995 .link_status
= link_status_1g
,
1998 static const struct niu_phy_ops phy_ops_1g_copper
= {
1999 .xcvr_init
= xcvr_init_1g
,
2000 .link_status
= link_status_1g
,
2003 struct niu_phy_template
{
2004 const struct niu_phy_ops
*ops
;
2008 static const struct niu_phy_template phy_template_niu
= {
2009 .ops
= &phy_ops_10g_fiber_niu
,
2010 .phy_addr_base
= 16,
2013 static const struct niu_phy_template phy_template_10g_fiber
= {
2014 .ops
= &phy_ops_10g_fiber
,
2018 static const struct niu_phy_template phy_template_10g_fiber_hotplug
= {
2019 .ops
= &phy_ops_10g_fiber_hotplug
,
2023 static const struct niu_phy_template phy_template_10g_copper
= {
2024 .ops
= &phy_ops_10g_copper
,
2025 .phy_addr_base
= 10,
2028 static const struct niu_phy_template phy_template_1g_fiber
= {
2029 .ops
= &phy_ops_1g_fiber
,
2033 static const struct niu_phy_template phy_template_1g_copper
= {
2034 .ops
= &phy_ops_1g_copper
,
2038 static const struct niu_phy_template phy_template_1g_rgmii
= {
2039 .ops
= &phy_ops_1g_rgmii
,
2043 static const struct niu_phy_template phy_template_10g_serdes
= {
2044 .ops
= &phy_ops_10g_serdes
,
2048 static int niu_atca_port_num
[4] = {
2052 static int serdes_init_10g_serdes(struct niu
*np
)
2054 struct niu_link_config
*lp
= &np
->link_config
;
2055 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
2056 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
2062 reset_val
= ENET_SERDES_RESET_0
;
2063 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
2064 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
2065 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
2068 reset_val
= ENET_SERDES_RESET_1
;
2069 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
2070 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
2071 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
2077 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
2078 ENET_SERDES_CTRL_SDET_1
|
2079 ENET_SERDES_CTRL_SDET_2
|
2080 ENET_SERDES_CTRL_SDET_3
|
2081 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
2082 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
2083 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
2084 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
2085 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
2086 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
2087 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
2088 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
2091 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
2092 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
2093 ENET_SERDES_TEST_MD_0_SHIFT
) |
2094 (ENET_TEST_MD_PAD_LOOPBACK
<<
2095 ENET_SERDES_TEST_MD_1_SHIFT
) |
2096 (ENET_TEST_MD_PAD_LOOPBACK
<<
2097 ENET_SERDES_TEST_MD_2_SHIFT
) |
2098 (ENET_TEST_MD_PAD_LOOPBACK
<<
2099 ENET_SERDES_TEST_MD_3_SHIFT
));
2103 nw64(pll_cfg
, ENET_SERDES_PLL_FBDIV2
);
2104 nw64(ctrl_reg
, ctrl_val
);
2105 nw64(test_cfg_reg
, test_cfg_val
);
2107 /* Initialize all 4 lanes of the SERDES. */
2108 for (i
= 0; i
< 4; i
++) {
2109 u32 rxtx_ctrl
, glue0
;
2111 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
2114 err
= esr_read_glue0(np
, i
, &glue0
);
2118 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
2119 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
2120 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
2122 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
2123 ESR_GLUE_CTRL0_THCNT
|
2124 ESR_GLUE_CTRL0_BLTIME
);
2125 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
2126 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
2127 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
2128 (BLTIME_300_CYCLES
<<
2129 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
2131 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
2134 err
= esr_write_glue0(np
, i
, glue0
);
2140 sig
= nr64(ESR_INT_SIGNALS
);
2143 mask
= ESR_INT_SIGNALS_P0_BITS
;
2144 val
= (ESR_INT_SRDY0_P0
|
2147 ESR_INT_XDP_P0_CH3
|
2148 ESR_INT_XDP_P0_CH2
|
2149 ESR_INT_XDP_P0_CH1
|
2150 ESR_INT_XDP_P0_CH0
);
2154 mask
= ESR_INT_SIGNALS_P1_BITS
;
2155 val
= (ESR_INT_SRDY0_P1
|
2158 ESR_INT_XDP_P1_CH3
|
2159 ESR_INT_XDP_P1_CH2
|
2160 ESR_INT_XDP_P1_CH1
|
2161 ESR_INT_XDP_P1_CH0
);
2168 if ((sig
& mask
) != val
) {
2170 err
= serdes_init_1g_serdes(np
);
2172 np
->flags
&= ~NIU_FLAGS_10G
;
2173 np
->mac_xcvr
= MAC_XCVR_PCS
;
2175 dev_err(np
->device
, PFX
"Port %u 10G/1G SERDES Link Failed \n",
2184 static int niu_determine_phy_disposition(struct niu
*np
)
2186 struct niu_parent
*parent
= np
->parent
;
2187 u8 plat_type
= parent
->plat_type
;
2188 const struct niu_phy_template
*tp
;
2189 u32 phy_addr_off
= 0;
2191 if (plat_type
== PLAT_TYPE_NIU
) {
2192 tp
= &phy_template_niu
;
2193 phy_addr_off
+= np
->port
;
2198 NIU_FLAGS_XCVR_SERDES
)) {
2201 tp
= &phy_template_1g_copper
;
2202 if (plat_type
== PLAT_TYPE_VF_P0
)
2204 else if (plat_type
== PLAT_TYPE_VF_P1
)
2207 phy_addr_off
+= (np
->port
^ 0x3);
2212 tp
= &phy_template_1g_copper
;
2215 case NIU_FLAGS_FIBER
:
2217 tp
= &phy_template_1g_fiber
;
2220 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2222 tp
= &phy_template_10g_fiber
;
2223 if (plat_type
== PLAT_TYPE_VF_P0
||
2224 plat_type
== PLAT_TYPE_VF_P1
)
2226 phy_addr_off
+= np
->port
;
2227 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
2228 tp
= &phy_template_10g_fiber_hotplug
;
2236 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2237 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
2238 case NIU_FLAGS_XCVR_SERDES
:
2242 tp
= &phy_template_10g_serdes
;
2246 tp
= &phy_template_1g_rgmii
;
2252 phy_addr_off
= niu_atca_port_num
[np
->port
];
2260 np
->phy_ops
= tp
->ops
;
2261 np
->phy_addr
= tp
->phy_addr_base
+ phy_addr_off
;
2266 static int niu_init_link(struct niu
*np
)
2268 struct niu_parent
*parent
= np
->parent
;
2271 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
2272 err
= niu_xcvr_init(np
);
2277 err
= niu_serdes_init(np
);
2281 err
= niu_xcvr_init(np
);
2283 niu_link_status(np
, &ignore
);
2287 static void niu_set_primary_mac(struct niu
*np
, unsigned char *addr
)
2289 u16 reg0
= addr
[4] << 8 | addr
[5];
2290 u16 reg1
= addr
[2] << 8 | addr
[3];
2291 u16 reg2
= addr
[0] << 8 | addr
[1];
2293 if (np
->flags
& NIU_FLAGS_XMAC
) {
2294 nw64_mac(XMAC_ADDR0
, reg0
);
2295 nw64_mac(XMAC_ADDR1
, reg1
);
2296 nw64_mac(XMAC_ADDR2
, reg2
);
2298 nw64_mac(BMAC_ADDR0
, reg0
);
2299 nw64_mac(BMAC_ADDR1
, reg1
);
2300 nw64_mac(BMAC_ADDR2
, reg2
);
2304 static int niu_num_alt_addr(struct niu
*np
)
2306 if (np
->flags
& NIU_FLAGS_XMAC
)
2307 return XMAC_NUM_ALT_ADDR
;
2309 return BMAC_NUM_ALT_ADDR
;
2312 static int niu_set_alt_mac(struct niu
*np
, int index
, unsigned char *addr
)
2314 u16 reg0
= addr
[4] << 8 | addr
[5];
2315 u16 reg1
= addr
[2] << 8 | addr
[3];
2316 u16 reg2
= addr
[0] << 8 | addr
[1];
2318 if (index
>= niu_num_alt_addr(np
))
2321 if (np
->flags
& NIU_FLAGS_XMAC
) {
2322 nw64_mac(XMAC_ALT_ADDR0(index
), reg0
);
2323 nw64_mac(XMAC_ALT_ADDR1(index
), reg1
);
2324 nw64_mac(XMAC_ALT_ADDR2(index
), reg2
);
2326 nw64_mac(BMAC_ALT_ADDR0(index
), reg0
);
2327 nw64_mac(BMAC_ALT_ADDR1(index
), reg1
);
2328 nw64_mac(BMAC_ALT_ADDR2(index
), reg2
);
2334 static int niu_enable_alt_mac(struct niu
*np
, int index
, int on
)
2339 if (index
>= niu_num_alt_addr(np
))
2342 if (np
->flags
& NIU_FLAGS_XMAC
) {
2343 reg
= XMAC_ADDR_CMPEN
;
2346 reg
= BMAC_ADDR_CMPEN
;
2347 mask
= 1 << (index
+ 1);
2350 val
= nr64_mac(reg
);
2360 static void __set_rdc_table_num_hw(struct niu
*np
, unsigned long reg
,
2361 int num
, int mac_pref
)
2363 u64 val
= nr64_mac(reg
);
2364 val
&= ~(HOST_INFO_MACRDCTBLN
| HOST_INFO_MPR
);
2367 val
|= HOST_INFO_MPR
;
2371 static int __set_rdc_table_num(struct niu
*np
,
2372 int xmac_index
, int bmac_index
,
2373 int rdc_table_num
, int mac_pref
)
2377 if (rdc_table_num
& ~HOST_INFO_MACRDCTBLN
)
2379 if (np
->flags
& NIU_FLAGS_XMAC
)
2380 reg
= XMAC_HOST_INFO(xmac_index
);
2382 reg
= BMAC_HOST_INFO(bmac_index
);
2383 __set_rdc_table_num_hw(np
, reg
, rdc_table_num
, mac_pref
);
2387 static int niu_set_primary_mac_rdc_table(struct niu
*np
, int table_num
,
2390 return __set_rdc_table_num(np
, 17, 0, table_num
, mac_pref
);
2393 static int niu_set_multicast_mac_rdc_table(struct niu
*np
, int table_num
,
2396 return __set_rdc_table_num(np
, 16, 8, table_num
, mac_pref
);
2399 static int niu_set_alt_mac_rdc_table(struct niu
*np
, int idx
,
2400 int table_num
, int mac_pref
)
2402 if (idx
>= niu_num_alt_addr(np
))
2404 return __set_rdc_table_num(np
, idx
, idx
+ 1, table_num
, mac_pref
);
2407 static u64
vlan_entry_set_parity(u64 reg_val
)
2412 port01_mask
= 0x00ff;
2413 port23_mask
= 0xff00;
2415 if (hweight64(reg_val
& port01_mask
) & 1)
2416 reg_val
|= ENET_VLAN_TBL_PARITY0
;
2418 reg_val
&= ~ENET_VLAN_TBL_PARITY0
;
2420 if (hweight64(reg_val
& port23_mask
) & 1)
2421 reg_val
|= ENET_VLAN_TBL_PARITY1
;
2423 reg_val
&= ~ENET_VLAN_TBL_PARITY1
;
2428 static void vlan_tbl_write(struct niu
*np
, unsigned long index
,
2429 int port
, int vpr
, int rdc_table
)
2431 u64 reg_val
= nr64(ENET_VLAN_TBL(index
));
2433 reg_val
&= ~((ENET_VLAN_TBL_VPR
|
2434 ENET_VLAN_TBL_VLANRDCTBLN
) <<
2435 ENET_VLAN_TBL_SHIFT(port
));
2437 reg_val
|= (ENET_VLAN_TBL_VPR
<<
2438 ENET_VLAN_TBL_SHIFT(port
));
2439 reg_val
|= (rdc_table
<< ENET_VLAN_TBL_SHIFT(port
));
2441 reg_val
= vlan_entry_set_parity(reg_val
);
2443 nw64(ENET_VLAN_TBL(index
), reg_val
);
2446 static void vlan_tbl_clear(struct niu
*np
)
2450 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++)
2451 nw64(ENET_VLAN_TBL(i
), 0);
2454 static int tcam_wait_bit(struct niu
*np
, u64 bit
)
2458 while (--limit
> 0) {
2459 if (nr64(TCAM_CTL
) & bit
)
2469 static int tcam_flush(struct niu
*np
, int index
)
2471 nw64(TCAM_KEY_0
, 0x00);
2472 nw64(TCAM_KEY_MASK_0
, 0xff);
2473 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2475 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2479 static int tcam_read(struct niu
*np
, int index
,
2480 u64
*key
, u64
*mask
)
2484 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_READ
| index
));
2485 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2487 key
[0] = nr64(TCAM_KEY_0
);
2488 key
[1] = nr64(TCAM_KEY_1
);
2489 key
[2] = nr64(TCAM_KEY_2
);
2490 key
[3] = nr64(TCAM_KEY_3
);
2491 mask
[0] = nr64(TCAM_KEY_MASK_0
);
2492 mask
[1] = nr64(TCAM_KEY_MASK_1
);
2493 mask
[2] = nr64(TCAM_KEY_MASK_2
);
2494 mask
[3] = nr64(TCAM_KEY_MASK_3
);
2500 static int tcam_write(struct niu
*np
, int index
,
2501 u64
*key
, u64
*mask
)
2503 nw64(TCAM_KEY_0
, key
[0]);
2504 nw64(TCAM_KEY_1
, key
[1]);
2505 nw64(TCAM_KEY_2
, key
[2]);
2506 nw64(TCAM_KEY_3
, key
[3]);
2507 nw64(TCAM_KEY_MASK_0
, mask
[0]);
2508 nw64(TCAM_KEY_MASK_1
, mask
[1]);
2509 nw64(TCAM_KEY_MASK_2
, mask
[2]);
2510 nw64(TCAM_KEY_MASK_3
, mask
[3]);
2511 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2513 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2517 static int tcam_assoc_read(struct niu
*np
, int index
, u64
*data
)
2521 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_READ
| index
));
2522 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2524 *data
= nr64(TCAM_KEY_1
);
2530 static int tcam_assoc_write(struct niu
*np
, int index
, u64 assoc_data
)
2532 nw64(TCAM_KEY_1
, assoc_data
);
2533 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_WRITE
| index
));
2535 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2538 static void tcam_enable(struct niu
*np
, int on
)
2540 u64 val
= nr64(FFLP_CFG_1
);
2543 val
&= ~FFLP_CFG_1_TCAM_DIS
;
2545 val
|= FFLP_CFG_1_TCAM_DIS
;
2546 nw64(FFLP_CFG_1
, val
);
2549 static void tcam_set_lat_and_ratio(struct niu
*np
, u64 latency
, u64 ratio
)
2551 u64 val
= nr64(FFLP_CFG_1
);
2553 val
&= ~(FFLP_CFG_1_FFLPINITDONE
|
2555 FFLP_CFG_1_CAMRATIO
);
2556 val
|= (latency
<< FFLP_CFG_1_CAMLAT_SHIFT
);
2557 val
|= (ratio
<< FFLP_CFG_1_CAMRATIO_SHIFT
);
2558 nw64(FFLP_CFG_1
, val
);
2560 val
= nr64(FFLP_CFG_1
);
2561 val
|= FFLP_CFG_1_FFLPINITDONE
;
2562 nw64(FFLP_CFG_1
, val
);
2565 static int tcam_user_eth_class_enable(struct niu
*np
, unsigned long class,
2571 if (class < CLASS_CODE_ETHERTYPE1
||
2572 class > CLASS_CODE_ETHERTYPE2
)
2575 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2587 static int tcam_user_eth_class_set(struct niu
*np
, unsigned long class,
2593 if (class < CLASS_CODE_ETHERTYPE1
||
2594 class > CLASS_CODE_ETHERTYPE2
||
2595 (ether_type
& ~(u64
)0xffff) != 0)
2598 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2600 val
&= ~L2_CLS_ETYPE
;
2601 val
|= (ether_type
<< L2_CLS_ETYPE_SHIFT
);
2608 static int tcam_user_ip_class_enable(struct niu
*np
, unsigned long class,
2614 if (class < CLASS_CODE_USER_PROG1
||
2615 class > CLASS_CODE_USER_PROG4
)
2618 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
2621 val
|= L3_CLS_VALID
;
2623 val
&= ~L3_CLS_VALID
;
2630 static int tcam_user_ip_class_set(struct niu
*np
, unsigned long class,
2631 int ipv6
, u64 protocol_id
,
2632 u64 tos_mask
, u64 tos_val
)
2637 if (class < CLASS_CODE_USER_PROG1
||
2638 class > CLASS_CODE_USER_PROG4
||
2639 (protocol_id
& ~(u64
)0xff) != 0 ||
2640 (tos_mask
& ~(u64
)0xff) != 0 ||
2641 (tos_val
& ~(u64
)0xff) != 0)
2644 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
2646 val
&= ~(L3_CLS_IPVER
| L3_CLS_PID
|
2647 L3_CLS_TOSMASK
| L3_CLS_TOS
);
2649 val
|= L3_CLS_IPVER
;
2650 val
|= (protocol_id
<< L3_CLS_PID_SHIFT
);
2651 val
|= (tos_mask
<< L3_CLS_TOSMASK_SHIFT
);
2652 val
|= (tos_val
<< L3_CLS_TOS_SHIFT
);
2659 static int tcam_early_init(struct niu
*np
)
2665 tcam_set_lat_and_ratio(np
,
2666 DEFAULT_TCAM_LATENCY
,
2667 DEFAULT_TCAM_ACCESS_RATIO
);
2668 for (i
= CLASS_CODE_ETHERTYPE1
; i
<= CLASS_CODE_ETHERTYPE2
; i
++) {
2669 err
= tcam_user_eth_class_enable(np
, i
, 0);
2673 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_USER_PROG4
; i
++) {
2674 err
= tcam_user_ip_class_enable(np
, i
, 0);
2682 static int tcam_flush_all(struct niu
*np
)
2686 for (i
= 0; i
< np
->parent
->tcam_num_entries
; i
++) {
2687 int err
= tcam_flush(np
, i
);
2694 static u64
hash_addr_regval(unsigned long index
, unsigned long num_entries
)
2696 return ((u64
)index
| (num_entries
== 1 ?
2697 HASH_TBL_ADDR_AUTOINC
: 0));
2701 static int hash_read(struct niu
*np
, unsigned long partition
,
2702 unsigned long index
, unsigned long num_entries
,
2705 u64 val
= hash_addr_regval(index
, num_entries
);
2708 if (partition
>= FCRAM_NUM_PARTITIONS
||
2709 index
+ num_entries
> FCRAM_SIZE
)
2712 nw64(HASH_TBL_ADDR(partition
), val
);
2713 for (i
= 0; i
< num_entries
; i
++)
2714 data
[i
] = nr64(HASH_TBL_DATA(partition
));
2720 static int hash_write(struct niu
*np
, unsigned long partition
,
2721 unsigned long index
, unsigned long num_entries
,
2724 u64 val
= hash_addr_regval(index
, num_entries
);
2727 if (partition
>= FCRAM_NUM_PARTITIONS
||
2728 index
+ (num_entries
* 8) > FCRAM_SIZE
)
2731 nw64(HASH_TBL_ADDR(partition
), val
);
2732 for (i
= 0; i
< num_entries
; i
++)
2733 nw64(HASH_TBL_DATA(partition
), data
[i
]);
2738 static void fflp_reset(struct niu
*np
)
2742 nw64(FFLP_CFG_1
, FFLP_CFG_1_PIO_FIO_RST
);
2744 nw64(FFLP_CFG_1
, 0);
2746 val
= FFLP_CFG_1_FCRAMOUTDR_NORMAL
| FFLP_CFG_1_FFLPINITDONE
;
2747 nw64(FFLP_CFG_1
, val
);
2750 static void fflp_set_timings(struct niu
*np
)
2752 u64 val
= nr64(FFLP_CFG_1
);
2754 val
&= ~FFLP_CFG_1_FFLPINITDONE
;
2755 val
|= (DEFAULT_FCRAMRATIO
<< FFLP_CFG_1_FCRAMRATIO_SHIFT
);
2756 nw64(FFLP_CFG_1
, val
);
2758 val
= nr64(FFLP_CFG_1
);
2759 val
|= FFLP_CFG_1_FFLPINITDONE
;
2760 nw64(FFLP_CFG_1
, val
);
2762 val
= nr64(FCRAM_REF_TMR
);
2763 val
&= ~(FCRAM_REF_TMR_MAX
| FCRAM_REF_TMR_MIN
);
2764 val
|= (DEFAULT_FCRAM_REFRESH_MAX
<< FCRAM_REF_TMR_MAX_SHIFT
);
2765 val
|= (DEFAULT_FCRAM_REFRESH_MIN
<< FCRAM_REF_TMR_MIN_SHIFT
);
2766 nw64(FCRAM_REF_TMR
, val
);
2769 static int fflp_set_partition(struct niu
*np
, u64 partition
,
2770 u64 mask
, u64 base
, int enable
)
2775 if (partition
>= FCRAM_NUM_PARTITIONS
||
2776 (mask
& ~(u64
)0x1f) != 0 ||
2777 (base
& ~(u64
)0x1f) != 0)
2780 reg
= FLW_PRT_SEL(partition
);
2783 val
&= ~(FLW_PRT_SEL_EXT
| FLW_PRT_SEL_MASK
| FLW_PRT_SEL_BASE
);
2784 val
|= (mask
<< FLW_PRT_SEL_MASK_SHIFT
);
2785 val
|= (base
<< FLW_PRT_SEL_BASE_SHIFT
);
2787 val
|= FLW_PRT_SEL_EXT
;
2793 static int fflp_disable_all_partitions(struct niu
*np
)
2797 for (i
= 0; i
< FCRAM_NUM_PARTITIONS
; i
++) {
2798 int err
= fflp_set_partition(np
, 0, 0, 0, 0);
2805 static void fflp_llcsnap_enable(struct niu
*np
, int on
)
2807 u64 val
= nr64(FFLP_CFG_1
);
2810 val
|= FFLP_CFG_1_LLCSNAP
;
2812 val
&= ~FFLP_CFG_1_LLCSNAP
;
2813 nw64(FFLP_CFG_1
, val
);
2816 static void fflp_errors_enable(struct niu
*np
, int on
)
2818 u64 val
= nr64(FFLP_CFG_1
);
2821 val
&= ~FFLP_CFG_1_ERRORDIS
;
2823 val
|= FFLP_CFG_1_ERRORDIS
;
2824 nw64(FFLP_CFG_1
, val
);
2827 static int fflp_hash_clear(struct niu
*np
)
2829 struct fcram_hash_ipv4 ent
;
2832 /* IPV4 hash entry with valid bit clear, rest is don't care. */
2833 memset(&ent
, 0, sizeof(ent
));
2834 ent
.header
= HASH_HEADER_EXT
;
2836 for (i
= 0; i
< FCRAM_SIZE
; i
+= sizeof(ent
)) {
2837 int err
= hash_write(np
, 0, i
, 1, (u64
*) &ent
);
2844 static int fflp_early_init(struct niu
*np
)
2846 struct niu_parent
*parent
;
2847 unsigned long flags
;
2850 niu_lock_parent(np
, flags
);
2852 parent
= np
->parent
;
2854 if (!(parent
->flags
& PARENT_FLGS_CLS_HWINIT
)) {
2855 niudbg(PROBE
, "fflp_early_init: Initting hw on port %u\n",
2857 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
2859 fflp_set_timings(np
);
2860 err
= fflp_disable_all_partitions(np
);
2862 niudbg(PROBE
, "fflp_disable_all_partitions "
2863 "failed, err=%d\n", err
);
2868 err
= tcam_early_init(np
);
2870 niudbg(PROBE
, "tcam_early_init failed, err=%d\n",
2874 fflp_llcsnap_enable(np
, 1);
2875 fflp_errors_enable(np
, 0);
2879 err
= tcam_flush_all(np
);
2881 niudbg(PROBE
, "tcam_flush_all failed, err=%d\n",
2885 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
2886 err
= fflp_hash_clear(np
);
2888 niudbg(PROBE
, "fflp_hash_clear failed, "
2896 niudbg(PROBE
, "fflp_early_init: Success\n");
2897 parent
->flags
|= PARENT_FLGS_CLS_HWINIT
;
2900 niu_unlock_parent(np
, flags
);
2904 static int niu_set_flow_key(struct niu
*np
, unsigned long class_code
, u64 key
)
2906 if (class_code
< CLASS_CODE_USER_PROG1
||
2907 class_code
> CLASS_CODE_SCTP_IPV6
)
2910 nw64(FLOW_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
2914 static int niu_set_tcam_key(struct niu
*np
, unsigned long class_code
, u64 key
)
2916 if (class_code
< CLASS_CODE_USER_PROG1
||
2917 class_code
> CLASS_CODE_SCTP_IPV6
)
2920 nw64(TCAM_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
2924 static void niu_rx_skb_append(struct sk_buff
*skb
, struct page
*page
,
2925 u32 offset
, u32 size
)
2927 int i
= skb_shinfo(skb
)->nr_frags
;
2928 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2931 frag
->page_offset
= offset
;
2935 skb
->data_len
+= size
;
2936 skb
->truesize
+= size
;
2938 skb_shinfo(skb
)->nr_frags
= i
+ 1;
2941 static unsigned int niu_hash_rxaddr(struct rx_ring_info
*rp
, u64 a
)
2944 a
^= (a
>> ilog2(MAX_RBR_RING_SIZE
));
2946 return (a
& (MAX_RBR_RING_SIZE
- 1));
2949 static struct page
*niu_find_rxpage(struct rx_ring_info
*rp
, u64 addr
,
2950 struct page
***link
)
2952 unsigned int h
= niu_hash_rxaddr(rp
, addr
);
2953 struct page
*p
, **pp
;
2956 pp
= &rp
->rxhash
[h
];
2957 for (; (p
= *pp
) != NULL
; pp
= (struct page
**) &p
->mapping
) {
2958 if (p
->index
== addr
) {
2967 static void niu_hash_page(struct rx_ring_info
*rp
, struct page
*page
, u64 base
)
2969 unsigned int h
= niu_hash_rxaddr(rp
, base
);
2972 page
->mapping
= (struct address_space
*) rp
->rxhash
[h
];
2973 rp
->rxhash
[h
] = page
;
2976 static int niu_rbr_add_page(struct niu
*np
, struct rx_ring_info
*rp
,
2977 gfp_t mask
, int start_index
)
2983 page
= alloc_page(mask
);
2987 addr
= np
->ops
->map_page(np
->device
, page
, 0,
2988 PAGE_SIZE
, DMA_FROM_DEVICE
);
2990 niu_hash_page(rp
, page
, addr
);
2991 if (rp
->rbr_blocks_per_page
> 1)
2992 atomic_add(rp
->rbr_blocks_per_page
- 1,
2993 &compound_head(page
)->_count
);
2995 for (i
= 0; i
< rp
->rbr_blocks_per_page
; i
++) {
2996 __le32
*rbr
= &rp
->rbr
[start_index
+ i
];
2998 *rbr
= cpu_to_le32(addr
>> RBR_DESCR_ADDR_SHIFT
);
2999 addr
+= rp
->rbr_block_size
;
3005 static void niu_rbr_refill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3007 int index
= rp
->rbr_index
;
3010 if ((rp
->rbr_pending
% rp
->rbr_blocks_per_page
) == 0) {
3011 int err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3013 if (unlikely(err
)) {
3018 rp
->rbr_index
+= rp
->rbr_blocks_per_page
;
3019 BUG_ON(rp
->rbr_index
> rp
->rbr_table_size
);
3020 if (rp
->rbr_index
== rp
->rbr_table_size
)
3023 if (rp
->rbr_pending
>= rp
->rbr_kick_thresh
) {
3024 nw64(RBR_KICK(rp
->rx_channel
), rp
->rbr_pending
);
3025 rp
->rbr_pending
= 0;
3030 static int niu_rx_pkt_ignore(struct niu
*np
, struct rx_ring_info
*rp
)
3032 unsigned int index
= rp
->rcr_index
;
3037 struct page
*page
, **link
;
3043 val
= le64_to_cpup(&rp
->rcr
[index
]);
3044 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3045 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3046 page
= niu_find_rxpage(rp
, addr
, &link
);
3048 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3049 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3050 if ((page
->index
+ PAGE_SIZE
) - rcr_size
== addr
) {
3051 *link
= (struct page
*) page
->mapping
;
3052 np
->ops
->unmap_page(np
->device
, page
->index
,
3053 PAGE_SIZE
, DMA_FROM_DEVICE
);
3055 page
->mapping
= NULL
;
3057 rp
->rbr_refill_pending
++;
3060 index
= NEXT_RCR(rp
, index
);
3061 if (!(val
& RCR_ENTRY_MULTI
))
3065 rp
->rcr_index
= index
;
3070 static int niu_process_rx_pkt(struct niu
*np
, struct rx_ring_info
*rp
)
3072 unsigned int index
= rp
->rcr_index
;
3073 struct sk_buff
*skb
;
3076 skb
= netdev_alloc_skb(np
->dev
, RX_SKB_ALLOC_SIZE
);
3078 return niu_rx_pkt_ignore(np
, rp
);
3082 struct page
*page
, **link
;
3083 u32 rcr_size
, append_size
;
3088 val
= le64_to_cpup(&rp
->rcr
[index
]);
3090 len
= (val
& RCR_ENTRY_L2_LEN
) >>
3091 RCR_ENTRY_L2_LEN_SHIFT
;
3094 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3095 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3096 page
= niu_find_rxpage(rp
, addr
, &link
);
3098 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3099 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3101 off
= addr
& ~PAGE_MASK
;
3102 append_size
= rcr_size
;
3109 ptype
= (val
>> RCR_ENTRY_PKT_TYPE_SHIFT
);
3110 if ((ptype
== RCR_PKT_TYPE_TCP
||
3111 ptype
== RCR_PKT_TYPE_UDP
) &&
3112 !(val
& (RCR_ENTRY_NOPORT
|
3114 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3116 skb
->ip_summed
= CHECKSUM_NONE
;
3118 if (!(val
& RCR_ENTRY_MULTI
))
3119 append_size
= len
- skb
->len
;
3121 niu_rx_skb_append(skb
, page
, off
, append_size
);
3122 if ((page
->index
+ rp
->rbr_block_size
) - rcr_size
== addr
) {
3123 *link
= (struct page
*) page
->mapping
;
3124 np
->ops
->unmap_page(np
->device
, page
->index
,
3125 PAGE_SIZE
, DMA_FROM_DEVICE
);
3127 page
->mapping
= NULL
;
3128 rp
->rbr_refill_pending
++;
3132 index
= NEXT_RCR(rp
, index
);
3133 if (!(val
& RCR_ENTRY_MULTI
))
3137 rp
->rcr_index
= index
;
3139 skb_reserve(skb
, NET_IP_ALIGN
);
3140 __pskb_pull_tail(skb
, min(len
, NIU_RXPULL_MAX
));
3143 rp
->rx_bytes
+= skb
->len
;
3145 skb
->protocol
= eth_type_trans(skb
, np
->dev
);
3146 netif_receive_skb(skb
);
3148 np
->dev
->last_rx
= jiffies
;
3153 static int niu_rbr_fill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3155 int blocks_per_page
= rp
->rbr_blocks_per_page
;
3156 int err
, index
= rp
->rbr_index
;
3159 while (index
< (rp
->rbr_table_size
- blocks_per_page
)) {
3160 err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3164 index
+= blocks_per_page
;
3167 rp
->rbr_index
= index
;
3171 static void niu_rbr_free(struct niu
*np
, struct rx_ring_info
*rp
)
3175 for (i
= 0; i
< MAX_RBR_RING_SIZE
; i
++) {
3178 page
= rp
->rxhash
[i
];
3180 struct page
*next
= (struct page
*) page
->mapping
;
3181 u64 base
= page
->index
;
3183 np
->ops
->unmap_page(np
->device
, base
, PAGE_SIZE
,
3186 page
->mapping
= NULL
;
3194 for (i
= 0; i
< rp
->rbr_table_size
; i
++)
3195 rp
->rbr
[i
] = cpu_to_le32(0);
3199 static int release_tx_packet(struct niu
*np
, struct tx_ring_info
*rp
, int idx
)
3201 struct tx_buff_info
*tb
= &rp
->tx_buffs
[idx
];
3202 struct sk_buff
*skb
= tb
->skb
;
3203 struct tx_pkt_hdr
*tp
;
3207 tp
= (struct tx_pkt_hdr
*) skb
->data
;
3208 tx_flags
= le64_to_cpup(&tp
->flags
);
3211 rp
->tx_bytes
+= (((tx_flags
& TXHDR_LEN
) >> TXHDR_LEN_SHIFT
) -
3212 ((tx_flags
& TXHDR_PAD
) / 2));
3214 len
= skb_headlen(skb
);
3215 np
->ops
->unmap_single(np
->device
, tb
->mapping
,
3216 len
, DMA_TO_DEVICE
);
3218 if (le64_to_cpu(rp
->descr
[idx
]) & TX_DESC_MARK
)
3223 idx
= NEXT_TX(rp
, idx
);
3224 len
-= MAX_TX_DESC_LEN
;
3227 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
3228 tb
= &rp
->tx_buffs
[idx
];
3229 BUG_ON(tb
->skb
!= NULL
);
3230 np
->ops
->unmap_page(np
->device
, tb
->mapping
,
3231 skb_shinfo(skb
)->frags
[i
].size
,
3233 idx
= NEXT_TX(rp
, idx
);
3241 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3243 static void niu_tx_work(struct niu
*np
, struct tx_ring_info
*rp
)
3250 if (unlikely(!(cs
& (TX_CS_MK
| TX_CS_MMK
))))
3253 tmp
= pkt_cnt
= (cs
& TX_CS_PKT_CNT
) >> TX_CS_PKT_CNT_SHIFT
;
3254 pkt_cnt
= (pkt_cnt
- rp
->last_pkt_cnt
) &
3255 (TX_CS_PKT_CNT
>> TX_CS_PKT_CNT_SHIFT
);
3257 rp
->last_pkt_cnt
= tmp
;
3261 niudbg(TX_DONE
, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3262 np
->dev
->name
, pkt_cnt
, cons
);
3265 cons
= release_tx_packet(np
, rp
, cons
);
3271 if (unlikely(netif_queue_stopped(np
->dev
) &&
3272 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))) {
3273 netif_tx_lock(np
->dev
);
3274 if (netif_queue_stopped(np
->dev
) &&
3275 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))
3276 netif_wake_queue(np
->dev
);
3277 netif_tx_unlock(np
->dev
);
3281 static int niu_rx_work(struct niu
*np
, struct rx_ring_info
*rp
, int budget
)
3283 int qlen
, rcr_done
= 0, work_done
= 0;
3284 struct rxdma_mailbox
*mbox
= rp
->mbox
;
3288 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3289 qlen
= nr64(RCRSTAT_A(rp
->rx_channel
)) & RCRSTAT_A_QLEN
;
3291 stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
3292 qlen
= (le64_to_cpup(&mbox
->rcrstat_a
) & RCRSTAT_A_QLEN
);
3294 mbox
->rx_dma_ctl_stat
= 0;
3295 mbox
->rcrstat_a
= 0;
3297 niudbg(RX_STATUS
, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3298 np
->dev
->name
, rp
->rx_channel
, (unsigned long long) stat
, qlen
);
3300 rcr_done
= work_done
= 0;
3301 qlen
= min(qlen
, budget
);
3302 while (work_done
< qlen
) {
3303 rcr_done
+= niu_process_rx_pkt(np
, rp
);
3307 if (rp
->rbr_refill_pending
>= rp
->rbr_kick_thresh
) {
3310 for (i
= 0; i
< rp
->rbr_refill_pending
; i
++)
3311 niu_rbr_refill(np
, rp
, GFP_ATOMIC
);
3312 rp
->rbr_refill_pending
= 0;
3315 stat
= (RX_DMA_CTL_STAT_MEX
|
3316 ((u64
)work_done
<< RX_DMA_CTL_STAT_PKTREAD_SHIFT
) |
3317 ((u64
)rcr_done
<< RX_DMA_CTL_STAT_PTRREAD_SHIFT
));
3319 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat
);
3324 static int niu_poll_core(struct niu
*np
, struct niu_ldg
*lp
, int budget
)
3327 u32 tx_vec
= (v0
>> 32);
3328 u32 rx_vec
= (v0
& 0xffffffff);
3329 int i
, work_done
= 0;
3331 niudbg(INTR
, "%s: niu_poll_core() v0[%016llx]\n",
3332 np
->dev
->name
, (unsigned long long) v0
);
3334 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3335 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3336 if (tx_vec
& (1 << rp
->tx_channel
))
3337 niu_tx_work(np
, rp
);
3338 nw64(LD_IM0(LDN_TXDMA(rp
->tx_channel
)), 0);
3341 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3342 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3344 if (rx_vec
& (1 << rp
->rx_channel
)) {
3347 this_work_done
= niu_rx_work(np
, rp
,
3350 budget
-= this_work_done
;
3351 work_done
+= this_work_done
;
3353 nw64(LD_IM0(LDN_RXDMA(rp
->rx_channel
)), 0);
3359 static int niu_poll(struct napi_struct
*napi
, int budget
)
3361 struct niu_ldg
*lp
= container_of(napi
, struct niu_ldg
, napi
);
3362 struct niu
*np
= lp
->np
;
3365 work_done
= niu_poll_core(np
, lp
, budget
);
3367 if (work_done
< budget
) {
3368 netif_rx_complete(np
->dev
, napi
);
3369 niu_ldg_rearm(np
, lp
, 1);
3374 static void niu_log_rxchan_errors(struct niu
*np
, struct rx_ring_info
*rp
,
3377 dev_err(np
->device
, PFX
"%s: RX channel %u errors ( ",
3378 np
->dev
->name
, rp
->rx_channel
);
3380 if (stat
& RX_DMA_CTL_STAT_RBR_TMOUT
)
3381 printk("RBR_TMOUT ");
3382 if (stat
& RX_DMA_CTL_STAT_RSP_CNT_ERR
)
3384 if (stat
& RX_DMA_CTL_STAT_BYTE_EN_BUS
)
3385 printk("BYTE_EN_BUS ");
3386 if (stat
& RX_DMA_CTL_STAT_RSP_DAT_ERR
)
3388 if (stat
& RX_DMA_CTL_STAT_RCR_ACK_ERR
)
3390 if (stat
& RX_DMA_CTL_STAT_RCR_SHA_PAR
)
3391 printk("RCR_SHA_PAR ");
3392 if (stat
& RX_DMA_CTL_STAT_RBR_PRE_PAR
)
3393 printk("RBR_PRE_PAR ");
3394 if (stat
& RX_DMA_CTL_STAT_CONFIG_ERR
)
3396 if (stat
& RX_DMA_CTL_STAT_RCRINCON
)
3397 printk("RCRINCON ");
3398 if (stat
& RX_DMA_CTL_STAT_RCRFULL
)
3400 if (stat
& RX_DMA_CTL_STAT_RBRFULL
)
3402 if (stat
& RX_DMA_CTL_STAT_RBRLOGPAGE
)
3403 printk("RBRLOGPAGE ");
3404 if (stat
& RX_DMA_CTL_STAT_CFIGLOGPAGE
)
3405 printk("CFIGLOGPAGE ");
3406 if (stat
& RX_DMA_CTL_STAT_DC_FIFO_ERR
)
3412 static int niu_rx_error(struct niu
*np
, struct rx_ring_info
*rp
)
3414 u64 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3418 if (stat
& (RX_DMA_CTL_STAT_CHAN_FATAL
|
3419 RX_DMA_CTL_STAT_PORT_FATAL
))
3423 dev_err(np
->device
, PFX
"%s: RX channel %u error, stat[%llx]\n",
3424 np
->dev
->name
, rp
->rx_channel
,
3425 (unsigned long long) stat
);
3427 niu_log_rxchan_errors(np
, rp
, stat
);
3430 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
3431 stat
& RX_DMA_CTL_WRITE_CLEAR_ERRS
);
3436 static void niu_log_txchan_errors(struct niu
*np
, struct tx_ring_info
*rp
,
3439 dev_err(np
->device
, PFX
"%s: TX channel %u errors ( ",
3440 np
->dev
->name
, rp
->tx_channel
);
3442 if (cs
& TX_CS_MBOX_ERR
)
3444 if (cs
& TX_CS_PKT_SIZE_ERR
)
3445 printk("PKT_SIZE ");
3446 if (cs
& TX_CS_TX_RING_OFLOW
)
3447 printk("TX_RING_OFLOW ");
3448 if (cs
& TX_CS_PREF_BUF_PAR_ERR
)
3449 printk("PREF_BUF_PAR ");
3450 if (cs
& TX_CS_NACK_PREF
)
3451 printk("NACK_PREF ");
3452 if (cs
& TX_CS_NACK_PKT_RD
)
3453 printk("NACK_PKT_RD ");
3454 if (cs
& TX_CS_CONF_PART_ERR
)
3455 printk("CONF_PART ");
3456 if (cs
& TX_CS_PKT_PRT_ERR
)
3462 static int niu_tx_error(struct niu
*np
, struct tx_ring_info
*rp
)
3466 cs
= nr64(TX_CS(rp
->tx_channel
));
3467 logh
= nr64(TX_RNG_ERR_LOGH(rp
->tx_channel
));
3468 logl
= nr64(TX_RNG_ERR_LOGL(rp
->tx_channel
));
3470 dev_err(np
->device
, PFX
"%s: TX channel %u error, "
3471 "cs[%llx] logh[%llx] logl[%llx]\n",
3472 np
->dev
->name
, rp
->tx_channel
,
3473 (unsigned long long) cs
,
3474 (unsigned long long) logh
,
3475 (unsigned long long) logl
);
3477 niu_log_txchan_errors(np
, rp
, cs
);
3482 static int niu_mif_interrupt(struct niu
*np
)
3484 u64 mif_status
= nr64(MIF_STATUS
);
3487 if (np
->flags
& NIU_FLAGS_XMAC
) {
3488 u64 xrxmac_stat
= nr64_mac(XRXMAC_STATUS
);
3490 if (xrxmac_stat
& XRXMAC_STATUS_PHY_MDINT
)
3494 dev_err(np
->device
, PFX
"%s: MIF interrupt, "
3495 "stat[%llx] phy_mdint(%d)\n",
3496 np
->dev
->name
, (unsigned long long) mif_status
, phy_mdint
);
3501 static void niu_xmac_interrupt(struct niu
*np
)
3503 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
3506 val
= nr64_mac(XTXMAC_STATUS
);
3507 if (val
& XTXMAC_STATUS_FRAME_CNT_EXP
)
3508 mp
->tx_frames
+= TXMAC_FRM_CNT_COUNT
;
3509 if (val
& XTXMAC_STATUS_BYTE_CNT_EXP
)
3510 mp
->tx_bytes
+= TXMAC_BYTE_CNT_COUNT
;
3511 if (val
& XTXMAC_STATUS_TXFIFO_XFR_ERR
)
3512 mp
->tx_fifo_errors
++;
3513 if (val
& XTXMAC_STATUS_TXMAC_OFLOW
)
3514 mp
->tx_overflow_errors
++;
3515 if (val
& XTXMAC_STATUS_MAX_PSIZE_ERR
)
3516 mp
->tx_max_pkt_size_errors
++;
3517 if (val
& XTXMAC_STATUS_TXMAC_UFLOW
)
3518 mp
->tx_underflow_errors
++;
3520 val
= nr64_mac(XRXMAC_STATUS
);
3521 if (val
& XRXMAC_STATUS_LCL_FLT_STATUS
)
3522 mp
->rx_local_faults
++;
3523 if (val
& XRXMAC_STATUS_RFLT_DET
)
3524 mp
->rx_remote_faults
++;
3525 if (val
& XRXMAC_STATUS_LFLT_CNT_EXP
)
3526 mp
->rx_link_faults
+= LINK_FAULT_CNT_COUNT
;
3527 if (val
& XRXMAC_STATUS_ALIGNERR_CNT_EXP
)
3528 mp
->rx_align_errors
+= RXMAC_ALIGN_ERR_CNT_COUNT
;
3529 if (val
& XRXMAC_STATUS_RXFRAG_CNT_EXP
)
3530 mp
->rx_frags
+= RXMAC_FRAG_CNT_COUNT
;
3531 if (val
& XRXMAC_STATUS_RXMULTF_CNT_EXP
)
3532 mp
->rx_mcasts
+= RXMAC_MC_FRM_CNT_COUNT
;
3533 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3534 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3535 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3536 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3537 if (val
& XRXMAC_STATUS_RXHIST1_CNT_EXP
)
3538 mp
->rx_hist_cnt1
+= RXMAC_HIST_CNT1_COUNT
;
3539 if (val
& XRXMAC_STATUS_RXHIST2_CNT_EXP
)
3540 mp
->rx_hist_cnt2
+= RXMAC_HIST_CNT2_COUNT
;
3541 if (val
& XRXMAC_STATUS_RXHIST3_CNT_EXP
)
3542 mp
->rx_hist_cnt3
+= RXMAC_HIST_CNT3_COUNT
;
3543 if (val
& XRXMAC_STATUS_RXHIST4_CNT_EXP
)
3544 mp
->rx_hist_cnt4
+= RXMAC_HIST_CNT4_COUNT
;
3545 if (val
& XRXMAC_STATUS_RXHIST5_CNT_EXP
)
3546 mp
->rx_hist_cnt5
+= RXMAC_HIST_CNT5_COUNT
;
3547 if (val
& XRXMAC_STATUS_RXHIST6_CNT_EXP
)
3548 mp
->rx_hist_cnt6
+= RXMAC_HIST_CNT6_COUNT
;
3549 if (val
& XRXMAC_STATUS_RXHIST7_CNT_EXP
)
3550 mp
->rx_hist_cnt7
+= RXMAC_HIST_CNT7_COUNT
;
3551 if (val
& XRXMAC_STAT_MSK_RXOCTET_CNT_EXP
)
3552 mp
->rx_octets
+= RXMAC_BT_CNT_COUNT
;
3553 if (val
& XRXMAC_STATUS_CVIOLERR_CNT_EXP
)
3554 mp
->rx_code_violations
+= RXMAC_CD_VIO_CNT_COUNT
;
3555 if (val
& XRXMAC_STATUS_LENERR_CNT_EXP
)
3556 mp
->rx_len_errors
+= RXMAC_MPSZER_CNT_COUNT
;
3557 if (val
& XRXMAC_STATUS_CRCERR_CNT_EXP
)
3558 mp
->rx_crc_errors
+= RXMAC_CRC_ER_CNT_COUNT
;
3559 if (val
& XRXMAC_STATUS_RXUFLOW
)
3560 mp
->rx_underflows
++;
3561 if (val
& XRXMAC_STATUS_RXOFLOW
)
3564 val
= nr64_mac(XMAC_FC_STAT
);
3565 if (val
& XMAC_FC_STAT_TX_MAC_NPAUSE
)
3566 mp
->pause_off_state
++;
3567 if (val
& XMAC_FC_STAT_TX_MAC_PAUSE
)
3568 mp
->pause_on_state
++;
3569 if (val
& XMAC_FC_STAT_RX_MAC_RPAUSE
)
3570 mp
->pause_received
++;
3573 static void niu_bmac_interrupt(struct niu
*np
)
3575 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
3578 val
= nr64_mac(BTXMAC_STATUS
);
3579 if (val
& BTXMAC_STATUS_UNDERRUN
)
3580 mp
->tx_underflow_errors
++;
3581 if (val
& BTXMAC_STATUS_MAX_PKT_ERR
)
3582 mp
->tx_max_pkt_size_errors
++;
3583 if (val
& BTXMAC_STATUS_BYTE_CNT_EXP
)
3584 mp
->tx_bytes
+= BTXMAC_BYTE_CNT_COUNT
;
3585 if (val
& BTXMAC_STATUS_FRAME_CNT_EXP
)
3586 mp
->tx_frames
+= BTXMAC_FRM_CNT_COUNT
;
3588 val
= nr64_mac(BRXMAC_STATUS
);
3589 if (val
& BRXMAC_STATUS_OVERFLOW
)
3591 if (val
& BRXMAC_STATUS_FRAME_CNT_EXP
)
3592 mp
->rx_frames
+= BRXMAC_FRAME_CNT_COUNT
;
3593 if (val
& BRXMAC_STATUS_ALIGN_ERR_EXP
)
3594 mp
->rx_align_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
3595 if (val
& BRXMAC_STATUS_CRC_ERR_EXP
)
3596 mp
->rx_crc_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
3597 if (val
& BRXMAC_STATUS_LEN_ERR_EXP
)
3598 mp
->rx_len_errors
+= BRXMAC_CODE_VIOL_ERR_CNT_COUNT
;
3600 val
= nr64_mac(BMAC_CTRL_STATUS
);
3601 if (val
& BMAC_CTRL_STATUS_NOPAUSE
)
3602 mp
->pause_off_state
++;
3603 if (val
& BMAC_CTRL_STATUS_PAUSE
)
3604 mp
->pause_on_state
++;
3605 if (val
& BMAC_CTRL_STATUS_PAUSE_RECV
)
3606 mp
->pause_received
++;
3609 static int niu_mac_interrupt(struct niu
*np
)
3611 if (np
->flags
& NIU_FLAGS_XMAC
)
3612 niu_xmac_interrupt(np
);
3614 niu_bmac_interrupt(np
);
3619 static void niu_log_device_error(struct niu
*np
, u64 stat
)
3621 dev_err(np
->device
, PFX
"%s: Core device errors ( ",
3624 if (stat
& SYS_ERR_MASK_META2
)
3626 if (stat
& SYS_ERR_MASK_META1
)
3628 if (stat
& SYS_ERR_MASK_PEU
)
3630 if (stat
& SYS_ERR_MASK_TXC
)
3632 if (stat
& SYS_ERR_MASK_RDMC
)
3634 if (stat
& SYS_ERR_MASK_TDMC
)
3636 if (stat
& SYS_ERR_MASK_ZCP
)
3638 if (stat
& SYS_ERR_MASK_FFLP
)
3640 if (stat
& SYS_ERR_MASK_IPP
)
3642 if (stat
& SYS_ERR_MASK_MAC
)
3644 if (stat
& SYS_ERR_MASK_SMX
)
3650 static int niu_device_error(struct niu
*np
)
3652 u64 stat
= nr64(SYS_ERR_STAT
);
3654 dev_err(np
->device
, PFX
"%s: Core device error, stat[%llx]\n",
3655 np
->dev
->name
, (unsigned long long) stat
);
3657 niu_log_device_error(np
, stat
);
3662 static int niu_slowpath_interrupt(struct niu
*np
, struct niu_ldg
*lp
,
3663 u64 v0
, u64 v1
, u64 v2
)
3672 if (v1
& 0x00000000ffffffffULL
) {
3673 u32 rx_vec
= (v1
& 0xffffffff);
3675 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3676 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3678 if (rx_vec
& (1 << rp
->rx_channel
)) {
3679 int r
= niu_rx_error(np
, rp
);
3684 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
3685 RX_DMA_CTL_STAT_MEX
);
3690 if (v1
& 0x7fffffff00000000ULL
) {
3691 u32 tx_vec
= (v1
>> 32) & 0x7fffffff;
3693 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3694 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3696 if (tx_vec
& (1 << rp
->tx_channel
)) {
3697 int r
= niu_tx_error(np
, rp
);
3703 if ((v0
| v1
) & 0x8000000000000000ULL
) {
3704 int r
= niu_mif_interrupt(np
);
3710 int r
= niu_mac_interrupt(np
);
3715 int r
= niu_device_error(np
);
3722 niu_enable_interrupts(np
, 0);
3727 static void niu_rxchan_intr(struct niu
*np
, struct rx_ring_info
*rp
,
3730 struct rxdma_mailbox
*mbox
= rp
->mbox
;
3731 u64 stat_write
, stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
3733 stat_write
= (RX_DMA_CTL_STAT_RCRTHRES
|
3734 RX_DMA_CTL_STAT_RCRTO
);
3735 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat_write
);
3737 niudbg(INTR
, "%s: rxchan_intr stat[%llx]\n",
3738 np
->dev
->name
, (unsigned long long) stat
);
3741 static void niu_txchan_intr(struct niu
*np
, struct tx_ring_info
*rp
,
3744 rp
->tx_cs
= nr64(TX_CS(rp
->tx_channel
));
3746 niudbg(INTR
, "%s: txchan_intr cs[%llx]\n",
3747 np
->dev
->name
, (unsigned long long) rp
->tx_cs
);
3750 static void __niu_fastpath_interrupt(struct niu
*np
, int ldg
, u64 v0
)
3752 struct niu_parent
*parent
= np
->parent
;
3756 tx_vec
= (v0
>> 32);
3757 rx_vec
= (v0
& 0xffffffff);
3759 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3760 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3761 int ldn
= LDN_RXDMA(rp
->rx_channel
);
3763 if (parent
->ldg_map
[ldn
] != ldg
)
3766 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
3767 if (rx_vec
& (1 << rp
->rx_channel
))
3768 niu_rxchan_intr(np
, rp
, ldn
);
3771 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3772 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3773 int ldn
= LDN_TXDMA(rp
->tx_channel
);
3775 if (parent
->ldg_map
[ldn
] != ldg
)
3778 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
3779 if (tx_vec
& (1 << rp
->tx_channel
))
3780 niu_txchan_intr(np
, rp
, ldn
);
3784 static void niu_schedule_napi(struct niu
*np
, struct niu_ldg
*lp
,
3785 u64 v0
, u64 v1
, u64 v2
)
3787 if (likely(netif_rx_schedule_prep(np
->dev
, &lp
->napi
))) {
3791 __niu_fastpath_interrupt(np
, lp
->ldg_num
, v0
);
3792 __netif_rx_schedule(np
->dev
, &lp
->napi
);
3796 static irqreturn_t
niu_interrupt(int irq
, void *dev_id
)
3798 struct niu_ldg
*lp
= dev_id
;
3799 struct niu
*np
= lp
->np
;
3800 int ldg
= lp
->ldg_num
;
3801 unsigned long flags
;
3804 if (netif_msg_intr(np
))
3805 printk(KERN_DEBUG PFX
"niu_interrupt() ldg[%p](%d) ",
3808 spin_lock_irqsave(&np
->lock
, flags
);
3810 v0
= nr64(LDSV0(ldg
));
3811 v1
= nr64(LDSV1(ldg
));
3812 v2
= nr64(LDSV2(ldg
));
3814 if (netif_msg_intr(np
))
3815 printk("v0[%llx] v1[%llx] v2[%llx]\n",
3816 (unsigned long long) v0
,
3817 (unsigned long long) v1
,
3818 (unsigned long long) v2
);
3820 if (unlikely(!v0
&& !v1
&& !v2
)) {
3821 spin_unlock_irqrestore(&np
->lock
, flags
);
3825 if (unlikely((v0
& ((u64
)1 << LDN_MIF
)) || v1
|| v2
)) {
3826 int err
= niu_slowpath_interrupt(np
, lp
, v0
, v1
, v2
);
3830 if (likely(v0
& ~((u64
)1 << LDN_MIF
)))
3831 niu_schedule_napi(np
, lp
, v0
, v1
, v2
);
3833 niu_ldg_rearm(np
, lp
, 1);
3835 spin_unlock_irqrestore(&np
->lock
, flags
);
3840 static void niu_free_rx_ring_info(struct niu
*np
, struct rx_ring_info
*rp
)
3843 np
->ops
->free_coherent(np
->device
,
3844 sizeof(struct rxdma_mailbox
),
3845 rp
->mbox
, rp
->mbox_dma
);
3849 np
->ops
->free_coherent(np
->device
,
3850 MAX_RCR_RING_SIZE
* sizeof(__le64
),
3851 rp
->rcr
, rp
->rcr_dma
);
3853 rp
->rcr_table_size
= 0;
3857 niu_rbr_free(np
, rp
);
3859 np
->ops
->free_coherent(np
->device
,
3860 MAX_RBR_RING_SIZE
* sizeof(__le32
),
3861 rp
->rbr
, rp
->rbr_dma
);
3863 rp
->rbr_table_size
= 0;
3870 static void niu_free_tx_ring_info(struct niu
*np
, struct tx_ring_info
*rp
)
3873 np
->ops
->free_coherent(np
->device
,
3874 sizeof(struct txdma_mailbox
),
3875 rp
->mbox
, rp
->mbox_dma
);
3881 for (i
= 0; i
< MAX_TX_RING_SIZE
; i
++) {
3882 if (rp
->tx_buffs
[i
].skb
)
3883 (void) release_tx_packet(np
, rp
, i
);
3886 np
->ops
->free_coherent(np
->device
,
3887 MAX_TX_RING_SIZE
* sizeof(__le64
),
3888 rp
->descr
, rp
->descr_dma
);
3897 static void niu_free_channels(struct niu
*np
)
3902 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3903 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3905 niu_free_rx_ring_info(np
, rp
);
3907 kfree(np
->rx_rings
);
3908 np
->rx_rings
= NULL
;
3909 np
->num_rx_rings
= 0;
3913 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3914 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3916 niu_free_tx_ring_info(np
, rp
);
3918 kfree(np
->tx_rings
);
3919 np
->tx_rings
= NULL
;
3920 np
->num_tx_rings
= 0;
3924 static int niu_alloc_rx_ring_info(struct niu
*np
,
3925 struct rx_ring_info
*rp
)
3927 BUILD_BUG_ON(sizeof(struct rxdma_mailbox
) != 64);
3929 rp
->rxhash
= kzalloc(MAX_RBR_RING_SIZE
* sizeof(struct page
*),
3934 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
3935 sizeof(struct rxdma_mailbox
),
3936 &rp
->mbox_dma
, GFP_KERNEL
);
3939 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
3940 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
3941 "RXDMA mailbox %p\n", np
->dev
->name
, rp
->mbox
);
3945 rp
->rcr
= np
->ops
->alloc_coherent(np
->device
,
3946 MAX_RCR_RING_SIZE
* sizeof(__le64
),
3947 &rp
->rcr_dma
, GFP_KERNEL
);
3950 if ((unsigned long)rp
->rcr
& (64UL - 1)) {
3951 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
3952 "RXDMA RCR table %p\n", np
->dev
->name
, rp
->rcr
);
3955 rp
->rcr_table_size
= MAX_RCR_RING_SIZE
;
3958 rp
->rbr
= np
->ops
->alloc_coherent(np
->device
,
3959 MAX_RBR_RING_SIZE
* sizeof(__le32
),
3960 &rp
->rbr_dma
, GFP_KERNEL
);
3963 if ((unsigned long)rp
->rbr
& (64UL - 1)) {
3964 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
3965 "RXDMA RBR table %p\n", np
->dev
->name
, rp
->rbr
);
3968 rp
->rbr_table_size
= MAX_RBR_RING_SIZE
;
3970 rp
->rbr_pending
= 0;
3975 static void niu_set_max_burst(struct niu
*np
, struct tx_ring_info
*rp
)
3977 int mtu
= np
->dev
->mtu
;
3979 /* These values are recommended by the HW designers for fair
3980 * utilization of DRR amongst the rings.
3982 rp
->max_burst
= mtu
+ 32;
3983 if (rp
->max_burst
> 4096)
3984 rp
->max_burst
= 4096;
3987 static int niu_alloc_tx_ring_info(struct niu
*np
,
3988 struct tx_ring_info
*rp
)
3990 BUILD_BUG_ON(sizeof(struct txdma_mailbox
) != 64);
3992 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
3993 sizeof(struct txdma_mailbox
),
3994 &rp
->mbox_dma
, GFP_KERNEL
);
3997 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
3998 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
3999 "TXDMA mailbox %p\n", np
->dev
->name
, rp
->mbox
);
4003 rp
->descr
= np
->ops
->alloc_coherent(np
->device
,
4004 MAX_TX_RING_SIZE
* sizeof(__le64
),
4005 &rp
->descr_dma
, GFP_KERNEL
);
4008 if ((unsigned long)rp
->descr
& (64UL - 1)) {
4009 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4010 "TXDMA descr table %p\n", np
->dev
->name
, rp
->descr
);
4014 rp
->pending
= MAX_TX_RING_SIZE
;
4019 /* XXX make these configurable... XXX */
4020 rp
->mark_freq
= rp
->pending
/ 4;
4022 niu_set_max_burst(np
, rp
);
4027 static void niu_size_rbr(struct niu
*np
, struct rx_ring_info
*rp
)
4031 bss
= min(PAGE_SHIFT
, 15);
4033 rp
->rbr_block_size
= 1 << bss
;
4034 rp
->rbr_blocks_per_page
= 1 << (PAGE_SHIFT
-bss
);
4036 rp
->rbr_sizes
[0] = 256;
4037 rp
->rbr_sizes
[1] = 1024;
4038 if (np
->dev
->mtu
> ETH_DATA_LEN
) {
4039 switch (PAGE_SIZE
) {
4041 rp
->rbr_sizes
[2] = 4096;
4045 rp
->rbr_sizes
[2] = 8192;
4049 rp
->rbr_sizes
[2] = 2048;
4051 rp
->rbr_sizes
[3] = rp
->rbr_block_size
;
4054 static int niu_alloc_channels(struct niu
*np
)
4056 struct niu_parent
*parent
= np
->parent
;
4057 int first_rx_channel
, first_tx_channel
;
4061 first_rx_channel
= first_tx_channel
= 0;
4062 for (i
= 0; i
< port
; i
++) {
4063 first_rx_channel
+= parent
->rxchan_per_port
[i
];
4064 first_tx_channel
+= parent
->txchan_per_port
[i
];
4067 np
->num_rx_rings
= parent
->rxchan_per_port
[port
];
4068 np
->num_tx_rings
= parent
->txchan_per_port
[port
];
4070 np
->rx_rings
= kzalloc(np
->num_rx_rings
* sizeof(struct rx_ring_info
),
4076 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4077 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4080 rp
->rx_channel
= first_rx_channel
+ i
;
4082 err
= niu_alloc_rx_ring_info(np
, rp
);
4086 niu_size_rbr(np
, rp
);
4088 /* XXX better defaults, configurable, etc... XXX */
4089 rp
->nonsyn_window
= 64;
4090 rp
->nonsyn_threshold
= rp
->rcr_table_size
- 64;
4091 rp
->syn_window
= 64;
4092 rp
->syn_threshold
= rp
->rcr_table_size
- 64;
4093 rp
->rcr_pkt_threshold
= 16;
4094 rp
->rcr_timeout
= 8;
4095 rp
->rbr_kick_thresh
= RBR_REFILL_MIN
;
4096 if (rp
->rbr_kick_thresh
< rp
->rbr_blocks_per_page
)
4097 rp
->rbr_kick_thresh
= rp
->rbr_blocks_per_page
;
4099 err
= niu_rbr_fill(np
, rp
, GFP_KERNEL
);
4104 np
->tx_rings
= kzalloc(np
->num_tx_rings
* sizeof(struct tx_ring_info
),
4110 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4111 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4114 rp
->tx_channel
= first_tx_channel
+ i
;
4116 err
= niu_alloc_tx_ring_info(np
, rp
);
4124 niu_free_channels(np
);
4128 static int niu_tx_cs_sng_poll(struct niu
*np
, int channel
)
4132 while (--limit
> 0) {
4133 u64 val
= nr64(TX_CS(channel
));
4134 if (val
& TX_CS_SNG_STATE
)
4140 static int niu_tx_channel_stop(struct niu
*np
, int channel
)
4142 u64 val
= nr64(TX_CS(channel
));
4144 val
|= TX_CS_STOP_N_GO
;
4145 nw64(TX_CS(channel
), val
);
4147 return niu_tx_cs_sng_poll(np
, channel
);
4150 static int niu_tx_cs_reset_poll(struct niu
*np
, int channel
)
4154 while (--limit
> 0) {
4155 u64 val
= nr64(TX_CS(channel
));
4156 if (!(val
& TX_CS_RST
))
4162 static int niu_tx_channel_reset(struct niu
*np
, int channel
)
4164 u64 val
= nr64(TX_CS(channel
));
4168 nw64(TX_CS(channel
), val
);
4170 err
= niu_tx_cs_reset_poll(np
, channel
);
4172 nw64(TX_RING_KICK(channel
), 0);
4177 static int niu_tx_channel_lpage_init(struct niu
*np
, int channel
)
4181 nw64(TX_LOG_MASK1(channel
), 0);
4182 nw64(TX_LOG_VAL1(channel
), 0);
4183 nw64(TX_LOG_MASK2(channel
), 0);
4184 nw64(TX_LOG_VAL2(channel
), 0);
4185 nw64(TX_LOG_PAGE_RELO1(channel
), 0);
4186 nw64(TX_LOG_PAGE_RELO2(channel
), 0);
4187 nw64(TX_LOG_PAGE_HDL(channel
), 0);
4189 val
= (u64
)np
->port
<< TX_LOG_PAGE_VLD_FUNC_SHIFT
;
4190 val
|= (TX_LOG_PAGE_VLD_PAGE0
| TX_LOG_PAGE_VLD_PAGE1
);
4191 nw64(TX_LOG_PAGE_VLD(channel
), val
);
4193 /* XXX TXDMA 32bit mode? XXX */
4198 static void niu_txc_enable_port(struct niu
*np
, int on
)
4200 unsigned long flags
;
4203 niu_lock_parent(np
, flags
);
4204 val
= nr64(TXC_CONTROL
);
4205 mask
= (u64
)1 << np
->port
;
4207 val
|= TXC_CONTROL_ENABLE
| mask
;
4210 if ((val
& ~TXC_CONTROL_ENABLE
) == 0)
4211 val
&= ~TXC_CONTROL_ENABLE
;
4213 nw64(TXC_CONTROL
, val
);
4214 niu_unlock_parent(np
, flags
);
4217 static void niu_txc_set_imask(struct niu
*np
, u64 imask
)
4219 unsigned long flags
;
4222 niu_lock_parent(np
, flags
);
4223 val
= nr64(TXC_INT_MASK
);
4224 val
&= ~TXC_INT_MASK_VAL(np
->port
);
4225 val
|= (imask
<< TXC_INT_MASK_VAL_SHIFT(np
->port
));
4226 niu_unlock_parent(np
, flags
);
4229 static void niu_txc_port_dma_enable(struct niu
*np
, int on
)
4236 for (i
= 0; i
< np
->num_tx_rings
; i
++)
4237 val
|= (1 << np
->tx_rings
[i
].tx_channel
);
4239 nw64(TXC_PORT_DMA(np
->port
), val
);
4242 static int niu_init_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
4244 int err
, channel
= rp
->tx_channel
;
4247 err
= niu_tx_channel_stop(np
, channel
);
4251 err
= niu_tx_channel_reset(np
, channel
);
4255 err
= niu_tx_channel_lpage_init(np
, channel
);
4259 nw64(TXC_DMA_MAX(channel
), rp
->max_burst
);
4260 nw64(TX_ENT_MSK(channel
), 0);
4262 if (rp
->descr_dma
& ~(TX_RNG_CFIG_STADDR_BASE
|
4263 TX_RNG_CFIG_STADDR
)) {
4264 dev_err(np
->device
, PFX
"%s: TX ring channel %d "
4265 "DMA addr (%llx) is not aligned.\n",
4266 np
->dev
->name
, channel
,
4267 (unsigned long long) rp
->descr_dma
);
4271 /* The length field in TX_RNG_CFIG is measured in 64-byte
4272 * blocks. rp->pending is the number of TX descriptors in
4273 * our ring, 8 bytes each, thus we divide by 8 bytes more
4274 * to get the proper value the chip wants.
4276 ring_len
= (rp
->pending
/ 8);
4278 val
= ((ring_len
<< TX_RNG_CFIG_LEN_SHIFT
) |
4280 nw64(TX_RNG_CFIG(channel
), val
);
4282 if (((rp
->mbox_dma
>> 32) & ~TXDMA_MBH_MBADDR
) ||
4283 ((u32
)rp
->mbox_dma
& ~TXDMA_MBL_MBADDR
)) {
4284 dev_err(np
->device
, PFX
"%s: TX ring channel %d "
4285 "MBOX addr (%llx) is has illegal bits.\n",
4286 np
->dev
->name
, channel
,
4287 (unsigned long long) rp
->mbox_dma
);
4290 nw64(TXDMA_MBH(channel
), rp
->mbox_dma
>> 32);
4291 nw64(TXDMA_MBL(channel
), rp
->mbox_dma
& TXDMA_MBL_MBADDR
);
4293 nw64(TX_CS(channel
), 0);
4295 rp
->last_pkt_cnt
= 0;
4300 static void niu_init_rdc_groups(struct niu
*np
)
4302 struct niu_rdc_tables
*tp
= &np
->parent
->rdc_group_cfg
[np
->port
];
4303 int i
, first_table_num
= tp
->first_table_num
;
4305 for (i
= 0; i
< tp
->num_tables
; i
++) {
4306 struct rdc_table
*tbl
= &tp
->tables
[i
];
4307 int this_table
= first_table_num
+ i
;
4310 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++)
4311 nw64(RDC_TBL(this_table
, slot
),
4312 tbl
->rxdma_channel
[slot
]);
4315 nw64(DEF_RDC(np
->port
), np
->parent
->rdc_default
[np
->port
]);
4318 static void niu_init_drr_weight(struct niu
*np
)
4320 int type
= phy_decode(np
->parent
->port_phy
, np
->port
);
4325 val
= PT_DRR_WEIGHT_DEFAULT_10G
;
4330 val
= PT_DRR_WEIGHT_DEFAULT_1G
;
4333 nw64(PT_DRR_WT(np
->port
), val
);
4336 static int niu_init_hostinfo(struct niu
*np
)
4338 struct niu_parent
*parent
= np
->parent
;
4339 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
4340 int i
, err
, num_alt
= niu_num_alt_addr(np
);
4341 int first_rdc_table
= tp
->first_table_num
;
4343 err
= niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
4347 err
= niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
4351 for (i
= 0; i
< num_alt
; i
++) {
4352 err
= niu_set_alt_mac_rdc_table(np
, i
, first_rdc_table
, 1);
4360 static int niu_rx_channel_reset(struct niu
*np
, int channel
)
4362 return niu_set_and_wait_clear(np
, RXDMA_CFIG1(channel
),
4363 RXDMA_CFIG1_RST
, 1000, 10,
4367 static int niu_rx_channel_lpage_init(struct niu
*np
, int channel
)
4371 nw64(RX_LOG_MASK1(channel
), 0);
4372 nw64(RX_LOG_VAL1(channel
), 0);
4373 nw64(RX_LOG_MASK2(channel
), 0);
4374 nw64(RX_LOG_VAL2(channel
), 0);
4375 nw64(RX_LOG_PAGE_RELO1(channel
), 0);
4376 nw64(RX_LOG_PAGE_RELO2(channel
), 0);
4377 nw64(RX_LOG_PAGE_HDL(channel
), 0);
4379 val
= (u64
)np
->port
<< RX_LOG_PAGE_VLD_FUNC_SHIFT
;
4380 val
|= (RX_LOG_PAGE_VLD_PAGE0
| RX_LOG_PAGE_VLD_PAGE1
);
4381 nw64(RX_LOG_PAGE_VLD(channel
), val
);
4386 static void niu_rx_channel_wred_init(struct niu
*np
, struct rx_ring_info
*rp
)
4390 val
= (((u64
)rp
->nonsyn_window
<< RDC_RED_PARA_WIN_SHIFT
) |
4391 ((u64
)rp
->nonsyn_threshold
<< RDC_RED_PARA_THRE_SHIFT
) |
4392 ((u64
)rp
->syn_window
<< RDC_RED_PARA_WIN_SYN_SHIFT
) |
4393 ((u64
)rp
->syn_threshold
<< RDC_RED_PARA_THRE_SYN_SHIFT
));
4394 nw64(RDC_RED_PARA(rp
->rx_channel
), val
);
4397 static int niu_compute_rbr_cfig_b(struct rx_ring_info
*rp
, u64
*ret
)
4401 switch (rp
->rbr_block_size
) {
4403 val
|= (RBR_BLKSIZE_4K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4406 val
|= (RBR_BLKSIZE_8K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4409 val
|= (RBR_BLKSIZE_16K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4412 val
|= (RBR_BLKSIZE_32K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4417 val
|= RBR_CFIG_B_VLD2
;
4418 switch (rp
->rbr_sizes
[2]) {
4420 val
|= (RBR_BUFSZ2_2K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4423 val
|= (RBR_BUFSZ2_4K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4426 val
|= (RBR_BUFSZ2_8K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4429 val
|= (RBR_BUFSZ2_16K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4435 val
|= RBR_CFIG_B_VLD1
;
4436 switch (rp
->rbr_sizes
[1]) {
4438 val
|= (RBR_BUFSZ1_1K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4441 val
|= (RBR_BUFSZ1_2K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4444 val
|= (RBR_BUFSZ1_4K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4447 val
|= (RBR_BUFSZ1_8K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4453 val
|= RBR_CFIG_B_VLD0
;
4454 switch (rp
->rbr_sizes
[0]) {
4456 val
|= (RBR_BUFSZ0_256
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4459 val
|= (RBR_BUFSZ0_512
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4462 val
|= (RBR_BUFSZ0_1K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4465 val
|= (RBR_BUFSZ0_2K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4476 static int niu_enable_rx_channel(struct niu
*np
, int channel
, int on
)
4478 u64 val
= nr64(RXDMA_CFIG1(channel
));
4482 val
|= RXDMA_CFIG1_EN
;
4484 val
&= ~RXDMA_CFIG1_EN
;
4485 nw64(RXDMA_CFIG1(channel
), val
);
4488 while (--limit
> 0) {
4489 if (nr64(RXDMA_CFIG1(channel
)) & RXDMA_CFIG1_QST
)
4498 static int niu_init_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
4500 int err
, channel
= rp
->rx_channel
;
4503 err
= niu_rx_channel_reset(np
, channel
);
4507 err
= niu_rx_channel_lpage_init(np
, channel
);
4511 niu_rx_channel_wred_init(np
, rp
);
4513 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_RBR_EMPTY
);
4514 nw64(RX_DMA_CTL_STAT(channel
),
4515 (RX_DMA_CTL_STAT_MEX
|
4516 RX_DMA_CTL_STAT_RCRTHRES
|
4517 RX_DMA_CTL_STAT_RCRTO
|
4518 RX_DMA_CTL_STAT_RBR_EMPTY
));
4519 nw64(RXDMA_CFIG1(channel
), rp
->mbox_dma
>> 32);
4520 nw64(RXDMA_CFIG2(channel
), (rp
->mbox_dma
& 0x00000000ffffffc0));
4521 nw64(RBR_CFIG_A(channel
),
4522 ((u64
)rp
->rbr_table_size
<< RBR_CFIG_A_LEN_SHIFT
) |
4523 (rp
->rbr_dma
& (RBR_CFIG_A_STADDR_BASE
| RBR_CFIG_A_STADDR
)));
4524 err
= niu_compute_rbr_cfig_b(rp
, &val
);
4527 nw64(RBR_CFIG_B(channel
), val
);
4528 nw64(RCRCFIG_A(channel
),
4529 ((u64
)rp
->rcr_table_size
<< RCRCFIG_A_LEN_SHIFT
) |
4530 (rp
->rcr_dma
& (RCRCFIG_A_STADDR_BASE
| RCRCFIG_A_STADDR
)));
4531 nw64(RCRCFIG_B(channel
),
4532 ((u64
)rp
->rcr_pkt_threshold
<< RCRCFIG_B_PTHRES_SHIFT
) |
4534 ((u64
)rp
->rcr_timeout
<< RCRCFIG_B_TIMEOUT_SHIFT
));
4536 err
= niu_enable_rx_channel(np
, channel
, 1);
4540 nw64(RBR_KICK(channel
), rp
->rbr_index
);
4542 val
= nr64(RX_DMA_CTL_STAT(channel
));
4543 val
|= RX_DMA_CTL_STAT_RBR_EMPTY
;
4544 nw64(RX_DMA_CTL_STAT(channel
), val
);
4549 static int niu_init_rx_channels(struct niu
*np
)
4551 unsigned long flags
;
4552 u64 seed
= jiffies_64
;
4555 niu_lock_parent(np
, flags
);
4556 nw64(RX_DMA_CK_DIV
, np
->parent
->rxdma_clock_divider
);
4557 nw64(RED_RAN_INIT
, RED_RAN_INIT_OPMODE
| (seed
& RED_RAN_INIT_VAL
));
4558 niu_unlock_parent(np
, flags
);
4560 /* XXX RXDMA 32bit mode? XXX */
4562 niu_init_rdc_groups(np
);
4563 niu_init_drr_weight(np
);
4565 err
= niu_init_hostinfo(np
);
4569 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4570 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4572 err
= niu_init_one_rx_channel(np
, rp
);
4580 static int niu_set_ip_frag_rule(struct niu
*np
)
4582 struct niu_parent
*parent
= np
->parent
;
4583 struct niu_classifier
*cp
= &np
->clas
;
4584 struct niu_tcam_entry
*tp
;
4587 /* XXX fix this allocation scheme XXX */
4588 index
= cp
->tcam_index
;
4589 tp
= &parent
->tcam
[index
];
4591 /* Note that the noport bit is the same in both ipv4 and
4592 * ipv6 format TCAM entries.
4594 memset(tp
, 0, sizeof(*tp
));
4595 tp
->key
[1] = TCAM_V4KEY1_NOPORT
;
4596 tp
->key_mask
[1] = TCAM_V4KEY1_NOPORT
;
4597 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
4598 ((u64
)0 << TCAM_ASSOCDATA_OFFSET_SHIFT
));
4599 err
= tcam_write(np
, index
, tp
->key
, tp
->key_mask
);
4602 err
= tcam_assoc_write(np
, index
, tp
->assoc_data
);
4609 static int niu_init_classifier_hw(struct niu
*np
)
4611 struct niu_parent
*parent
= np
->parent
;
4612 struct niu_classifier
*cp
= &np
->clas
;
4615 nw64(H1POLY
, cp
->h1_init
);
4616 nw64(H2POLY
, cp
->h2_init
);
4618 err
= niu_init_hostinfo(np
);
4622 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++) {
4623 struct niu_vlan_rdc
*vp
= &cp
->vlan_mappings
[i
];
4625 vlan_tbl_write(np
, i
, np
->port
,
4626 vp
->vlan_pref
, vp
->rdc_num
);
4629 for (i
= 0; i
< cp
->num_alt_mac_mappings
; i
++) {
4630 struct niu_altmac_rdc
*ap
= &cp
->alt_mac_mappings
[i
];
4632 err
= niu_set_alt_mac_rdc_table(np
, ap
->alt_mac_num
,
4633 ap
->rdc_num
, ap
->mac_pref
);
4638 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
4639 int index
= i
- CLASS_CODE_USER_PROG1
;
4641 err
= niu_set_tcam_key(np
, i
, parent
->tcam_key
[index
]);
4644 err
= niu_set_flow_key(np
, i
, parent
->flow_key
[index
]);
4649 err
= niu_set_ip_frag_rule(np
);
4658 static int niu_zcp_write(struct niu
*np
, int index
, u64
*data
)
4660 nw64(ZCP_RAM_DATA0
, data
[0]);
4661 nw64(ZCP_RAM_DATA1
, data
[1]);
4662 nw64(ZCP_RAM_DATA2
, data
[2]);
4663 nw64(ZCP_RAM_DATA3
, data
[3]);
4664 nw64(ZCP_RAM_DATA4
, data
[4]);
4665 nw64(ZCP_RAM_BE
, ZCP_RAM_BE_VAL
);
4667 (ZCP_RAM_ACC_WRITE
|
4668 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
4669 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
4671 return niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
4675 static int niu_zcp_read(struct niu
*np
, int index
, u64
*data
)
4679 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
4682 dev_err(np
->device
, PFX
"%s: ZCP read busy won't clear, "
4683 "ZCP_RAM_ACC[%llx]\n", np
->dev
->name
,
4684 (unsigned long long) nr64(ZCP_RAM_ACC
));
4690 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
4691 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
4693 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
4696 dev_err(np
->device
, PFX
"%s: ZCP read busy2 won't clear, "
4697 "ZCP_RAM_ACC[%llx]\n", np
->dev
->name
,
4698 (unsigned long long) nr64(ZCP_RAM_ACC
));
4702 data
[0] = nr64(ZCP_RAM_DATA0
);
4703 data
[1] = nr64(ZCP_RAM_DATA1
);
4704 data
[2] = nr64(ZCP_RAM_DATA2
);
4705 data
[3] = nr64(ZCP_RAM_DATA3
);
4706 data
[4] = nr64(ZCP_RAM_DATA4
);
4711 static void niu_zcp_cfifo_reset(struct niu
*np
)
4713 u64 val
= nr64(RESET_CFIFO
);
4715 val
|= RESET_CFIFO_RST(np
->port
);
4716 nw64(RESET_CFIFO
, val
);
4719 val
&= ~RESET_CFIFO_RST(np
->port
);
4720 nw64(RESET_CFIFO
, val
);
4723 static int niu_init_zcp(struct niu
*np
)
4725 u64 data
[5], rbuf
[5];
4728 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
4729 if (np
->port
== 0 || np
->port
== 1)
4730 max
= ATLAS_P0_P1_CFIFO_ENTRIES
;
4732 max
= ATLAS_P2_P3_CFIFO_ENTRIES
;
4734 max
= NIU_CFIFO_ENTRIES
;
4742 for (i
= 0; i
< max
; i
++) {
4743 err
= niu_zcp_write(np
, i
, data
);
4746 err
= niu_zcp_read(np
, i
, rbuf
);
4751 niu_zcp_cfifo_reset(np
);
4752 nw64(CFIFO_ECC(np
->port
), 0);
4753 nw64(ZCP_INT_STAT
, ZCP_INT_STAT_ALL
);
4754 (void) nr64(ZCP_INT_STAT
);
4755 nw64(ZCP_INT_MASK
, ZCP_INT_MASK_ALL
);
4760 static void niu_ipp_write(struct niu
*np
, int index
, u64
*data
)
4762 u64 val
= nr64_ipp(IPP_CFIG
);
4764 nw64_ipp(IPP_CFIG
, val
| IPP_CFIG_DFIFO_PIO_W
);
4765 nw64_ipp(IPP_DFIFO_WR_PTR
, index
);
4766 nw64_ipp(IPP_DFIFO_WR0
, data
[0]);
4767 nw64_ipp(IPP_DFIFO_WR1
, data
[1]);
4768 nw64_ipp(IPP_DFIFO_WR2
, data
[2]);
4769 nw64_ipp(IPP_DFIFO_WR3
, data
[3]);
4770 nw64_ipp(IPP_DFIFO_WR4
, data
[4]);
4771 nw64_ipp(IPP_CFIG
, val
& ~IPP_CFIG_DFIFO_PIO_W
);
4774 static void niu_ipp_read(struct niu
*np
, int index
, u64
*data
)
4776 nw64_ipp(IPP_DFIFO_RD_PTR
, index
);
4777 data
[0] = nr64_ipp(IPP_DFIFO_RD0
);
4778 data
[1] = nr64_ipp(IPP_DFIFO_RD1
);
4779 data
[2] = nr64_ipp(IPP_DFIFO_RD2
);
4780 data
[3] = nr64_ipp(IPP_DFIFO_RD3
);
4781 data
[4] = nr64_ipp(IPP_DFIFO_RD4
);
4784 static int niu_ipp_reset(struct niu
*np
)
4786 return niu_set_and_wait_clear_ipp(np
, IPP_CFIG
, IPP_CFIG_SOFT_RST
,
4787 1000, 100, "IPP_CFIG");
4790 static int niu_init_ipp(struct niu
*np
)
4792 u64 data
[5], rbuf
[5], val
;
4795 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
4796 if (np
->port
== 0 || np
->port
== 1)
4797 max
= ATLAS_P0_P1_DFIFO_ENTRIES
;
4799 max
= ATLAS_P2_P3_DFIFO_ENTRIES
;
4801 max
= NIU_DFIFO_ENTRIES
;
4809 for (i
= 0; i
< max
; i
++) {
4810 niu_ipp_write(np
, i
, data
);
4811 niu_ipp_read(np
, i
, rbuf
);
4814 (void) nr64_ipp(IPP_INT_STAT
);
4815 (void) nr64_ipp(IPP_INT_STAT
);
4817 err
= niu_ipp_reset(np
);
4821 (void) nr64_ipp(IPP_PKT_DIS
);
4822 (void) nr64_ipp(IPP_BAD_CS_CNT
);
4823 (void) nr64_ipp(IPP_ECC
);
4825 (void) nr64_ipp(IPP_INT_STAT
);
4827 nw64_ipp(IPP_MSK
, ~IPP_MSK_ALL
);
4829 val
= nr64_ipp(IPP_CFIG
);
4830 val
&= ~IPP_CFIG_IP_MAX_PKT
;
4831 val
|= (IPP_CFIG_IPP_ENABLE
|
4832 IPP_CFIG_DFIFO_ECC_EN
|
4833 IPP_CFIG_DROP_BAD_CRC
|
4835 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT
));
4836 nw64_ipp(IPP_CFIG
, val
);
4841 static void niu_handle_led(struct niu
*np
, int status
)
4844 val
= nr64_mac(XMAC_CONFIG
);
4846 if ((np
->flags
& NIU_FLAGS_10G
) != 0 &&
4847 (np
->flags
& NIU_FLAGS_FIBER
) != 0) {
4849 val
|= XMAC_CONFIG_LED_POLARITY
;
4850 val
&= ~XMAC_CONFIG_FORCE_LED_ON
;
4852 val
|= XMAC_CONFIG_FORCE_LED_ON
;
4853 val
&= ~XMAC_CONFIG_LED_POLARITY
;
4857 nw64_mac(XMAC_CONFIG
, val
);
4860 static void niu_init_xif_xmac(struct niu
*np
)
4862 struct niu_link_config
*lp
= &np
->link_config
;
4865 if (np
->flags
& NIU_FLAGS_XCVR_SERDES
) {
4866 val
= nr64(MIF_CONFIG
);
4867 val
|= MIF_CONFIG_ATCA_GE
;
4868 nw64(MIF_CONFIG
, val
);
4871 val
= nr64_mac(XMAC_CONFIG
);
4872 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
4874 val
|= XMAC_CONFIG_TX_OUTPUT_EN
;
4876 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
4877 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
4878 val
|= XMAC_CONFIG_LOOPBACK
;
4880 val
&= ~XMAC_CONFIG_LOOPBACK
;
4883 if (np
->flags
& NIU_FLAGS_10G
) {
4884 val
&= ~XMAC_CONFIG_LFS_DISABLE
;
4886 val
|= XMAC_CONFIG_LFS_DISABLE
;
4887 if (!(np
->flags
& NIU_FLAGS_FIBER
) &&
4888 !(np
->flags
& NIU_FLAGS_XCVR_SERDES
))
4889 val
|= XMAC_CONFIG_1G_PCS_BYPASS
;
4891 val
&= ~XMAC_CONFIG_1G_PCS_BYPASS
;
4894 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
4896 if (lp
->active_speed
== SPEED_100
)
4897 val
|= XMAC_CONFIG_SEL_CLK_25MHZ
;
4899 val
&= ~XMAC_CONFIG_SEL_CLK_25MHZ
;
4901 nw64_mac(XMAC_CONFIG
, val
);
4903 val
= nr64_mac(XMAC_CONFIG
);
4904 val
&= ~XMAC_CONFIG_MODE_MASK
;
4905 if (np
->flags
& NIU_FLAGS_10G
) {
4906 val
|= XMAC_CONFIG_MODE_XGMII
;
4908 if (lp
->active_speed
== SPEED_100
)
4909 val
|= XMAC_CONFIG_MODE_MII
;
4911 val
|= XMAC_CONFIG_MODE_GMII
;
4914 nw64_mac(XMAC_CONFIG
, val
);
4917 static void niu_init_xif_bmac(struct niu
*np
)
4919 struct niu_link_config
*lp
= &np
->link_config
;
4922 val
= BMAC_XIF_CONFIG_TX_OUTPUT_EN
;
4924 if (lp
->loopback_mode
== LOOPBACK_MAC
)
4925 val
|= BMAC_XIF_CONFIG_MII_LOOPBACK
;
4927 val
&= ~BMAC_XIF_CONFIG_MII_LOOPBACK
;
4929 if (lp
->active_speed
== SPEED_1000
)
4930 val
|= BMAC_XIF_CONFIG_GMII_MODE
;
4932 val
&= ~BMAC_XIF_CONFIG_GMII_MODE
;
4934 val
&= ~(BMAC_XIF_CONFIG_LINK_LED
|
4935 BMAC_XIF_CONFIG_LED_POLARITY
);
4937 if (!(np
->flags
& NIU_FLAGS_10G
) &&
4938 !(np
->flags
& NIU_FLAGS_FIBER
) &&
4939 lp
->active_speed
== SPEED_100
)
4940 val
|= BMAC_XIF_CONFIG_25MHZ_CLOCK
;
4942 val
&= ~BMAC_XIF_CONFIG_25MHZ_CLOCK
;
4944 nw64_mac(BMAC_XIF_CONFIG
, val
);
4947 static void niu_init_xif(struct niu
*np
)
4949 if (np
->flags
& NIU_FLAGS_XMAC
)
4950 niu_init_xif_xmac(np
);
4952 niu_init_xif_bmac(np
);
4955 static void niu_pcs_mii_reset(struct niu
*np
)
4958 u64 val
= nr64_pcs(PCS_MII_CTL
);
4959 val
|= PCS_MII_CTL_RST
;
4960 nw64_pcs(PCS_MII_CTL
, val
);
4961 while ((--limit
>= 0) && (val
& PCS_MII_CTL_RST
)) {
4963 val
= nr64_pcs(PCS_MII_CTL
);
4967 static void niu_xpcs_reset(struct niu
*np
)
4970 u64 val
= nr64_xpcs(XPCS_CONTROL1
);
4971 val
|= XPCS_CONTROL1_RESET
;
4972 nw64_xpcs(XPCS_CONTROL1
, val
);
4973 while ((--limit
>= 0) && (val
& XPCS_CONTROL1_RESET
)) {
4975 val
= nr64_xpcs(XPCS_CONTROL1
);
4979 static int niu_init_pcs(struct niu
*np
)
4981 struct niu_link_config
*lp
= &np
->link_config
;
4984 switch (np
->flags
& (NIU_FLAGS_10G
|
4986 NIU_FLAGS_XCVR_SERDES
)) {
4987 case NIU_FLAGS_FIBER
:
4989 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
4990 nw64_pcs(PCS_DPATH_MODE
, 0);
4991 niu_pcs_mii_reset(np
);
4995 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
4996 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
4998 if (!(np
->flags
& NIU_FLAGS_XMAC
))
5001 /* 10G copper or fiber */
5002 val
= nr64_mac(XMAC_CONFIG
);
5003 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5004 nw64_mac(XMAC_CONFIG
, val
);
5008 val
= nr64_xpcs(XPCS_CONTROL1
);
5009 if (lp
->loopback_mode
== LOOPBACK_PHY
)
5010 val
|= XPCS_CONTROL1_LOOPBACK
;
5012 val
&= ~XPCS_CONTROL1_LOOPBACK
;
5013 nw64_xpcs(XPCS_CONTROL1
, val
);
5015 nw64_xpcs(XPCS_DESKEW_ERR_CNT
, 0);
5016 (void) nr64_xpcs(XPCS_SYMERR_CNT01
);
5017 (void) nr64_xpcs(XPCS_SYMERR_CNT23
);
5021 case NIU_FLAGS_XCVR_SERDES
:
5023 niu_pcs_mii_reset(np
);
5024 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5025 nw64_pcs(PCS_DPATH_MODE
, 0);
5030 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
5031 /* 1G RGMII FIBER */
5032 nw64_pcs(PCS_DPATH_MODE
, PCS_DPATH_MODE_MII
);
5033 niu_pcs_mii_reset(np
);
5043 static int niu_reset_tx_xmac(struct niu
*np
)
5045 return niu_set_and_wait_clear_mac(np
, XTXMAC_SW_RST
,
5046 (XTXMAC_SW_RST_REG_RS
|
5047 XTXMAC_SW_RST_SOFT_RST
),
5048 1000, 100, "XTXMAC_SW_RST");
5051 static int niu_reset_tx_bmac(struct niu
*np
)
5055 nw64_mac(BTXMAC_SW_RST
, BTXMAC_SW_RST_RESET
);
5057 while (--limit
>= 0) {
5058 if (!(nr64_mac(BTXMAC_SW_RST
) & BTXMAC_SW_RST_RESET
))
5063 dev_err(np
->device
, PFX
"Port %u TX BMAC would not reset, "
5064 "BTXMAC_SW_RST[%llx]\n",
5066 (unsigned long long) nr64_mac(BTXMAC_SW_RST
));
5073 static int niu_reset_tx_mac(struct niu
*np
)
5075 if (np
->flags
& NIU_FLAGS_XMAC
)
5076 return niu_reset_tx_xmac(np
);
5078 return niu_reset_tx_bmac(np
);
5081 static void niu_init_tx_xmac(struct niu
*np
, u64 min
, u64 max
)
5085 val
= nr64_mac(XMAC_MIN
);
5086 val
&= ~(XMAC_MIN_TX_MIN_PKT_SIZE
|
5087 XMAC_MIN_RX_MIN_PKT_SIZE
);
5088 val
|= (min
<< XMAC_MIN_RX_MIN_PKT_SIZE_SHFT
);
5089 val
|= (min
<< XMAC_MIN_TX_MIN_PKT_SIZE_SHFT
);
5090 nw64_mac(XMAC_MIN
, val
);
5092 nw64_mac(XMAC_MAX
, max
);
5094 nw64_mac(XTXMAC_STAT_MSK
, ~(u64
)0);
5096 val
= nr64_mac(XMAC_IPG
);
5097 if (np
->flags
& NIU_FLAGS_10G
) {
5098 val
&= ~XMAC_IPG_IPG_XGMII
;
5099 val
|= (IPG_12_15_XGMII
<< XMAC_IPG_IPG_XGMII_SHIFT
);
5101 val
&= ~XMAC_IPG_IPG_MII_GMII
;
5102 val
|= (IPG_12_MII_GMII
<< XMAC_IPG_IPG_MII_GMII_SHIFT
);
5104 nw64_mac(XMAC_IPG
, val
);
5106 val
= nr64_mac(XMAC_CONFIG
);
5107 val
&= ~(XMAC_CONFIG_ALWAYS_NO_CRC
|
5108 XMAC_CONFIG_STRETCH_MODE
|
5109 XMAC_CONFIG_VAR_MIN_IPG_EN
|
5110 XMAC_CONFIG_TX_ENABLE
);
5111 nw64_mac(XMAC_CONFIG
, val
);
5113 nw64_mac(TXMAC_FRM_CNT
, 0);
5114 nw64_mac(TXMAC_BYTE_CNT
, 0);
5117 static void niu_init_tx_bmac(struct niu
*np
, u64 min
, u64 max
)
5121 nw64_mac(BMAC_MIN_FRAME
, min
);
5122 nw64_mac(BMAC_MAX_FRAME
, max
);
5124 nw64_mac(BTXMAC_STATUS_MASK
, ~(u64
)0);
5125 nw64_mac(BMAC_CTRL_TYPE
, 0x8808);
5126 nw64_mac(BMAC_PREAMBLE_SIZE
, 7);
5128 val
= nr64_mac(BTXMAC_CONFIG
);
5129 val
&= ~(BTXMAC_CONFIG_FCS_DISABLE
|
5130 BTXMAC_CONFIG_ENABLE
);
5131 nw64_mac(BTXMAC_CONFIG
, val
);
5134 static void niu_init_tx_mac(struct niu
*np
)
5139 if (np
->dev
->mtu
> ETH_DATA_LEN
)
5144 /* The XMAC_MIN register only accepts values for TX min which
5145 * have the low 3 bits cleared.
5147 BUILD_BUG_ON(min
& 0x7);
5149 if (np
->flags
& NIU_FLAGS_XMAC
)
5150 niu_init_tx_xmac(np
, min
, max
);
5152 niu_init_tx_bmac(np
, min
, max
);
5155 static int niu_reset_rx_xmac(struct niu
*np
)
5159 nw64_mac(XRXMAC_SW_RST
,
5160 XRXMAC_SW_RST_REG_RS
| XRXMAC_SW_RST_SOFT_RST
);
5162 while (--limit
>= 0) {
5163 if (!(nr64_mac(XRXMAC_SW_RST
) & (XRXMAC_SW_RST_REG_RS
|
5164 XRXMAC_SW_RST_SOFT_RST
)))
5169 dev_err(np
->device
, PFX
"Port %u RX XMAC would not reset, "
5170 "XRXMAC_SW_RST[%llx]\n",
5172 (unsigned long long) nr64_mac(XRXMAC_SW_RST
));
5179 static int niu_reset_rx_bmac(struct niu
*np
)
5183 nw64_mac(BRXMAC_SW_RST
, BRXMAC_SW_RST_RESET
);
5185 while (--limit
>= 0) {
5186 if (!(nr64_mac(BRXMAC_SW_RST
) & BRXMAC_SW_RST_RESET
))
5191 dev_err(np
->device
, PFX
"Port %u RX BMAC would not reset, "
5192 "BRXMAC_SW_RST[%llx]\n",
5194 (unsigned long long) nr64_mac(BRXMAC_SW_RST
));
5201 static int niu_reset_rx_mac(struct niu
*np
)
5203 if (np
->flags
& NIU_FLAGS_XMAC
)
5204 return niu_reset_rx_xmac(np
);
5206 return niu_reset_rx_bmac(np
);
5209 static void niu_init_rx_xmac(struct niu
*np
)
5211 struct niu_parent
*parent
= np
->parent
;
5212 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5213 int first_rdc_table
= tp
->first_table_num
;
5217 nw64_mac(XMAC_ADD_FILT0
, 0);
5218 nw64_mac(XMAC_ADD_FILT1
, 0);
5219 nw64_mac(XMAC_ADD_FILT2
, 0);
5220 nw64_mac(XMAC_ADD_FILT12_MASK
, 0);
5221 nw64_mac(XMAC_ADD_FILT00_MASK
, 0);
5222 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5223 nw64_mac(XMAC_HASH_TBL(i
), 0);
5224 nw64_mac(XRXMAC_STAT_MSK
, ~(u64
)0);
5225 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5226 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5228 val
= nr64_mac(XMAC_CONFIG
);
5229 val
&= ~(XMAC_CONFIG_RX_MAC_ENABLE
|
5230 XMAC_CONFIG_PROMISCUOUS
|
5231 XMAC_CONFIG_PROMISC_GROUP
|
5232 XMAC_CONFIG_ERR_CHK_DIS
|
5233 XMAC_CONFIG_RX_CRC_CHK_DIS
|
5234 XMAC_CONFIG_RESERVED_MULTICAST
|
5235 XMAC_CONFIG_RX_CODEV_CHK_DIS
|
5236 XMAC_CONFIG_ADDR_FILTER_EN
|
5237 XMAC_CONFIG_RCV_PAUSE_ENABLE
|
5238 XMAC_CONFIG_STRIP_CRC
|
5239 XMAC_CONFIG_PASS_FLOW_CTRL
|
5240 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN
);
5241 val
|= (XMAC_CONFIG_HASH_FILTER_EN
);
5242 nw64_mac(XMAC_CONFIG
, val
);
5244 nw64_mac(RXMAC_BT_CNT
, 0);
5245 nw64_mac(RXMAC_BC_FRM_CNT
, 0);
5246 nw64_mac(RXMAC_MC_FRM_CNT
, 0);
5247 nw64_mac(RXMAC_FRAG_CNT
, 0);
5248 nw64_mac(RXMAC_HIST_CNT1
, 0);
5249 nw64_mac(RXMAC_HIST_CNT2
, 0);
5250 nw64_mac(RXMAC_HIST_CNT3
, 0);
5251 nw64_mac(RXMAC_HIST_CNT4
, 0);
5252 nw64_mac(RXMAC_HIST_CNT5
, 0);
5253 nw64_mac(RXMAC_HIST_CNT6
, 0);
5254 nw64_mac(RXMAC_HIST_CNT7
, 0);
5255 nw64_mac(RXMAC_MPSZER_CNT
, 0);
5256 nw64_mac(RXMAC_CRC_ER_CNT
, 0);
5257 nw64_mac(RXMAC_CD_VIO_CNT
, 0);
5258 nw64_mac(LINK_FAULT_CNT
, 0);
5261 static void niu_init_rx_bmac(struct niu
*np
)
5263 struct niu_parent
*parent
= np
->parent
;
5264 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5265 int first_rdc_table
= tp
->first_table_num
;
5269 nw64_mac(BMAC_ADD_FILT0
, 0);
5270 nw64_mac(BMAC_ADD_FILT1
, 0);
5271 nw64_mac(BMAC_ADD_FILT2
, 0);
5272 nw64_mac(BMAC_ADD_FILT12_MASK
, 0);
5273 nw64_mac(BMAC_ADD_FILT00_MASK
, 0);
5274 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5275 nw64_mac(BMAC_HASH_TBL(i
), 0);
5276 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5277 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5278 nw64_mac(BRXMAC_STATUS_MASK
, ~(u64
)0);
5280 val
= nr64_mac(BRXMAC_CONFIG
);
5281 val
&= ~(BRXMAC_CONFIG_ENABLE
|
5282 BRXMAC_CONFIG_STRIP_PAD
|
5283 BRXMAC_CONFIG_STRIP_FCS
|
5284 BRXMAC_CONFIG_PROMISC
|
5285 BRXMAC_CONFIG_PROMISC_GRP
|
5286 BRXMAC_CONFIG_ADDR_FILT_EN
|
5287 BRXMAC_CONFIG_DISCARD_DIS
);
5288 val
|= (BRXMAC_CONFIG_HASH_FILT_EN
);
5289 nw64_mac(BRXMAC_CONFIG
, val
);
5291 val
= nr64_mac(BMAC_ADDR_CMPEN
);
5292 val
|= BMAC_ADDR_CMPEN_EN0
;
5293 nw64_mac(BMAC_ADDR_CMPEN
, val
);
5296 static void niu_init_rx_mac(struct niu
*np
)
5298 niu_set_primary_mac(np
, np
->dev
->dev_addr
);
5300 if (np
->flags
& NIU_FLAGS_XMAC
)
5301 niu_init_rx_xmac(np
);
5303 niu_init_rx_bmac(np
);
5306 static void niu_enable_tx_xmac(struct niu
*np
, int on
)
5308 u64 val
= nr64_mac(XMAC_CONFIG
);
5311 val
|= XMAC_CONFIG_TX_ENABLE
;
5313 val
&= ~XMAC_CONFIG_TX_ENABLE
;
5314 nw64_mac(XMAC_CONFIG
, val
);
5317 static void niu_enable_tx_bmac(struct niu
*np
, int on
)
5319 u64 val
= nr64_mac(BTXMAC_CONFIG
);
5322 val
|= BTXMAC_CONFIG_ENABLE
;
5324 val
&= ~BTXMAC_CONFIG_ENABLE
;
5325 nw64_mac(BTXMAC_CONFIG
, val
);
5328 static void niu_enable_tx_mac(struct niu
*np
, int on
)
5330 if (np
->flags
& NIU_FLAGS_XMAC
)
5331 niu_enable_tx_xmac(np
, on
);
5333 niu_enable_tx_bmac(np
, on
);
5336 static void niu_enable_rx_xmac(struct niu
*np
, int on
)
5338 u64 val
= nr64_mac(XMAC_CONFIG
);
5340 val
&= ~(XMAC_CONFIG_HASH_FILTER_EN
|
5341 XMAC_CONFIG_PROMISCUOUS
);
5343 if (np
->flags
& NIU_FLAGS_MCAST
)
5344 val
|= XMAC_CONFIG_HASH_FILTER_EN
;
5345 if (np
->flags
& NIU_FLAGS_PROMISC
)
5346 val
|= XMAC_CONFIG_PROMISCUOUS
;
5349 val
|= XMAC_CONFIG_RX_MAC_ENABLE
;
5351 val
&= ~XMAC_CONFIG_RX_MAC_ENABLE
;
5352 nw64_mac(XMAC_CONFIG
, val
);
5355 static void niu_enable_rx_bmac(struct niu
*np
, int on
)
5357 u64 val
= nr64_mac(BRXMAC_CONFIG
);
5359 val
&= ~(BRXMAC_CONFIG_HASH_FILT_EN
|
5360 BRXMAC_CONFIG_PROMISC
);
5362 if (np
->flags
& NIU_FLAGS_MCAST
)
5363 val
|= BRXMAC_CONFIG_HASH_FILT_EN
;
5364 if (np
->flags
& NIU_FLAGS_PROMISC
)
5365 val
|= BRXMAC_CONFIG_PROMISC
;
5368 val
|= BRXMAC_CONFIG_ENABLE
;
5370 val
&= ~BRXMAC_CONFIG_ENABLE
;
5371 nw64_mac(BRXMAC_CONFIG
, val
);
5374 static void niu_enable_rx_mac(struct niu
*np
, int on
)
5376 if (np
->flags
& NIU_FLAGS_XMAC
)
5377 niu_enable_rx_xmac(np
, on
);
5379 niu_enable_rx_bmac(np
, on
);
5382 static int niu_init_mac(struct niu
*np
)
5387 err
= niu_init_pcs(np
);
5391 err
= niu_reset_tx_mac(np
);
5394 niu_init_tx_mac(np
);
5395 err
= niu_reset_rx_mac(np
);
5398 niu_init_rx_mac(np
);
5400 /* This looks hookey but the RX MAC reset we just did will
5401 * undo some of the state we setup in niu_init_tx_mac() so we
5402 * have to call it again. In particular, the RX MAC reset will
5403 * set the XMAC_MAX register back to it's default value.
5405 niu_init_tx_mac(np
);
5406 niu_enable_tx_mac(np
, 1);
5408 niu_enable_rx_mac(np
, 1);
5413 static void niu_stop_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5415 (void) niu_tx_channel_stop(np
, rp
->tx_channel
);
5418 static void niu_stop_tx_channels(struct niu
*np
)
5422 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5423 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5425 niu_stop_one_tx_channel(np
, rp
);
5429 static void niu_reset_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5431 (void) niu_tx_channel_reset(np
, rp
->tx_channel
);
5434 static void niu_reset_tx_channels(struct niu
*np
)
5438 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5439 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5441 niu_reset_one_tx_channel(np
, rp
);
5445 static void niu_stop_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5447 (void) niu_enable_rx_channel(np
, rp
->rx_channel
, 0);
5450 static void niu_stop_rx_channels(struct niu
*np
)
5454 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5455 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5457 niu_stop_one_rx_channel(np
, rp
);
5461 static void niu_reset_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5463 int channel
= rp
->rx_channel
;
5465 (void) niu_rx_channel_reset(np
, channel
);
5466 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_ALL
);
5467 nw64(RX_DMA_CTL_STAT(channel
), 0);
5468 (void) niu_enable_rx_channel(np
, channel
, 0);
5471 static void niu_reset_rx_channels(struct niu
*np
)
5475 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5476 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5478 niu_reset_one_rx_channel(np
, rp
);
5482 static void niu_disable_ipp(struct niu
*np
)
5487 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5488 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5490 while (--limit
>= 0 && (rd
!= wr
)) {
5491 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5492 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5495 (rd
!= 0 && wr
!= 1)) {
5496 dev_err(np
->device
, PFX
"%s: IPP would not quiesce, "
5497 "rd_ptr[%llx] wr_ptr[%llx]\n",
5499 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR
),
5500 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR
));
5503 val
= nr64_ipp(IPP_CFIG
);
5504 val
&= ~(IPP_CFIG_IPP_ENABLE
|
5505 IPP_CFIG_DFIFO_ECC_EN
|
5506 IPP_CFIG_DROP_BAD_CRC
|
5508 nw64_ipp(IPP_CFIG
, val
);
5510 (void) niu_ipp_reset(np
);
5513 static int niu_init_hw(struct niu
*np
)
5517 niudbg(IFUP
, "%s: Initialize TXC\n", np
->dev
->name
);
5518 niu_txc_enable_port(np
, 1);
5519 niu_txc_port_dma_enable(np
, 1);
5520 niu_txc_set_imask(np
, 0);
5522 niudbg(IFUP
, "%s: Initialize TX channels\n", np
->dev
->name
);
5523 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5524 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5526 err
= niu_init_one_tx_channel(np
, rp
);
5531 niudbg(IFUP
, "%s: Initialize RX channels\n", np
->dev
->name
);
5532 err
= niu_init_rx_channels(np
);
5534 goto out_uninit_tx_channels
;
5536 niudbg(IFUP
, "%s: Initialize classifier\n", np
->dev
->name
);
5537 err
= niu_init_classifier_hw(np
);
5539 goto out_uninit_rx_channels
;
5541 niudbg(IFUP
, "%s: Initialize ZCP\n", np
->dev
->name
);
5542 err
= niu_init_zcp(np
);
5544 goto out_uninit_rx_channels
;
5546 niudbg(IFUP
, "%s: Initialize IPP\n", np
->dev
->name
);
5547 err
= niu_init_ipp(np
);
5549 goto out_uninit_rx_channels
;
5551 niudbg(IFUP
, "%s: Initialize MAC\n", np
->dev
->name
);
5552 err
= niu_init_mac(np
);
5554 goto out_uninit_ipp
;
5559 niudbg(IFUP
, "%s: Uninit IPP\n", np
->dev
->name
);
5560 niu_disable_ipp(np
);
5562 out_uninit_rx_channels
:
5563 niudbg(IFUP
, "%s: Uninit RX channels\n", np
->dev
->name
);
5564 niu_stop_rx_channels(np
);
5565 niu_reset_rx_channels(np
);
5567 out_uninit_tx_channels
:
5568 niudbg(IFUP
, "%s: Uninit TX channels\n", np
->dev
->name
);
5569 niu_stop_tx_channels(np
);
5570 niu_reset_tx_channels(np
);
5575 static void niu_stop_hw(struct niu
*np
)
5577 niudbg(IFDOWN
, "%s: Disable interrupts\n", np
->dev
->name
);
5578 niu_enable_interrupts(np
, 0);
5580 niudbg(IFDOWN
, "%s: Disable RX MAC\n", np
->dev
->name
);
5581 niu_enable_rx_mac(np
, 0);
5583 niudbg(IFDOWN
, "%s: Disable IPP\n", np
->dev
->name
);
5584 niu_disable_ipp(np
);
5586 niudbg(IFDOWN
, "%s: Stop TX channels\n", np
->dev
->name
);
5587 niu_stop_tx_channels(np
);
5589 niudbg(IFDOWN
, "%s: Stop RX channels\n", np
->dev
->name
);
5590 niu_stop_rx_channels(np
);
5592 niudbg(IFDOWN
, "%s: Reset TX channels\n", np
->dev
->name
);
5593 niu_reset_tx_channels(np
);
5595 niudbg(IFDOWN
, "%s: Reset RX channels\n", np
->dev
->name
);
5596 niu_reset_rx_channels(np
);
5599 static int niu_request_irq(struct niu
*np
)
5604 for (i
= 0; i
< np
->num_ldg
; i
++) {
5605 struct niu_ldg
*lp
= &np
->ldg
[i
];
5607 err
= request_irq(lp
->irq
, niu_interrupt
,
5608 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
,
5618 for (j
= 0; j
< i
; j
++) {
5619 struct niu_ldg
*lp
= &np
->ldg
[j
];
5621 free_irq(lp
->irq
, lp
);
5626 static void niu_free_irq(struct niu
*np
)
5630 for (i
= 0; i
< np
->num_ldg
; i
++) {
5631 struct niu_ldg
*lp
= &np
->ldg
[i
];
5633 free_irq(lp
->irq
, lp
);
5637 static void niu_enable_napi(struct niu
*np
)
5641 for (i
= 0; i
< np
->num_ldg
; i
++)
5642 napi_enable(&np
->ldg
[i
].napi
);
5645 static void niu_disable_napi(struct niu
*np
)
5649 for (i
= 0; i
< np
->num_ldg
; i
++)
5650 napi_disable(&np
->ldg
[i
].napi
);
5653 static int niu_open(struct net_device
*dev
)
5655 struct niu
*np
= netdev_priv(dev
);
5658 netif_carrier_off(dev
);
5660 err
= niu_alloc_channels(np
);
5664 err
= niu_enable_interrupts(np
, 0);
5666 goto out_free_channels
;
5668 err
= niu_request_irq(np
);
5670 goto out_free_channels
;
5672 niu_enable_napi(np
);
5674 spin_lock_irq(&np
->lock
);
5676 err
= niu_init_hw(np
);
5678 init_timer(&np
->timer
);
5679 np
->timer
.expires
= jiffies
+ HZ
;
5680 np
->timer
.data
= (unsigned long) np
;
5681 np
->timer
.function
= niu_timer
;
5683 err
= niu_enable_interrupts(np
, 1);
5688 spin_unlock_irq(&np
->lock
);
5691 niu_disable_napi(np
);
5695 netif_start_queue(dev
);
5697 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
5698 netif_carrier_on(dev
);
5700 add_timer(&np
->timer
);
5708 niu_free_channels(np
);
5714 static void niu_full_shutdown(struct niu
*np
, struct net_device
*dev
)
5716 cancel_work_sync(&np
->reset_task
);
5718 niu_disable_napi(np
);
5719 netif_stop_queue(dev
);
5721 del_timer_sync(&np
->timer
);
5723 spin_lock_irq(&np
->lock
);
5727 spin_unlock_irq(&np
->lock
);
5730 static int niu_close(struct net_device
*dev
)
5732 struct niu
*np
= netdev_priv(dev
);
5734 niu_full_shutdown(np
, dev
);
5738 niu_free_channels(np
);
5740 niu_handle_led(np
, 0);
5745 static void niu_sync_xmac_stats(struct niu
*np
)
5747 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
5749 mp
->tx_frames
+= nr64_mac(TXMAC_FRM_CNT
);
5750 mp
->tx_bytes
+= nr64_mac(TXMAC_BYTE_CNT
);
5752 mp
->rx_link_faults
+= nr64_mac(LINK_FAULT_CNT
);
5753 mp
->rx_align_errors
+= nr64_mac(RXMAC_ALIGN_ERR_CNT
);
5754 mp
->rx_frags
+= nr64_mac(RXMAC_FRAG_CNT
);
5755 mp
->rx_mcasts
+= nr64_mac(RXMAC_MC_FRM_CNT
);
5756 mp
->rx_bcasts
+= nr64_mac(RXMAC_BC_FRM_CNT
);
5757 mp
->rx_hist_cnt1
+= nr64_mac(RXMAC_HIST_CNT1
);
5758 mp
->rx_hist_cnt2
+= nr64_mac(RXMAC_HIST_CNT2
);
5759 mp
->rx_hist_cnt3
+= nr64_mac(RXMAC_HIST_CNT3
);
5760 mp
->rx_hist_cnt4
+= nr64_mac(RXMAC_HIST_CNT4
);
5761 mp
->rx_hist_cnt5
+= nr64_mac(RXMAC_HIST_CNT5
);
5762 mp
->rx_hist_cnt6
+= nr64_mac(RXMAC_HIST_CNT6
);
5763 mp
->rx_hist_cnt7
+= nr64_mac(RXMAC_HIST_CNT7
);
5764 mp
->rx_octets
+= nr64_mac(RXMAC_BT_CNT
);
5765 mp
->rx_code_violations
+= nr64_mac(RXMAC_CD_VIO_CNT
);
5766 mp
->rx_len_errors
+= nr64_mac(RXMAC_MPSZER_CNT
);
5767 mp
->rx_crc_errors
+= nr64_mac(RXMAC_CRC_ER_CNT
);
5770 static void niu_sync_bmac_stats(struct niu
*np
)
5772 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
5774 mp
->tx_bytes
+= nr64_mac(BTXMAC_BYTE_CNT
);
5775 mp
->tx_frames
+= nr64_mac(BTXMAC_FRM_CNT
);
5777 mp
->rx_frames
+= nr64_mac(BRXMAC_FRAME_CNT
);
5778 mp
->rx_align_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
5779 mp
->rx_crc_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
5780 mp
->rx_len_errors
+= nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT
);
5783 static void niu_sync_mac_stats(struct niu
*np
)
5785 if (np
->flags
& NIU_FLAGS_XMAC
)
5786 niu_sync_xmac_stats(np
);
5788 niu_sync_bmac_stats(np
);
5791 static void niu_get_rx_stats(struct niu
*np
)
5793 unsigned long pkts
, dropped
, errors
, bytes
;
5796 pkts
= dropped
= errors
= bytes
= 0;
5797 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5798 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5800 pkts
+= rp
->rx_packets
;
5801 bytes
+= rp
->rx_bytes
;
5802 dropped
+= rp
->rx_dropped
;
5803 errors
+= rp
->rx_errors
;
5805 np
->net_stats
.rx_packets
= pkts
;
5806 np
->net_stats
.rx_bytes
= bytes
;
5807 np
->net_stats
.rx_dropped
= dropped
;
5808 np
->net_stats
.rx_errors
= errors
;
5811 static void niu_get_tx_stats(struct niu
*np
)
5813 unsigned long pkts
, errors
, bytes
;
5816 pkts
= errors
= bytes
= 0;
5817 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5818 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5820 pkts
+= rp
->tx_packets
;
5821 bytes
+= rp
->tx_bytes
;
5822 errors
+= rp
->tx_errors
;
5824 np
->net_stats
.tx_packets
= pkts
;
5825 np
->net_stats
.tx_bytes
= bytes
;
5826 np
->net_stats
.tx_errors
= errors
;
5829 static struct net_device_stats
*niu_get_stats(struct net_device
*dev
)
5831 struct niu
*np
= netdev_priv(dev
);
5833 niu_get_rx_stats(np
);
5834 niu_get_tx_stats(np
);
5836 return &np
->net_stats
;
5839 static void niu_load_hash_xmac(struct niu
*np
, u16
*hash
)
5843 for (i
= 0; i
< 16; i
++)
5844 nw64_mac(XMAC_HASH_TBL(i
), hash
[i
]);
5847 static void niu_load_hash_bmac(struct niu
*np
, u16
*hash
)
5851 for (i
= 0; i
< 16; i
++)
5852 nw64_mac(BMAC_HASH_TBL(i
), hash
[i
]);
5855 static void niu_load_hash(struct niu
*np
, u16
*hash
)
5857 if (np
->flags
& NIU_FLAGS_XMAC
)
5858 niu_load_hash_xmac(np
, hash
);
5860 niu_load_hash_bmac(np
, hash
);
5863 static void niu_set_rx_mode(struct net_device
*dev
)
5865 struct niu
*np
= netdev_priv(dev
);
5866 int i
, alt_cnt
, err
;
5867 struct dev_addr_list
*addr
;
5868 unsigned long flags
;
5869 u16 hash
[16] = { 0, };
5871 spin_lock_irqsave(&np
->lock
, flags
);
5872 niu_enable_rx_mac(np
, 0);
5874 np
->flags
&= ~(NIU_FLAGS_MCAST
| NIU_FLAGS_PROMISC
);
5875 if (dev
->flags
& IFF_PROMISC
)
5876 np
->flags
|= NIU_FLAGS_PROMISC
;
5877 if ((dev
->flags
& IFF_ALLMULTI
) || (dev
->mc_count
> 0))
5878 np
->flags
|= NIU_FLAGS_MCAST
;
5880 alt_cnt
= dev
->uc_count
;
5881 if (alt_cnt
> niu_num_alt_addr(np
)) {
5883 np
->flags
|= NIU_FLAGS_PROMISC
;
5889 for (addr
= dev
->uc_list
; addr
; addr
= addr
->next
) {
5890 err
= niu_set_alt_mac(np
, index
,
5893 printk(KERN_WARNING PFX
"%s: Error %d "
5894 "adding alt mac %d\n",
5895 dev
->name
, err
, index
);
5896 err
= niu_enable_alt_mac(np
, index
, 1);
5898 printk(KERN_WARNING PFX
"%s: Error %d "
5899 "enabling alt mac %d\n",
5900 dev
->name
, err
, index
);
5906 if (np
->flags
& NIU_FLAGS_XMAC
)
5910 for (i
= alt_start
; i
< niu_num_alt_addr(np
); i
++) {
5911 err
= niu_enable_alt_mac(np
, i
, 0);
5913 printk(KERN_WARNING PFX
"%s: Error %d "
5914 "disabling alt mac %d\n",
5918 if (dev
->flags
& IFF_ALLMULTI
) {
5919 for (i
= 0; i
< 16; i
++)
5921 } else if (dev
->mc_count
> 0) {
5922 for (addr
= dev
->mc_list
; addr
; addr
= addr
->next
) {
5923 u32 crc
= ether_crc_le(ETH_ALEN
, addr
->da_addr
);
5926 hash
[crc
>> 4] |= (1 << (15 - (crc
& 0xf)));
5930 if (np
->flags
& NIU_FLAGS_MCAST
)
5931 niu_load_hash(np
, hash
);
5933 niu_enable_rx_mac(np
, 1);
5934 spin_unlock_irqrestore(&np
->lock
, flags
);
5937 static int niu_set_mac_addr(struct net_device
*dev
, void *p
)
5939 struct niu
*np
= netdev_priv(dev
);
5940 struct sockaddr
*addr
= p
;
5941 unsigned long flags
;
5943 if (!is_valid_ether_addr(addr
->sa_data
))
5946 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
5948 if (!netif_running(dev
))
5951 spin_lock_irqsave(&np
->lock
, flags
);
5952 niu_enable_rx_mac(np
, 0);
5953 niu_set_primary_mac(np
, dev
->dev_addr
);
5954 niu_enable_rx_mac(np
, 1);
5955 spin_unlock_irqrestore(&np
->lock
, flags
);
5960 static int niu_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
5965 static void niu_netif_stop(struct niu
*np
)
5967 np
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
5969 niu_disable_napi(np
);
5971 netif_tx_disable(np
->dev
);
5974 static void niu_netif_start(struct niu
*np
)
5976 /* NOTE: unconditional netif_wake_queue is only appropriate
5977 * so long as all callers are assured to have free tx slots
5978 * (such as after niu_init_hw).
5980 netif_wake_queue(np
->dev
);
5982 niu_enable_napi(np
);
5984 niu_enable_interrupts(np
, 1);
5987 static void niu_reset_task(struct work_struct
*work
)
5989 struct niu
*np
= container_of(work
, struct niu
, reset_task
);
5990 unsigned long flags
;
5993 spin_lock_irqsave(&np
->lock
, flags
);
5994 if (!netif_running(np
->dev
)) {
5995 spin_unlock_irqrestore(&np
->lock
, flags
);
5999 spin_unlock_irqrestore(&np
->lock
, flags
);
6001 del_timer_sync(&np
->timer
);
6005 spin_lock_irqsave(&np
->lock
, flags
);
6009 err
= niu_init_hw(np
);
6011 np
->timer
.expires
= jiffies
+ HZ
;
6012 add_timer(&np
->timer
);
6013 niu_netif_start(np
);
6016 spin_unlock_irqrestore(&np
->lock
, flags
);
6019 static void niu_tx_timeout(struct net_device
*dev
)
6021 struct niu
*np
= netdev_priv(dev
);
6023 dev_err(np
->device
, PFX
"%s: Transmit timed out, resetting\n",
6026 schedule_work(&np
->reset_task
);
6029 static void niu_set_txd(struct tx_ring_info
*rp
, int index
,
6030 u64 mapping
, u64 len
, u64 mark
,
6033 __le64
*desc
= &rp
->descr
[index
];
6035 *desc
= cpu_to_le64(mark
|
6036 (n_frags
<< TX_DESC_NUM_PTR_SHIFT
) |
6037 (len
<< TX_DESC_TR_LEN_SHIFT
) |
6038 (mapping
& TX_DESC_SAD
));
6041 static u64
niu_compute_tx_flags(struct sk_buff
*skb
, struct ethhdr
*ehdr
,
6042 u64 pad_bytes
, u64 len
)
6044 u16 eth_proto
, eth_proto_inner
;
6045 u64 csum_bits
, l3off
, ihl
, ret
;
6049 eth_proto
= be16_to_cpu(ehdr
->h_proto
);
6050 eth_proto_inner
= eth_proto
;
6051 if (eth_proto
== ETH_P_8021Q
) {
6052 struct vlan_ethhdr
*vp
= (struct vlan_ethhdr
*) ehdr
;
6053 __be16 val
= vp
->h_vlan_encapsulated_proto
;
6055 eth_proto_inner
= be16_to_cpu(val
);
6059 switch (skb
->protocol
) {
6060 case __constant_htons(ETH_P_IP
):
6061 ip_proto
= ip_hdr(skb
)->protocol
;
6062 ihl
= ip_hdr(skb
)->ihl
;
6064 case __constant_htons(ETH_P_IPV6
):
6065 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
6074 csum_bits
= TXHDR_CSUM_NONE
;
6075 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6078 csum_bits
= (ip_proto
== IPPROTO_TCP
?
6080 (ip_proto
== IPPROTO_UDP
?
6081 TXHDR_CSUM_UDP
: TXHDR_CSUM_SCTP
));
6083 start
= skb_transport_offset(skb
) -
6084 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6085 stuff
= start
+ skb
->csum_offset
;
6087 csum_bits
|= (start
/ 2) << TXHDR_L4START_SHIFT
;
6088 csum_bits
|= (stuff
/ 2) << TXHDR_L4STUFF_SHIFT
;
6091 l3off
= skb_network_offset(skb
) -
6092 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6094 ret
= (((pad_bytes
/ 2) << TXHDR_PAD_SHIFT
) |
6095 (len
<< TXHDR_LEN_SHIFT
) |
6096 ((l3off
/ 2) << TXHDR_L3START_SHIFT
) |
6097 (ihl
<< TXHDR_IHL_SHIFT
) |
6098 ((eth_proto_inner
< 1536) ? TXHDR_LLC
: 0) |
6099 ((eth_proto
== ETH_P_8021Q
) ? TXHDR_VLAN
: 0) |
6100 (ipv6
? TXHDR_IP_VER
: 0) |
6106 static struct tx_ring_info
*tx_ring_select(struct niu
*np
, struct sk_buff
*skb
)
6108 return &np
->tx_rings
[0];
6111 static int niu_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
6113 struct niu
*np
= netdev_priv(dev
);
6114 unsigned long align
, headroom
;
6115 struct tx_ring_info
*rp
;
6116 struct tx_pkt_hdr
*tp
;
6117 unsigned int len
, nfg
;
6118 struct ethhdr
*ehdr
;
6122 rp
= tx_ring_select(np
, skb
);
6124 if (niu_tx_avail(rp
) <= (skb_shinfo(skb
)->nr_frags
+ 1)) {
6125 netif_stop_queue(dev
);
6126 dev_err(np
->device
, PFX
"%s: BUG! Tx ring full when "
6127 "queue awake!\n", dev
->name
);
6129 return NETDEV_TX_BUSY
;
6132 if (skb
->len
< ETH_ZLEN
) {
6133 unsigned int pad_bytes
= ETH_ZLEN
- skb
->len
;
6135 if (skb_pad(skb
, pad_bytes
))
6137 skb_put(skb
, pad_bytes
);
6140 len
= sizeof(struct tx_pkt_hdr
) + 15;
6141 if (skb_headroom(skb
) < len
) {
6142 struct sk_buff
*skb_new
;
6144 skb_new
= skb_realloc_headroom(skb
, len
);
6154 align
= ((unsigned long) skb
->data
& (16 - 1));
6155 headroom
= align
+ sizeof(struct tx_pkt_hdr
);
6157 ehdr
= (struct ethhdr
*) skb
->data
;
6158 tp
= (struct tx_pkt_hdr
*) skb_push(skb
, headroom
);
6160 len
= skb
->len
- sizeof(struct tx_pkt_hdr
);
6161 tp
->flags
= cpu_to_le64(niu_compute_tx_flags(skb
, ehdr
, align
, len
));
6164 len
= skb_headlen(skb
);
6165 mapping
= np
->ops
->map_single(np
->device
, skb
->data
,
6166 len
, DMA_TO_DEVICE
);
6170 rp
->tx_buffs
[prod
].skb
= skb
;
6171 rp
->tx_buffs
[prod
].mapping
= mapping
;
6174 if (++rp
->mark_counter
== rp
->mark_freq
) {
6175 rp
->mark_counter
= 0;
6176 mrk
|= TX_DESC_MARK
;
6181 nfg
= skb_shinfo(skb
)->nr_frags
;
6183 tlen
-= MAX_TX_DESC_LEN
;
6188 unsigned int this_len
= len
;
6190 if (this_len
> MAX_TX_DESC_LEN
)
6191 this_len
= MAX_TX_DESC_LEN
;
6193 niu_set_txd(rp
, prod
, mapping
, this_len
, mrk
, nfg
);
6196 prod
= NEXT_TX(rp
, prod
);
6197 mapping
+= this_len
;
6201 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
6202 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6205 mapping
= np
->ops
->map_page(np
->device
, frag
->page
,
6206 frag
->page_offset
, len
,
6209 rp
->tx_buffs
[prod
].skb
= NULL
;
6210 rp
->tx_buffs
[prod
].mapping
= mapping
;
6212 niu_set_txd(rp
, prod
, mapping
, len
, 0, 0);
6214 prod
= NEXT_TX(rp
, prod
);
6217 if (prod
< rp
->prod
)
6218 rp
->wrap_bit
^= TX_RING_KICK_WRAP
;
6221 nw64(TX_RING_KICK(rp
->tx_channel
), rp
->wrap_bit
| (prod
<< 3));
6223 if (unlikely(niu_tx_avail(rp
) <= (MAX_SKB_FRAGS
+ 1))) {
6224 netif_stop_queue(dev
);
6225 if (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
))
6226 netif_wake_queue(dev
);
6229 dev
->trans_start
= jiffies
;
6232 return NETDEV_TX_OK
;
6240 static int niu_change_mtu(struct net_device
*dev
, int new_mtu
)
6242 struct niu
*np
= netdev_priv(dev
);
6243 int err
, orig_jumbo
, new_jumbo
;
6245 if (new_mtu
< 68 || new_mtu
> NIU_MAX_MTU
)
6248 orig_jumbo
= (dev
->mtu
> ETH_DATA_LEN
);
6249 new_jumbo
= (new_mtu
> ETH_DATA_LEN
);
6253 if (!netif_running(dev
) ||
6254 (orig_jumbo
== new_jumbo
))
6257 niu_full_shutdown(np
, dev
);
6259 niu_free_channels(np
);
6261 niu_enable_napi(np
);
6263 err
= niu_alloc_channels(np
);
6267 spin_lock_irq(&np
->lock
);
6269 err
= niu_init_hw(np
);
6271 init_timer(&np
->timer
);
6272 np
->timer
.expires
= jiffies
+ HZ
;
6273 np
->timer
.data
= (unsigned long) np
;
6274 np
->timer
.function
= niu_timer
;
6276 err
= niu_enable_interrupts(np
, 1);
6281 spin_unlock_irq(&np
->lock
);
6284 netif_start_queue(dev
);
6285 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6286 netif_carrier_on(dev
);
6288 add_timer(&np
->timer
);
6294 static void niu_get_drvinfo(struct net_device
*dev
,
6295 struct ethtool_drvinfo
*info
)
6297 struct niu
*np
= netdev_priv(dev
);
6298 struct niu_vpd
*vpd
= &np
->vpd
;
6300 strcpy(info
->driver
, DRV_MODULE_NAME
);
6301 strcpy(info
->version
, DRV_MODULE_VERSION
);
6302 sprintf(info
->fw_version
, "%d.%d",
6303 vpd
->fcode_major
, vpd
->fcode_minor
);
6304 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
)
6305 strcpy(info
->bus_info
, pci_name(np
->pdev
));
6308 static int niu_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6310 struct niu
*np
= netdev_priv(dev
);
6311 struct niu_link_config
*lp
;
6313 lp
= &np
->link_config
;
6315 memset(cmd
, 0, sizeof(*cmd
));
6316 cmd
->phy_address
= np
->phy_addr
;
6317 cmd
->supported
= lp
->supported
;
6318 cmd
->advertising
= lp
->advertising
;
6319 cmd
->autoneg
= lp
->autoneg
;
6320 cmd
->speed
= lp
->active_speed
;
6321 cmd
->duplex
= lp
->active_duplex
;
6326 static int niu_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6331 static u32
niu_get_msglevel(struct net_device
*dev
)
6333 struct niu
*np
= netdev_priv(dev
);
6334 return np
->msg_enable
;
6337 static void niu_set_msglevel(struct net_device
*dev
, u32 value
)
6339 struct niu
*np
= netdev_priv(dev
);
6340 np
->msg_enable
= value
;
6343 static int niu_get_eeprom_len(struct net_device
*dev
)
6345 struct niu
*np
= netdev_priv(dev
);
6347 return np
->eeprom_len
;
6350 static int niu_get_eeprom(struct net_device
*dev
,
6351 struct ethtool_eeprom
*eeprom
, u8
*data
)
6353 struct niu
*np
= netdev_priv(dev
);
6354 u32 offset
, len
, val
;
6356 offset
= eeprom
->offset
;
6359 if (offset
+ len
< offset
)
6361 if (offset
>= np
->eeprom_len
)
6363 if (offset
+ len
> np
->eeprom_len
)
6364 len
= eeprom
->len
= np
->eeprom_len
- offset
;
6367 u32 b_offset
, b_count
;
6369 b_offset
= offset
& 3;
6370 b_count
= 4 - b_offset
;
6374 val
= nr64(ESPC_NCR((offset
- b_offset
) / 4));
6375 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
6381 val
= nr64(ESPC_NCR(offset
/ 4));
6382 memcpy(data
, &val
, 4);
6388 val
= nr64(ESPC_NCR(offset
/ 4));
6389 memcpy(data
, &val
, len
);
6394 static const struct {
6395 const char string
[ETH_GSTRING_LEN
];
6396 } niu_xmac_stat_keys
[] = {
6399 { "tx_fifo_errors" },
6400 { "tx_overflow_errors" },
6401 { "tx_max_pkt_size_errors" },
6402 { "tx_underflow_errors" },
6403 { "rx_local_faults" },
6404 { "rx_remote_faults" },
6405 { "rx_link_faults" },
6406 { "rx_align_errors" },
6418 { "rx_code_violations" },
6419 { "rx_len_errors" },
6420 { "rx_crc_errors" },
6421 { "rx_underflows" },
6423 { "pause_off_state" },
6424 { "pause_on_state" },
6425 { "pause_received" },
6428 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
6430 static const struct {
6431 const char string
[ETH_GSTRING_LEN
];
6432 } niu_bmac_stat_keys
[] = {
6433 { "tx_underflow_errors" },
6434 { "tx_max_pkt_size_errors" },
6439 { "rx_align_errors" },
6440 { "rx_crc_errors" },
6441 { "rx_len_errors" },
6442 { "pause_off_state" },
6443 { "pause_on_state" },
6444 { "pause_received" },
6447 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
6449 static const struct {
6450 const char string
[ETH_GSTRING_LEN
];
6451 } niu_rxchan_stat_keys
[] = {
6459 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
6461 static const struct {
6462 const char string
[ETH_GSTRING_LEN
];
6463 } niu_txchan_stat_keys
[] = {
6470 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
6472 static void niu_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
6474 struct niu
*np
= netdev_priv(dev
);
6477 if (stringset
!= ETH_SS_STATS
)
6480 if (np
->flags
& NIU_FLAGS_XMAC
) {
6481 memcpy(data
, niu_xmac_stat_keys
,
6482 sizeof(niu_xmac_stat_keys
));
6483 data
+= sizeof(niu_xmac_stat_keys
);
6485 memcpy(data
, niu_bmac_stat_keys
,
6486 sizeof(niu_bmac_stat_keys
));
6487 data
+= sizeof(niu_bmac_stat_keys
);
6489 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6490 memcpy(data
, niu_rxchan_stat_keys
,
6491 sizeof(niu_rxchan_stat_keys
));
6492 data
+= sizeof(niu_rxchan_stat_keys
);
6494 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6495 memcpy(data
, niu_txchan_stat_keys
,
6496 sizeof(niu_txchan_stat_keys
));
6497 data
+= sizeof(niu_txchan_stat_keys
);
6501 static int niu_get_stats_count(struct net_device
*dev
)
6503 struct niu
*np
= netdev_priv(dev
);
6505 return ((np
->flags
& NIU_FLAGS_XMAC
?
6506 NUM_XMAC_STAT_KEYS
:
6507 NUM_BMAC_STAT_KEYS
) +
6508 (np
->num_rx_rings
* NUM_RXCHAN_STAT_KEYS
) +
6509 (np
->num_tx_rings
* NUM_TXCHAN_STAT_KEYS
));
6512 static void niu_get_ethtool_stats(struct net_device
*dev
,
6513 struct ethtool_stats
*stats
, u64
*data
)
6515 struct niu
*np
= netdev_priv(dev
);
6518 niu_sync_mac_stats(np
);
6519 if (np
->flags
& NIU_FLAGS_XMAC
) {
6520 memcpy(data
, &np
->mac_stats
.xmac
,
6521 sizeof(struct niu_xmac_stats
));
6522 data
+= (sizeof(struct niu_xmac_stats
) / sizeof(u64
));
6524 memcpy(data
, &np
->mac_stats
.bmac
,
6525 sizeof(struct niu_bmac_stats
));
6526 data
+= (sizeof(struct niu_bmac_stats
) / sizeof(u64
));
6528 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6529 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
6531 data
[0] = rp
->rx_channel
;
6532 data
[1] = rp
->rx_packets
;
6533 data
[2] = rp
->rx_bytes
;
6534 data
[3] = rp
->rx_dropped
;
6535 data
[4] = rp
->rx_errors
;
6538 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6539 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6541 data
[0] = rp
->tx_channel
;
6542 data
[1] = rp
->tx_packets
;
6543 data
[2] = rp
->tx_bytes
;
6544 data
[3] = rp
->tx_errors
;
6549 static u64
niu_led_state_save(struct niu
*np
)
6551 if (np
->flags
& NIU_FLAGS_XMAC
)
6552 return nr64_mac(XMAC_CONFIG
);
6554 return nr64_mac(BMAC_XIF_CONFIG
);
6557 static void niu_led_state_restore(struct niu
*np
, u64 val
)
6559 if (np
->flags
& NIU_FLAGS_XMAC
)
6560 nw64_mac(XMAC_CONFIG
, val
);
6562 nw64_mac(BMAC_XIF_CONFIG
, val
);
6565 static void niu_force_led(struct niu
*np
, int on
)
6569 if (np
->flags
& NIU_FLAGS_XMAC
) {
6571 bit
= XMAC_CONFIG_FORCE_LED_ON
;
6573 reg
= BMAC_XIF_CONFIG
;
6574 bit
= BMAC_XIF_CONFIG_LINK_LED
;
6577 val
= nr64_mac(reg
);
6585 static int niu_phys_id(struct net_device
*dev
, u32 data
)
6587 struct niu
*np
= netdev_priv(dev
);
6591 if (!netif_running(dev
))
6597 orig_led_state
= niu_led_state_save(np
);
6598 for (i
= 0; i
< (data
* 2); i
++) {
6599 int on
= ((i
% 2) == 0);
6601 niu_force_led(np
, on
);
6603 if (msleep_interruptible(500))
6606 niu_led_state_restore(np
, orig_led_state
);
6611 static const struct ethtool_ops niu_ethtool_ops
= {
6612 .get_drvinfo
= niu_get_drvinfo
,
6613 .get_link
= ethtool_op_get_link
,
6614 .get_msglevel
= niu_get_msglevel
,
6615 .set_msglevel
= niu_set_msglevel
,
6616 .get_eeprom_len
= niu_get_eeprom_len
,
6617 .get_eeprom
= niu_get_eeprom
,
6618 .get_settings
= niu_get_settings
,
6619 .set_settings
= niu_set_settings
,
6620 .get_strings
= niu_get_strings
,
6621 .get_stats_count
= niu_get_stats_count
,
6622 .get_ethtool_stats
= niu_get_ethtool_stats
,
6623 .phys_id
= niu_phys_id
,
6626 static int niu_ldg_assign_ldn(struct niu
*np
, struct niu_parent
*parent
,
6629 if (ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
)
6631 if (ldn
< 0 || ldn
> LDN_MAX
)
6634 parent
->ldg_map
[ldn
] = ldg
;
6636 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
) {
6637 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
6638 * the firmware, and we're not supposed to change them.
6639 * Validate the mapping, because if it's wrong we probably
6640 * won't get any interrupts and that's painful to debug.
6642 if (nr64(LDG_NUM(ldn
)) != ldg
) {
6643 dev_err(np
->device
, PFX
"Port %u, mis-matched "
6645 "for ldn %d, should be %d is %llu\n",
6647 (unsigned long long) nr64(LDG_NUM(ldn
)));
6651 nw64(LDG_NUM(ldn
), ldg
);
6656 static int niu_set_ldg_timer_res(struct niu
*np
, int res
)
6658 if (res
< 0 || res
> LDG_TIMER_RES_VAL
)
6662 nw64(LDG_TIMER_RES
, res
);
6667 static int niu_set_ldg_sid(struct niu
*np
, int ldg
, int func
, int vector
)
6669 if ((ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
) ||
6670 (func
< 0 || func
> 3) ||
6671 (vector
< 0 || vector
> 0x1f))
6674 nw64(SID(ldg
), (func
<< SID_FUNC_SHIFT
) | vector
);
6679 static int __devinit
niu_pci_eeprom_read(struct niu
*np
, u32 addr
)
6681 u64 frame
, frame_base
= (ESPC_PIO_STAT_READ_START
|
6682 (addr
<< ESPC_PIO_STAT_ADDR_SHIFT
));
6685 if (addr
> (ESPC_PIO_STAT_ADDR
>> ESPC_PIO_STAT_ADDR_SHIFT
))
6689 nw64(ESPC_PIO_STAT
, frame
);
6693 frame
= nr64(ESPC_PIO_STAT
);
6694 if (frame
& ESPC_PIO_STAT_READ_END
)
6697 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
6698 dev_err(np
->device
, PFX
"EEPROM read timeout frame[%llx]\n",
6699 (unsigned long long) frame
);
6704 nw64(ESPC_PIO_STAT
, frame
);
6708 frame
= nr64(ESPC_PIO_STAT
);
6709 if (frame
& ESPC_PIO_STAT_READ_END
)
6712 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
6713 dev_err(np
->device
, PFX
"EEPROM read timeout frame[%llx]\n",
6714 (unsigned long long) frame
);
6718 frame
= nr64(ESPC_PIO_STAT
);
6719 return (frame
& ESPC_PIO_STAT_DATA
) >> ESPC_PIO_STAT_DATA_SHIFT
;
6722 static int __devinit
niu_pci_eeprom_read16(struct niu
*np
, u32 off
)
6724 int err
= niu_pci_eeprom_read(np
, off
);
6730 err
= niu_pci_eeprom_read(np
, off
+ 1);
6733 val
|= (err
& 0xff);
6738 static int __devinit
niu_pci_eeprom_read16_swp(struct niu
*np
, u32 off
)
6740 int err
= niu_pci_eeprom_read(np
, off
);
6747 err
= niu_pci_eeprom_read(np
, off
+ 1);
6751 val
|= (err
& 0xff) << 8;
6756 static int __devinit
niu_pci_vpd_get_propname(struct niu
*np
,
6763 for (i
= 0; i
< namebuf_len
; i
++) {
6764 int err
= niu_pci_eeprom_read(np
, off
+ i
);
6771 if (i
>= namebuf_len
)
6777 static void __devinit
niu_vpd_parse_version(struct niu
*np
)
6779 struct niu_vpd
*vpd
= &np
->vpd
;
6780 int len
= strlen(vpd
->version
) + 1;
6781 const char *s
= vpd
->version
;
6784 for (i
= 0; i
< len
- 5; i
++) {
6785 if (!strncmp(s
+ i
, "FCode ", 5))
6792 sscanf(s
, "%d.%d", &vpd
->fcode_major
, &vpd
->fcode_minor
);
6794 niudbg(PROBE
, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
6795 vpd
->fcode_major
, vpd
->fcode_minor
);
6796 if (vpd
->fcode_major
> NIU_VPD_MIN_MAJOR
||
6797 (vpd
->fcode_major
== NIU_VPD_MIN_MAJOR
&&
6798 vpd
->fcode_minor
>= NIU_VPD_MIN_MINOR
))
6799 np
->flags
|= NIU_FLAGS_VPD_VALID
;
6802 /* ESPC_PIO_EN_ENABLE must be set */
6803 static int __devinit
niu_pci_vpd_scan_props(struct niu
*np
,
6806 unsigned int found_mask
= 0;
6807 #define FOUND_MASK_MODEL 0x00000001
6808 #define FOUND_MASK_BMODEL 0x00000002
6809 #define FOUND_MASK_VERS 0x00000004
6810 #define FOUND_MASK_MAC 0x00000008
6811 #define FOUND_MASK_NMAC 0x00000010
6812 #define FOUND_MASK_PHY 0x00000020
6813 #define FOUND_MASK_ALL 0x0000003f
6815 niudbg(PROBE
, "VPD_SCAN: start[%x] end[%x]\n",
6817 while (start
< end
) {
6818 int len
, err
, instance
, type
, prop_len
;
6823 if (found_mask
== FOUND_MASK_ALL
) {
6824 niu_vpd_parse_version(np
);
6828 err
= niu_pci_eeprom_read(np
, start
+ 2);
6834 instance
= niu_pci_eeprom_read(np
, start
);
6835 type
= niu_pci_eeprom_read(np
, start
+ 3);
6836 prop_len
= niu_pci_eeprom_read(np
, start
+ 4);
6837 err
= niu_pci_vpd_get_propname(np
, start
+ 5, namebuf
, 64);
6843 if (!strcmp(namebuf
, "model")) {
6844 prop_buf
= np
->vpd
.model
;
6845 max_len
= NIU_VPD_MODEL_MAX
;
6846 found_mask
|= FOUND_MASK_MODEL
;
6847 } else if (!strcmp(namebuf
, "board-model")) {
6848 prop_buf
= np
->vpd
.board_model
;
6849 max_len
= NIU_VPD_BD_MODEL_MAX
;
6850 found_mask
|= FOUND_MASK_BMODEL
;
6851 } else if (!strcmp(namebuf
, "version")) {
6852 prop_buf
= np
->vpd
.version
;
6853 max_len
= NIU_VPD_VERSION_MAX
;
6854 found_mask
|= FOUND_MASK_VERS
;
6855 } else if (!strcmp(namebuf
, "local-mac-address")) {
6856 prop_buf
= np
->vpd
.local_mac
;
6858 found_mask
|= FOUND_MASK_MAC
;
6859 } else if (!strcmp(namebuf
, "num-mac-addresses")) {
6860 prop_buf
= &np
->vpd
.mac_num
;
6862 found_mask
|= FOUND_MASK_NMAC
;
6863 } else if (!strcmp(namebuf
, "phy-type")) {
6864 prop_buf
= np
->vpd
.phy_type
;
6865 max_len
= NIU_VPD_PHY_TYPE_MAX
;
6866 found_mask
|= FOUND_MASK_PHY
;
6869 if (max_len
&& prop_len
> max_len
) {
6870 dev_err(np
->device
, PFX
"Property '%s' length (%d) is "
6871 "too long.\n", namebuf
, prop_len
);
6876 u32 off
= start
+ 5 + err
;
6879 niudbg(PROBE
, "VPD_SCAN: Reading in property [%s] "
6880 "len[%d]\n", namebuf
, prop_len
);
6881 for (i
= 0; i
< prop_len
; i
++)
6882 *prop_buf
++ = niu_pci_eeprom_read(np
, off
+ i
);
6891 /* ESPC_PIO_EN_ENABLE must be set */
6892 static void __devinit
niu_pci_vpd_fetch(struct niu
*np
, u32 start
)
6897 err
= niu_pci_eeprom_read16_swp(np
, start
+ 1);
6903 while (start
+ offset
< ESPC_EEPROM_SIZE
) {
6904 u32 here
= start
+ offset
;
6907 err
= niu_pci_eeprom_read(np
, here
);
6911 err
= niu_pci_eeprom_read16_swp(np
, here
+ 1);
6915 here
= start
+ offset
+ 3;
6916 end
= start
+ offset
+ err
;
6920 err
= niu_pci_vpd_scan_props(np
, here
, end
);
6921 if (err
< 0 || err
== 1)
6926 /* ESPC_PIO_EN_ENABLE must be set */
6927 static u32 __devinit
niu_pci_vpd_offset(struct niu
*np
)
6929 u32 start
= 0, end
= ESPC_EEPROM_SIZE
, ret
;
6932 while (start
< end
) {
6935 /* ROM header signature? */
6936 err
= niu_pci_eeprom_read16(np
, start
+ 0);
6940 /* Apply offset to PCI data structure. */
6941 err
= niu_pci_eeprom_read16(np
, start
+ 23);
6946 /* Check for "PCIR" signature. */
6947 err
= niu_pci_eeprom_read16(np
, start
+ 0);
6950 err
= niu_pci_eeprom_read16(np
, start
+ 2);
6954 /* Check for OBP image type. */
6955 err
= niu_pci_eeprom_read(np
, start
+ 20);
6959 err
= niu_pci_eeprom_read(np
, ret
+ 2);
6963 start
= ret
+ (err
* 512);
6967 err
= niu_pci_eeprom_read16_swp(np
, start
+ 8);
6972 err
= niu_pci_eeprom_read(np
, ret
+ 0);
6982 static int __devinit
niu_phy_type_prop_decode(struct niu
*np
,
6983 const char *phy_prop
)
6985 if (!strcmp(phy_prop
, "mif")) {
6986 /* 1G copper, MII */
6987 np
->flags
&= ~(NIU_FLAGS_FIBER
|
6989 np
->mac_xcvr
= MAC_XCVR_MII
;
6990 } else if (!strcmp(phy_prop
, "xgf")) {
6991 /* 10G fiber, XPCS */
6992 np
->flags
|= (NIU_FLAGS_10G
|
6994 np
->mac_xcvr
= MAC_XCVR_XPCS
;
6995 } else if (!strcmp(phy_prop
, "pcs")) {
6997 np
->flags
&= ~NIU_FLAGS_10G
;
6998 np
->flags
|= NIU_FLAGS_FIBER
;
6999 np
->mac_xcvr
= MAC_XCVR_PCS
;
7000 } else if (!strcmp(phy_prop
, "xgc")) {
7001 /* 10G copper, XPCS */
7002 np
->flags
|= NIU_FLAGS_10G
;
7003 np
->flags
&= ~NIU_FLAGS_FIBER
;
7004 np
->mac_xcvr
= MAC_XCVR_XPCS
;
7011 /* niu board models have a trailing dash version incremented
7012 * with HW rev change. Need to ingnore the dash version while
7013 * checking for match
7015 * for example, for the 10G card the current vpd.board_model
7016 * is 501-5283-04, of which -04 is the dash version and have
7019 static int niu_board_model_match(struct niu
*np
, const char *model
)
7021 return !strncmp(np
->vpd
.board_model
, model
, strlen(model
));
7024 static int niu_pci_vpd_get_nports(struct niu
*np
)
7028 if ((niu_board_model_match(np
, NIU_QGC_LP_BM_STR
)) ||
7029 (niu_board_model_match(np
, NIU_QGC_PEM_BM_STR
)) ||
7030 (niu_board_model_match(np
, NIU_ALONSO_BM_STR
))) {
7032 } else if ((niu_board_model_match(np
, NIU_2XGF_LP_BM_STR
)) ||
7033 (niu_board_model_match(np
, NIU_2XGF_PEM_BM_STR
)) ||
7034 (niu_board_model_match(np
, NIU_FOXXY_BM_STR
)) ||
7035 (niu_board_model_match(np
, NIU_2XGF_MRVL_BM_STR
))) {
7042 static void __devinit
niu_pci_vpd_validate(struct niu
*np
)
7044 struct net_device
*dev
= np
->dev
;
7045 struct niu_vpd
*vpd
= &np
->vpd
;
7048 if (!is_valid_ether_addr(&vpd
->local_mac
[0])) {
7049 dev_err(np
->device
, PFX
"VPD MAC invalid, "
7050 "falling back to SPROM.\n");
7052 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
7056 if (!strcmp(np
->vpd
.model
, "SUNW,CP3220") ||
7057 !strcmp(np
->vpd
.model
, "SUNW,CP3260")) {
7058 np
->flags
|= NIU_FLAGS_10G
;
7059 np
->flags
&= ~NIU_FLAGS_FIBER
;
7060 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
7061 np
->mac_xcvr
= MAC_XCVR_PCS
;
7063 np
->flags
|= NIU_FLAGS_FIBER
;
7064 np
->flags
&= ~NIU_FLAGS_10G
;
7066 if (np
->flags
& NIU_FLAGS_10G
)
7067 np
->mac_xcvr
= MAC_XCVR_XPCS
;
7068 } else if (niu_board_model_match(np
, NIU_FOXXY_BM_STR
)) {
7069 np
->flags
|= (NIU_FLAGS_10G
| NIU_FLAGS_FIBER
|
7070 NIU_FLAGS_HOTPLUG_PHY
);
7071 } else if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
7072 dev_err(np
->device
, PFX
"Illegal phy string [%s].\n",
7074 dev_err(np
->device
, PFX
"Falling back to SPROM.\n");
7075 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
7079 memcpy(dev
->perm_addr
, vpd
->local_mac
, ETH_ALEN
);
7081 val8
= dev
->perm_addr
[5];
7082 dev
->perm_addr
[5] += np
->port
;
7083 if (dev
->perm_addr
[5] < val8
)
7084 dev
->perm_addr
[4]++;
7086 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
7089 static int __devinit
niu_pci_probe_sprom(struct niu
*np
)
7091 struct net_device
*dev
= np
->dev
;
7096 val
= (nr64(ESPC_VER_IMGSZ
) & ESPC_VER_IMGSZ_IMGSZ
);
7097 val
>>= ESPC_VER_IMGSZ_IMGSZ_SHIFT
;
7100 np
->eeprom_len
= len
;
7102 niudbg(PROBE
, "SPROM: Image size %llu\n", (unsigned long long) val
);
7105 for (i
= 0; i
< len
; i
++) {
7106 val
= nr64(ESPC_NCR(i
));
7107 sum
+= (val
>> 0) & 0xff;
7108 sum
+= (val
>> 8) & 0xff;
7109 sum
+= (val
>> 16) & 0xff;
7110 sum
+= (val
>> 24) & 0xff;
7112 niudbg(PROBE
, "SPROM: Checksum %x\n", (int)(sum
& 0xff));
7113 if ((sum
& 0xff) != 0xab) {
7114 dev_err(np
->device
, PFX
"Bad SPROM checksum "
7115 "(%x, should be 0xab)\n", (int) (sum
& 0xff));
7119 val
= nr64(ESPC_PHY_TYPE
);
7122 val8
= (val
& ESPC_PHY_TYPE_PORT0
) >>
7123 ESPC_PHY_TYPE_PORT0_SHIFT
;
7126 val8
= (val
& ESPC_PHY_TYPE_PORT1
) >>
7127 ESPC_PHY_TYPE_PORT1_SHIFT
;
7130 val8
= (val
& ESPC_PHY_TYPE_PORT2
) >>
7131 ESPC_PHY_TYPE_PORT2_SHIFT
;
7134 val8
= (val
& ESPC_PHY_TYPE_PORT3
) >>
7135 ESPC_PHY_TYPE_PORT3_SHIFT
;
7138 dev_err(np
->device
, PFX
"Bogus port number %u\n",
7142 niudbg(PROBE
, "SPROM: PHY type %x\n", val8
);
7145 case ESPC_PHY_TYPE_1G_COPPER
:
7146 /* 1G copper, MII */
7147 np
->flags
&= ~(NIU_FLAGS_FIBER
|
7149 np
->mac_xcvr
= MAC_XCVR_MII
;
7152 case ESPC_PHY_TYPE_1G_FIBER
:
7154 np
->flags
&= ~NIU_FLAGS_10G
;
7155 np
->flags
|= NIU_FLAGS_FIBER
;
7156 np
->mac_xcvr
= MAC_XCVR_PCS
;
7159 case ESPC_PHY_TYPE_10G_COPPER
:
7160 /* 10G copper, XPCS */
7161 np
->flags
|= NIU_FLAGS_10G
;
7162 np
->flags
&= ~NIU_FLAGS_FIBER
;
7163 np
->mac_xcvr
= MAC_XCVR_XPCS
;
7166 case ESPC_PHY_TYPE_10G_FIBER
:
7167 /* 10G fiber, XPCS */
7168 np
->flags
|= (NIU_FLAGS_10G
|
7170 np
->mac_xcvr
= MAC_XCVR_XPCS
;
7174 dev_err(np
->device
, PFX
"Bogus SPROM phy type %u\n", val8
);
7178 val
= nr64(ESPC_MAC_ADDR0
);
7179 niudbg(PROBE
, "SPROM: MAC_ADDR0[%08llx]\n",
7180 (unsigned long long) val
);
7181 dev
->perm_addr
[0] = (val
>> 0) & 0xff;
7182 dev
->perm_addr
[1] = (val
>> 8) & 0xff;
7183 dev
->perm_addr
[2] = (val
>> 16) & 0xff;
7184 dev
->perm_addr
[3] = (val
>> 24) & 0xff;
7186 val
= nr64(ESPC_MAC_ADDR1
);
7187 niudbg(PROBE
, "SPROM: MAC_ADDR1[%08llx]\n",
7188 (unsigned long long) val
);
7189 dev
->perm_addr
[4] = (val
>> 0) & 0xff;
7190 dev
->perm_addr
[5] = (val
>> 8) & 0xff;
7192 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
7193 dev_err(np
->device
, PFX
"SPROM MAC address invalid\n");
7194 dev_err(np
->device
, PFX
"[ \n");
7195 for (i
= 0; i
< 6; i
++)
7196 printk("%02x ", dev
->perm_addr
[i
]);
7201 val8
= dev
->perm_addr
[5];
7202 dev
->perm_addr
[5] += np
->port
;
7203 if (dev
->perm_addr
[5] < val8
)
7204 dev
->perm_addr
[4]++;
7206 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
7208 val
= nr64(ESPC_MOD_STR_LEN
);
7209 niudbg(PROBE
, "SPROM: MOD_STR_LEN[%llu]\n",
7210 (unsigned long long) val
);
7214 for (i
= 0; i
< val
; i
+= 4) {
7215 u64 tmp
= nr64(ESPC_NCR(5 + (i
/ 4)));
7217 np
->vpd
.model
[i
+ 3] = (tmp
>> 0) & 0xff;
7218 np
->vpd
.model
[i
+ 2] = (tmp
>> 8) & 0xff;
7219 np
->vpd
.model
[i
+ 1] = (tmp
>> 16) & 0xff;
7220 np
->vpd
.model
[i
+ 0] = (tmp
>> 24) & 0xff;
7222 np
->vpd
.model
[val
] = '\0';
7224 val
= nr64(ESPC_BD_MOD_STR_LEN
);
7225 niudbg(PROBE
, "SPROM: BD_MOD_STR_LEN[%llu]\n",
7226 (unsigned long long) val
);
7230 for (i
= 0; i
< val
; i
+= 4) {
7231 u64 tmp
= nr64(ESPC_NCR(14 + (i
/ 4)));
7233 np
->vpd
.board_model
[i
+ 3] = (tmp
>> 0) & 0xff;
7234 np
->vpd
.board_model
[i
+ 2] = (tmp
>> 8) & 0xff;
7235 np
->vpd
.board_model
[i
+ 1] = (tmp
>> 16) & 0xff;
7236 np
->vpd
.board_model
[i
+ 0] = (tmp
>> 24) & 0xff;
7238 np
->vpd
.board_model
[val
] = '\0';
7241 nr64(ESPC_NUM_PORTS_MACS
) & ESPC_NUM_PORTS_MACS_VAL
;
7242 niudbg(PROBE
, "SPROM: NUM_PORTS_MACS[%d]\n",
7248 static int __devinit
niu_get_and_validate_port(struct niu
*np
)
7250 struct niu_parent
*parent
= np
->parent
;
7253 np
->flags
|= NIU_FLAGS_XMAC
;
7255 if (!parent
->num_ports
) {
7256 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
7257 parent
->num_ports
= 2;
7259 parent
->num_ports
= niu_pci_vpd_get_nports(np
);
7260 if (!parent
->num_ports
) {
7261 /* Fall back to SPROM as last resort.
7262 * This will fail on most cards.
7264 parent
->num_ports
= nr64(ESPC_NUM_PORTS_MACS
) &
7265 ESPC_NUM_PORTS_MACS_VAL
;
7267 if (!parent
->num_ports
)
7273 niudbg(PROBE
, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
7274 np
->port
, parent
->num_ports
);
7275 if (np
->port
>= parent
->num_ports
)
7281 static int __devinit
phy_record(struct niu_parent
*parent
,
7282 struct phy_probe_info
*p
,
7283 int dev_id_1
, int dev_id_2
, u8 phy_port
,
7286 u32 id
= (dev_id_1
<< 16) | dev_id_2
;
7289 if (dev_id_1
< 0 || dev_id_2
< 0)
7291 if (type
== PHY_TYPE_PMA_PMD
|| type
== PHY_TYPE_PCS
) {
7292 if (((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8704
) &&
7293 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_MRVL88X2011
) &&
7294 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8706
))
7297 if ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM5464R
)
7301 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7303 (type
== PHY_TYPE_PMA_PMD
?
7305 (type
== PHY_TYPE_PCS
?
7309 if (p
->cur
[type
] >= NIU_MAX_PORTS
) {
7310 printk(KERN_ERR PFX
"Too many PHY ports.\n");
7314 p
->phy_id
[type
][idx
] = id
;
7315 p
->phy_port
[type
][idx
] = phy_port
;
7316 p
->cur
[type
] = idx
+ 1;
7320 static int __devinit
port_has_10g(struct phy_probe_info
*p
, int port
)
7324 for (i
= 0; i
< p
->cur
[PHY_TYPE_PMA_PMD
]; i
++) {
7325 if (p
->phy_port
[PHY_TYPE_PMA_PMD
][i
] == port
)
7328 for (i
= 0; i
< p
->cur
[PHY_TYPE_PCS
]; i
++) {
7329 if (p
->phy_port
[PHY_TYPE_PCS
][i
] == port
)
7336 static int __devinit
count_10g_ports(struct phy_probe_info
*p
, int *lowest
)
7342 for (port
= 8; port
< 32; port
++) {
7343 if (port_has_10g(p
, port
)) {
7353 static int __devinit
count_1g_ports(struct phy_probe_info
*p
, int *lowest
)
7356 if (p
->cur
[PHY_TYPE_MII
])
7357 *lowest
= p
->phy_port
[PHY_TYPE_MII
][0];
7359 return p
->cur
[PHY_TYPE_MII
];
7362 static void __devinit
niu_n2_divide_channels(struct niu_parent
*parent
)
7364 int num_ports
= parent
->num_ports
;
7367 for (i
= 0; i
< num_ports
; i
++) {
7368 parent
->rxchan_per_port
[i
] = (16 / num_ports
);
7369 parent
->txchan_per_port
[i
] = (16 / num_ports
);
7371 pr_info(PFX
"niu%d: Port %u [%u RX chans] "
7374 parent
->rxchan_per_port
[i
],
7375 parent
->txchan_per_port
[i
]);
7379 static void __devinit
niu_divide_channels(struct niu_parent
*parent
,
7380 int num_10g
, int num_1g
)
7382 int num_ports
= parent
->num_ports
;
7383 int rx_chans_per_10g
, rx_chans_per_1g
;
7384 int tx_chans_per_10g
, tx_chans_per_1g
;
7385 int i
, tot_rx
, tot_tx
;
7387 if (!num_10g
|| !num_1g
) {
7388 rx_chans_per_10g
= rx_chans_per_1g
=
7389 (NIU_NUM_RXCHAN
/ num_ports
);
7390 tx_chans_per_10g
= tx_chans_per_1g
=
7391 (NIU_NUM_TXCHAN
/ num_ports
);
7393 rx_chans_per_1g
= NIU_NUM_RXCHAN
/ 8;
7394 rx_chans_per_10g
= (NIU_NUM_RXCHAN
-
7395 (rx_chans_per_1g
* num_1g
)) /
7398 tx_chans_per_1g
= NIU_NUM_TXCHAN
/ 6;
7399 tx_chans_per_10g
= (NIU_NUM_TXCHAN
-
7400 (tx_chans_per_1g
* num_1g
)) /
7404 tot_rx
= tot_tx
= 0;
7405 for (i
= 0; i
< num_ports
; i
++) {
7406 int type
= phy_decode(parent
->port_phy
, i
);
7408 if (type
== PORT_TYPE_10G
) {
7409 parent
->rxchan_per_port
[i
] = rx_chans_per_10g
;
7410 parent
->txchan_per_port
[i
] = tx_chans_per_10g
;
7412 parent
->rxchan_per_port
[i
] = rx_chans_per_1g
;
7413 parent
->txchan_per_port
[i
] = tx_chans_per_1g
;
7415 pr_info(PFX
"niu%d: Port %u [%u RX chans] "
7418 parent
->rxchan_per_port
[i
],
7419 parent
->txchan_per_port
[i
]);
7420 tot_rx
+= parent
->rxchan_per_port
[i
];
7421 tot_tx
+= parent
->txchan_per_port
[i
];
7424 if (tot_rx
> NIU_NUM_RXCHAN
) {
7425 printk(KERN_ERR PFX
"niu%d: Too many RX channels (%d), "
7426 "resetting to one per port.\n",
7427 parent
->index
, tot_rx
);
7428 for (i
= 0; i
< num_ports
; i
++)
7429 parent
->rxchan_per_port
[i
] = 1;
7431 if (tot_tx
> NIU_NUM_TXCHAN
) {
7432 printk(KERN_ERR PFX
"niu%d: Too many TX channels (%d), "
7433 "resetting to one per port.\n",
7434 parent
->index
, tot_tx
);
7435 for (i
= 0; i
< num_ports
; i
++)
7436 parent
->txchan_per_port
[i
] = 1;
7438 if (tot_rx
< NIU_NUM_RXCHAN
|| tot_tx
< NIU_NUM_TXCHAN
) {
7439 printk(KERN_WARNING PFX
"niu%d: Driver bug, wasted channels, "
7441 parent
->index
, tot_rx
, tot_tx
);
7445 static void __devinit
niu_divide_rdc_groups(struct niu_parent
*parent
,
7446 int num_10g
, int num_1g
)
7448 int i
, num_ports
= parent
->num_ports
;
7449 int rdc_group
, rdc_groups_per_port
;
7450 int rdc_channel_base
;
7453 rdc_groups_per_port
= NIU_NUM_RDC_TABLES
/ num_ports
;
7455 rdc_channel_base
= 0;
7457 for (i
= 0; i
< num_ports
; i
++) {
7458 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[i
];
7459 int grp
, num_channels
= parent
->rxchan_per_port
[i
];
7460 int this_channel_offset
;
7462 tp
->first_table_num
= rdc_group
;
7463 tp
->num_tables
= rdc_groups_per_port
;
7464 this_channel_offset
= 0;
7465 for (grp
= 0; grp
< tp
->num_tables
; grp
++) {
7466 struct rdc_table
*rt
= &tp
->tables
[grp
];
7469 pr_info(PFX
"niu%d: Port %d RDC tbl(%d) [ ",
7470 parent
->index
, i
, tp
->first_table_num
+ grp
);
7471 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++) {
7472 rt
->rxdma_channel
[slot
] =
7473 rdc_channel_base
+ this_channel_offset
;
7475 printk("%d ", rt
->rxdma_channel
[slot
]);
7477 if (++this_channel_offset
== num_channels
)
7478 this_channel_offset
= 0;
7483 parent
->rdc_default
[i
] = rdc_channel_base
;
7485 rdc_channel_base
+= num_channels
;
7486 rdc_group
+= rdc_groups_per_port
;
7490 static int __devinit
fill_phy_probe_info(struct niu
*np
,
7491 struct niu_parent
*parent
,
7492 struct phy_probe_info
*info
)
7494 unsigned long flags
;
7497 memset(info
, 0, sizeof(*info
));
7499 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
7500 niu_lock_parent(np
, flags
);
7502 for (port
= 8; port
< 32; port
++) {
7503 int dev_id_1
, dev_id_2
;
7505 dev_id_1
= mdio_read(np
, port
,
7506 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID1
);
7507 dev_id_2
= mdio_read(np
, port
,
7508 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID2
);
7509 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
7513 dev_id_1
= mdio_read(np
, port
,
7514 NIU_PCS_DEV_ADDR
, MII_PHYSID1
);
7515 dev_id_2
= mdio_read(np
, port
,
7516 NIU_PCS_DEV_ADDR
, MII_PHYSID2
);
7517 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
7521 dev_id_1
= mii_read(np
, port
, MII_PHYSID1
);
7522 dev_id_2
= mii_read(np
, port
, MII_PHYSID2
);
7523 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
7528 niu_unlock_parent(np
, flags
);
7533 static int __devinit
walk_phys(struct niu
*np
, struct niu_parent
*parent
)
7535 struct phy_probe_info
*info
= &parent
->phy_probe_info
;
7536 int lowest_10g
, lowest_1g
;
7537 int num_10g
, num_1g
;
7541 if (!strcmp(np
->vpd
.model
, "SUNW,CP3220") ||
7542 !strcmp(np
->vpd
.model
, "SUNW,CP3260")) {
7545 parent
->plat_type
= PLAT_TYPE_ATCA_CP3220
;
7546 parent
->num_ports
= 4;
7547 val
= (phy_encode(PORT_TYPE_1G
, 0) |
7548 phy_encode(PORT_TYPE_1G
, 1) |
7549 phy_encode(PORT_TYPE_1G
, 2) |
7550 phy_encode(PORT_TYPE_1G
, 3));
7551 } else if (niu_board_model_match(np
, NIU_FOXXY_BM_STR
)) {
7554 parent
->num_ports
= 2;
7555 val
= (phy_encode(PORT_TYPE_10G
, 0) |
7556 phy_encode(PORT_TYPE_10G
, 1));
7558 err
= fill_phy_probe_info(np
, parent
, info
);
7562 num_10g
= count_10g_ports(info
, &lowest_10g
);
7563 num_1g
= count_1g_ports(info
, &lowest_1g
);
7565 switch ((num_10g
<< 4) | num_1g
) {
7567 if (lowest_1g
== 10)
7568 parent
->plat_type
= PLAT_TYPE_VF_P0
;
7569 else if (lowest_1g
== 26)
7570 parent
->plat_type
= PLAT_TYPE_VF_P1
;
7572 goto unknown_vg_1g_port
;
7576 val
= (phy_encode(PORT_TYPE_10G
, 0) |
7577 phy_encode(PORT_TYPE_10G
, 1) |
7578 phy_encode(PORT_TYPE_1G
, 2) |
7579 phy_encode(PORT_TYPE_1G
, 3));
7583 val
= (phy_encode(PORT_TYPE_10G
, 0) |
7584 phy_encode(PORT_TYPE_10G
, 1));
7588 val
= phy_encode(PORT_TYPE_10G
, np
->port
);
7592 if (lowest_1g
== 10)
7593 parent
->plat_type
= PLAT_TYPE_VF_P0
;
7594 else if (lowest_1g
== 26)
7595 parent
->plat_type
= PLAT_TYPE_VF_P1
;
7597 goto unknown_vg_1g_port
;
7601 if ((lowest_10g
& 0x7) == 0)
7602 val
= (phy_encode(PORT_TYPE_10G
, 0) |
7603 phy_encode(PORT_TYPE_1G
, 1) |
7604 phy_encode(PORT_TYPE_1G
, 2) |
7605 phy_encode(PORT_TYPE_1G
, 3));
7607 val
= (phy_encode(PORT_TYPE_1G
, 0) |
7608 phy_encode(PORT_TYPE_10G
, 1) |
7609 phy_encode(PORT_TYPE_1G
, 2) |
7610 phy_encode(PORT_TYPE_1G
, 3));
7614 if (lowest_1g
== 10)
7615 parent
->plat_type
= PLAT_TYPE_VF_P0
;
7616 else if (lowest_1g
== 26)
7617 parent
->plat_type
= PLAT_TYPE_VF_P1
;
7619 goto unknown_vg_1g_port
;
7621 val
= (phy_encode(PORT_TYPE_1G
, 0) |
7622 phy_encode(PORT_TYPE_1G
, 1) |
7623 phy_encode(PORT_TYPE_1G
, 2) |
7624 phy_encode(PORT_TYPE_1G
, 3));
7628 printk(KERN_ERR PFX
"Unsupported port config "
7635 parent
->port_phy
= val
;
7637 if (parent
->plat_type
== PLAT_TYPE_NIU
)
7638 niu_n2_divide_channels(parent
);
7640 niu_divide_channels(parent
, num_10g
, num_1g
);
7642 niu_divide_rdc_groups(parent
, num_10g
, num_1g
);
7647 printk(KERN_ERR PFX
"Cannot identify platform type, 1gport=%d\n",
7652 static int __devinit
niu_probe_ports(struct niu
*np
)
7654 struct niu_parent
*parent
= np
->parent
;
7657 niudbg(PROBE
, "niu_probe_ports(): port_phy[%08x]\n",
7660 if (parent
->port_phy
== PORT_PHY_UNKNOWN
) {
7661 err
= walk_phys(np
, parent
);
7665 niu_set_ldg_timer_res(np
, 2);
7666 for (i
= 0; i
<= LDN_MAX
; i
++)
7667 niu_ldn_irq_enable(np
, i
, 0);
7670 if (parent
->port_phy
== PORT_PHY_INVALID
)
7676 static int __devinit
niu_classifier_swstate_init(struct niu
*np
)
7678 struct niu_classifier
*cp
= &np
->clas
;
7680 niudbg(PROBE
, "niu_classifier_swstate_init: num_tcam(%d)\n",
7681 np
->parent
->tcam_num_entries
);
7683 cp
->tcam_index
= (u16
) np
->port
;
7684 cp
->h1_init
= 0xffffffff;
7685 cp
->h2_init
= 0xffff;
7687 return fflp_early_init(np
);
7690 static void __devinit
niu_link_config_init(struct niu
*np
)
7692 struct niu_link_config
*lp
= &np
->link_config
;
7694 lp
->advertising
= (ADVERTISED_10baseT_Half
|
7695 ADVERTISED_10baseT_Full
|
7696 ADVERTISED_100baseT_Half
|
7697 ADVERTISED_100baseT_Full
|
7698 ADVERTISED_1000baseT_Half
|
7699 ADVERTISED_1000baseT_Full
|
7700 ADVERTISED_10000baseT_Full
|
7701 ADVERTISED_Autoneg
);
7702 lp
->speed
= lp
->active_speed
= SPEED_INVALID
;
7703 lp
->duplex
= lp
->active_duplex
= DUPLEX_INVALID
;
7705 lp
->loopback_mode
= LOOPBACK_MAC
;
7706 lp
->active_speed
= SPEED_10000
;
7707 lp
->active_duplex
= DUPLEX_FULL
;
7709 lp
->loopback_mode
= LOOPBACK_DISABLED
;
7713 static int __devinit
niu_init_mac_ipp_pcs_base(struct niu
*np
)
7717 np
->mac_regs
= np
->regs
+ XMAC_PORT0_OFF
;
7718 np
->ipp_off
= 0x00000;
7719 np
->pcs_off
= 0x04000;
7720 np
->xpcs_off
= 0x02000;
7724 np
->mac_regs
= np
->regs
+ XMAC_PORT1_OFF
;
7725 np
->ipp_off
= 0x08000;
7726 np
->pcs_off
= 0x0a000;
7727 np
->xpcs_off
= 0x08000;
7731 np
->mac_regs
= np
->regs
+ BMAC_PORT2_OFF
;
7732 np
->ipp_off
= 0x04000;
7733 np
->pcs_off
= 0x0e000;
7734 np
->xpcs_off
= ~0UL;
7738 np
->mac_regs
= np
->regs
+ BMAC_PORT3_OFF
;
7739 np
->ipp_off
= 0x0c000;
7740 np
->pcs_off
= 0x12000;
7741 np
->xpcs_off
= ~0UL;
7745 dev_err(np
->device
, PFX
"Port %u is invalid, cannot "
7746 "compute MAC block offset.\n", np
->port
);
7753 static void __devinit
niu_try_msix(struct niu
*np
, u8
*ldg_num_map
)
7755 struct msix_entry msi_vec
[NIU_NUM_LDG
];
7756 struct niu_parent
*parent
= np
->parent
;
7757 struct pci_dev
*pdev
= np
->pdev
;
7758 int i
, num_irqs
, err
;
7761 first_ldg
= (NIU_NUM_LDG
/ parent
->num_ports
) * np
->port
;
7762 for (i
= 0; i
< (NIU_NUM_LDG
/ parent
->num_ports
); i
++)
7763 ldg_num_map
[i
] = first_ldg
+ i
;
7765 num_irqs
= (parent
->rxchan_per_port
[np
->port
] +
7766 parent
->txchan_per_port
[np
->port
] +
7767 (np
->port
== 0 ? 3 : 1));
7768 BUG_ON(num_irqs
> (NIU_NUM_LDG
/ parent
->num_ports
));
7771 for (i
= 0; i
< num_irqs
; i
++) {
7772 msi_vec
[i
].vector
= 0;
7773 msi_vec
[i
].entry
= i
;
7776 err
= pci_enable_msix(pdev
, msi_vec
, num_irqs
);
7778 np
->flags
&= ~NIU_FLAGS_MSIX
;
7786 np
->flags
|= NIU_FLAGS_MSIX
;
7787 for (i
= 0; i
< num_irqs
; i
++)
7788 np
->ldg
[i
].irq
= msi_vec
[i
].vector
;
7789 np
->num_ldg
= num_irqs
;
7792 static int __devinit
niu_n2_irq_init(struct niu
*np
, u8
*ldg_num_map
)
7794 #ifdef CONFIG_SPARC64
7795 struct of_device
*op
= np
->op
;
7796 const u32
*int_prop
;
7799 int_prop
= of_get_property(op
->node
, "interrupts", NULL
);
7803 for (i
= 0; i
< op
->num_irqs
; i
++) {
7804 ldg_num_map
[i
] = int_prop
[i
];
7805 np
->ldg
[i
].irq
= op
->irqs
[i
];
7808 np
->num_ldg
= op
->num_irqs
;
7816 static int __devinit
niu_ldg_init(struct niu
*np
)
7818 struct niu_parent
*parent
= np
->parent
;
7819 u8 ldg_num_map
[NIU_NUM_LDG
];
7820 int first_chan
, num_chan
;
7821 int i
, err
, ldg_rotor
;
7825 np
->ldg
[0].irq
= np
->dev
->irq
;
7826 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
7827 err
= niu_n2_irq_init(np
, ldg_num_map
);
7831 niu_try_msix(np
, ldg_num_map
);
7834 for (i
= 0; i
< np
->num_ldg
; i
++) {
7835 struct niu_ldg
*lp
= &np
->ldg
[i
];
7837 netif_napi_add(np
->dev
, &lp
->napi
, niu_poll
, 64);
7840 lp
->ldg_num
= ldg_num_map
[i
];
7841 lp
->timer
= 2; /* XXX */
7843 /* On N2 NIU the firmware has setup the SID mappings so they go
7844 * to the correct values that will route the LDG to the proper
7845 * interrupt in the NCU interrupt table.
7847 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
7848 err
= niu_set_ldg_sid(np
, lp
->ldg_num
, port
, i
);
7854 /* We adopt the LDG assignment ordering used by the N2 NIU
7855 * 'interrupt' properties because that simplifies a lot of
7856 * things. This ordering is:
7859 * MIF (if port zero)
7860 * SYSERR (if port zero)
7867 err
= niu_ldg_assign_ldn(np
, parent
, ldg_num_map
[ldg_rotor
],
7873 if (ldg_rotor
== np
->num_ldg
)
7877 err
= niu_ldg_assign_ldn(np
, parent
,
7878 ldg_num_map
[ldg_rotor
],
7884 if (ldg_rotor
== np
->num_ldg
)
7887 err
= niu_ldg_assign_ldn(np
, parent
,
7888 ldg_num_map
[ldg_rotor
],
7894 if (ldg_rotor
== np
->num_ldg
)
7900 for (i
= 0; i
< port
; i
++)
7901 first_chan
+= parent
->rxchan_per_port
[port
];
7902 num_chan
= parent
->rxchan_per_port
[port
];
7904 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
7905 err
= niu_ldg_assign_ldn(np
, parent
,
7906 ldg_num_map
[ldg_rotor
],
7911 if (ldg_rotor
== np
->num_ldg
)
7916 for (i
= 0; i
< port
; i
++)
7917 first_chan
+= parent
->txchan_per_port
[port
];
7918 num_chan
= parent
->txchan_per_port
[port
];
7919 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
7920 err
= niu_ldg_assign_ldn(np
, parent
,
7921 ldg_num_map
[ldg_rotor
],
7926 if (ldg_rotor
== np
->num_ldg
)
7933 static void __devexit
niu_ldg_free(struct niu
*np
)
7935 if (np
->flags
& NIU_FLAGS_MSIX
)
7936 pci_disable_msix(np
->pdev
);
7939 static int __devinit
niu_get_of_props(struct niu
*np
)
7941 #ifdef CONFIG_SPARC64
7942 struct net_device
*dev
= np
->dev
;
7943 struct device_node
*dp
;
7944 const char *phy_type
;
7948 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
7951 dp
= pci_device_to_OF_node(np
->pdev
);
7953 phy_type
= of_get_property(dp
, "phy-type", &prop_len
);
7955 dev_err(np
->device
, PFX
"%s: OF node lacks "
7956 "phy-type property\n",
7961 if (!strcmp(phy_type
, "none"))
7964 strcpy(np
->vpd
.phy_type
, phy_type
);
7966 if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
7967 dev_err(np
->device
, PFX
"%s: Illegal phy string [%s].\n",
7968 dp
->full_name
, np
->vpd
.phy_type
);
7972 mac_addr
= of_get_property(dp
, "local-mac-address", &prop_len
);
7974 dev_err(np
->device
, PFX
"%s: OF node lacks "
7975 "local-mac-address property\n",
7979 if (prop_len
!= dev
->addr_len
) {
7980 dev_err(np
->device
, PFX
"%s: OF MAC address prop len (%d) "
7982 dp
->full_name
, prop_len
);
7984 memcpy(dev
->perm_addr
, mac_addr
, dev
->addr_len
);
7985 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
7988 dev_err(np
->device
, PFX
"%s: OF MAC address is invalid\n",
7990 dev_err(np
->device
, PFX
"%s: [ \n",
7992 for (i
= 0; i
< 6; i
++)
7993 printk("%02x ", dev
->perm_addr
[i
]);
7998 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
8006 static int __devinit
niu_get_invariants(struct niu
*np
)
8008 int err
, have_props
;
8011 err
= niu_get_of_props(np
);
8017 err
= niu_init_mac_ipp_pcs_base(np
);
8022 err
= niu_get_and_validate_port(np
);
8027 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
8030 nw64(ESPC_PIO_EN
, ESPC_PIO_EN_ENABLE
);
8031 offset
= niu_pci_vpd_offset(np
);
8032 niudbg(PROBE
, "niu_get_invariants: VPD offset [%08x]\n",
8035 niu_pci_vpd_fetch(np
, offset
);
8036 nw64(ESPC_PIO_EN
, 0);
8038 if (np
->flags
& NIU_FLAGS_VPD_VALID
) {
8039 niu_pci_vpd_validate(np
);
8040 err
= niu_get_and_validate_port(np
);
8045 if (!(np
->flags
& NIU_FLAGS_VPD_VALID
)) {
8046 err
= niu_get_and_validate_port(np
);
8049 err
= niu_pci_probe_sprom(np
);
8055 err
= niu_probe_ports(np
);
8061 niu_classifier_swstate_init(np
);
8062 niu_link_config_init(np
);
8064 err
= niu_determine_phy_disposition(np
);
8066 err
= niu_init_link(np
);
8071 static LIST_HEAD(niu_parent_list
);
8072 static DEFINE_MUTEX(niu_parent_lock
);
8073 static int niu_parent_index
;
8075 static ssize_t
show_port_phy(struct device
*dev
,
8076 struct device_attribute
*attr
, char *buf
)
8078 struct platform_device
*plat_dev
= to_platform_device(dev
);
8079 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
8080 u32 port_phy
= p
->port_phy
;
8081 char *orig_buf
= buf
;
8084 if (port_phy
== PORT_PHY_UNKNOWN
||
8085 port_phy
== PORT_PHY_INVALID
)
8088 for (i
= 0; i
< p
->num_ports
; i
++) {
8089 const char *type_str
;
8092 type
= phy_decode(port_phy
, i
);
8093 if (type
== PORT_TYPE_10G
)
8098 (i
== 0) ? "%s" : " %s",
8101 buf
+= sprintf(buf
, "\n");
8102 return buf
- orig_buf
;
8105 static ssize_t
show_plat_type(struct device
*dev
,
8106 struct device_attribute
*attr
, char *buf
)
8108 struct platform_device
*plat_dev
= to_platform_device(dev
);
8109 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
8110 const char *type_str
;
8112 switch (p
->plat_type
) {
8113 case PLAT_TYPE_ATLAS
:
8119 case PLAT_TYPE_VF_P0
:
8122 case PLAT_TYPE_VF_P1
:
8126 type_str
= "unknown";
8130 return sprintf(buf
, "%s\n", type_str
);
8133 static ssize_t
__show_chan_per_port(struct device
*dev
,
8134 struct device_attribute
*attr
, char *buf
,
8137 struct platform_device
*plat_dev
= to_platform_device(dev
);
8138 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
8139 char *orig_buf
= buf
;
8143 arr
= (rx
? p
->rxchan_per_port
: p
->txchan_per_port
);
8145 for (i
= 0; i
< p
->num_ports
; i
++) {
8147 (i
== 0) ? "%d" : " %d",
8150 buf
+= sprintf(buf
, "\n");
8152 return buf
- orig_buf
;
8155 static ssize_t
show_rxchan_per_port(struct device
*dev
,
8156 struct device_attribute
*attr
, char *buf
)
8158 return __show_chan_per_port(dev
, attr
, buf
, 1);
8161 static ssize_t
show_txchan_per_port(struct device
*dev
,
8162 struct device_attribute
*attr
, char *buf
)
8164 return __show_chan_per_port(dev
, attr
, buf
, 1);
8167 static ssize_t
show_num_ports(struct device
*dev
,
8168 struct device_attribute
*attr
, char *buf
)
8170 struct platform_device
*plat_dev
= to_platform_device(dev
);
8171 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
8173 return sprintf(buf
, "%d\n", p
->num_ports
);
8176 static struct device_attribute niu_parent_attributes
[] = {
8177 __ATTR(port_phy
, S_IRUGO
, show_port_phy
, NULL
),
8178 __ATTR(plat_type
, S_IRUGO
, show_plat_type
, NULL
),
8179 __ATTR(rxchan_per_port
, S_IRUGO
, show_rxchan_per_port
, NULL
),
8180 __ATTR(txchan_per_port
, S_IRUGO
, show_txchan_per_port
, NULL
),
8181 __ATTR(num_ports
, S_IRUGO
, show_num_ports
, NULL
),
8185 static struct niu_parent
* __devinit
niu_new_parent(struct niu
*np
,
8186 union niu_parent_id
*id
,
8189 struct platform_device
*plat_dev
;
8190 struct niu_parent
*p
;
8193 niudbg(PROBE
, "niu_new_parent: Creating new parent.\n");
8195 plat_dev
= platform_device_register_simple("niu", niu_parent_index
,
8200 for (i
= 0; attr_name(niu_parent_attributes
[i
]); i
++) {
8201 int err
= device_create_file(&plat_dev
->dev
,
8202 &niu_parent_attributes
[i
]);
8204 goto fail_unregister
;
8207 p
= kzalloc(sizeof(*p
), GFP_KERNEL
);
8209 goto fail_unregister
;
8211 p
->index
= niu_parent_index
++;
8213 plat_dev
->dev
.platform_data
= p
;
8214 p
->plat_dev
= plat_dev
;
8216 memcpy(&p
->id
, id
, sizeof(*id
));
8217 p
->plat_type
= ptype
;
8218 INIT_LIST_HEAD(&p
->list
);
8219 atomic_set(&p
->refcnt
, 0);
8220 list_add(&p
->list
, &niu_parent_list
);
8221 spin_lock_init(&p
->lock
);
8223 p
->rxdma_clock_divider
= 7500;
8225 p
->tcam_num_entries
= NIU_PCI_TCAM_ENTRIES
;
8226 if (p
->plat_type
== PLAT_TYPE_NIU
)
8227 p
->tcam_num_entries
= NIU_NONPCI_TCAM_ENTRIES
;
8229 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
8230 int index
= i
- CLASS_CODE_USER_PROG1
;
8232 p
->tcam_key
[index
] = TCAM_KEY_TSEL
;
8233 p
->flow_key
[index
] = (FLOW_KEY_IPSA
|
8236 (FLOW_KEY_L4_BYTE12
<<
8237 FLOW_KEY_L4_0_SHIFT
) |
8238 (FLOW_KEY_L4_BYTE12
<<
8239 FLOW_KEY_L4_1_SHIFT
));
8242 for (i
= 0; i
< LDN_MAX
+ 1; i
++)
8243 p
->ldg_map
[i
] = LDG_INVALID
;
8248 platform_device_unregister(plat_dev
);
8252 static struct niu_parent
* __devinit
niu_get_parent(struct niu
*np
,
8253 union niu_parent_id
*id
,
8256 struct niu_parent
*p
, *tmp
;
8257 int port
= np
->port
;
8259 niudbg(PROBE
, "niu_get_parent: platform_type[%u] port[%u]\n",
8262 mutex_lock(&niu_parent_lock
);
8264 list_for_each_entry(tmp
, &niu_parent_list
, list
) {
8265 if (!memcmp(id
, &tmp
->id
, sizeof(*id
))) {
8271 p
= niu_new_parent(np
, id
, ptype
);
8277 sprintf(port_name
, "port%d", port
);
8278 err
= sysfs_create_link(&p
->plat_dev
->dev
.kobj
,
8282 p
->ports
[port
] = np
;
8283 atomic_inc(&p
->refcnt
);
8286 mutex_unlock(&niu_parent_lock
);
8291 static void niu_put_parent(struct niu
*np
)
8293 struct niu_parent
*p
= np
->parent
;
8297 BUG_ON(!p
|| p
->ports
[port
] != np
);
8299 niudbg(PROBE
, "niu_put_parent: port[%u]\n", port
);
8301 sprintf(port_name
, "port%d", port
);
8303 mutex_lock(&niu_parent_lock
);
8305 sysfs_remove_link(&p
->plat_dev
->dev
.kobj
, port_name
);
8307 p
->ports
[port
] = NULL
;
8310 if (atomic_dec_and_test(&p
->refcnt
)) {
8312 platform_device_unregister(p
->plat_dev
);
8315 mutex_unlock(&niu_parent_lock
);
8318 static void *niu_pci_alloc_coherent(struct device
*dev
, size_t size
,
8319 u64
*handle
, gfp_t flag
)
8324 ret
= dma_alloc_coherent(dev
, size
, &dh
, flag
);
8330 static void niu_pci_free_coherent(struct device
*dev
, size_t size
,
8331 void *cpu_addr
, u64 handle
)
8333 dma_free_coherent(dev
, size
, cpu_addr
, handle
);
8336 static u64
niu_pci_map_page(struct device
*dev
, struct page
*page
,
8337 unsigned long offset
, size_t size
,
8338 enum dma_data_direction direction
)
8340 return dma_map_page(dev
, page
, offset
, size
, direction
);
8343 static void niu_pci_unmap_page(struct device
*dev
, u64 dma_address
,
8344 size_t size
, enum dma_data_direction direction
)
8346 return dma_unmap_page(dev
, dma_address
, size
, direction
);
8349 static u64
niu_pci_map_single(struct device
*dev
, void *cpu_addr
,
8351 enum dma_data_direction direction
)
8353 return dma_map_single(dev
, cpu_addr
, size
, direction
);
8356 static void niu_pci_unmap_single(struct device
*dev
, u64 dma_address
,
8358 enum dma_data_direction direction
)
8360 dma_unmap_single(dev
, dma_address
, size
, direction
);
8363 static const struct niu_ops niu_pci_ops
= {
8364 .alloc_coherent
= niu_pci_alloc_coherent
,
8365 .free_coherent
= niu_pci_free_coherent
,
8366 .map_page
= niu_pci_map_page
,
8367 .unmap_page
= niu_pci_unmap_page
,
8368 .map_single
= niu_pci_map_single
,
8369 .unmap_single
= niu_pci_unmap_single
,
8372 static void __devinit
niu_driver_version(void)
8374 static int niu_version_printed
;
8376 if (niu_version_printed
++ == 0)
8377 pr_info("%s", version
);
8380 static struct net_device
* __devinit
niu_alloc_and_init(
8381 struct device
*gen_dev
, struct pci_dev
*pdev
,
8382 struct of_device
*op
, const struct niu_ops
*ops
,
8385 struct net_device
*dev
= alloc_etherdev(sizeof(struct niu
));
8389 dev_err(gen_dev
, PFX
"Etherdev alloc failed, aborting.\n");
8393 SET_NETDEV_DEV(dev
, gen_dev
);
8395 np
= netdev_priv(dev
);
8399 np
->device
= gen_dev
;
8402 np
->msg_enable
= niu_debug
;
8404 spin_lock_init(&np
->lock
);
8405 INIT_WORK(&np
->reset_task
, niu_reset_task
);
8412 static void __devinit
niu_assign_netdev_ops(struct net_device
*dev
)
8414 dev
->open
= niu_open
;
8415 dev
->stop
= niu_close
;
8416 dev
->get_stats
= niu_get_stats
;
8417 dev
->set_multicast_list
= niu_set_rx_mode
;
8418 dev
->set_mac_address
= niu_set_mac_addr
;
8419 dev
->do_ioctl
= niu_ioctl
;
8420 dev
->tx_timeout
= niu_tx_timeout
;
8421 dev
->hard_start_xmit
= niu_start_xmit
;
8422 dev
->ethtool_ops
= &niu_ethtool_ops
;
8423 dev
->watchdog_timeo
= NIU_TX_TIMEOUT
;
8424 dev
->change_mtu
= niu_change_mtu
;
8427 static void __devinit
niu_device_announce(struct niu
*np
)
8429 struct net_device
*dev
= np
->dev
;
8430 DECLARE_MAC_BUF(mac
);
8432 pr_info("%s: NIU Ethernet %s\n",
8433 dev
->name
, print_mac(mac
, dev
->dev_addr
));
8435 if (np
->parent
->plat_type
== PLAT_TYPE_ATCA_CP3220
) {
8436 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8438 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
8439 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
8440 (np
->flags
& NIU_FLAGS_FIBER
? "RGMII FIBER" : "SERDES"),
8441 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
8442 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
8445 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8447 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
8448 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
8449 (np
->flags
& NIU_FLAGS_FIBER
? "FIBER" : "COPPER"),
8450 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
8451 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
8456 static int __devinit
niu_pci_init_one(struct pci_dev
*pdev
,
8457 const struct pci_device_id
*ent
)
8459 unsigned long niureg_base
, niureg_len
;
8460 union niu_parent_id parent_id
;
8461 struct net_device
*dev
;
8467 niu_driver_version();
8469 err
= pci_enable_device(pdev
);
8471 dev_err(&pdev
->dev
, PFX
"Cannot enable PCI device, "
8476 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
) ||
8477 !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
8478 dev_err(&pdev
->dev
, PFX
"Cannot find proper PCI device "
8479 "base addresses, aborting.\n");
8481 goto err_out_disable_pdev
;
8484 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
8486 dev_err(&pdev
->dev
, PFX
"Cannot obtain PCI resources, "
8488 goto err_out_disable_pdev
;
8491 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
8493 dev_err(&pdev
->dev
, PFX
"Cannot find PCI Express capability, "
8495 goto err_out_free_res
;
8498 dev
= niu_alloc_and_init(&pdev
->dev
, pdev
, NULL
,
8499 &niu_pci_ops
, PCI_FUNC(pdev
->devfn
));
8502 goto err_out_free_res
;
8504 np
= netdev_priv(dev
);
8506 memset(&parent_id
, 0, sizeof(parent_id
));
8507 parent_id
.pci
.domain
= pci_domain_nr(pdev
->bus
);
8508 parent_id
.pci
.bus
= pdev
->bus
->number
;
8509 parent_id
.pci
.device
= PCI_SLOT(pdev
->devfn
);
8511 np
->parent
= niu_get_parent(np
, &parent_id
,
8515 goto err_out_free_dev
;
8518 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, &val16
);
8519 val16
&= ~PCI_EXP_DEVCTL_NOSNOOP_EN
;
8520 val16
|= (PCI_EXP_DEVCTL_CERE
|
8521 PCI_EXP_DEVCTL_NFERE
|
8522 PCI_EXP_DEVCTL_FERE
|
8523 PCI_EXP_DEVCTL_URRE
|
8524 PCI_EXP_DEVCTL_RELAX_EN
);
8525 pci_write_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, val16
);
8527 dma_mask
= DMA_44BIT_MASK
;
8528 err
= pci_set_dma_mask(pdev
, dma_mask
);
8530 dev
->features
|= NETIF_F_HIGHDMA
;
8531 err
= pci_set_consistent_dma_mask(pdev
, dma_mask
);
8533 dev_err(&pdev
->dev
, PFX
"Unable to obtain 44 bit "
8534 "DMA for consistent allocations, "
8536 goto err_out_release_parent
;
8539 if (err
|| dma_mask
== DMA_32BIT_MASK
) {
8540 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
8542 dev_err(&pdev
->dev
, PFX
"No usable DMA configuration, "
8544 goto err_out_release_parent
;
8548 dev
->features
|= (NETIF_F_SG
| NETIF_F_HW_CSUM
);
8550 niureg_base
= pci_resource_start(pdev
, 0);
8551 niureg_len
= pci_resource_len(pdev
, 0);
8553 np
->regs
= ioremap_nocache(niureg_base
, niureg_len
);
8555 dev_err(&pdev
->dev
, PFX
"Cannot map device registers, "
8558 goto err_out_release_parent
;
8561 pci_set_master(pdev
);
8562 pci_save_state(pdev
);
8564 dev
->irq
= pdev
->irq
;
8566 niu_assign_netdev_ops(dev
);
8568 err
= niu_get_invariants(np
);
8571 dev_err(&pdev
->dev
, PFX
"Problem fetching invariants "
8572 "of chip, aborting.\n");
8573 goto err_out_iounmap
;
8576 err
= register_netdev(dev
);
8578 dev_err(&pdev
->dev
, PFX
"Cannot register net device, "
8580 goto err_out_iounmap
;
8583 pci_set_drvdata(pdev
, dev
);
8585 niu_device_announce(np
);
8595 err_out_release_parent
:
8602 pci_release_regions(pdev
);
8604 err_out_disable_pdev
:
8605 pci_disable_device(pdev
);
8606 pci_set_drvdata(pdev
, NULL
);
8611 static void __devexit
niu_pci_remove_one(struct pci_dev
*pdev
)
8613 struct net_device
*dev
= pci_get_drvdata(pdev
);
8616 struct niu
*np
= netdev_priv(dev
);
8618 unregister_netdev(dev
);
8629 pci_release_regions(pdev
);
8630 pci_disable_device(pdev
);
8631 pci_set_drvdata(pdev
, NULL
);
8635 static int niu_suspend(struct pci_dev
*pdev
, pm_message_t state
)
8637 struct net_device
*dev
= pci_get_drvdata(pdev
);
8638 struct niu
*np
= netdev_priv(dev
);
8639 unsigned long flags
;
8641 if (!netif_running(dev
))
8644 flush_scheduled_work();
8647 del_timer_sync(&np
->timer
);
8649 spin_lock_irqsave(&np
->lock
, flags
);
8650 niu_enable_interrupts(np
, 0);
8651 spin_unlock_irqrestore(&np
->lock
, flags
);
8653 netif_device_detach(dev
);
8655 spin_lock_irqsave(&np
->lock
, flags
);
8657 spin_unlock_irqrestore(&np
->lock
, flags
);
8659 pci_save_state(pdev
);
8664 static int niu_resume(struct pci_dev
*pdev
)
8666 struct net_device
*dev
= pci_get_drvdata(pdev
);
8667 struct niu
*np
= netdev_priv(dev
);
8668 unsigned long flags
;
8671 if (!netif_running(dev
))
8674 pci_restore_state(pdev
);
8676 netif_device_attach(dev
);
8678 spin_lock_irqsave(&np
->lock
, flags
);
8680 err
= niu_init_hw(np
);
8682 np
->timer
.expires
= jiffies
+ HZ
;
8683 add_timer(&np
->timer
);
8684 niu_netif_start(np
);
8687 spin_unlock_irqrestore(&np
->lock
, flags
);
8692 static struct pci_driver niu_pci_driver
= {
8693 .name
= DRV_MODULE_NAME
,
8694 .id_table
= niu_pci_tbl
,
8695 .probe
= niu_pci_init_one
,
8696 .remove
= __devexit_p(niu_pci_remove_one
),
8697 .suspend
= niu_suspend
,
8698 .resume
= niu_resume
,
8701 #ifdef CONFIG_SPARC64
8702 static void *niu_phys_alloc_coherent(struct device
*dev
, size_t size
,
8703 u64
*dma_addr
, gfp_t flag
)
8705 unsigned long order
= get_order(size
);
8706 unsigned long page
= __get_free_pages(flag
, order
);
8710 memset((char *)page
, 0, PAGE_SIZE
<< order
);
8711 *dma_addr
= __pa(page
);
8713 return (void *) page
;
8716 static void niu_phys_free_coherent(struct device
*dev
, size_t size
,
8717 void *cpu_addr
, u64 handle
)
8719 unsigned long order
= get_order(size
);
8721 free_pages((unsigned long) cpu_addr
, order
);
8724 static u64
niu_phys_map_page(struct device
*dev
, struct page
*page
,
8725 unsigned long offset
, size_t size
,
8726 enum dma_data_direction direction
)
8728 return page_to_phys(page
) + offset
;
8731 static void niu_phys_unmap_page(struct device
*dev
, u64 dma_address
,
8732 size_t size
, enum dma_data_direction direction
)
8734 /* Nothing to do. */
8737 static u64
niu_phys_map_single(struct device
*dev
, void *cpu_addr
,
8739 enum dma_data_direction direction
)
8741 return __pa(cpu_addr
);
8744 static void niu_phys_unmap_single(struct device
*dev
, u64 dma_address
,
8746 enum dma_data_direction direction
)
8748 /* Nothing to do. */
8751 static const struct niu_ops niu_phys_ops
= {
8752 .alloc_coherent
= niu_phys_alloc_coherent
,
8753 .free_coherent
= niu_phys_free_coherent
,
8754 .map_page
= niu_phys_map_page
,
8755 .unmap_page
= niu_phys_unmap_page
,
8756 .map_single
= niu_phys_map_single
,
8757 .unmap_single
= niu_phys_unmap_single
,
8760 static unsigned long res_size(struct resource
*r
)
8762 return r
->end
- r
->start
+ 1UL;
8765 static int __devinit
niu_of_probe(struct of_device
*op
,
8766 const struct of_device_id
*match
)
8768 union niu_parent_id parent_id
;
8769 struct net_device
*dev
;
8774 niu_driver_version();
8776 reg
= of_get_property(op
->node
, "reg", NULL
);
8778 dev_err(&op
->dev
, PFX
"%s: No 'reg' property, aborting.\n",
8779 op
->node
->full_name
);
8783 dev
= niu_alloc_and_init(&op
->dev
, NULL
, op
,
8784 &niu_phys_ops
, reg
[0] & 0x1);
8789 np
= netdev_priv(dev
);
8791 memset(&parent_id
, 0, sizeof(parent_id
));
8792 parent_id
.of
= of_get_parent(op
->node
);
8794 np
->parent
= niu_get_parent(np
, &parent_id
,
8798 goto err_out_free_dev
;
8801 dev
->features
|= (NETIF_F_SG
| NETIF_F_HW_CSUM
);
8803 np
->regs
= of_ioremap(&op
->resource
[1], 0,
8804 res_size(&op
->resource
[1]),
8807 dev_err(&op
->dev
, PFX
"Cannot map device registers, "
8810 goto err_out_release_parent
;
8813 np
->vir_regs_1
= of_ioremap(&op
->resource
[2], 0,
8814 res_size(&op
->resource
[2]),
8816 if (!np
->vir_regs_1
) {
8817 dev_err(&op
->dev
, PFX
"Cannot map device vir registers 1, "
8820 goto err_out_iounmap
;
8823 np
->vir_regs_2
= of_ioremap(&op
->resource
[3], 0,
8824 res_size(&op
->resource
[3]),
8826 if (!np
->vir_regs_2
) {
8827 dev_err(&op
->dev
, PFX
"Cannot map device vir registers 2, "
8830 goto err_out_iounmap
;
8833 niu_assign_netdev_ops(dev
);
8835 err
= niu_get_invariants(np
);
8838 dev_err(&op
->dev
, PFX
"Problem fetching invariants "
8839 "of chip, aborting.\n");
8840 goto err_out_iounmap
;
8843 err
= register_netdev(dev
);
8845 dev_err(&op
->dev
, PFX
"Cannot register net device, "
8847 goto err_out_iounmap
;
8850 dev_set_drvdata(&op
->dev
, dev
);
8852 niu_device_announce(np
);
8857 if (np
->vir_regs_1
) {
8858 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
8859 res_size(&op
->resource
[2]));
8860 np
->vir_regs_1
= NULL
;
8863 if (np
->vir_regs_2
) {
8864 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
8865 res_size(&op
->resource
[3]));
8866 np
->vir_regs_2
= NULL
;
8870 of_iounmap(&op
->resource
[1], np
->regs
,
8871 res_size(&op
->resource
[1]));
8875 err_out_release_parent
:
8885 static int __devexit
niu_of_remove(struct of_device
*op
)
8887 struct net_device
*dev
= dev_get_drvdata(&op
->dev
);
8890 struct niu
*np
= netdev_priv(dev
);
8892 unregister_netdev(dev
);
8894 if (np
->vir_regs_1
) {
8895 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
8896 res_size(&op
->resource
[2]));
8897 np
->vir_regs_1
= NULL
;
8900 if (np
->vir_regs_2
) {
8901 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
8902 res_size(&op
->resource
[3]));
8903 np
->vir_regs_2
= NULL
;
8907 of_iounmap(&op
->resource
[1], np
->regs
,
8908 res_size(&op
->resource
[1]));
8917 dev_set_drvdata(&op
->dev
, NULL
);
8922 static struct of_device_id niu_match
[] = {
8925 .compatible
= "SUNW,niusl",
8929 MODULE_DEVICE_TABLE(of
, niu_match
);
8931 static struct of_platform_driver niu_of_driver
= {
8933 .match_table
= niu_match
,
8934 .probe
= niu_of_probe
,
8935 .remove
= __devexit_p(niu_of_remove
),
8938 #endif /* CONFIG_SPARC64 */
8940 static int __init
niu_init(void)
8944 BUILD_BUG_ON(PAGE_SIZE
< 4 * 1024);
8946 niu_debug
= netif_msg_init(debug
, NIU_MSG_DEFAULT
);
8948 #ifdef CONFIG_SPARC64
8949 err
= of_register_driver(&niu_of_driver
, &of_bus_type
);
8953 err
= pci_register_driver(&niu_pci_driver
);
8954 #ifdef CONFIG_SPARC64
8956 of_unregister_driver(&niu_of_driver
);
8963 static void __exit
niu_exit(void)
8965 pci_unregister_driver(&niu_pci_driver
);
8966 #ifdef CONFIG_SPARC64
8967 of_unregister_driver(&niu_of_driver
);
8971 module_init(niu_init
);
8972 module_exit(niu_exit
);