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iop_adma: directly reclaim descriptors on allocation failure
[linux-2.6/kvm.git] / drivers / dma / iop-adma.c
blob8acbc3ab0b926d42a58dda6075555edae16e09d1
1 /*
2 * offload engine driver for the Intel Xscale series of i/o processors
3 * Copyright © 2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20 /*
21 * This driver supports the asynchrounous DMA copy and RAID engines available
22 * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/async_tx.h>
28 #include <linux/delay.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/spinlock.h>
31 #include <linux/interrupt.h>
32 #include <linux/platform_device.h>
33 #include <linux/memory.h>
34 #include <linux/ioport.h>
35
36 #include <asm/arch/adma.h>
37
38 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
39 #define to_iop_adma_device(dev) \
40 container_of(dev, struct iop_adma_device, common)
41 #define tx_to_iop_adma_slot(tx) \
42 container_of(tx, struct iop_adma_desc_slot, async_tx)
43
44 /**
45 * iop_adma_free_slots - flags descriptor slots for reuse
46 * @slot: Slot to free
47 * Caller must hold &iop_chan->lock while calling this function
48 */
49 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
50 {
51 int stride = slot->slots_per_op;
52
53 while (stride--) {
54 slot->slots_per_op = 0;
55 slot = list_entry(slot->slot_node.next,
56 struct iop_adma_desc_slot,
57 slot_node);
58 }
59 }
60
61 static dma_cookie_t
62 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
63 struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
64 {
65 BUG_ON(desc->async_tx.cookie < 0);
66 if (desc->async_tx.cookie > 0) {
67 cookie = desc->async_tx.cookie;
68 desc->async_tx.cookie = 0;
69
70 /* call the callback (must not sleep or submit new
71 * operations to this channel)
72 */
73 if (desc->async_tx.callback)
74 desc->async_tx.callback(
75 desc->async_tx.callback_param);
76
77 /* unmap dma addresses
78 * (unmap_single vs unmap_page?)
79 */
80 if (desc->group_head && desc->unmap_len) {
81 struct iop_adma_desc_slot *unmap = desc->group_head;
82 struct device *dev =
83 &iop_chan->device->pdev->dev;
84 u32 len = unmap->unmap_len;
85 enum dma_ctrl_flags flags = desc->async_tx.flags;
86 u32 src_cnt;
87 dma_addr_t addr;
88
89 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
90 addr = iop_desc_get_dest_addr(unmap, iop_chan);
91 dma_unmap_page(dev, addr, len, DMA_FROM_DEVICE);
92 }
93
94 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
95 src_cnt = unmap->unmap_src_cnt;
96 while (src_cnt--) {
97 addr = iop_desc_get_src_addr(unmap,
98 iop_chan,
99 src_cnt);
100 dma_unmap_page(dev, addr, len,
101 DMA_TO_DEVICE);
102 }
103 }
104 desc->group_head = NULL;
105 }
106 }
107
108 /* run dependent operations */
109 async_tx_run_dependencies(&desc->async_tx);
110
111 return cookie;
112 }
113
114 static int
115 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
116 struct iop_adma_chan *iop_chan)
117 {
118 /* the client is allowed to attach dependent operations
119 * until 'ack' is set
120 */
121 if (!async_tx_test_ack(&desc->async_tx))
122 return 0;
123
124 /* leave the last descriptor in the chain
125 * so we can append to it
126 */
127 if (desc->chain_node.next == &iop_chan->chain)
128 return 1;
129
130 dev_dbg(iop_chan->device->common.dev,
131 "\tfree slot: %d slots_per_op: %d\n",
132 desc->idx, desc->slots_per_op);
133
134 list_del(&desc->chain_node);
135 iop_adma_free_slots(desc);
136
137 return 0;
138 }
139
140 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
141 {
142 struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
143 dma_cookie_t cookie = 0;
144 u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
145 int busy = iop_chan_is_busy(iop_chan);
146 int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
147
148 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
149 /* free completed slots from the chain starting with
150 * the oldest descriptor
151 */
152 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
153 chain_node) {
154 pr_debug("\tcookie: %d slot: %d busy: %d "
155 "this_desc: %#x next_desc: %#x ack: %d\n",
156 iter->async_tx.cookie, iter->idx, busy,
157 iter->async_tx.phys, iop_desc_get_next_desc(iter),
158 async_tx_test_ack(&iter->async_tx));
159 prefetch(_iter);
160 prefetch(&_iter->async_tx);
161
162 /* do not advance past the current descriptor loaded into the
163 * hardware channel, subsequent descriptors are either in
164 * process or have not been submitted
165 */
166 if (seen_current)
167 break;
168
169 /* stop the search if we reach the current descriptor and the
170 * channel is busy, or if it appears that the current descriptor
171 * needs to be re-read (i.e. has been appended to)
172 */
173 if (iter->async_tx.phys == current_desc) {
174 BUG_ON(seen_current++);
175 if (busy || iop_desc_get_next_desc(iter))
176 break;
177 }
178
179 /* detect the start of a group transaction */
180 if (!slot_cnt && !slots_per_op) {
181 slot_cnt = iter->slot_cnt;
182 slots_per_op = iter->slots_per_op;
183 if (slot_cnt <= slots_per_op) {
184 slot_cnt = 0;
185 slots_per_op = 0;
186 }
187 }
188
189 if (slot_cnt) {
190 pr_debug("\tgroup++\n");
191 if (!grp_start)
192 grp_start = iter;
193 slot_cnt -= slots_per_op;
194 }
195
196 /* all the members of a group are complete */
197 if (slots_per_op != 0 && slot_cnt == 0) {
198 struct iop_adma_desc_slot *grp_iter, *_grp_iter;
199 int end_of_chain = 0;
200 pr_debug("\tgroup end\n");
201
202 /* collect the total results */
203 if (grp_start->xor_check_result) {
204 u32 zero_sum_result = 0;
205 slot_cnt = grp_start->slot_cnt;
206 grp_iter = grp_start;
207
208 list_for_each_entry_from(grp_iter,
209 &iop_chan->chain, chain_node) {
210 zero_sum_result |=
211 iop_desc_get_zero_result(grp_iter);
212 pr_debug("\titer%d result: %d\n",
213 grp_iter->idx, zero_sum_result);
214 slot_cnt -= slots_per_op;
215 if (slot_cnt == 0)
216 break;
217 }
218 pr_debug("\tgrp_start->xor_check_result: %p\n",
219 grp_start->xor_check_result);
220 *grp_start->xor_check_result = zero_sum_result;
221 }
222
223 /* clean up the group */
224 slot_cnt = grp_start->slot_cnt;
225 grp_iter = grp_start;
226 list_for_each_entry_safe_from(grp_iter, _grp_iter,
227 &iop_chan->chain, chain_node) {
228 cookie = iop_adma_run_tx_complete_actions(
229 grp_iter, iop_chan, cookie);
230
231 slot_cnt -= slots_per_op;
232 end_of_chain = iop_adma_clean_slot(grp_iter,
233 iop_chan);
234
235 if (slot_cnt == 0 || end_of_chain)
236 break;
237 }
238
239 /* the group should be complete at this point */
240 BUG_ON(slot_cnt);
241
242 slots_per_op = 0;
243 grp_start = NULL;
244 if (end_of_chain)
245 break;
246 else
247 continue;
248 } else if (slots_per_op) /* wait for group completion */
249 continue;
250
251 /* write back zero sum results (single descriptor case) */
252 if (iter->xor_check_result && iter->async_tx.cookie)
253 *iter->xor_check_result =
254 iop_desc_get_zero_result(iter);
255
256 cookie = iop_adma_run_tx_complete_actions(
257 iter, iop_chan, cookie);
258
259 if (iop_adma_clean_slot(iter, iop_chan))
260 break;
261 }
262
263 BUG_ON(!seen_current);
264
265 if (cookie > 0) {
266 iop_chan->completed_cookie = cookie;
267 pr_debug("\tcompleted cookie %d\n", cookie);
268 }
269 }
270
271 static void
272 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
273 {
274 spin_lock_bh(&iop_chan->lock);
275 __iop_adma_slot_cleanup(iop_chan);
276 spin_unlock_bh(&iop_chan->lock);
277 }
278
279 static void iop_adma_tasklet(unsigned long data)
280 {
281 struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
282
283 spin_lock(&iop_chan->lock);
284 __iop_adma_slot_cleanup(iop_chan);
285 spin_unlock(&iop_chan->lock);
286 }
287
288 static struct iop_adma_desc_slot *
289 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
290 int slots_per_op)
291 {
292 struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
293 LIST_HEAD(chain);
294 int slots_found, retry = 0;
295
296 /* start search from the last allocated descrtiptor
297 * if a contiguous allocation can not be found start searching
298 * from the beginning of the list
299 */
300 retry:
301 slots_found = 0;
302 if (retry == 0)
303 iter = iop_chan->last_used;
304 else
305 iter = list_entry(&iop_chan->all_slots,
306 struct iop_adma_desc_slot,
307 slot_node);
308
309 list_for_each_entry_safe_continue(
310 iter, _iter, &iop_chan->all_slots, slot_node) {
311 prefetch(_iter);
312 prefetch(&_iter->async_tx);
313 if (iter->slots_per_op) {
314 /* give up after finding the first busy slot
315 * on the second pass through the list
316 */
317 if (retry)
318 break;
319
320 slots_found = 0;
321 continue;
322 }
323
324 /* start the allocation if the slot is correctly aligned */
325 if (!slots_found++) {
326 if (iop_desc_is_aligned(iter, slots_per_op))
327 alloc_start = iter;
328 else {
329 slots_found = 0;
330 continue;
331 }
332 }
333
334 if (slots_found == num_slots) {
335 struct iop_adma_desc_slot *alloc_tail = NULL;
336 struct iop_adma_desc_slot *last_used = NULL;
337 iter = alloc_start;
338 while (num_slots) {
339 int i;
340 dev_dbg(iop_chan->device->common.dev,
341 "allocated slot: %d "
342 "(desc %p phys: %#x) slots_per_op %d\n",
343 iter->idx, iter->hw_desc,
344 iter->async_tx.phys, slots_per_op);
345
346 /* pre-ack all but the last descriptor */
347 if (num_slots != slots_per_op)
348 async_tx_ack(&iter->async_tx);
349
350 list_add_tail(&iter->chain_node, &chain);
351 alloc_tail = iter;
352 iter->async_tx.cookie = 0;
353 iter->slot_cnt = num_slots;
354 iter->xor_check_result = NULL;
355 for (i = 0; i < slots_per_op; i++) {
356 iter->slots_per_op = slots_per_op - i;
357 last_used = iter;
358 iter = list_entry(iter->slot_node.next,
359 struct iop_adma_desc_slot,
360 slot_node);
361 }
362 num_slots -= slots_per_op;
363 }
364 alloc_tail->group_head = alloc_start;
365 alloc_tail->async_tx.cookie = -EBUSY;
366 list_splice(&chain, &alloc_tail->async_tx.tx_list);
367 iop_chan->last_used = last_used;
368 iop_desc_clear_next_desc(alloc_start);
369 iop_desc_clear_next_desc(alloc_tail);
370 return alloc_tail;
371 }
372 }
373 if (!retry++)
374 goto retry;
375
376 /* perform direct reclaim if the allocation fails */
377 __iop_adma_slot_cleanup(iop_chan);
378
379 return NULL;
380 }
381
382 static dma_cookie_t
383 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
384 struct iop_adma_desc_slot *desc)
385 {
386 dma_cookie_t cookie = iop_chan->common.cookie;
387 cookie++;
388 if (cookie < 0)
389 cookie = 1;
390 iop_chan->common.cookie = desc->async_tx.cookie = cookie;
391 return cookie;
392 }
393
394 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
395 {
396 dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
397 iop_chan->pending);
398
399 if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
400 iop_chan->pending = 0;
401 iop_chan_append(iop_chan);
402 }
403 }
404
405 static dma_cookie_t
406 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
407 {
408 struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
409 struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
410 struct iop_adma_desc_slot *grp_start, *old_chain_tail;
411 int slot_cnt;
412 int slots_per_op;
413 dma_cookie_t cookie;
414
415 grp_start = sw_desc->group_head;
416 slot_cnt = grp_start->slot_cnt;
417 slots_per_op = grp_start->slots_per_op;
418
419 spin_lock_bh(&iop_chan->lock);
420 cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
421
422 old_chain_tail = list_entry(iop_chan->chain.prev,
423 struct iop_adma_desc_slot, chain_node);
424 list_splice_init(&sw_desc->async_tx.tx_list,
425 &old_chain_tail->chain_node);
426
427 /* fix up the hardware chain */
428 iop_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
429
430 /* 1/ don't add pre-chained descriptors
431 * 2/ dummy read to flush next_desc write
432 */
433 BUG_ON(iop_desc_get_next_desc(sw_desc));
434
435 /* increment the pending count by the number of slots
436 * memcpy operations have a 1:1 (slot:operation) relation
437 * other operations are heavier and will pop the threshold
438 * more often.
439 */
440 iop_chan->pending += slot_cnt;
441 iop_adma_check_threshold(iop_chan);
442 spin_unlock_bh(&iop_chan->lock);
443
444 dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
445 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
446
447 return cookie;
448 }
449
450 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
451 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
452
453 /* returns the number of allocated descriptors */
454 static int iop_adma_alloc_chan_resources(struct dma_chan *chan,
455 struct dma_client *client)
456 {
457 char *hw_desc;
458 int idx;
459 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
460 struct iop_adma_desc_slot *slot = NULL;
461 int init = iop_chan->slots_allocated ? 0 : 1;
462 struct iop_adma_platform_data *plat_data =
463 iop_chan->device->pdev->dev.platform_data;
464 int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
465
466 /* Allocate descriptor slots */
467 do {
468 idx = iop_chan->slots_allocated;
469 if (idx == num_descs_in_pool)
470 break;
471
472 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
473 if (!slot) {
474 printk(KERN_INFO "IOP ADMA Channel only initialized"
475 " %d descriptor slots", idx);
476 break;
477 }
478 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
479 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
480
481 dma_async_tx_descriptor_init(&slot->async_tx, chan);
482 slot->async_tx.tx_submit = iop_adma_tx_submit;
483 INIT_LIST_HEAD(&slot->chain_node);
484 INIT_LIST_HEAD(&slot->slot_node);
485 INIT_LIST_HEAD(&slot->async_tx.tx_list);
486 hw_desc = (char *) iop_chan->device->dma_desc_pool;
487 slot->async_tx.phys =
488 (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
489 slot->idx = idx;
490
491 spin_lock_bh(&iop_chan->lock);
492 iop_chan->slots_allocated++;
493 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
494 spin_unlock_bh(&iop_chan->lock);
495 } while (iop_chan->slots_allocated < num_descs_in_pool);
496
497 if (idx && !iop_chan->last_used)
498 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
499 struct iop_adma_desc_slot,
500 slot_node);
501
502 dev_dbg(iop_chan->device->common.dev,
503 "allocated %d descriptor slots last_used: %p\n",
504 iop_chan->slots_allocated, iop_chan->last_used);
505
506 /* initialize the channel and the chain with a null operation */
507 if (init) {
508 if (dma_has_cap(DMA_MEMCPY,
509 iop_chan->device->common.cap_mask))
510 iop_chan_start_null_memcpy(iop_chan);
511 else if (dma_has_cap(DMA_XOR,
512 iop_chan->device->common.cap_mask))
513 iop_chan_start_null_xor(iop_chan);
514 else
515 BUG();
516 }
517
518 return (idx > 0) ? idx : -ENOMEM;
519 }
520
521 static struct dma_async_tx_descriptor *
522 iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
523 {
524 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
525 struct iop_adma_desc_slot *sw_desc, *grp_start;
526 int slot_cnt, slots_per_op;
527
528 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
529
530 spin_lock_bh(&iop_chan->lock);
531 slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
532 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
533 if (sw_desc) {
534 grp_start = sw_desc->group_head;
535 iop_desc_init_interrupt(grp_start, iop_chan);
536 grp_start->unmap_len = 0;
537 sw_desc->async_tx.flags = flags;
538 }
539 spin_unlock_bh(&iop_chan->lock);
540
541 return sw_desc ? &sw_desc->async_tx : NULL;
542 }
543
544 static struct dma_async_tx_descriptor *
545 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
546 dma_addr_t dma_src, size_t len, unsigned long flags)
547 {
548 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
549 struct iop_adma_desc_slot *sw_desc, *grp_start;
550 int slot_cnt, slots_per_op;
551
552 if (unlikely(!len))
553 return NULL;
554 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
555
556 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
557 __func__, len);
558
559 spin_lock_bh(&iop_chan->lock);
560 slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
561 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
562 if (sw_desc) {
563 grp_start = sw_desc->group_head;
564 iop_desc_init_memcpy(grp_start, flags);
565 iop_desc_set_byte_count(grp_start, iop_chan, len);
566 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
567 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
568 sw_desc->unmap_src_cnt = 1;
569 sw_desc->unmap_len = len;
570 sw_desc->async_tx.flags = flags;
571 }
572 spin_unlock_bh(&iop_chan->lock);
573
574 return sw_desc ? &sw_desc->async_tx : NULL;
575 }
576
577 static struct dma_async_tx_descriptor *
578 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
579 int value, size_t len, unsigned long flags)
580 {
581 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
582 struct iop_adma_desc_slot *sw_desc, *grp_start;
583 int slot_cnt, slots_per_op;
584
585 if (unlikely(!len))
586 return NULL;
587 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
588
589 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
590 __func__, len);
591
592 spin_lock_bh(&iop_chan->lock);
593 slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
594 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
595 if (sw_desc) {
596 grp_start = sw_desc->group_head;
597 iop_desc_init_memset(grp_start, flags);
598 iop_desc_set_byte_count(grp_start, iop_chan, len);
599 iop_desc_set_block_fill_val(grp_start, value);
600 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
601 sw_desc->unmap_src_cnt = 1;
602 sw_desc->unmap_len = len;
603 sw_desc->async_tx.flags = flags;
604 }
605 spin_unlock_bh(&iop_chan->lock);
606
607 return sw_desc ? &sw_desc->async_tx : NULL;
608 }
609
610 static struct dma_async_tx_descriptor *
611 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
612 dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
613 unsigned long flags)
614 {
615 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
616 struct iop_adma_desc_slot *sw_desc, *grp_start;
617 int slot_cnt, slots_per_op;
618
619 if (unlikely(!len))
620 return NULL;
621 BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
622
623 dev_dbg(iop_chan->device->common.dev,
624 "%s src_cnt: %d len: %u flags: %lx\n",
625 __func__, src_cnt, len, flags);
626
627 spin_lock_bh(&iop_chan->lock);
628 slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
629 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
630 if (sw_desc) {
631 grp_start = sw_desc->group_head;
632 iop_desc_init_xor(grp_start, src_cnt, flags);
633 iop_desc_set_byte_count(grp_start, iop_chan, len);
634 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
635 sw_desc->unmap_src_cnt = src_cnt;
636 sw_desc->unmap_len = len;
637 sw_desc->async_tx.flags = flags;
638 while (src_cnt--)
639 iop_desc_set_xor_src_addr(grp_start, src_cnt,
640 dma_src[src_cnt]);
641 }
642 spin_unlock_bh(&iop_chan->lock);
643
644 return sw_desc ? &sw_desc->async_tx : NULL;
645 }
646
647 static struct dma_async_tx_descriptor *
648 iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src,
649 unsigned int src_cnt, size_t len, u32 *result,
650 unsigned long flags)
651 {
652 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
653 struct iop_adma_desc_slot *sw_desc, *grp_start;
654 int slot_cnt, slots_per_op;
655
656 if (unlikely(!len))
657 return NULL;
658
659 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
660 __func__, src_cnt, len);
661
662 spin_lock_bh(&iop_chan->lock);
663 slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
664 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
665 if (sw_desc) {
666 grp_start = sw_desc->group_head;
667 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
668 iop_desc_set_zero_sum_byte_count(grp_start, len);
669 grp_start->xor_check_result = result;
670 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
671 __func__, grp_start->xor_check_result);
672 sw_desc->unmap_src_cnt = src_cnt;
673 sw_desc->unmap_len = len;
674 sw_desc->async_tx.flags = flags;
675 while (src_cnt--)
676 iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
677 dma_src[src_cnt]);
678 }
679 spin_unlock_bh(&iop_chan->lock);
680
681 return sw_desc ? &sw_desc->async_tx : NULL;
682 }
683
684 static void iop_adma_free_chan_resources(struct dma_chan *chan)
685 {
686 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
687 struct iop_adma_desc_slot *iter, *_iter;
688 int in_use_descs = 0;
689
690 iop_adma_slot_cleanup(iop_chan);
691
692 spin_lock_bh(&iop_chan->lock);
693 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
694 chain_node) {
695 in_use_descs++;
696 list_del(&iter->chain_node);
697 }
698 list_for_each_entry_safe_reverse(
699 iter, _iter, &iop_chan->all_slots, slot_node) {
700 list_del(&iter->slot_node);
701 kfree(iter);
702 iop_chan->slots_allocated--;
703 }
704 iop_chan->last_used = NULL;
705
706 dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
707 __func__, iop_chan->slots_allocated);
708 spin_unlock_bh(&iop_chan->lock);
709
710 /* one is ok since we left it on there on purpose */
711 if (in_use_descs > 1)
712 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
713 in_use_descs - 1);
714 }
715
716 /**
717 * iop_adma_is_complete - poll the status of an ADMA transaction
718 * @chan: ADMA channel handle
719 * @cookie: ADMA transaction identifier
720 */
721 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
722 dma_cookie_t cookie,
723 dma_cookie_t *done,
724 dma_cookie_t *used)
725 {
726 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
727 dma_cookie_t last_used;
728 dma_cookie_t last_complete;
729 enum dma_status ret;
730
731 last_used = chan->cookie;
732 last_complete = iop_chan->completed_cookie;
733
734 if (done)
735 *done = last_complete;
736 if (used)
737 *used = last_used;
738
739 ret = dma_async_is_complete(cookie, last_complete, last_used);
740 if (ret == DMA_SUCCESS)
741 return ret;
742
743 iop_adma_slot_cleanup(iop_chan);
744
745 last_used = chan->cookie;
746 last_complete = iop_chan->completed_cookie;
747
748 if (done)
749 *done = last_complete;
750 if (used)
751 *used = last_used;
752
753 return dma_async_is_complete(cookie, last_complete, last_used);
754 }
755
756 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
757 {
758 struct iop_adma_chan *chan = data;
759
760 dev_dbg(chan->device->common.dev, "%s\n", __func__);
761
762 tasklet_schedule(&chan->irq_tasklet);
763
764 iop_adma_device_clear_eot_status(chan);
765
766 return IRQ_HANDLED;
767 }
768
769 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
770 {
771 struct iop_adma_chan *chan = data;
772
773 dev_dbg(chan->device->common.dev, "%s\n", __func__);
774
775 tasklet_schedule(&chan->irq_tasklet);
776
777 iop_adma_device_clear_eoc_status(chan);
778
779 return IRQ_HANDLED;
780 }
781
782 static irqreturn_t iop_adma_err_handler(int irq, void *data)
783 {
784 struct iop_adma_chan *chan = data;
785 unsigned long status = iop_chan_get_status(chan);
786
787 dev_printk(KERN_ERR, chan->device->common.dev,
788 "error ( %s%s%s%s%s%s%s)\n",
789 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
790 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
791 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
792 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
793 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
794 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
795 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
796
797 iop_adma_device_clear_err_status(chan);
798
799 BUG();
800
801 return IRQ_HANDLED;
802 }
803
804 static void iop_adma_issue_pending(struct dma_chan *chan)
805 {
806 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
807
808 if (iop_chan->pending) {
809 iop_chan->pending = 0;
810 iop_chan_append(iop_chan);
811 }
812 }
813
814 /*
815 * Perform a transaction to verify the HW works.
816 */
817 #define IOP_ADMA_TEST_SIZE 2000
818
819 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
820 {
821 int i;
822 void *src, *dest;
823 dma_addr_t src_dma, dest_dma;
824 struct dma_chan *dma_chan;
825 dma_cookie_t cookie;
826 struct dma_async_tx_descriptor *tx;
827 int err = 0;
828 struct iop_adma_chan *iop_chan;
829
830 dev_dbg(device->common.dev, "%s\n", __func__);
831
832 src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
833 if (!src)
834 return -ENOMEM;
835 dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
836 if (!dest) {
837 kfree(src);
838 return -ENOMEM;
839 }
840
841 /* Fill in src buffer */
842 for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
843 ((u8 *) src)[i] = (u8)i;
844
845 /* Start copy, using first DMA channel */
846 dma_chan = container_of(device->common.channels.next,
847 struct dma_chan,
848 device_node);
849 if (iop_adma_alloc_chan_resources(dma_chan, NULL) < 1) {
850 err = -ENODEV;
851 goto out;
852 }
853
854 dest_dma = dma_map_single(dma_chan->device->dev, dest,
855 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
856 src_dma = dma_map_single(dma_chan->device->dev, src,
857 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
858 tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
859 IOP_ADMA_TEST_SIZE,
860 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
861
862 cookie = iop_adma_tx_submit(tx);
863 iop_adma_issue_pending(dma_chan);
864 msleep(1);
865
866 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
867 DMA_SUCCESS) {
868 dev_printk(KERN_ERR, dma_chan->device->dev,
869 "Self-test copy timed out, disabling\n");
870 err = -ENODEV;
871 goto free_resources;
872 }
873
874 iop_chan = to_iop_adma_chan(dma_chan);
875 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
876 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
877 if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
878 dev_printk(KERN_ERR, dma_chan->device->dev,
879 "Self-test copy failed compare, disabling\n");
880 err = -ENODEV;
881 goto free_resources;
882 }
883
884 free_resources:
885 iop_adma_free_chan_resources(dma_chan);
886 out:
887 kfree(src);
888 kfree(dest);
889 return err;
890 }
891
892 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
893 static int __devinit
894 iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device)
895 {
896 int i, src_idx;
897 struct page *dest;
898 struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
899 struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
900 dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
901 dma_addr_t dma_addr, dest_dma;
902 struct dma_async_tx_descriptor *tx;
903 struct dma_chan *dma_chan;
904 dma_cookie_t cookie;
905 u8 cmp_byte = 0;
906 u32 cmp_word;
907 u32 zero_sum_result;
908 int err = 0;
909 struct iop_adma_chan *iop_chan;
910
911 dev_dbg(device->common.dev, "%s\n", __func__);
912
913 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
914 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
915 if (!xor_srcs[src_idx])
916 while (src_idx--) {
917 __free_page(xor_srcs[src_idx]);
918 return -ENOMEM;
919 }
920 }
921
922 dest = alloc_page(GFP_KERNEL);
923 if (!dest)
924 while (src_idx--) {
925 __free_page(xor_srcs[src_idx]);
926 return -ENOMEM;
927 }
928
929 /* Fill in src buffers */
930 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
931 u8 *ptr = page_address(xor_srcs[src_idx]);
932 for (i = 0; i < PAGE_SIZE; i++)
933 ptr[i] = (1 << src_idx);
934 }
935
936 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
937 cmp_byte ^= (u8) (1 << src_idx);
938
939 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
940 (cmp_byte << 8) | cmp_byte;
941
942 memset(page_address(dest), 0, PAGE_SIZE);
943
944 dma_chan = container_of(device->common.channels.next,
945 struct dma_chan,
946 device_node);
947 if (iop_adma_alloc_chan_resources(dma_chan, NULL) < 1) {
948 err = -ENODEV;
949 goto out;
950 }
951
952 /* test xor */
953 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
954 PAGE_SIZE, DMA_FROM_DEVICE);
955 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
956 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
957 0, PAGE_SIZE, DMA_TO_DEVICE);
958 tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
959 IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
960 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
961
962 cookie = iop_adma_tx_submit(tx);
963 iop_adma_issue_pending(dma_chan);
964 msleep(8);
965
966 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
967 DMA_SUCCESS) {
968 dev_printk(KERN_ERR, dma_chan->device->dev,
969 "Self-test xor timed out, disabling\n");
970 err = -ENODEV;
971 goto free_resources;
972 }
973
974 iop_chan = to_iop_adma_chan(dma_chan);
975 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
976 PAGE_SIZE, DMA_FROM_DEVICE);
977 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
978 u32 *ptr = page_address(dest);
979 if (ptr[i] != cmp_word) {
980 dev_printk(KERN_ERR, dma_chan->device->dev,
981 "Self-test xor failed compare, disabling\n");
982 err = -ENODEV;
983 goto free_resources;
984 }
985 }
986 dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
987 PAGE_SIZE, DMA_TO_DEVICE);
988
989 /* skip zero sum if the capability is not present */
990 if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask))
991 goto free_resources;
992
993 /* zero sum the sources with the destintation page */
994 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
995 zero_sum_srcs[i] = xor_srcs[i];
996 zero_sum_srcs[i] = dest;
997
998 zero_sum_result = 1;
999
1000 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1001 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1002 zero_sum_srcs[i], 0, PAGE_SIZE,
1003 DMA_TO_DEVICE);
1004 tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1005 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1006 &zero_sum_result,
1007 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1008
1009 cookie = iop_adma_tx_submit(tx);
1010 iop_adma_issue_pending(dma_chan);
1011 msleep(8);
1012
1013 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1014 dev_printk(KERN_ERR, dma_chan->device->dev,
1015 "Self-test zero sum timed out, disabling\n");
1016 err = -ENODEV;
1017 goto free_resources;
1018 }
1019
1020 if (zero_sum_result != 0) {
1021 dev_printk(KERN_ERR, dma_chan->device->dev,
1022 "Self-test zero sum failed compare, disabling\n");
1023 err = -ENODEV;
1024 goto free_resources;
1025 }
1026
1027 /* test memset */
1028 dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1029 PAGE_SIZE, DMA_FROM_DEVICE);
1030 tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1031 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1032
1033 cookie = iop_adma_tx_submit(tx);
1034 iop_adma_issue_pending(dma_chan);
1035 msleep(8);
1036
1037 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1038 dev_printk(KERN_ERR, dma_chan->device->dev,
1039 "Self-test memset timed out, disabling\n");
1040 err = -ENODEV;
1041 goto free_resources;
1042 }
1043
1044 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1045 u32 *ptr = page_address(dest);
1046 if (ptr[i]) {
1047 dev_printk(KERN_ERR, dma_chan->device->dev,
1048 "Self-test memset failed compare, disabling\n");
1049 err = -ENODEV;
1050 goto free_resources;
1051 }
1052 }
1053
1054 /* test for non-zero parity sum */
1055 zero_sum_result = 0;
1056 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1057 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1058 zero_sum_srcs[i], 0, PAGE_SIZE,
1059 DMA_TO_DEVICE);
1060 tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1061 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1062 &zero_sum_result,
1063 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1064
1065 cookie = iop_adma_tx_submit(tx);
1066 iop_adma_issue_pending(dma_chan);
1067 msleep(8);
1068
1069 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1070 dev_printk(KERN_ERR, dma_chan->device->dev,
1071 "Self-test non-zero sum timed out, disabling\n");
1072 err = -ENODEV;
1073 goto free_resources;
1074 }
1075
1076 if (zero_sum_result != 1) {
1077 dev_printk(KERN_ERR, dma_chan->device->dev,
1078 "Self-test non-zero sum failed compare, disabling\n");
1079 err = -ENODEV;
1080 goto free_resources;
1081 }
1082
1083 free_resources:
1084 iop_adma_free_chan_resources(dma_chan);
1085 out:
1086 src_idx = IOP_ADMA_NUM_SRC_TEST;
1087 while (src_idx--)
1088 __free_page(xor_srcs[src_idx]);
1089 __free_page(dest);
1090 return err;
1091 }
1092
1093 static int __devexit iop_adma_remove(struct platform_device *dev)
1094 {
1095 struct iop_adma_device *device = platform_get_drvdata(dev);
1096 struct dma_chan *chan, *_chan;
1097 struct iop_adma_chan *iop_chan;
1098 int i;
1099 struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1100
1101 dma_async_device_unregister(&device->common);
1102
1103 for (i = 0; i < 3; i++) {
1104 unsigned int irq;
1105 irq = platform_get_irq(dev, i);
1106 free_irq(irq, device);
1107 }
1108
1109 dma_free_coherent(&dev->dev, plat_data->pool_size,
1110 device->dma_desc_pool_virt, device->dma_desc_pool);
1111
1112 do {
1113 struct resource *res;
1114 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1115 release_mem_region(res->start, res->end - res->start);
1116 } while (0);
1117
1118 list_for_each_entry_safe(chan, _chan, &device->common.channels,
1119 device_node) {
1120 iop_chan = to_iop_adma_chan(chan);
1121 list_del(&chan->device_node);
1122 kfree(iop_chan);
1123 }
1124 kfree(device);
1125
1126 return 0;
1127 }
1128
1129 static int __devinit iop_adma_probe(struct platform_device *pdev)
1130 {
1131 struct resource *res;
1132 int ret = 0, i;
1133 struct iop_adma_device *adev;
1134 struct iop_adma_chan *iop_chan;
1135 struct dma_device *dma_dev;
1136 struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1137
1138 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1139 if (!res)
1140 return -ENODEV;
1141
1142 if (!devm_request_mem_region(&pdev->dev, res->start,
1143 res->end - res->start, pdev->name))
1144 return -EBUSY;
1145
1146 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1147 if (!adev)
1148 return -ENOMEM;
1149 dma_dev = &adev->common;
1150
1151 /* allocate coherent memory for hardware descriptors
1152 * note: writecombine gives slightly better performance, but
1153 * requires that we explicitly flush the writes
1154 */
1155 if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1156 plat_data->pool_size,
1157 &adev->dma_desc_pool,
1158 GFP_KERNEL)) == NULL) {
1159 ret = -ENOMEM;
1160 goto err_free_adev;
1161 }
1162
1163 dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1164 __func__, adev->dma_desc_pool_virt,
1165 (void *) adev->dma_desc_pool);
1166
1167 adev->id = plat_data->hw_id;
1168
1169 /* discover transaction capabilites from the platform data */
1170 dma_dev->cap_mask = plat_data->cap_mask;
1171
1172 adev->pdev = pdev;
1173 platform_set_drvdata(pdev, adev);
1174
1175 INIT_LIST_HEAD(&dma_dev->channels);
1176
1177 /* set base routines */
1178 dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1179 dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1180 dma_dev->device_is_tx_complete = iop_adma_is_complete;
1181 dma_dev->device_issue_pending = iop_adma_issue_pending;
1182 dma_dev->dev = &pdev->dev;
1183
1184 /* set prep routines based on capability */
1185 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1186 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1187 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1188 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1189 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1190 dma_dev->max_xor = iop_adma_get_max_xor();
1191 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1192 }
1193 if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask))
1194 dma_dev->device_prep_dma_zero_sum =
1195 iop_adma_prep_dma_zero_sum;
1196 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1197 dma_dev->device_prep_dma_interrupt =
1198 iop_adma_prep_dma_interrupt;
1199
1200 iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1201 if (!iop_chan) {
1202 ret = -ENOMEM;
1203 goto err_free_dma;
1204 }
1205 iop_chan->device = adev;
1206
1207 iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1208 res->end - res->start);
1209 if (!iop_chan->mmr_base) {
1210 ret = -ENOMEM;
1211 goto err_free_iop_chan;
1212 }
1213 tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1214 iop_chan);
1215
1216 /* clear errors before enabling interrupts */
1217 iop_adma_device_clear_err_status(iop_chan);
1218
1219 for (i = 0; i < 3; i++) {
1220 irq_handler_t handler[] = { iop_adma_eot_handler,
1221 iop_adma_eoc_handler,
1222 iop_adma_err_handler };
1223 int irq = platform_get_irq(pdev, i);
1224 if (irq < 0) {
1225 ret = -ENXIO;
1226 goto err_free_iop_chan;
1227 } else {
1228 ret = devm_request_irq(&pdev->dev, irq,
1229 handler[i], 0, pdev->name, iop_chan);
1230 if (ret)
1231 goto err_free_iop_chan;
1232 }
1233 }
1234
1235 spin_lock_init(&iop_chan->lock);
1236 INIT_LIST_HEAD(&iop_chan->chain);
1237 INIT_LIST_HEAD(&iop_chan->all_slots);
1238 INIT_RCU_HEAD(&iop_chan->common.rcu);
1239 iop_chan->common.device = dma_dev;
1240 list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1241
1242 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1243 ret = iop_adma_memcpy_self_test(adev);
1244 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1245 if (ret)
1246 goto err_free_iop_chan;
1247 }
1248
1249 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1250 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1251 ret = iop_adma_xor_zero_sum_self_test(adev);
1252 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1253 if (ret)
1254 goto err_free_iop_chan;
1255 }
1256
1257 dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1258 "( %s%s%s%s%s%s%s%s%s%s)\n",
1259 dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "",
1260 dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1261 dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "",
1262 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1263 dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1264 dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "",
1265 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "",
1266 dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1267 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1268 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1269
1270 dma_async_device_register(dma_dev);
1271 goto out;
1272
1273 err_free_iop_chan:
1274 kfree(iop_chan);
1275 err_free_dma:
1276 dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1277 adev->dma_desc_pool_virt, adev->dma_desc_pool);
1278 err_free_adev:
1279 kfree(adev);
1280 out:
1281 return ret;
1282 }
1283
1284 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1285 {
1286 struct iop_adma_desc_slot *sw_desc, *grp_start;
1287 dma_cookie_t cookie;
1288 int slot_cnt, slots_per_op;
1289
1290 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1291
1292 spin_lock_bh(&iop_chan->lock);
1293 slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1294 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1295 if (sw_desc) {
1296 grp_start = sw_desc->group_head;
1297
1298 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1299 async_tx_ack(&sw_desc->async_tx);
1300 iop_desc_init_memcpy(grp_start, 0);
1301 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1302 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1303 iop_desc_set_memcpy_src_addr(grp_start, 0);
1304
1305 cookie = iop_chan->common.cookie;
1306 cookie++;
1307 if (cookie <= 1)
1308 cookie = 2;
1309
1310 /* initialize the completed cookie to be less than
1311 * the most recently used cookie
1312 */
1313 iop_chan->completed_cookie = cookie - 1;
1314 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1315
1316 /* channel should not be busy */
1317 BUG_ON(iop_chan_is_busy(iop_chan));
1318
1319 /* clear any prior error-status bits */
1320 iop_adma_device_clear_err_status(iop_chan);
1321
1322 /* disable operation */
1323 iop_chan_disable(iop_chan);
1324
1325 /* set the descriptor address */
1326 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1327
1328 /* 1/ don't add pre-chained descriptors
1329 * 2/ dummy read to flush next_desc write
1330 */
1331 BUG_ON(iop_desc_get_next_desc(sw_desc));
1332
1333 /* run the descriptor */
1334 iop_chan_enable(iop_chan);
1335 } else
1336 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1337 "failed to allocate null descriptor\n");
1338 spin_unlock_bh(&iop_chan->lock);
1339 }
1340
1341 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1342 {
1343 struct iop_adma_desc_slot *sw_desc, *grp_start;
1344 dma_cookie_t cookie;
1345 int slot_cnt, slots_per_op;
1346
1347 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1348
1349 spin_lock_bh(&iop_chan->lock);
1350 slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1351 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1352 if (sw_desc) {
1353 grp_start = sw_desc->group_head;
1354 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1355 async_tx_ack(&sw_desc->async_tx);
1356 iop_desc_init_null_xor(grp_start, 2, 0);
1357 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1358 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1359 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1360 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1361
1362 cookie = iop_chan->common.cookie;
1363 cookie++;
1364 if (cookie <= 1)
1365 cookie = 2;
1366
1367 /* initialize the completed cookie to be less than
1368 * the most recently used cookie
1369 */
1370 iop_chan->completed_cookie = cookie - 1;
1371 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1372
1373 /* channel should not be busy */
1374 BUG_ON(iop_chan_is_busy(iop_chan));
1375
1376 /* clear any prior error-status bits */
1377 iop_adma_device_clear_err_status(iop_chan);
1378
1379 /* disable operation */
1380 iop_chan_disable(iop_chan);
1381
1382 /* set the descriptor address */
1383 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1384
1385 /* 1/ don't add pre-chained descriptors
1386 * 2/ dummy read to flush next_desc write
1387 */
1388 BUG_ON(iop_desc_get_next_desc(sw_desc));
1389
1390 /* run the descriptor */
1391 iop_chan_enable(iop_chan);
1392 } else
1393 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1394 "failed to allocate null descriptor\n");
1395 spin_unlock_bh(&iop_chan->lock);
1396 }
1397
1398 MODULE_ALIAS("platform:iop-adma");
1399
1400 static struct platform_driver iop_adma_driver = {
1401 .probe = iop_adma_probe,
1402 .remove = iop_adma_remove,
1403 .driver = {
1404 .owner = THIS_MODULE,
1405 .name = "iop-adma",
1406 },
1407 };
1408
1409 static int __init iop_adma_init (void)
1410 {
1411 return platform_driver_register(&iop_adma_driver);
1412 }
1413
1414 /* it's currently unsafe to unload this module */
1415 #if 0
1416 static void __exit iop_adma_exit (void)
1417 {
1418 platform_driver_unregister(&iop_adma_driver);
1419 return;
1420 }
1421 module_exit(iop_adma_exit);
1422 #endif
1423
1424 module_init(iop_adma_init);
1425
1426 MODULE_AUTHOR("Intel Corporation");
1427 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1428 MODULE_LICENSE("GPL");
kernel-based virtual machine