arch/mips/mm/sc-rm7k.c

   1 /*
   2  * sc-rm7k.c: RM7000 cache management functions.
   3  *
   4  * Copyright (C) 1997, 2001, 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
   5  */
   6
   7 #undef DEBUG
   8
   9 #include <linux/init.h>
  10 #include <linux/kernel.h>
  11 #include <linux/mm.h>
  12
  13 #include <asm/addrspace.h>
  14 #include <asm/bcache.h>
  15 #include <asm/cacheops.h>
  16 #include <asm/mipsregs.h>
  17 #include <asm/processor.h>
  18 #include <asm/cacheflush.h> /* for run_uncached() */
  19
  20 /* Primary cache parameters. */
  21 #define sc_lsize        32
  22 #define tc_pagesize     (32*128)
  23
  24 /* Secondary cache parameters. */
  25 #define scache_size     (256*1024)      /* Fixed to 256KiB on RM7000 */
  26
  27 extern unsigned long icache_way_size, dcache_way_size;
  28
  29 #include <asm/r4kcache.h>
  30
  31 int rm7k_tcache_enabled;
  32
  33 /*
  34  * Writeback and invalidate the primary cache dcache before DMA.
  35  * (XXX These need to be fixed ...)
  36  */
  37 static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
  38 {
  39         unsigned long end, a;
  40
  41         pr_debug("rm7k_sc_wback_inv[%08lx,%08lx]", addr, size);
  42
  43         /* Catch bad driver code */
  44         BUG_ON(size == 0);
  45
  46         a = addr & ~(sc_lsize - 1);
  47         end = (addr + size - 1) & ~(sc_lsize - 1);
  48         while (1) {
  49                 flush_scache_line(a);   /* Hit_Writeback_Inv_SD */
  50                 if (a == end)
  51                         break;
  52                 a += sc_lsize;
  53         }
  54
  55         if (!rm7k_tcache_enabled)
  56                 return;
  57
  58         a = addr & ~(tc_pagesize - 1);
  59         end = (addr + size - 1) & ~(tc_pagesize - 1);
  60         while(1) {
  61                 invalidate_tcache_page(a);      /* Page_Invalidate_T */
  62                 if (a == end)
  63                         break;
  64                 a += tc_pagesize;
  65         }
  66 }
  67
  68 static void rm7k_sc_inv(unsigned long addr, unsigned long size)
  69 {
  70         unsigned long end, a;
  71
  72         pr_debug("rm7k_sc_inv[%08lx,%08lx]", addr, size);
  73
  74         /* Catch bad driver code */
  75         BUG_ON(size == 0);
  76
  77         a = addr & ~(sc_lsize - 1);
  78         end = (addr + size - 1) & ~(sc_lsize - 1);
  79         while (1) {
  80                 invalidate_scache_line(a);      /* Hit_Invalidate_SD */
  81                 if (a == end)
  82                         break;
  83                 a += sc_lsize;
  84         }
  85
  86         if (!rm7k_tcache_enabled)
  87                 return;
  88
  89         a = addr & ~(tc_pagesize - 1);
  90         end = (addr + size - 1) & ~(tc_pagesize - 1);
  91         while(1) {
  92                 invalidate_tcache_page(a);      /* Page_Invalidate_T */
  93                 if (a == end)
  94                         break;
  95                 a += tc_pagesize;
  96         }
  97 }
  98
  99 /*
 100  * This function is executed in uncached address space.
 101  */
 102 static __init void __rm7k_sc_enable(void)
 103 {
 104         int i;
 105
 106         set_c0_config(RM7K_CONF_SE);
 107
 108         write_c0_taglo(0);
 109         write_c0_taghi(0);
 110
 111         for (i = 0; i < scache_size; i += sc_lsize) {
 112                 __asm__ __volatile__ (
 113                       ".set noreorder\n\t"
 114                       ".set mips3\n\t"
 115                       "cache %1, (%0)\n\t"
 116                       ".set mips0\n\t"
 117                       ".set reorder"
 118                       :
 119                       : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
 120         }
 121 }
 122
 123 static __init void rm7k_sc_enable(void)
 124 {
 125         if (read_c0_config() & RM7K_CONF_SE)
 126                 return;
 127
 128         printk(KERN_INFO "Enabling secondary cache...\n");
 129         run_uncached(__rm7k_sc_enable);
 130 }
 131
 132 static void rm7k_sc_disable(void)
 133 {
 134         clear_c0_config(RM7K_CONF_SE);
 135 }
 136
 137 struct bcache_ops rm7k_sc_ops = {
 138         .bc_enable = rm7k_sc_enable,
 139         .bc_disable = rm7k_sc_disable,
 140         .bc_wback_inv = rm7k_sc_wback_inv,
 141         .bc_inv = rm7k_sc_inv
 142 };
 143
 144 void __init rm7k_sc_init(void)
 145 {
 146         unsigned int config = read_c0_config();
 147
 148         if ((config & RM7K_CONF_SC))
 149                 return;
 150
 151         printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
 152                (scache_size >> 10), sc_lsize);
 153
 154         if (!(config & RM7K_CONF_SE))
 155                 rm7k_sc_enable();
 156
 157         /*
 158          * While we're at it let's deal with the tertiary cache.
 159          */
 160         if (!(config & RM7K_CONF_TC)) {
 161
 162                 /*
 163                  * We can't enable the L3 cache yet. There may be board-specific
 164                  * magic necessary to turn it on, and blindly asking the CPU to
 165                  * start using it would may give cache errors.
 166                  *
 167                  * Also, board-specific knowledge may allow us to use the
 168                  * CACHE Flash_Invalidate_T instruction if the tag RAM supports
 169                  * it, and may specify the size of the L3 cache so we don't have
 170                  * to probe it.
 171                  */
 172                 printk(KERN_INFO "Tertiary cache present, %s enabled\n",
 173                        (config & RM7K_CONF_TE) ? "already" : "not (yet)");
 174
 175                 if ((config & RM7K_CONF_TE))
 176                         rm7k_tcache_enabled = 1;
 177         }
 178
 179         bcops = &rm7k_sc_ops;
 180 }