?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[NET]: Make NAPI polling independent of struct net_device objects.
[linux-2.6/kvm.git] / drivers / net / myri10ge / myri10ge.c
bloba30146ea51f03a7ce519c87e8db7053d0850c2d6
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005 - 2007 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/ip.h>
52 #include <linux/inet.h>
53 #include <linux/in.h>
54 #include <linux/ethtool.h>
55 #include <linux/firmware.h>
56 #include <linux/delay.h>
57 #include <linux/version.h>
58 #include <linux/timer.h>
59 #include <linux/vmalloc.h>
60 #include <linux/crc32.h>
61 #include <linux/moduleparam.h>
62 #include <linux/io.h>
63 #include <linux/log2.h>
64 #include <net/checksum.h>
65 #include <asm/byteorder.h>
66 #include <asm/io.h>
67 #include <asm/processor.h>
68 #ifdef CONFIG_MTRR
69 #include <asm/mtrr.h>
70 #endif
71
72 #include "myri10ge_mcp.h"
73 #include "myri10ge_mcp_gen_header.h"
74
75 #define MYRI10GE_VERSION_STR "1.3.2-1.269"
76
77 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
78 MODULE_AUTHOR("Maintainer: help@myri.com");
79 MODULE_VERSION(MYRI10GE_VERSION_STR);
80 MODULE_LICENSE("Dual BSD/GPL");
81
82 #define MYRI10GE_MAX_ETHER_MTU 9014
83
84 #define MYRI10GE_ETH_STOPPED 0
85 #define MYRI10GE_ETH_STOPPING 1
86 #define MYRI10GE_ETH_STARTING 2
87 #define MYRI10GE_ETH_RUNNING 3
88 #define MYRI10GE_ETH_OPEN_FAILED 4
89
90 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
91 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
92
93 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
94 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
95
96 #define MYRI10GE_ALLOC_ORDER 0
97 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
98 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
99
100 struct myri10ge_rx_buffer_state {
101 struct page *page;
102 int page_offset;
103 DECLARE_PCI_UNMAP_ADDR(bus)
104 DECLARE_PCI_UNMAP_LEN(len)
105 };
106
107 struct myri10ge_tx_buffer_state {
108 struct sk_buff *skb;
109 int last;
110 DECLARE_PCI_UNMAP_ADDR(bus)
111 DECLARE_PCI_UNMAP_LEN(len)
112 };
113
114 struct myri10ge_cmd {
115 u32 data0;
116 u32 data1;
117 u32 data2;
118 };
119
120 struct myri10ge_rx_buf {
121 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
122 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
123 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
124 struct myri10ge_rx_buffer_state *info;
125 struct page *page;
126 dma_addr_t bus;
127 int page_offset;
128 int cnt;
129 int fill_cnt;
130 int alloc_fail;
131 int mask; /* number of rx slots -1 */
132 int watchdog_needed;
133 };
134
135 struct myri10ge_tx_buf {
136 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
137 u8 __iomem *wc_fifo; /* w/c send fifo address */
138 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
139 char *req_bytes;
140 struct myri10ge_tx_buffer_state *info;
141 int mask; /* number of transmit slots -1 */
142 int boundary; /* boundary transmits cannot cross */
143 int req ____cacheline_aligned; /* transmit slots submitted */
144 int pkt_start; /* packets started */
145 int done ____cacheline_aligned; /* transmit slots completed */
146 int pkt_done; /* packets completed */
147 };
148
149 struct myri10ge_rx_done {
150 struct mcp_slot *entry;
151 dma_addr_t bus;
152 int cnt;
153 int idx;
154 };
155
156 struct myri10ge_priv {
157 int running; /* running? */
158 int csum_flag; /* rx_csums? */
159 struct myri10ge_tx_buf tx; /* transmit ring */
160 struct myri10ge_rx_buf rx_small;
161 struct myri10ge_rx_buf rx_big;
162 struct myri10ge_rx_done rx_done;
163 int small_bytes;
164 int big_bytes;
165 struct net_device *dev;
166 struct napi_struct napi;
167 struct net_device_stats stats;
168 u8 __iomem *sram;
169 int sram_size;
170 unsigned long board_span;
171 unsigned long iomem_base;
172 __be32 __iomem *irq_claim;
173 __be32 __iomem *irq_deassert;
174 char *mac_addr_string;
175 struct mcp_cmd_response *cmd;
176 dma_addr_t cmd_bus;
177 struct mcp_irq_data *fw_stats;
178 dma_addr_t fw_stats_bus;
179 struct pci_dev *pdev;
180 int msi_enabled;
181 __be32 link_state;
182 unsigned int rdma_tags_available;
183 int intr_coal_delay;
184 __be32 __iomem *intr_coal_delay_ptr;
185 int mtrr;
186 int wc_enabled;
187 int wake_queue;
188 int stop_queue;
189 int down_cnt;
190 wait_queue_head_t down_wq;
191 struct work_struct watchdog_work;
192 struct timer_list watchdog_timer;
193 int watchdog_tx_done;
194 int watchdog_tx_req;
195 int watchdog_pause;
196 int watchdog_resets;
197 int tx_linearized;
198 int pause;
199 char *fw_name;
200 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
201 char fw_version[128];
202 int fw_ver_major;
203 int fw_ver_minor;
204 int fw_ver_tiny;
205 int adopted_rx_filter_bug;
206 u8 mac_addr[6]; /* eeprom mac address */
207 unsigned long serial_number;
208 int vendor_specific_offset;
209 int fw_multicast_support;
210 u32 read_dma;
211 u32 write_dma;
212 u32 read_write_dma;
213 u32 link_changes;
214 u32 msg_enable;
215 };
216
217 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
218 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
219
220 static char *myri10ge_fw_name = NULL;
221 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
222 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
223
224 static int myri10ge_ecrc_enable = 1;
225 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
226 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
227
228 static int myri10ge_max_intr_slots = 1024;
229 module_param(myri10ge_max_intr_slots, int, S_IRUGO);
230 MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
231
232 static int myri10ge_small_bytes = -1; /* -1 == auto */
233 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
234 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
235
236 static int myri10ge_msi = 1; /* enable msi by default */
237 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
238 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
239
240 static int myri10ge_intr_coal_delay = 75;
241 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
242 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
243
244 static int myri10ge_flow_control = 1;
245 module_param(myri10ge_flow_control, int, S_IRUGO);
246 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
247
248 static int myri10ge_deassert_wait = 1;
249 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
250 MODULE_PARM_DESC(myri10ge_deassert_wait,
251 "Wait when deasserting legacy interrupts\n");
252
253 static int myri10ge_force_firmware = 0;
254 module_param(myri10ge_force_firmware, int, S_IRUGO);
255 MODULE_PARM_DESC(myri10ge_force_firmware,
256 "Force firmware to assume aligned completions\n");
257
258 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
259 module_param(myri10ge_initial_mtu, int, S_IRUGO);
260 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
261
262 static int myri10ge_napi_weight = 64;
263 module_param(myri10ge_napi_weight, int, S_IRUGO);
264 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
265
266 static int myri10ge_watchdog_timeout = 1;
267 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
268 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
269
270 static int myri10ge_max_irq_loops = 1048576;
271 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
272 MODULE_PARM_DESC(myri10ge_max_irq_loops,
273 "Set stuck legacy IRQ detection threshold\n");
274
275 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
276
277 static int myri10ge_debug = -1; /* defaults above */
278 module_param(myri10ge_debug, int, 0);
279 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
280
281 static int myri10ge_fill_thresh = 256;
282 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
283 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
284
285 static int myri10ge_reset_recover = 1;
286
287 static int myri10ge_wcfifo = 0;
288 module_param(myri10ge_wcfifo, int, S_IRUGO);
289 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
290
291 #define MYRI10GE_FW_OFFSET 1024*1024
292 #define MYRI10GE_HIGHPART_TO_U32(X) \
293 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
294 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
295
296 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
297
298 static void myri10ge_set_multicast_list(struct net_device *dev);
299
300 static inline void put_be32(__be32 val, __be32 __iomem * p)
301 {
302 __raw_writel((__force __u32) val, (__force void __iomem *)p);
303 }
304
305 static int
306 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
307 struct myri10ge_cmd *data, int atomic)
308 {
309 struct mcp_cmd *buf;
310 char buf_bytes[sizeof(*buf) + 8];
311 struct mcp_cmd_response *response = mgp->cmd;
312 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
313 u32 dma_low, dma_high, result, value;
314 int sleep_total = 0;
315
316 /* ensure buf is aligned to 8 bytes */
317 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
318
319 buf->data0 = htonl(data->data0);
320 buf->data1 = htonl(data->data1);
321 buf->data2 = htonl(data->data2);
322 buf->cmd = htonl(cmd);
323 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
324 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
325
326 buf->response_addr.low = htonl(dma_low);
327 buf->response_addr.high = htonl(dma_high);
328 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
329 mb();
330 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
331
332 /* wait up to 15ms. Longest command is the DMA benchmark,
333 * which is capped at 5ms, but runs from a timeout handler
334 * that runs every 7.8ms. So a 15ms timeout leaves us with
335 * a 2.2ms margin
336 */
337 if (atomic) {
338 /* if atomic is set, do not sleep,
339 * and try to get the completion quickly
340 * (1ms will be enough for those commands) */
341 for (sleep_total = 0;
342 sleep_total < 1000
343 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
344 sleep_total += 10)
345 udelay(10);
346 } else {
347 /* use msleep for most command */
348 for (sleep_total = 0;
349 sleep_total < 15
350 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
351 sleep_total++)
352 msleep(1);
353 }
354
355 result = ntohl(response->result);
356 value = ntohl(response->data);
357 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
358 if (result == 0) {
359 data->data0 = value;
360 return 0;
361 } else if (result == MXGEFW_CMD_UNKNOWN) {
362 return -ENOSYS;
363 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
364 return -E2BIG;
365 } else {
366 dev_err(&mgp->pdev->dev,
367 "command %d failed, result = %d\n",
368 cmd, result);
369 return -ENXIO;
370 }
371 }
372
373 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
374 cmd, result);
375 return -EAGAIN;
376 }
377
378 /*
379 * The eeprom strings on the lanaiX have the format
380 * SN=x\0
381 * MAC=x:x:x:x:x:x\0
382 * PT:ddd mmm xx xx:xx:xx xx\0
383 * PV:ddd mmm xx xx:xx:xx xx\0
384 */
385 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
386 {
387 char *ptr, *limit;
388 int i;
389
390 ptr = mgp->eeprom_strings;
391 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
392
393 while (*ptr != '\0' && ptr < limit) {
394 if (memcmp(ptr, "MAC=", 4) == 0) {
395 ptr += 4;
396 mgp->mac_addr_string = ptr;
397 for (i = 0; i < 6; i++) {
398 if ((ptr + 2) > limit)
399 goto abort;
400 mgp->mac_addr[i] =
401 simple_strtoul(ptr, &ptr, 16);
402 ptr += 1;
403 }
404 }
405 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
406 ptr += 3;
407 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
408 }
409 while (ptr < limit && *ptr++) ;
410 }
411
412 return 0;
413
414 abort:
415 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
416 return -ENXIO;
417 }
418
419 /*
420 * Enable or disable periodic RDMAs from the host to make certain
421 * chipsets resend dropped PCIe messages
422 */
423
424 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
425 {
426 char __iomem *submit;
427 __be32 buf[16];
428 u32 dma_low, dma_high;
429 int i;
430
431 /* clear confirmation addr */
432 mgp->cmd->data = 0;
433 mb();
434
435 /* send a rdma command to the PCIe engine, and wait for the
436 * response in the confirmation address. The firmware should
437 * write a -1 there to indicate it is alive and well
438 */
439 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
440 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
441
442 buf[0] = htonl(dma_high); /* confirm addr MSW */
443 buf[1] = htonl(dma_low); /* confirm addr LSW */
444 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
445 buf[3] = htonl(dma_high); /* dummy addr MSW */
446 buf[4] = htonl(dma_low); /* dummy addr LSW */
447 buf[5] = htonl(enable); /* enable? */
448
449 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
450
451 myri10ge_pio_copy(submit, &buf, sizeof(buf));
452 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
453 msleep(1);
454 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
455 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
456 (enable ? "enable" : "disable"));
457 }
458
459 static int
460 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
461 struct mcp_gen_header *hdr)
462 {
463 struct device *dev = &mgp->pdev->dev;
464
465 /* check firmware type */
466 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
467 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
468 return -EINVAL;
469 }
470
471 /* save firmware version for ethtool */
472 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
473
474 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
475 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
476
477 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
478 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
479 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
480 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
481 MXGEFW_VERSION_MINOR);
482 return -EINVAL;
483 }
484 return 0;
485 }
486
487 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
488 {
489 unsigned crc, reread_crc;
490 const struct firmware *fw;
491 struct device *dev = &mgp->pdev->dev;
492 struct mcp_gen_header *hdr;
493 size_t hdr_offset;
494 int status;
495 unsigned i;
496
497 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
498 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
499 mgp->fw_name);
500 status = -EINVAL;
501 goto abort_with_nothing;
502 }
503
504 /* check size */
505
506 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
507 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
508 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
509 status = -EINVAL;
510 goto abort_with_fw;
511 }
512
513 /* check id */
514 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
515 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
516 dev_err(dev, "Bad firmware file\n");
517 status = -EINVAL;
518 goto abort_with_fw;
519 }
520 hdr = (void *)(fw->data + hdr_offset);
521
522 status = myri10ge_validate_firmware(mgp, hdr);
523 if (status != 0)
524 goto abort_with_fw;
525
526 crc = crc32(~0, fw->data, fw->size);
527 for (i = 0; i < fw->size; i += 256) {
528 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
529 fw->data + i,
530 min(256U, (unsigned)(fw->size - i)));
531 mb();
532 readb(mgp->sram);
533 }
534 /* corruption checking is good for parity recovery and buggy chipset */
535 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
536 reread_crc = crc32(~0, fw->data, fw->size);
537 if (crc != reread_crc) {
538 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
539 (unsigned)fw->size, reread_crc, crc);
540 status = -EIO;
541 goto abort_with_fw;
542 }
543 *size = (u32) fw->size;
544
545 abort_with_fw:
546 release_firmware(fw);
547
548 abort_with_nothing:
549 return status;
550 }
551
552 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
553 {
554 struct mcp_gen_header *hdr;
555 struct device *dev = &mgp->pdev->dev;
556 const size_t bytes = sizeof(struct mcp_gen_header);
557 size_t hdr_offset;
558 int status;
559
560 /* find running firmware header */
561 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
562
563 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
564 dev_err(dev, "Running firmware has bad header offset (%d)\n",
565 (int)hdr_offset);
566 return -EIO;
567 }
568
569 /* copy header of running firmware from SRAM to host memory to
570 * validate firmware */
571 hdr = kmalloc(bytes, GFP_KERNEL);
572 if (hdr == NULL) {
573 dev_err(dev, "could not malloc firmware hdr\n");
574 return -ENOMEM;
575 }
576 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
577 status = myri10ge_validate_firmware(mgp, hdr);
578 kfree(hdr);
579
580 /* check to see if adopted firmware has bug where adopting
581 * it will cause broadcasts to be filtered unless the NIC
582 * is kept in ALLMULTI mode */
583 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
584 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
585 mgp->adopted_rx_filter_bug = 1;
586 dev_warn(dev, "Adopting fw %d.%d.%d: "
587 "working around rx filter bug\n",
588 mgp->fw_ver_major, mgp->fw_ver_minor,
589 mgp->fw_ver_tiny);
590 }
591 return status;
592 }
593
594 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
595 {
596 char __iomem *submit;
597 __be32 buf[16];
598 u32 dma_low, dma_high, size;
599 int status, i;
600
601 size = 0;
602 status = myri10ge_load_hotplug_firmware(mgp, &size);
603 if (status) {
604 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
605
606 /* Do not attempt to adopt firmware if there
607 * was a bad crc */
608 if (status == -EIO)
609 return status;
610
611 status = myri10ge_adopt_running_firmware(mgp);
612 if (status != 0) {
613 dev_err(&mgp->pdev->dev,
614 "failed to adopt running firmware\n");
615 return status;
616 }
617 dev_info(&mgp->pdev->dev,
618 "Successfully adopted running firmware\n");
619 if (mgp->tx.boundary == 4096) {
620 dev_warn(&mgp->pdev->dev,
621 "Using firmware currently running on NIC"
622 ". For optimal\n");
623 dev_warn(&mgp->pdev->dev,
624 "performance consider loading optimized "
625 "firmware\n");
626 dev_warn(&mgp->pdev->dev, "via hotplug\n");
627 }
628
629 mgp->fw_name = "adopted";
630 mgp->tx.boundary = 2048;
631 return status;
632 }
633
634 /* clear confirmation addr */
635 mgp->cmd->data = 0;
636 mb();
637
638 /* send a reload command to the bootstrap MCP, and wait for the
639 * response in the confirmation address. The firmware should
640 * write a -1 there to indicate it is alive and well
641 */
642 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
643 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
644
645 buf[0] = htonl(dma_high); /* confirm addr MSW */
646 buf[1] = htonl(dma_low); /* confirm addr LSW */
647 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
648
649 /* FIX: All newest firmware should un-protect the bottom of
650 * the sram before handoff. However, the very first interfaces
651 * do not. Therefore the handoff copy must skip the first 8 bytes
652 */
653 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
654 buf[4] = htonl(size - 8); /* length of code */
655 buf[5] = htonl(8); /* where to copy to */
656 buf[6] = htonl(0); /* where to jump to */
657
658 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
659
660 myri10ge_pio_copy(submit, &buf, sizeof(buf));
661 mb();
662 msleep(1);
663 mb();
664 i = 0;
665 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
666 msleep(1);
667 i++;
668 }
669 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
670 dev_err(&mgp->pdev->dev, "handoff failed\n");
671 return -ENXIO;
672 }
673 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
674 myri10ge_dummy_rdma(mgp, 1);
675
676 return 0;
677 }
678
679 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
680 {
681 struct myri10ge_cmd cmd;
682 int status;
683
684 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
685 | (addr[2] << 8) | addr[3]);
686
687 cmd.data1 = ((addr[4] << 8) | (addr[5]));
688
689 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
690 return status;
691 }
692
693 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
694 {
695 struct myri10ge_cmd cmd;
696 int status, ctl;
697
698 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
699 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
700
701 if (status) {
702 printk(KERN_ERR
703 "myri10ge: %s: Failed to set flow control mode\n",
704 mgp->dev->name);
705 return status;
706 }
707 mgp->pause = pause;
708 return 0;
709 }
710
711 static void
712 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
713 {
714 struct myri10ge_cmd cmd;
715 int status, ctl;
716
717 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
718 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
719 if (status)
720 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
721 mgp->dev->name);
722 }
723
724 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
725 {
726 struct myri10ge_cmd cmd;
727 int status;
728 u32 len;
729 struct page *dmatest_page;
730 dma_addr_t dmatest_bus;
731 char *test = " ";
732
733 dmatest_page = alloc_page(GFP_KERNEL);
734 if (!dmatest_page)
735 return -ENOMEM;
736 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
737 DMA_BIDIRECTIONAL);
738
739 /* Run a small DMA test.
740 * The magic multipliers to the length tell the firmware
741 * to do DMA read, write, or read+write tests. The
742 * results are returned in cmd.data0. The upper 16
743 * bits or the return is the number of transfers completed.
744 * The lower 16 bits is the time in 0.5us ticks that the
745 * transfers took to complete.
746 */
747
748 len = mgp->tx.boundary;
749
750 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
751 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
752 cmd.data2 = len * 0x10000;
753 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
754 if (status != 0) {
755 test = "read";
756 goto abort;
757 }
758 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
759 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
760 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
761 cmd.data2 = len * 0x1;
762 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
763 if (status != 0) {
764 test = "write";
765 goto abort;
766 }
767 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
768
769 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
770 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
771 cmd.data2 = len * 0x10001;
772 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
773 if (status != 0) {
774 test = "read/write";
775 goto abort;
776 }
777 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
778 (cmd.data0 & 0xffff);
779
780 abort:
781 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
782 put_page(dmatest_page);
783
784 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
785 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
786 test, status);
787
788 return status;
789 }
790
791 static int myri10ge_reset(struct myri10ge_priv *mgp)
792 {
793 struct myri10ge_cmd cmd;
794 int status;
795 size_t bytes;
796
797 /* try to send a reset command to the card to see if it
798 * is alive */
799 memset(&cmd, 0, sizeof(cmd));
800 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
801 if (status != 0) {
802 dev_err(&mgp->pdev->dev, "failed reset\n");
803 return -ENXIO;
804 }
805
806 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
807
808 /* Now exchange information about interrupts */
809
810 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
811 memset(mgp->rx_done.entry, 0, bytes);
812 cmd.data0 = (u32) bytes;
813 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
814 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
815 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
816 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
817
818 status |=
819 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
820 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
821 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
822 &cmd, 0);
823 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
824
825 status |= myri10ge_send_cmd
826 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
827 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
828 if (status != 0) {
829 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
830 return status;
831 }
832 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
833
834 memset(mgp->rx_done.entry, 0, bytes);
835
836 /* reset mcp/driver shared state back to 0 */
837 mgp->tx.req = 0;
838 mgp->tx.done = 0;
839 mgp->tx.pkt_start = 0;
840 mgp->tx.pkt_done = 0;
841 mgp->rx_big.cnt = 0;
842 mgp->rx_small.cnt = 0;
843 mgp->rx_done.idx = 0;
844 mgp->rx_done.cnt = 0;
845 mgp->link_changes = 0;
846 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
847 myri10ge_change_pause(mgp, mgp->pause);
848 myri10ge_set_multicast_list(mgp->dev);
849 return status;
850 }
851
852 static inline void
853 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
854 struct mcp_kreq_ether_recv *src)
855 {
856 __be32 low;
857
858 low = src->addr_low;
859 src->addr_low = htonl(DMA_32BIT_MASK);
860 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
861 mb();
862 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
863 mb();
864 src->addr_low = low;
865 put_be32(low, &dst->addr_low);
866 mb();
867 }
868
869 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
870 {
871 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
872
873 if ((skb->protocol == htons(ETH_P_8021Q)) &&
874 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
875 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
876 skb->csum = hw_csum;
877 skb->ip_summed = CHECKSUM_COMPLETE;
878 }
879 }
880
881 static inline void
882 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
883 struct skb_frag_struct *rx_frags, int len, int hlen)
884 {
885 struct skb_frag_struct *skb_frags;
886
887 skb->len = skb->data_len = len;
888 skb->truesize = len + sizeof(struct sk_buff);
889 /* attach the page(s) */
890
891 skb_frags = skb_shinfo(skb)->frags;
892 while (len > 0) {
893 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
894 len -= rx_frags->size;
895 skb_frags++;
896 rx_frags++;
897 skb_shinfo(skb)->nr_frags++;
898 }
899
900 /* pskb_may_pull is not available in irq context, but
901 * skb_pull() (for ether_pad and eth_type_trans()) requires
902 * the beginning of the packet in skb_headlen(), move it
903 * manually */
904 skb_copy_to_linear_data(skb, va, hlen);
905 skb_shinfo(skb)->frags[0].page_offset += hlen;
906 skb_shinfo(skb)->frags[0].size -= hlen;
907 skb->data_len -= hlen;
908 skb->tail += hlen;
909 skb_pull(skb, MXGEFW_PAD);
910 }
911
912 static void
913 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
914 int bytes, int watchdog)
915 {
916 struct page *page;
917 int idx;
918
919 if (unlikely(rx->watchdog_needed && !watchdog))
920 return;
921
922 /* try to refill entire ring */
923 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
924 idx = rx->fill_cnt & rx->mask;
925 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
926 /* we can use part of previous page */
927 get_page(rx->page);
928 } else {
929 /* we need a new page */
930 page =
931 alloc_pages(GFP_ATOMIC | __GFP_COMP,
932 MYRI10GE_ALLOC_ORDER);
933 if (unlikely(page == NULL)) {
934 if (rx->fill_cnt - rx->cnt < 16)
935 rx->watchdog_needed = 1;
936 return;
937 }
938 rx->page = page;
939 rx->page_offset = 0;
940 rx->bus = pci_map_page(mgp->pdev, page, 0,
941 MYRI10GE_ALLOC_SIZE,
942 PCI_DMA_FROMDEVICE);
943 }
944 rx->info[idx].page = rx->page;
945 rx->info[idx].page_offset = rx->page_offset;
946 /* note that this is the address of the start of the
947 * page */
948 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
949 rx->shadow[idx].addr_low =
950 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
951 rx->shadow[idx].addr_high =
952 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
953
954 /* start next packet on a cacheline boundary */
955 rx->page_offset += SKB_DATA_ALIGN(bytes);
956
957 #if MYRI10GE_ALLOC_SIZE > 4096
958 /* don't cross a 4KB boundary */
959 if ((rx->page_offset >> 12) !=
960 ((rx->page_offset + bytes - 1) >> 12))
961 rx->page_offset = (rx->page_offset + 4096) & ~4095;
962 #endif
963 rx->fill_cnt++;
964
965 /* copy 8 descriptors to the firmware at a time */
966 if ((idx & 7) == 7) {
967 if (rx->wc_fifo == NULL)
968 myri10ge_submit_8rx(&rx->lanai[idx - 7],
969 &rx->shadow[idx - 7]);
970 else {
971 mb();
972 myri10ge_pio_copy(rx->wc_fifo,
973 &rx->shadow[idx - 7], 64);
974 }
975 }
976 }
977 }
978
979 static inline void
980 myri10ge_unmap_rx_page(struct pci_dev *pdev,
981 struct myri10ge_rx_buffer_state *info, int bytes)
982 {
983 /* unmap the recvd page if we're the only or last user of it */
984 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
985 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
986 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
987 & ~(MYRI10GE_ALLOC_SIZE - 1)),
988 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
989 }
990 }
991
992 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
993 * page into an skb */
994
995 static inline int
996 myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
997 int bytes, int len, __wsum csum)
998 {
999 struct sk_buff *skb;
1000 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1001 int i, idx, hlen, remainder;
1002 struct pci_dev *pdev = mgp->pdev;
1003 struct net_device *dev = mgp->dev;
1004 u8 *va;
1005
1006 len += MXGEFW_PAD;
1007 idx = rx->cnt & rx->mask;
1008 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1009 prefetch(va);
1010 /* Fill skb_frag_struct(s) with data from our receive */
1011 for (i = 0, remainder = len; remainder > 0; i++) {
1012 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1013 rx_frags[i].page = rx->info[idx].page;
1014 rx_frags[i].page_offset = rx->info[idx].page_offset;
1015 if (remainder < MYRI10GE_ALLOC_SIZE)
1016 rx_frags[i].size = remainder;
1017 else
1018 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1019 rx->cnt++;
1020 idx = rx->cnt & rx->mask;
1021 remainder -= MYRI10GE_ALLOC_SIZE;
1022 }
1023
1024 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1025
1026 /* allocate an skb to attach the page(s) to. */
1027
1028 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1029 if (unlikely(skb == NULL)) {
1030 mgp->stats.rx_dropped++;
1031 do {
1032 i--;
1033 put_page(rx_frags[i].page);
1034 } while (i != 0);
1035 return 0;
1036 }
1037
1038 /* Attach the pages to the skb, and trim off any padding */
1039 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1040 if (skb_shinfo(skb)->frags[0].size <= 0) {
1041 put_page(skb_shinfo(skb)->frags[0].page);
1042 skb_shinfo(skb)->nr_frags = 0;
1043 }
1044 skb->protocol = eth_type_trans(skb, dev);
1045
1046 if (mgp->csum_flag) {
1047 if ((skb->protocol == htons(ETH_P_IP)) ||
1048 (skb->protocol == htons(ETH_P_IPV6))) {
1049 skb->csum = csum;
1050 skb->ip_summed = CHECKSUM_COMPLETE;
1051 } else
1052 myri10ge_vlan_ip_csum(skb, csum);
1053 }
1054 netif_receive_skb(skb);
1055 dev->last_rx = jiffies;
1056 return 1;
1057 }
1058
1059 static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1060 {
1061 struct pci_dev *pdev = mgp->pdev;
1062 struct myri10ge_tx_buf *tx = &mgp->tx;
1063 struct sk_buff *skb;
1064 int idx, len;
1065
1066 while (tx->pkt_done != mcp_index) {
1067 idx = tx->done & tx->mask;
1068 skb = tx->info[idx].skb;
1069
1070 /* Mark as free */
1071 tx->info[idx].skb = NULL;
1072 if (tx->info[idx].last) {
1073 tx->pkt_done++;
1074 tx->info[idx].last = 0;
1075 }
1076 tx->done++;
1077 len = pci_unmap_len(&tx->info[idx], len);
1078 pci_unmap_len_set(&tx->info[idx], len, 0);
1079 if (skb) {
1080 mgp->stats.tx_bytes += skb->len;
1081 mgp->stats.tx_packets++;
1082 dev_kfree_skb_irq(skb);
1083 if (len)
1084 pci_unmap_single(pdev,
1085 pci_unmap_addr(&tx->info[idx],
1086 bus), len,
1087 PCI_DMA_TODEVICE);
1088 } else {
1089 if (len)
1090 pci_unmap_page(pdev,
1091 pci_unmap_addr(&tx->info[idx],
1092 bus), len,
1093 PCI_DMA_TODEVICE);
1094 }
1095 }
1096 /* start the queue if we've stopped it */
1097 if (netif_queue_stopped(mgp->dev)
1098 && tx->req - tx->done < (tx->mask >> 1)) {
1099 mgp->wake_queue++;
1100 netif_wake_queue(mgp->dev);
1101 }
1102 }
1103
1104 static inline int myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int budget)
1105 {
1106 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1107 unsigned long rx_bytes = 0;
1108 unsigned long rx_packets = 0;
1109 unsigned long rx_ok;
1110
1111 int idx = rx_done->idx;
1112 int cnt = rx_done->cnt;
1113 int work_done = 0;
1114 u16 length;
1115 __wsum checksum;
1116
1117 while (rx_done->entry[idx].length != 0 && work_done++ < budget) {
1118 length = ntohs(rx_done->entry[idx].length);
1119 rx_done->entry[idx].length = 0;
1120 checksum = csum_unfold(rx_done->entry[idx].checksum);
1121 if (length <= mgp->small_bytes)
1122 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1123 mgp->small_bytes,
1124 length, checksum);
1125 else
1126 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1127 mgp->big_bytes,
1128 length, checksum);
1129 rx_packets += rx_ok;
1130 rx_bytes += rx_ok * (unsigned long)length;
1131 cnt++;
1132 idx = cnt & (myri10ge_max_intr_slots - 1);
1133 }
1134 rx_done->idx = idx;
1135 rx_done->cnt = cnt;
1136 mgp->stats.rx_packets += rx_packets;
1137 mgp->stats.rx_bytes += rx_bytes;
1138
1139 /* restock receive rings if needed */
1140 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1141 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1142 mgp->small_bytes + MXGEFW_PAD, 0);
1143 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1144 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1145
1146 return work_done;
1147 }
1148
1149 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1150 {
1151 struct mcp_irq_data *stats = mgp->fw_stats;
1152
1153 if (unlikely(stats->stats_updated)) {
1154 unsigned link_up = ntohl(stats->link_up);
1155 if (mgp->link_state != link_up) {
1156 mgp->link_state = link_up;
1157
1158 if (mgp->link_state == MXGEFW_LINK_UP) {
1159 if (netif_msg_link(mgp))
1160 printk(KERN_INFO
1161 "myri10ge: %s: link up\n",
1162 mgp->dev->name);
1163 netif_carrier_on(mgp->dev);
1164 mgp->link_changes++;
1165 } else {
1166 if (netif_msg_link(mgp))
1167 printk(KERN_INFO
1168 "myri10ge: %s: link %s\n",
1169 mgp->dev->name,
1170 (link_up == MXGEFW_LINK_MYRINET ?
1171 "mismatch (Myrinet detected)" :
1172 "down"));
1173 netif_carrier_off(mgp->dev);
1174 mgp->link_changes++;
1175 }
1176 }
1177 if (mgp->rdma_tags_available !=
1178 ntohl(mgp->fw_stats->rdma_tags_available)) {
1179 mgp->rdma_tags_available =
1180 ntohl(mgp->fw_stats->rdma_tags_available);
1181 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1182 "%d tags left\n", mgp->dev->name,
1183 mgp->rdma_tags_available);
1184 }
1185 mgp->down_cnt += stats->link_down;
1186 if (stats->link_down)
1187 wake_up(&mgp->down_wq);
1188 }
1189 }
1190
1191 static int myri10ge_poll(struct napi_struct *napi, int budget)
1192 {
1193 struct myri10ge_priv *mgp = container_of(napi, struct myri10ge_priv, napi);
1194 struct net_device *netdev = mgp->dev;
1195 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1196 int work_done;
1197
1198 /* process as many rx events as NAPI will allow */
1199 work_done = myri10ge_clean_rx_done(mgp, budget);
1200
1201 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1202 netif_rx_complete(netdev, napi);
1203 put_be32(htonl(3), mgp->irq_claim);
1204 }
1205 return work_done;
1206 }
1207
1208 static irqreturn_t myri10ge_intr(int irq, void *arg)
1209 {
1210 struct myri10ge_priv *mgp = arg;
1211 struct mcp_irq_data *stats = mgp->fw_stats;
1212 struct myri10ge_tx_buf *tx = &mgp->tx;
1213 u32 send_done_count;
1214 int i;
1215
1216 /* make sure it is our IRQ, and that the DMA has finished */
1217 if (unlikely(!stats->valid))
1218 return (IRQ_NONE);
1219
1220 /* low bit indicates receives are present, so schedule
1221 * napi poll handler */
1222 if (stats->valid & 1)
1223 netif_rx_schedule(mgp->dev, &mgp->napi);
1224
1225 if (!mgp->msi_enabled) {
1226 put_be32(0, mgp->irq_deassert);
1227 if (!myri10ge_deassert_wait)
1228 stats->valid = 0;
1229 mb();
1230 } else
1231 stats->valid = 0;
1232
1233 /* Wait for IRQ line to go low, if using INTx */
1234 i = 0;
1235 while (1) {
1236 i++;
1237 /* check for transmit completes and receives */
1238 send_done_count = ntohl(stats->send_done_count);
1239 if (send_done_count != tx->pkt_done)
1240 myri10ge_tx_done(mgp, (int)send_done_count);
1241 if (unlikely(i > myri10ge_max_irq_loops)) {
1242 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1243 mgp->dev->name);
1244 stats->valid = 0;
1245 schedule_work(&mgp->watchdog_work);
1246 }
1247 if (likely(stats->valid == 0))
1248 break;
1249 cpu_relax();
1250 barrier();
1251 }
1252
1253 myri10ge_check_statblock(mgp);
1254
1255 put_be32(htonl(3), mgp->irq_claim + 1);
1256 return (IRQ_HANDLED);
1257 }
1258
1259 static int
1260 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1261 {
1262 cmd->autoneg = AUTONEG_DISABLE;
1263 cmd->speed = SPEED_10000;
1264 cmd->duplex = DUPLEX_FULL;
1265 return 0;
1266 }
1267
1268 static void
1269 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1270 {
1271 struct myri10ge_priv *mgp = netdev_priv(netdev);
1272
1273 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1274 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1275 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1276 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1277 }
1278
1279 static int
1280 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1281 {
1282 struct myri10ge_priv *mgp = netdev_priv(netdev);
1283 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1284 return 0;
1285 }
1286
1287 static int
1288 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1289 {
1290 struct myri10ge_priv *mgp = netdev_priv(netdev);
1291
1292 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1293 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1294 return 0;
1295 }
1296
1297 static void
1298 myri10ge_get_pauseparam(struct net_device *netdev,
1299 struct ethtool_pauseparam *pause)
1300 {
1301 struct myri10ge_priv *mgp = netdev_priv(netdev);
1302
1303 pause->autoneg = 0;
1304 pause->rx_pause = mgp->pause;
1305 pause->tx_pause = mgp->pause;
1306 }
1307
1308 static int
1309 myri10ge_set_pauseparam(struct net_device *netdev,
1310 struct ethtool_pauseparam *pause)
1311 {
1312 struct myri10ge_priv *mgp = netdev_priv(netdev);
1313
1314 if (pause->tx_pause != mgp->pause)
1315 return myri10ge_change_pause(mgp, pause->tx_pause);
1316 if (pause->rx_pause != mgp->pause)
1317 return myri10ge_change_pause(mgp, pause->tx_pause);
1318 if (pause->autoneg != 0)
1319 return -EINVAL;
1320 return 0;
1321 }
1322
1323 static void
1324 myri10ge_get_ringparam(struct net_device *netdev,
1325 struct ethtool_ringparam *ring)
1326 {
1327 struct myri10ge_priv *mgp = netdev_priv(netdev);
1328
1329 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1330 ring->rx_max_pending = mgp->rx_big.mask + 1;
1331 ring->rx_jumbo_max_pending = 0;
1332 ring->tx_max_pending = mgp->rx_small.mask + 1;
1333 ring->rx_mini_pending = ring->rx_mini_max_pending;
1334 ring->rx_pending = ring->rx_max_pending;
1335 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1336 ring->tx_pending = ring->tx_max_pending;
1337 }
1338
1339 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1340 {
1341 struct myri10ge_priv *mgp = netdev_priv(netdev);
1342 if (mgp->csum_flag)
1343 return 1;
1344 else
1345 return 0;
1346 }
1347
1348 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1349 {
1350 struct myri10ge_priv *mgp = netdev_priv(netdev);
1351 if (csum_enabled)
1352 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1353 else
1354 mgp->csum_flag = 0;
1355 return 0;
1356 }
1357
1358 static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1359 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1360 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1361 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1362 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1363 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1364 "tx_heartbeat_errors", "tx_window_errors",
1365 /* device-specific stats */
1366 "tx_boundary", "WC", "irq", "MSI",
1367 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1368 "serial_number", "tx_pkt_start", "tx_pkt_done",
1369 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1370 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1371 "link_changes", "link_up", "dropped_link_overflow",
1372 "dropped_link_error_or_filtered",
1373 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1374 "dropped_unicast_filtered", "dropped_multicast_filtered",
1375 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1376 "dropped_no_big_buffer"
1377 };
1378
1379 #define MYRI10GE_NET_STATS_LEN 21
1380 #define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1381
1382 static void
1383 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1384 {
1385 switch (stringset) {
1386 case ETH_SS_STATS:
1387 memcpy(data, *myri10ge_gstrings_stats,
1388 sizeof(myri10ge_gstrings_stats));
1389 break;
1390 }
1391 }
1392
1393 static int myri10ge_get_stats_count(struct net_device *netdev)
1394 {
1395 return MYRI10GE_STATS_LEN;
1396 }
1397
1398 static void
1399 myri10ge_get_ethtool_stats(struct net_device *netdev,
1400 struct ethtool_stats *stats, u64 * data)
1401 {
1402 struct myri10ge_priv *mgp = netdev_priv(netdev);
1403 int i;
1404
1405 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1406 data[i] = ((unsigned long *)&mgp->stats)[i];
1407
1408 data[i++] = (unsigned int)mgp->tx.boundary;
1409 data[i++] = (unsigned int)mgp->wc_enabled;
1410 data[i++] = (unsigned int)mgp->pdev->irq;
1411 data[i++] = (unsigned int)mgp->msi_enabled;
1412 data[i++] = (unsigned int)mgp->read_dma;
1413 data[i++] = (unsigned int)mgp->write_dma;
1414 data[i++] = (unsigned int)mgp->read_write_dma;
1415 data[i++] = (unsigned int)mgp->serial_number;
1416 data[i++] = (unsigned int)mgp->tx.pkt_start;
1417 data[i++] = (unsigned int)mgp->tx.pkt_done;
1418 data[i++] = (unsigned int)mgp->tx.req;
1419 data[i++] = (unsigned int)mgp->tx.done;
1420 data[i++] = (unsigned int)mgp->rx_small.cnt;
1421 data[i++] = (unsigned int)mgp->rx_big.cnt;
1422 data[i++] = (unsigned int)mgp->wake_queue;
1423 data[i++] = (unsigned int)mgp->stop_queue;
1424 data[i++] = (unsigned int)mgp->watchdog_resets;
1425 data[i++] = (unsigned int)mgp->tx_linearized;
1426 data[i++] = (unsigned int)mgp->link_changes;
1427 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1428 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1429 data[i++] =
1430 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1431 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1432 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1433 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1434 data[i++] =
1435 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
1436 data[i++] =
1437 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
1438 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1439 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1440 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1441 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1442 }
1443
1444 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1445 {
1446 struct myri10ge_priv *mgp = netdev_priv(netdev);
1447 mgp->msg_enable = value;
1448 }
1449
1450 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1451 {
1452 struct myri10ge_priv *mgp = netdev_priv(netdev);
1453 return mgp->msg_enable;
1454 }
1455
1456 static const struct ethtool_ops myri10ge_ethtool_ops = {
1457 .get_settings = myri10ge_get_settings,
1458 .get_drvinfo = myri10ge_get_drvinfo,
1459 .get_coalesce = myri10ge_get_coalesce,
1460 .set_coalesce = myri10ge_set_coalesce,
1461 .get_pauseparam = myri10ge_get_pauseparam,
1462 .set_pauseparam = myri10ge_set_pauseparam,
1463 .get_ringparam = myri10ge_get_ringparam,
1464 .get_rx_csum = myri10ge_get_rx_csum,
1465 .set_rx_csum = myri10ge_set_rx_csum,
1466 .get_tx_csum = ethtool_op_get_tx_csum,
1467 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1468 .get_sg = ethtool_op_get_sg,
1469 .set_sg = ethtool_op_set_sg,
1470 .get_tso = ethtool_op_get_tso,
1471 .set_tso = ethtool_op_set_tso,
1472 .get_link = ethtool_op_get_link,
1473 .get_strings = myri10ge_get_strings,
1474 .get_stats_count = myri10ge_get_stats_count,
1475 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1476 .set_msglevel = myri10ge_set_msglevel,
1477 .get_msglevel = myri10ge_get_msglevel
1478 };
1479
1480 static int myri10ge_allocate_rings(struct net_device *dev)
1481 {
1482 struct myri10ge_priv *mgp;
1483 struct myri10ge_cmd cmd;
1484 int tx_ring_size, rx_ring_size;
1485 int tx_ring_entries, rx_ring_entries;
1486 int i, status;
1487 size_t bytes;
1488
1489 mgp = netdev_priv(dev);
1490
1491 /* get ring sizes */
1492
1493 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1494 tx_ring_size = cmd.data0;
1495 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1496 if (status != 0)
1497 return status;
1498 rx_ring_size = cmd.data0;
1499
1500 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1501 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1502 mgp->tx.mask = tx_ring_entries - 1;
1503 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1504
1505 status = -ENOMEM;
1506
1507 /* allocate the host shadow rings */
1508
1509 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1510 * sizeof(*mgp->tx.req_list);
1511 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1512 if (mgp->tx.req_bytes == NULL)
1513 goto abort_with_nothing;
1514
1515 /* ensure req_list entries are aligned to 8 bytes */
1516 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1517 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1518
1519 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1520 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1521 if (mgp->rx_small.shadow == NULL)
1522 goto abort_with_tx_req_bytes;
1523
1524 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1525 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1526 if (mgp->rx_big.shadow == NULL)
1527 goto abort_with_rx_small_shadow;
1528
1529 /* allocate the host info rings */
1530
1531 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1532 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1533 if (mgp->tx.info == NULL)
1534 goto abort_with_rx_big_shadow;
1535
1536 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1537 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1538 if (mgp->rx_small.info == NULL)
1539 goto abort_with_tx_info;
1540
1541 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1542 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1543 if (mgp->rx_big.info == NULL)
1544 goto abort_with_rx_small_info;
1545
1546 /* Fill the receive rings */
1547 mgp->rx_big.cnt = 0;
1548 mgp->rx_small.cnt = 0;
1549 mgp->rx_big.fill_cnt = 0;
1550 mgp->rx_small.fill_cnt = 0;
1551 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1552 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1553 mgp->rx_small.watchdog_needed = 0;
1554 mgp->rx_big.watchdog_needed = 0;
1555 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1556 mgp->small_bytes + MXGEFW_PAD, 0);
1557
1558 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1559 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1560 dev->name, mgp->rx_small.fill_cnt);
1561 goto abort_with_rx_small_ring;
1562 }
1563
1564 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1565 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1566 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1567 dev->name, mgp->rx_big.fill_cnt);
1568 goto abort_with_rx_big_ring;
1569 }
1570
1571 return 0;
1572
1573 abort_with_rx_big_ring:
1574 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1575 int idx = i & mgp->rx_big.mask;
1576 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1577 mgp->big_bytes);
1578 put_page(mgp->rx_big.info[idx].page);
1579 }
1580
1581 abort_with_rx_small_ring:
1582 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1583 int idx = i & mgp->rx_small.mask;
1584 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1585 mgp->small_bytes + MXGEFW_PAD);
1586 put_page(mgp->rx_small.info[idx].page);
1587 }
1588
1589 kfree(mgp->rx_big.info);
1590
1591 abort_with_rx_small_info:
1592 kfree(mgp->rx_small.info);
1593
1594 abort_with_tx_info:
1595 kfree(mgp->tx.info);
1596
1597 abort_with_rx_big_shadow:
1598 kfree(mgp->rx_big.shadow);
1599
1600 abort_with_rx_small_shadow:
1601 kfree(mgp->rx_small.shadow);
1602
1603 abort_with_tx_req_bytes:
1604 kfree(mgp->tx.req_bytes);
1605 mgp->tx.req_bytes = NULL;
1606 mgp->tx.req_list = NULL;
1607
1608 abort_with_nothing:
1609 return status;
1610 }
1611
1612 static void myri10ge_free_rings(struct net_device *dev)
1613 {
1614 struct myri10ge_priv *mgp;
1615 struct sk_buff *skb;
1616 struct myri10ge_tx_buf *tx;
1617 int i, len, idx;
1618
1619 mgp = netdev_priv(dev);
1620
1621 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1622 idx = i & mgp->rx_big.mask;
1623 if (i == mgp->rx_big.fill_cnt - 1)
1624 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1625 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1626 mgp->big_bytes);
1627 put_page(mgp->rx_big.info[idx].page);
1628 }
1629
1630 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1631 idx = i & mgp->rx_small.mask;
1632 if (i == mgp->rx_small.fill_cnt - 1)
1633 mgp->rx_small.info[idx].page_offset =
1634 MYRI10GE_ALLOC_SIZE;
1635 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1636 mgp->small_bytes + MXGEFW_PAD);
1637 put_page(mgp->rx_small.info[idx].page);
1638 }
1639 tx = &mgp->tx;
1640 while (tx->done != tx->req) {
1641 idx = tx->done & tx->mask;
1642 skb = tx->info[idx].skb;
1643
1644 /* Mark as free */
1645 tx->info[idx].skb = NULL;
1646 tx->done++;
1647 len = pci_unmap_len(&tx->info[idx], len);
1648 pci_unmap_len_set(&tx->info[idx], len, 0);
1649 if (skb) {
1650 mgp->stats.tx_dropped++;
1651 dev_kfree_skb_any(skb);
1652 if (len)
1653 pci_unmap_single(mgp->pdev,
1654 pci_unmap_addr(&tx->info[idx],
1655 bus), len,
1656 PCI_DMA_TODEVICE);
1657 } else {
1658 if (len)
1659 pci_unmap_page(mgp->pdev,
1660 pci_unmap_addr(&tx->info[idx],
1661 bus), len,
1662 PCI_DMA_TODEVICE);
1663 }
1664 }
1665 kfree(mgp->rx_big.info);
1666
1667 kfree(mgp->rx_small.info);
1668
1669 kfree(mgp->tx.info);
1670
1671 kfree(mgp->rx_big.shadow);
1672
1673 kfree(mgp->rx_small.shadow);
1674
1675 kfree(mgp->tx.req_bytes);
1676 mgp->tx.req_bytes = NULL;
1677 mgp->tx.req_list = NULL;
1678 }
1679
1680 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1681 {
1682 struct pci_dev *pdev = mgp->pdev;
1683 int status;
1684
1685 if (myri10ge_msi) {
1686 status = pci_enable_msi(pdev);
1687 if (status != 0)
1688 dev_err(&pdev->dev,
1689 "Error %d setting up MSI; falling back to xPIC\n",
1690 status);
1691 else
1692 mgp->msi_enabled = 1;
1693 } else {
1694 mgp->msi_enabled = 0;
1695 }
1696 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1697 mgp->dev->name, mgp);
1698 if (status != 0) {
1699 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1700 if (mgp->msi_enabled)
1701 pci_disable_msi(pdev);
1702 }
1703 return status;
1704 }
1705
1706 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1707 {
1708 struct pci_dev *pdev = mgp->pdev;
1709
1710 free_irq(pdev->irq, mgp);
1711 if (mgp->msi_enabled)
1712 pci_disable_msi(pdev);
1713 }
1714
1715 static int myri10ge_open(struct net_device *dev)
1716 {
1717 struct myri10ge_priv *mgp;
1718 struct myri10ge_cmd cmd;
1719 int status, big_pow2;
1720
1721 mgp = netdev_priv(dev);
1722
1723 if (mgp->running != MYRI10GE_ETH_STOPPED)
1724 return -EBUSY;
1725
1726 mgp->running = MYRI10GE_ETH_STARTING;
1727 status = myri10ge_reset(mgp);
1728 if (status != 0) {
1729 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1730 goto abort_with_nothing;
1731 }
1732
1733 status = myri10ge_request_irq(mgp);
1734 if (status != 0)
1735 goto abort_with_nothing;
1736
1737 /* decide what small buffer size to use. For good TCP rx
1738 * performance, it is important to not receive 1514 byte
1739 * frames into jumbo buffers, as it confuses the socket buffer
1740 * accounting code, leading to drops and erratic performance.
1741 */
1742
1743 if (dev->mtu <= ETH_DATA_LEN)
1744 /* enough for a TCP header */
1745 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1746 ? (128 - MXGEFW_PAD)
1747 : (SMP_CACHE_BYTES - MXGEFW_PAD);
1748 else
1749 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1750 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
1751
1752 /* Override the small buffer size? */
1753 if (myri10ge_small_bytes > 0)
1754 mgp->small_bytes = myri10ge_small_bytes;
1755
1756 /* get the lanai pointers to the send and receive rings */
1757
1758 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1759 mgp->tx.lanai =
1760 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1761
1762 status |=
1763 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1764 mgp->rx_small.lanai =
1765 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1766
1767 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1768 mgp->rx_big.lanai =
1769 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1770
1771 if (status != 0) {
1772 printk(KERN_ERR
1773 "myri10ge: %s: failed to get ring sizes or locations\n",
1774 dev->name);
1775 mgp->running = MYRI10GE_ETH_STOPPED;
1776 goto abort_with_irq;
1777 }
1778
1779 if (myri10ge_wcfifo && mgp->wc_enabled) {
1780 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1781 mgp->rx_small.wc_fifo =
1782 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1783 mgp->rx_big.wc_fifo =
1784 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1785 } else {
1786 mgp->tx.wc_fifo = NULL;
1787 mgp->rx_small.wc_fifo = NULL;
1788 mgp->rx_big.wc_fifo = NULL;
1789 }
1790
1791 /* Firmware needs the big buff size as a power of 2. Lie and
1792 * tell him the buffer is larger, because we only use 1
1793 * buffer/pkt, and the mtu will prevent overruns.
1794 */
1795 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1796 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1797 while (!is_power_of_2(big_pow2))
1798 big_pow2++;
1799 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1800 } else {
1801 big_pow2 = MYRI10GE_ALLOC_SIZE;
1802 mgp->big_bytes = big_pow2;
1803 }
1804
1805 status = myri10ge_allocate_rings(dev);
1806 if (status != 0)
1807 goto abort_with_irq;
1808
1809 /* now give firmware buffers sizes, and MTU */
1810 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1811 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1812 cmd.data0 = mgp->small_bytes;
1813 status |=
1814 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1815 cmd.data0 = big_pow2;
1816 status |=
1817 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1818 if (status) {
1819 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1820 dev->name);
1821 goto abort_with_rings;
1822 }
1823
1824 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1825 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1826 cmd.data2 = sizeof(struct mcp_irq_data);
1827 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1828 if (status == -ENOSYS) {
1829 dma_addr_t bus = mgp->fw_stats_bus;
1830 bus += offsetof(struct mcp_irq_data, send_done_count);
1831 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1832 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1833 status = myri10ge_send_cmd(mgp,
1834 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1835 &cmd, 0);
1836 /* Firmware cannot support multicast without STATS_DMA_V2 */
1837 mgp->fw_multicast_support = 0;
1838 } else {
1839 mgp->fw_multicast_support = 1;
1840 }
1841 if (status) {
1842 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1843 dev->name);
1844 goto abort_with_rings;
1845 }
1846
1847 mgp->link_state = htonl(~0U);
1848 mgp->rdma_tags_available = 15;
1849
1850 napi_enable(&mgp->napi); /* must happen prior to any irq */
1851
1852 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1853 if (status) {
1854 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1855 dev->name);
1856 goto abort_with_rings;
1857 }
1858
1859 mgp->wake_queue = 0;
1860 mgp->stop_queue = 0;
1861 mgp->running = MYRI10GE_ETH_RUNNING;
1862 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1863 add_timer(&mgp->watchdog_timer);
1864 netif_wake_queue(dev);
1865 return 0;
1866
1867 abort_with_rings:
1868 myri10ge_free_rings(dev);
1869
1870 abort_with_irq:
1871 myri10ge_free_irq(mgp);
1872
1873 abort_with_nothing:
1874 mgp->running = MYRI10GE_ETH_STOPPED;
1875 return -ENOMEM;
1876 }
1877
1878 static int myri10ge_close(struct net_device *dev)
1879 {
1880 struct myri10ge_priv *mgp;
1881 struct myri10ge_cmd cmd;
1882 int status, old_down_cnt;
1883
1884 mgp = netdev_priv(dev);
1885
1886 if (mgp->running != MYRI10GE_ETH_RUNNING)
1887 return 0;
1888
1889 if (mgp->tx.req_bytes == NULL)
1890 return 0;
1891
1892 del_timer_sync(&mgp->watchdog_timer);
1893 mgp->running = MYRI10GE_ETH_STOPPING;
1894 napi_disable(&mgp->napi);
1895 netif_carrier_off(dev);
1896 netif_stop_queue(dev);
1897 old_down_cnt = mgp->down_cnt;
1898 mb();
1899 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1900 if (status)
1901 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1902 dev->name);
1903
1904 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1905 if (old_down_cnt == mgp->down_cnt)
1906 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1907
1908 netif_tx_disable(dev);
1909 myri10ge_free_irq(mgp);
1910 myri10ge_free_rings(dev);
1911
1912 mgp->running = MYRI10GE_ETH_STOPPED;
1913 return 0;
1914 }
1915
1916 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1917 * backwards one at a time and handle ring wraps */
1918
1919 static inline void
1920 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1921 struct mcp_kreq_ether_send *src, int cnt)
1922 {
1923 int idx, starting_slot;
1924 starting_slot = tx->req;
1925 while (cnt > 1) {
1926 cnt--;
1927 idx = (starting_slot + cnt) & tx->mask;
1928 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1929 mb();
1930 }
1931 }
1932
1933 /*
1934 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1935 * at most 32 bytes at a time, so as to avoid involving the software
1936 * pio handler in the nic. We re-write the first segment's flags
1937 * to mark them valid only after writing the entire chain.
1938 */
1939
1940 static inline void
1941 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1942 int cnt)
1943 {
1944 int idx, i;
1945 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1946 struct mcp_kreq_ether_send *srcp;
1947 u8 last_flags;
1948
1949 idx = tx->req & tx->mask;
1950
1951 last_flags = src->flags;
1952 src->flags = 0;
1953 mb();
1954 dst = dstp = &tx->lanai[idx];
1955 srcp = src;
1956
1957 if ((idx + cnt) < tx->mask) {
1958 for (i = 0; i < (cnt - 1); i += 2) {
1959 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1960 mb(); /* force write every 32 bytes */
1961 srcp += 2;
1962 dstp += 2;
1963 }
1964 } else {
1965 /* submit all but the first request, and ensure
1966 * that it is submitted below */
1967 myri10ge_submit_req_backwards(tx, src, cnt);
1968 i = 0;
1969 }
1970 if (i < cnt) {
1971 /* submit the first request */
1972 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1973 mb(); /* barrier before setting valid flag */
1974 }
1975
1976 /* re-write the last 32-bits with the valid flags */
1977 src->flags = last_flags;
1978 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
1979 tx->req += cnt;
1980 mb();
1981 }
1982
1983 static inline void
1984 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1985 struct mcp_kreq_ether_send *src, int cnt)
1986 {
1987 tx->req += cnt;
1988 mb();
1989 while (cnt >= 4) {
1990 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1991 mb();
1992 src += 4;
1993 cnt -= 4;
1994 }
1995 if (cnt > 0) {
1996 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1997 * needs to be so that we don't overrun it */
1998 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1999 src, 64);
2000 mb();
2001 }
2002 }
2003
2004 /*
2005 * Transmit a packet. We need to split the packet so that a single
2006 * segment does not cross myri10ge->tx.boundary, so this makes segment
2007 * counting tricky. So rather than try to count segments up front, we
2008 * just give up if there are too few segments to hold a reasonably
2009 * fragmented packet currently available. If we run
2010 * out of segments while preparing a packet for DMA, we just linearize
2011 * it and try again.
2012 */
2013
2014 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2015 {
2016 struct myri10ge_priv *mgp = netdev_priv(dev);
2017 struct mcp_kreq_ether_send *req;
2018 struct myri10ge_tx_buf *tx = &mgp->tx;
2019 struct skb_frag_struct *frag;
2020 dma_addr_t bus;
2021 u32 low;
2022 __be32 high_swapped;
2023 unsigned int len;
2024 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2025 u16 pseudo_hdr_offset, cksum_offset;
2026 int cum_len, seglen, boundary, rdma_count;
2027 u8 flags, odd_flag;
2028
2029 again:
2030 req = tx->req_list;
2031 avail = tx->mask - 1 - (tx->req - tx->done);
2032
2033 mss = 0;
2034 max_segments = MXGEFW_MAX_SEND_DESC;
2035
2036 if (skb_is_gso(skb)) {
2037 mss = skb_shinfo(skb)->gso_size;
2038 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2039 }
2040
2041 if ((unlikely(avail < max_segments))) {
2042 /* we are out of transmit resources */
2043 mgp->stop_queue++;
2044 netif_stop_queue(dev);
2045 return 1;
2046 }
2047
2048 /* Setup checksum offloading, if needed */
2049 cksum_offset = 0;
2050 pseudo_hdr_offset = 0;
2051 odd_flag = 0;
2052 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2053 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2054 cksum_offset = skb_transport_offset(skb);
2055 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2056 /* If the headers are excessively large, then we must
2057 * fall back to a software checksum */
2058 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
2059 if (skb_checksum_help(skb))
2060 goto drop;
2061 cksum_offset = 0;
2062 pseudo_hdr_offset = 0;
2063 } else {
2064 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2065 flags |= MXGEFW_FLAGS_CKSUM;
2066 }
2067 }
2068
2069 cum_len = 0;
2070
2071 if (mss) { /* TSO */
2072 /* this removes any CKSUM flag from before */
2073 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2074
2075 /* negative cum_len signifies to the
2076 * send loop that we are still in the
2077 * header portion of the TSO packet.
2078 * TSO header must be at most 134 bytes long */
2079 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2080
2081 /* for TSO, pseudo_hdr_offset holds mss.
2082 * The firmware figures out where to put
2083 * the checksum by parsing the header. */
2084 pseudo_hdr_offset = mss;
2085 } else
2086 /* Mark small packets, and pad out tiny packets */
2087 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2088 flags |= MXGEFW_FLAGS_SMALL;
2089
2090 /* pad frames to at least ETH_ZLEN bytes */
2091 if (unlikely(skb->len < ETH_ZLEN)) {
2092 if (skb_padto(skb, ETH_ZLEN)) {
2093 /* The packet is gone, so we must
2094 * return 0 */
2095 mgp->stats.tx_dropped += 1;
2096 return 0;
2097 }
2098 /* adjust the len to account for the zero pad
2099 * so that the nic can know how long it is */
2100 skb->len = ETH_ZLEN;
2101 }
2102 }
2103
2104 /* map the skb for DMA */
2105 len = skb->len - skb->data_len;
2106 idx = tx->req & tx->mask;
2107 tx->info[idx].skb = skb;
2108 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2109 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2110 pci_unmap_len_set(&tx->info[idx], len, len);
2111
2112 frag_cnt = skb_shinfo(skb)->nr_frags;
2113 frag_idx = 0;
2114 count = 0;
2115 rdma_count = 0;
2116
2117 /* "rdma_count" is the number of RDMAs belonging to the
2118 * current packet BEFORE the current send request. For
2119 * non-TSO packets, this is equal to "count".
2120 * For TSO packets, rdma_count needs to be reset
2121 * to 0 after a segment cut.
2122 *
2123 * The rdma_count field of the send request is
2124 * the number of RDMAs of the packet starting at
2125 * that request. For TSO send requests with one ore more cuts
2126 * in the middle, this is the number of RDMAs starting
2127 * after the last cut in the request. All previous
2128 * segments before the last cut implicitly have 1 RDMA.
2129 *
2130 * Since the number of RDMAs is not known beforehand,
2131 * it must be filled-in retroactively - after each
2132 * segmentation cut or at the end of the entire packet.
2133 */
2134
2135 while (1) {
2136 /* Break the SKB or Fragment up into pieces which
2137 * do not cross mgp->tx.boundary */
2138 low = MYRI10GE_LOWPART_TO_U32(bus);
2139 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2140 while (len) {
2141 u8 flags_next;
2142 int cum_len_next;
2143
2144 if (unlikely(count == max_segments))
2145 goto abort_linearize;
2146
2147 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2148 seglen = boundary - low;
2149 if (seglen > len)
2150 seglen = len;
2151 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2152 cum_len_next = cum_len + seglen;
2153 if (mss) { /* TSO */
2154 (req - rdma_count)->rdma_count = rdma_count + 1;
2155
2156 if (likely(cum_len >= 0)) { /* payload */
2157 int next_is_first, chop;
2158
2159 chop = (cum_len_next > mss);
2160 cum_len_next = cum_len_next % mss;
2161 next_is_first = (cum_len_next == 0);
2162 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2163 flags_next |= next_is_first *
2164 MXGEFW_FLAGS_FIRST;
2165 rdma_count |= -(chop | next_is_first);
2166 rdma_count += chop & !next_is_first;
2167 } else if (likely(cum_len_next >= 0)) { /* header ends */
2168 int small;
2169
2170 rdma_count = -1;
2171 cum_len_next = 0;
2172 seglen = -cum_len;
2173 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2174 flags_next = MXGEFW_FLAGS_TSO_PLD |
2175 MXGEFW_FLAGS_FIRST |
2176 (small * MXGEFW_FLAGS_SMALL);
2177 }
2178 }
2179 req->addr_high = high_swapped;
2180 req->addr_low = htonl(low);
2181 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2182 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2183 req->rdma_count = 1;
2184 req->length = htons(seglen);
2185 req->cksum_offset = cksum_offset;
2186 req->flags = flags | ((cum_len & 1) * odd_flag);
2187
2188 low += seglen;
2189 len -= seglen;
2190 cum_len = cum_len_next;
2191 flags = flags_next;
2192 req++;
2193 count++;
2194 rdma_count++;
2195 if (unlikely(cksum_offset > seglen))
2196 cksum_offset -= seglen;
2197 else
2198 cksum_offset = 0;
2199 }
2200 if (frag_idx == frag_cnt)
2201 break;
2202
2203 /* map next fragment for DMA */
2204 idx = (count + tx->req) & tx->mask;
2205 frag = &skb_shinfo(skb)->frags[frag_idx];
2206 frag_idx++;
2207 len = frag->size;
2208 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2209 len, PCI_DMA_TODEVICE);
2210 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2211 pci_unmap_len_set(&tx->info[idx], len, len);
2212 }
2213
2214 (req - rdma_count)->rdma_count = rdma_count;
2215 if (mss)
2216 do {
2217 req--;
2218 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2219 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2220 MXGEFW_FLAGS_FIRST)));
2221 idx = ((count - 1) + tx->req) & tx->mask;
2222 tx->info[idx].last = 1;
2223 if (tx->wc_fifo == NULL)
2224 myri10ge_submit_req(tx, tx->req_list, count);
2225 else
2226 myri10ge_submit_req_wc(tx, tx->req_list, count);
2227 tx->pkt_start++;
2228 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2229 mgp->stop_queue++;
2230 netif_stop_queue(dev);
2231 }
2232 dev->trans_start = jiffies;
2233 return 0;
2234
2235 abort_linearize:
2236 /* Free any DMA resources we've alloced and clear out the skb
2237 * slot so as to not trip up assertions, and to avoid a
2238 * double-free if linearizing fails */
2239
2240 last_idx = (idx + 1) & tx->mask;
2241 idx = tx->req & tx->mask;
2242 tx->info[idx].skb = NULL;
2243 do {
2244 len = pci_unmap_len(&tx->info[idx], len);
2245 if (len) {
2246 if (tx->info[idx].skb != NULL)
2247 pci_unmap_single(mgp->pdev,
2248 pci_unmap_addr(&tx->info[idx],
2249 bus), len,
2250 PCI_DMA_TODEVICE);
2251 else
2252 pci_unmap_page(mgp->pdev,
2253 pci_unmap_addr(&tx->info[idx],
2254 bus), len,
2255 PCI_DMA_TODEVICE);
2256 pci_unmap_len_set(&tx->info[idx], len, 0);
2257 tx->info[idx].skb = NULL;
2258 }
2259 idx = (idx + 1) & tx->mask;
2260 } while (idx != last_idx);
2261 if (skb_is_gso(skb)) {
2262 printk(KERN_ERR
2263 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2264 mgp->dev->name);
2265 goto drop;
2266 }
2267
2268 if (skb_linearize(skb))
2269 goto drop;
2270
2271 mgp->tx_linearized++;
2272 goto again;
2273
2274 drop:
2275 dev_kfree_skb_any(skb);
2276 mgp->stats.tx_dropped += 1;
2277 return 0;
2278
2279 }
2280
2281 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2282 {
2283 struct myri10ge_priv *mgp = netdev_priv(dev);
2284 return &mgp->stats;
2285 }
2286
2287 static void myri10ge_set_multicast_list(struct net_device *dev)
2288 {
2289 struct myri10ge_cmd cmd;
2290 struct myri10ge_priv *mgp;
2291 struct dev_mc_list *mc_list;
2292 __be32 data[2] = { 0, 0 };
2293 int err;
2294
2295 mgp = netdev_priv(dev);
2296 /* can be called from atomic contexts,
2297 * pass 1 to force atomicity in myri10ge_send_cmd() */
2298 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2299
2300 /* This firmware is known to not support multicast */
2301 if (!mgp->fw_multicast_support)
2302 return;
2303
2304 /* Disable multicast filtering */
2305
2306 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2307 if (err != 0) {
2308 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2309 " error status: %d\n", dev->name, err);
2310 goto abort;
2311 }
2312
2313 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2314 /* request to disable multicast filtering, so quit here */
2315 return;
2316 }
2317
2318 /* Flush the filters */
2319
2320 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2321 &cmd, 1);
2322 if (err != 0) {
2323 printk(KERN_ERR
2324 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2325 ", error status: %d\n", dev->name, err);
2326 goto abort;
2327 }
2328
2329 /* Walk the multicast list, and add each address */
2330 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2331 memcpy(data, &mc_list->dmi_addr, 6);
2332 cmd.data0 = ntohl(data[0]);
2333 cmd.data1 = ntohl(data[1]);
2334 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2335 &cmd, 1);
2336
2337 if (err != 0) {
2338 printk(KERN_ERR "myri10ge: %s: Failed "
2339 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2340 "%d\t", dev->name, err);
2341 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2342 ((unsigned char *)&mc_list->dmi_addr)[0],
2343 ((unsigned char *)&mc_list->dmi_addr)[1],
2344 ((unsigned char *)&mc_list->dmi_addr)[2],
2345 ((unsigned char *)&mc_list->dmi_addr)[3],
2346 ((unsigned char *)&mc_list->dmi_addr)[4],
2347 ((unsigned char *)&mc_list->dmi_addr)[5]
2348 );
2349 goto abort;
2350 }
2351 }
2352 /* Enable multicast filtering */
2353 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2354 if (err != 0) {
2355 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2356 "error status: %d\n", dev->name, err);
2357 goto abort;
2358 }
2359
2360 return;
2361
2362 abort:
2363 return;
2364 }
2365
2366 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2367 {
2368 struct sockaddr *sa = addr;
2369 struct myri10ge_priv *mgp = netdev_priv(dev);
2370 int status;
2371
2372 if (!is_valid_ether_addr(sa->sa_data))
2373 return -EADDRNOTAVAIL;
2374
2375 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2376 if (status != 0) {
2377 printk(KERN_ERR
2378 "myri10ge: %s: changing mac address failed with %d\n",
2379 dev->name, status);
2380 return status;
2381 }
2382
2383 /* change the dev structure */
2384 memcpy(dev->dev_addr, sa->sa_data, 6);
2385 return 0;
2386 }
2387
2388 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2389 {
2390 struct myri10ge_priv *mgp = netdev_priv(dev);
2391 int error = 0;
2392
2393 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2394 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2395 dev->name, new_mtu);
2396 return -EINVAL;
2397 }
2398 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2399 dev->name, dev->mtu, new_mtu);
2400 if (mgp->running) {
2401 /* if we change the mtu on an active device, we must
2402 * reset the device so the firmware sees the change */
2403 myri10ge_close(dev);
2404 dev->mtu = new_mtu;
2405 myri10ge_open(dev);
2406 } else
2407 dev->mtu = new_mtu;
2408
2409 return error;
2410 }
2411
2412 /*
2413 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2414 * Only do it if the bridge is a root port since we don't want to disturb
2415 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2416 */
2417
2418 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2419 {
2420 struct pci_dev *bridge = mgp->pdev->bus->self;
2421 struct device *dev = &mgp->pdev->dev;
2422 unsigned cap;
2423 unsigned err_cap;
2424 u16 val;
2425 u8 ext_type;
2426 int ret;
2427
2428 if (!myri10ge_ecrc_enable || !bridge)
2429 return;
2430
2431 /* check that the bridge is a root port */
2432 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2433 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2434 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2435 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2436 if (myri10ge_ecrc_enable > 1) {
2437 struct pci_dev *old_bridge = bridge;
2438
2439 /* Walk the hierarchy up to the root port
2440 * where ECRC has to be enabled */
2441 do {
2442 bridge = bridge->bus->self;
2443 if (!bridge) {
2444 dev_err(dev,
2445 "Failed to find root port"
2446 " to force ECRC\n");
2447 return;
2448 }
2449 cap =
2450 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2451 pci_read_config_word(bridge,
2452 cap + PCI_CAP_FLAGS, &val);
2453 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2454 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2455
2456 dev_info(dev,
2457 "Forcing ECRC on non-root port %s"
2458 " (enabling on root port %s)\n",
2459 pci_name(old_bridge), pci_name(bridge));
2460 } else {
2461 dev_err(dev,
2462 "Not enabling ECRC on non-root port %s\n",
2463 pci_name(bridge));
2464 return;
2465 }
2466 }
2467
2468 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2469 if (!cap)
2470 return;
2471
2472 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2473 if (ret) {
2474 dev_err(dev, "failed reading ext-conf-space of %s\n",
2475 pci_name(bridge));
2476 dev_err(dev, "\t pci=nommconf in use? "
2477 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2478 return;
2479 }
2480 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2481 return;
2482
2483 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2484 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2485 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2486 }
2487
2488 /*
2489 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2490 * when the PCI-E Completion packets are aligned on an 8-byte
2491 * boundary. Some PCI-E chip sets always align Completion packets; on
2492 * the ones that do not, the alignment can be enforced by enabling
2493 * ECRC generation (if supported).
2494 *
2495 * When PCI-E Completion packets are not aligned, it is actually more
2496 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2497 *
2498 * If the driver can neither enable ECRC nor verify that it has
2499 * already been enabled, then it must use a firmware image which works
2500 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2501 * should also ensure that it never gives the device a Read-DMA which is
2502 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2503 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2504 * firmware image, and set tx.boundary to 4KB.
2505 */
2506
2507 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
2508 {
2509 struct pci_dev *pdev = mgp->pdev;
2510 struct device *dev = &pdev->dev;
2511 int status;
2512
2513 mgp->tx.boundary = 4096;
2514 /*
2515 * Verify the max read request size was set to 4KB
2516 * before trying the test with 4KB.
2517 */
2518 status = pcie_get_readrq(pdev);
2519 if (status < 0) {
2520 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2521 goto abort;
2522 }
2523 if (status != 4096) {
2524 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
2525 mgp->tx.boundary = 2048;
2526 }
2527 /*
2528 * load the optimized firmware (which assumes aligned PCIe
2529 * completions) in order to see if it works on this host.
2530 */
2531 mgp->fw_name = myri10ge_fw_aligned;
2532 status = myri10ge_load_firmware(mgp);
2533 if (status != 0) {
2534 goto abort;
2535 }
2536
2537 /*
2538 * Enable ECRC if possible
2539 */
2540 myri10ge_enable_ecrc(mgp);
2541
2542 /*
2543 * Run a DMA test which watches for unaligned completions and
2544 * aborts on the first one seen.
2545 */
2546
2547 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2548 if (status == 0)
2549 return; /* keep the aligned firmware */
2550
2551 if (status != -E2BIG)
2552 dev_warn(dev, "DMA test failed: %d\n", status);
2553 if (status == -ENOSYS)
2554 dev_warn(dev, "Falling back to ethp! "
2555 "Please install up to date fw\n");
2556 abort:
2557 /* fall back to using the unaligned firmware */
2558 mgp->tx.boundary = 2048;
2559 mgp->fw_name = myri10ge_fw_unaligned;
2560
2561 }
2562
2563 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2564 {
2565 if (myri10ge_force_firmware == 0) {
2566 int link_width, exp_cap;
2567 u16 lnk;
2568
2569 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2570 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2571 link_width = (lnk >> 4) & 0x3f;
2572
2573 /* Check to see if Link is less than 8 or if the
2574 * upstream bridge is known to provide aligned
2575 * completions */
2576 if (link_width < 8) {
2577 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2578 link_width);
2579 mgp->tx.boundary = 4096;
2580 mgp->fw_name = myri10ge_fw_aligned;
2581 } else {
2582 myri10ge_firmware_probe(mgp);
2583 }
2584 } else {
2585 if (myri10ge_force_firmware == 1) {
2586 dev_info(&mgp->pdev->dev,
2587 "Assuming aligned completions (forced)\n");
2588 mgp->tx.boundary = 4096;
2589 mgp->fw_name = myri10ge_fw_aligned;
2590 } else {
2591 dev_info(&mgp->pdev->dev,
2592 "Assuming unaligned completions (forced)\n");
2593 mgp->tx.boundary = 2048;
2594 mgp->fw_name = myri10ge_fw_unaligned;
2595 }
2596 }
2597 if (myri10ge_fw_name != NULL) {
2598 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2599 myri10ge_fw_name);
2600 mgp->fw_name = myri10ge_fw_name;
2601 }
2602 }
2603
2604 #ifdef CONFIG_PM
2605
2606 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2607 {
2608 struct myri10ge_priv *mgp;
2609 struct net_device *netdev;
2610
2611 mgp = pci_get_drvdata(pdev);
2612 if (mgp == NULL)
2613 return -EINVAL;
2614 netdev = mgp->dev;
2615
2616 netif_device_detach(netdev);
2617 if (netif_running(netdev)) {
2618 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2619 rtnl_lock();
2620 myri10ge_close(netdev);
2621 rtnl_unlock();
2622 }
2623 myri10ge_dummy_rdma(mgp, 0);
2624 pci_save_state(pdev);
2625 pci_disable_device(pdev);
2626
2627 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
2628 }
2629
2630 static int myri10ge_resume(struct pci_dev *pdev)
2631 {
2632 struct myri10ge_priv *mgp;
2633 struct net_device *netdev;
2634 int status;
2635 u16 vendor;
2636
2637 mgp = pci_get_drvdata(pdev);
2638 if (mgp == NULL)
2639 return -EINVAL;
2640 netdev = mgp->dev;
2641 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2642 msleep(5); /* give card time to respond */
2643 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2644 if (vendor == 0xffff) {
2645 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2646 mgp->dev->name);
2647 return -EIO;
2648 }
2649
2650 status = pci_restore_state(pdev);
2651 if (status)
2652 return status;
2653
2654 status = pci_enable_device(pdev);
2655 if (status) {
2656 dev_err(&pdev->dev, "failed to enable device\n");
2657 return status;
2658 }
2659
2660 pci_set_master(pdev);
2661
2662 myri10ge_reset(mgp);
2663 myri10ge_dummy_rdma(mgp, 1);
2664
2665 /* Save configuration space to be restored if the
2666 * nic resets due to a parity error */
2667 pci_save_state(pdev);
2668
2669 if (netif_running(netdev)) {
2670 rtnl_lock();
2671 status = myri10ge_open(netdev);
2672 rtnl_unlock();
2673 if (status != 0)
2674 goto abort_with_enabled;
2675
2676 }
2677 netif_device_attach(netdev);
2678
2679 return 0;
2680
2681 abort_with_enabled:
2682 pci_disable_device(pdev);
2683 return -EIO;
2684
2685 }
2686
2687 #endif /* CONFIG_PM */
2688
2689 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2690 {
2691 struct pci_dev *pdev = mgp->pdev;
2692 int vs = mgp->vendor_specific_offset;
2693 u32 reboot;
2694
2695 /*enter read32 mode */
2696 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2697
2698 /*read REBOOT_STATUS (0xfffffff0) */
2699 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2700 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2701 return reboot;
2702 }
2703
2704 /*
2705 * This watchdog is used to check whether the board has suffered
2706 * from a parity error and needs to be recovered.
2707 */
2708 static void myri10ge_watchdog(struct work_struct *work)
2709 {
2710 struct myri10ge_priv *mgp =
2711 container_of(work, struct myri10ge_priv, watchdog_work);
2712 u32 reboot;
2713 int status;
2714 u16 cmd, vendor;
2715
2716 mgp->watchdog_resets++;
2717 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2718 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2719 /* Bus master DMA disabled? Check to see
2720 * if the card rebooted due to a parity error
2721 * For now, just report it */
2722 reboot = myri10ge_read_reboot(mgp);
2723 printk(KERN_ERR
2724 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
2725 mgp->dev->name, reboot,
2726 myri10ge_reset_recover ? " " : " not");
2727 if (myri10ge_reset_recover == 0)
2728 return;
2729
2730 myri10ge_reset_recover--;
2731
2732 /*
2733 * A rebooted nic will come back with config space as
2734 * it was after power was applied to PCIe bus.
2735 * Attempt to restore config space which was saved
2736 * when the driver was loaded, or the last time the
2737 * nic was resumed from power saving mode.
2738 */
2739 pci_restore_state(mgp->pdev);
2740
2741 /* save state again for accounting reasons */
2742 pci_save_state(mgp->pdev);
2743
2744 } else {
2745 /* if we get back -1's from our slot, perhaps somebody
2746 * powered off our card. Don't try to reset it in
2747 * this case */
2748 if (cmd == 0xffff) {
2749 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2750 if (vendor == 0xffff) {
2751 printk(KERN_ERR
2752 "myri10ge: %s: device disappeared!\n",
2753 mgp->dev->name);
2754 return;
2755 }
2756 }
2757 /* Perhaps it is a software error. Try to reset */
2758
2759 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2760 mgp->dev->name);
2761 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2762 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2763 mgp->tx.pkt_start, mgp->tx.pkt_done,
2764 (int)ntohl(mgp->fw_stats->send_done_count));
2765 msleep(2000);
2766 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2767 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2768 mgp->tx.pkt_start, mgp->tx.pkt_done,
2769 (int)ntohl(mgp->fw_stats->send_done_count));
2770 }
2771 rtnl_lock();
2772 myri10ge_close(mgp->dev);
2773 status = myri10ge_load_firmware(mgp);
2774 if (status != 0)
2775 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2776 mgp->dev->name);
2777 else
2778 myri10ge_open(mgp->dev);
2779 rtnl_unlock();
2780 }
2781
2782 /*
2783 * We use our own timer routine rather than relying upon
2784 * netdev->tx_timeout because we have a very large hardware transmit
2785 * queue. Due to the large queue, the netdev->tx_timeout function
2786 * cannot detect a NIC with a parity error in a timely fashion if the
2787 * NIC is lightly loaded.
2788 */
2789 static void myri10ge_watchdog_timer(unsigned long arg)
2790 {
2791 struct myri10ge_priv *mgp;
2792 u32 rx_pause_cnt;
2793
2794 mgp = (struct myri10ge_priv *)arg;
2795
2796 if (mgp->rx_small.watchdog_needed) {
2797 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2798 mgp->small_bytes + MXGEFW_PAD, 1);
2799 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2800 myri10ge_fill_thresh)
2801 mgp->rx_small.watchdog_needed = 0;
2802 }
2803 if (mgp->rx_big.watchdog_needed) {
2804 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2805 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2806 myri10ge_fill_thresh)
2807 mgp->rx_big.watchdog_needed = 0;
2808 }
2809 rx_pause_cnt = ntohl(mgp->fw_stats->dropped_pause);
2810
2811 if (mgp->tx.req != mgp->tx.done &&
2812 mgp->tx.done == mgp->watchdog_tx_done &&
2813 mgp->watchdog_tx_req != mgp->watchdog_tx_done) {
2814 /* nic seems like it might be stuck.. */
2815 if (rx_pause_cnt != mgp->watchdog_pause) {
2816 if (net_ratelimit())
2817 printk(KERN_WARNING "myri10ge %s:"
2818 "TX paused, check link partner\n",
2819 mgp->dev->name);
2820 } else {
2821 schedule_work(&mgp->watchdog_work);
2822 return;
2823 }
2824 }
2825 /* rearm timer */
2826 mod_timer(&mgp->watchdog_timer,
2827 jiffies + myri10ge_watchdog_timeout * HZ);
2828 mgp->watchdog_tx_done = mgp->tx.done;
2829 mgp->watchdog_tx_req = mgp->tx.req;
2830 mgp->watchdog_pause = rx_pause_cnt;
2831 }
2832
2833 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2834 {
2835 struct net_device *netdev;
2836 struct myri10ge_priv *mgp;
2837 struct device *dev = &pdev->dev;
2838 size_t bytes;
2839 int i;
2840 int status = -ENXIO;
2841 int dac_enabled;
2842
2843 netdev = alloc_etherdev(sizeof(*mgp));
2844 if (netdev == NULL) {
2845 dev_err(dev, "Could not allocate ethernet device\n");
2846 return -ENOMEM;
2847 }
2848
2849 SET_NETDEV_DEV(netdev, &pdev->dev);
2850
2851 mgp = netdev_priv(netdev);
2852 memset(mgp, 0, sizeof(*mgp));
2853 mgp->dev = netdev;
2854 netif_napi_add(netdev, &mgp->napi,
2855 myri10ge_poll, myri10ge_napi_weight);
2856 mgp->pdev = pdev;
2857 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2858 mgp->pause = myri10ge_flow_control;
2859 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2860 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2861 init_waitqueue_head(&mgp->down_wq);
2862
2863 if (pci_enable_device(pdev)) {
2864 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2865 status = -ENODEV;
2866 goto abort_with_netdev;
2867 }
2868
2869 /* Find the vendor-specific cap so we can check
2870 * the reboot register later on */
2871 mgp->vendor_specific_offset
2872 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2873
2874 /* Set our max read request to 4KB */
2875 status = pcie_set_readrq(pdev, 4096);
2876 if (status != 0) {
2877 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2878 status);
2879 goto abort_with_netdev;
2880 }
2881
2882 pci_set_master(pdev);
2883 dac_enabled = 1;
2884 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2885 if (status != 0) {
2886 dac_enabled = 0;
2887 dev_err(&pdev->dev,
2888 "64-bit pci address mask was refused, trying 32-bit");
2889 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2890 }
2891 if (status != 0) {
2892 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2893 goto abort_with_netdev;
2894 }
2895 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2896 &mgp->cmd_bus, GFP_KERNEL);
2897 if (mgp->cmd == NULL)
2898 goto abort_with_netdev;
2899
2900 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2901 &mgp->fw_stats_bus, GFP_KERNEL);
2902 if (mgp->fw_stats == NULL)
2903 goto abort_with_cmd;
2904
2905 mgp->board_span = pci_resource_len(pdev, 0);
2906 mgp->iomem_base = pci_resource_start(pdev, 0);
2907 mgp->mtrr = -1;
2908 mgp->wc_enabled = 0;
2909 #ifdef CONFIG_MTRR
2910 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2911 MTRR_TYPE_WRCOMB, 1);
2912 if (mgp->mtrr >= 0)
2913 mgp->wc_enabled = 1;
2914 #endif
2915 /* Hack. need to get rid of these magic numbers */
2916 mgp->sram_size =
2917 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2918 if (mgp->sram_size > mgp->board_span) {
2919 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2920 mgp->board_span);
2921 goto abort_with_wc;
2922 }
2923 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2924 if (mgp->sram == NULL) {
2925 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2926 mgp->board_span, mgp->iomem_base);
2927 status = -ENXIO;
2928 goto abort_with_wc;
2929 }
2930 memcpy_fromio(mgp->eeprom_strings,
2931 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2932 MYRI10GE_EEPROM_STRINGS_SIZE);
2933 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2934 status = myri10ge_read_mac_addr(mgp);
2935 if (status)
2936 goto abort_with_ioremap;
2937
2938 for (i = 0; i < ETH_ALEN; i++)
2939 netdev->dev_addr[i] = mgp->mac_addr[i];
2940
2941 /* allocate rx done ring */
2942 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2943 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2944 &mgp->rx_done.bus, GFP_KERNEL);
2945 if (mgp->rx_done.entry == NULL)
2946 goto abort_with_ioremap;
2947 memset(mgp->rx_done.entry, 0, bytes);
2948
2949 myri10ge_select_firmware(mgp);
2950
2951 status = myri10ge_load_firmware(mgp);
2952 if (status != 0) {
2953 dev_err(&pdev->dev, "failed to load firmware\n");
2954 goto abort_with_rx_done;
2955 }
2956
2957 status = myri10ge_reset(mgp);
2958 if (status != 0) {
2959 dev_err(&pdev->dev, "failed reset\n");
2960 goto abort_with_firmware;
2961 }
2962
2963 pci_set_drvdata(pdev, mgp);
2964 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2965 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2966 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2967 myri10ge_initial_mtu = 68;
2968 netdev->mtu = myri10ge_initial_mtu;
2969 netdev->open = myri10ge_open;
2970 netdev->stop = myri10ge_close;
2971 netdev->hard_start_xmit = myri10ge_xmit;
2972 netdev->get_stats = myri10ge_get_stats;
2973 netdev->base_addr = mgp->iomem_base;
2974 netdev->change_mtu = myri10ge_change_mtu;
2975 netdev->set_multicast_list = myri10ge_set_multicast_list;
2976 netdev->set_mac_address = myri10ge_set_mac_address;
2977 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2978 if (dac_enabled)
2979 netdev->features |= NETIF_F_HIGHDMA;
2980
2981 /* make sure we can get an irq, and that MSI can be
2982 * setup (if available). Also ensure netdev->irq
2983 * is set to correct value if MSI is enabled */
2984 status = myri10ge_request_irq(mgp);
2985 if (status != 0)
2986 goto abort_with_firmware;
2987 netdev->irq = pdev->irq;
2988 myri10ge_free_irq(mgp);
2989
2990 /* Save configuration space to be restored if the
2991 * nic resets due to a parity error */
2992 pci_save_state(pdev);
2993
2994 /* Setup the watchdog timer */
2995 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2996 (unsigned long)mgp);
2997
2998 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
2999 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3000 status = register_netdev(netdev);
3001 if (status != 0) {
3002 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3003 goto abort_with_state;
3004 }
3005 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3006 (mgp->msi_enabled ? "MSI" : "xPIC"),
3007 netdev->irq, mgp->tx.boundary, mgp->fw_name,
3008 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3009
3010 return 0;
3011
3012 abort_with_state:
3013 pci_restore_state(pdev);
3014
3015 abort_with_firmware:
3016 myri10ge_dummy_rdma(mgp, 0);
3017
3018 abort_with_rx_done:
3019 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
3020 dma_free_coherent(&pdev->dev, bytes,
3021 mgp->rx_done.entry, mgp->rx_done.bus);
3022
3023 abort_with_ioremap:
3024 iounmap(mgp->sram);
3025
3026 abort_with_wc:
3027 #ifdef CONFIG_MTRR
3028 if (mgp->mtrr >= 0)
3029 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3030 #endif
3031 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3032 mgp->fw_stats, mgp->fw_stats_bus);
3033
3034 abort_with_cmd:
3035 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3036 mgp->cmd, mgp->cmd_bus);
3037
3038 abort_with_netdev:
3039
3040 free_netdev(netdev);
3041 return status;
3042 }
3043
3044 /*
3045 * myri10ge_remove
3046 *
3047 * Does what is necessary to shutdown one Myrinet device. Called
3048 * once for each Myrinet card by the kernel when a module is
3049 * unloaded.
3050 */
3051 static void myri10ge_remove(struct pci_dev *pdev)
3052 {
3053 struct myri10ge_priv *mgp;
3054 struct net_device *netdev;
3055 size_t bytes;
3056
3057 mgp = pci_get_drvdata(pdev);
3058 if (mgp == NULL)
3059 return;
3060
3061 flush_scheduled_work();
3062 netdev = mgp->dev;
3063 unregister_netdev(netdev);
3064
3065 myri10ge_dummy_rdma(mgp, 0);
3066
3067 /* avoid a memory leak */
3068 pci_restore_state(pdev);
3069
3070 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
3071 dma_free_coherent(&pdev->dev, bytes,
3072 mgp->rx_done.entry, mgp->rx_done.bus);
3073
3074 iounmap(mgp->sram);
3075
3076 #ifdef CONFIG_MTRR
3077 if (mgp->mtrr >= 0)
3078 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3079 #endif
3080 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3081 mgp->fw_stats, mgp->fw_stats_bus);
3082
3083 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3084 mgp->cmd, mgp->cmd_bus);
3085
3086 free_netdev(netdev);
3087 pci_set_drvdata(pdev, NULL);
3088 }
3089
3090 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
3091 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
3092
3093 static struct pci_device_id myri10ge_pci_tbl[] = {
3094 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3095 {PCI_DEVICE
3096 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
3097 {0},
3098 };
3099
3100 static struct pci_driver myri10ge_driver = {
3101 .name = "myri10ge",
3102 .probe = myri10ge_probe,
3103 .remove = myri10ge_remove,
3104 .id_table = myri10ge_pci_tbl,
3105 #ifdef CONFIG_PM
3106 .suspend = myri10ge_suspend,
3107 .resume = myri10ge_resume,
3108 #endif
3109 };
3110
3111 static __init int myri10ge_init_module(void)
3112 {
3113 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3114 MYRI10GE_VERSION_STR);
3115 return pci_register_driver(&myri10ge_driver);
3116 }
3117
3118 module_init(myri10ge_init_module);
3119
3120 static __exit void myri10ge_cleanup_module(void)
3121 {
3122 pci_unregister_driver(&myri10ge_driver);
3123 }
3124
3125 module_exit(myri10ge_cleanup_module);
kernel-based virtual machine