drivers/net/wireless/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <net/mac80211.h>
  23 #include <linux/leds.h>
  24 #include <linux/rfkill.h>
  25
  26 #include "hw.h"
  27 #include "rc.h"
  28 #include "debug.h"
  29
  30 struct ath_node;
  31
  32 /* Macro to expand scalars to 64-bit objects */
  33
  34 #define ito64(x) (sizeof(x) == 8) ?                     \
  35         (((unsigned long long int)(x)) & (0xff)) :      \
  36         (sizeof(x) == 16) ?                             \
  37         (((unsigned long long int)(x)) & 0xffff) :      \
  38         ((sizeof(x) == 32) ?                            \
  39          (((unsigned long long int)(x)) & 0xffffffff) : \
  40          (unsigned long long int)(x))
  41
  42 /* increment with wrap-around */
  43 #define INCR(_l, _sz)   do {                    \
  44                 (_l)++;                         \
  45                 (_l) &= ((_sz) - 1);            \
  46         } while (0)
  47
  48 /* decrement with wrap-around */
  49 #define DECR(_l,  _sz)  do {                    \
  50                 (_l)--;                         \
  51                 (_l) &= ((_sz) - 1);            \
  52         } while (0)
  53
  54 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  55
  56 #define ASSERT(exp) BUG_ON(!(exp))
  57
  58 #define TSF_TO_TU(_h,_l) \
  59         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  60
  61 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
  62
  63 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  64
  65 struct ath_config {
  66         u32 ath_aggr_prot;
  67         u16 txpowlimit;
  68         u8 cabqReadytime;
  69         u8 swBeaconProcess;
  70 };
  71
  72 /*************************/
  73 /* Descriptor Management */
  74 /*************************/
  75
  76 #define ATH_TXBUF_RESET(_bf) do {                               \
  77                 (_bf)->bf_status = 0;                           \
  78                 (_bf)->bf_lastbf = NULL;                        \
  79                 (_bf)->bf_next = NULL;                          \
  80                 memset(&((_bf)->bf_state), 0,                   \
  81                        sizeof(struct ath_buf_state));           \
  82         } while (0)
  83
  84 /**
  85  * enum buffer_type - Buffer type flags
  86  *
  87  * @BUF_HT: Send this buffer using HT capabilities
  88  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  89  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  90  *      (used in aggregation scheduling)
  91  * @BUF_RETRY: Indicates whether the buffer is retried
  92  * @BUF_XRETRY: To denote excessive retries of the buffer
  93  */
  94 enum buffer_type {
  95         BUF_HT                  = BIT(1),
  96         BUF_AMPDU               = BIT(2),
  97         BUF_AGGR                = BIT(3),
  98         BUF_RETRY               = BIT(4),
  99         BUF_XRETRY              = BIT(5),
 100 };
 101
 102 struct ath_buf_state {
 103         int bfs_nframes;
 104         u16 bfs_al;
 105         u16 bfs_frmlen;
 106         int bfs_seqno;
 107         int bfs_tidno;
 108         int bfs_retries;
 109         u32 bf_type;
 110         u32 bfs_keyix;
 111         enum ath9k_key_type bfs_keytype;
 112 };
 113
 114 #define bf_nframes              bf_state.bfs_nframes
 115 #define bf_al                   bf_state.bfs_al
 116 #define bf_frmlen               bf_state.bfs_frmlen
 117 #define bf_retries              bf_state.bfs_retries
 118 #define bf_seqno                bf_state.bfs_seqno
 119 #define bf_tidno                bf_state.bfs_tidno
 120 #define bf_keyix                bf_state.bfs_keyix
 121 #define bf_keytype              bf_state.bfs_keytype
 122 #define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 123 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 124 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 125 #define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 126 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 127
 128 struct ath_buf {
 129         struct list_head list;
 130         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 131                                            an aggregate) */
 132         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 133         void *bf_mpdu;                  /* enclosing frame structure */
 134         struct ath_desc *bf_desc;       /* virtual addr of desc */
 135         dma_addr_t bf_daddr;            /* physical addr of desc */
 136         dma_addr_t bf_buf_addr;         /* physical addr of data buffer */
 137         u32 bf_status;
 138         u16 bf_flags;
 139         struct ath_buf_state bf_state;
 140         dma_addr_t bf_dmacontext;
 141 };
 142
 143 #define ATH_RXBUF_RESET(_bf)    ((_bf)->bf_status = 0)
 144 #define ATH_BUFSTATUS_STALE     0x00000002
 145
 146 struct ath_descdma {
 147         const char *dd_name;
 148         struct ath_desc *dd_desc;
 149         dma_addr_t dd_desc_paddr;
 150         u32 dd_desc_len;
 151         struct ath_buf *dd_bufptr;
 152         dma_addr_t dd_dmacontext;
 153 };
 154
 155 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 156                       struct list_head *head, const char *name,
 157                       int nbuf, int ndesc);
 158 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 159                          struct list_head *head);
 160
 161 /***********/
 162 /* RX / TX */
 163 /***********/
 164
 165 #define ATH_MAX_ANTENNA         3
 166 #define ATH_RXBUF               512
 167 #define WME_NUM_TID             16
 168 #define ATH_TXBUF               512
 169 #define ATH_TXMAXTRY            13
 170 #define ATH_11N_TXMAXTRY        10
 171 #define ATH_MGT_TXMAXTRY        4
 172 #define WME_BA_BMP_SIZE         64
 173 #define WME_MAX_BA              WME_BA_BMP_SIZE
 174 #define ATH_TID_MAX_BUFS        (2 * WME_MAX_BA)
 175
 176 #define TID_TO_WME_AC(_tid)                             \
 177         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 178          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 179          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 180          WME_AC_VO)
 181
 182 #define WME_AC_BE   0
 183 #define WME_AC_BK   1
 184 #define WME_AC_VI   2
 185 #define WME_AC_VO   3
 186 #define WME_NUM_AC  4
 187
 188 #define ADDBA_EXCHANGE_ATTEMPTS    10
 189 #define ATH_AGGR_DELIM_SZ          4
 190 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 191 /* number of delimiters for encryption padding */
 192 #define ATH_AGGR_ENCRYPTDELIM      10
 193 /* minimum h/w qdepth to be sustained to maximize aggregation */
 194 #define ATH_AGGR_MIN_QDEPTH        2
 195 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 196 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
 197 #define ATH_AMPDU_LIMIT_DEFAULT    ATH_AMPDU_LIMIT_MAX
 198
 199 #define IEEE80211_SEQ_SEQ_SHIFT    4
 200 #define IEEE80211_SEQ_MAX          4096
 201 #define IEEE80211_MIN_AMPDU_BUF    0x8
 202 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
 203 #define IEEE80211_WEP_IVLEN        3
 204 #define IEEE80211_WEP_KIDLEN       1
 205 #define IEEE80211_WEP_CRCLEN       4
 206 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 207                                     (IEEE80211_WEP_IVLEN +      \
 208                                      IEEE80211_WEP_KIDLEN +     \
 209                                      IEEE80211_WEP_CRCLEN))
 210
 211 /* return whether a bit at index _n in bitmap _bm is set
 212  * _sz is the size of the bitmap  */
 213 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 214                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 215
 216 /* return block-ack bitmap index given sequence and starting sequence */
 217 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 218
 219 /* returns delimiter padding required given the packet length */
 220 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 221         (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
 222           (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
 223
 224 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 225         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 226
 227 #define ATH_DS_BA_SEQ(_ds)         ((_ds)->ds_us.tx.ts_seqnum)
 228 #define ATH_DS_BA_BITMAP(_ds)      (&(_ds)->ds_us.tx.ba_low)
 229 #define ATH_DS_TX_BA(_ds)          ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
 230 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 231
 232 enum ATH_AGGR_STATUS {
 233         ATH_AGGR_DONE,
 234         ATH_AGGR_BAW_CLOSED,
 235         ATH_AGGR_LIMITED,
 236 };
 237
 238 struct ath_txq {
 239         u32 axq_qnum;
 240         u32 *axq_link;
 241         struct list_head axq_q;
 242         spinlock_t axq_lock;
 243         u32 axq_depth;
 244         u8 axq_aggr_depth;
 245         u32 axq_totalqueued;
 246         bool stopped;
 247         struct ath_buf *axq_linkbuf;
 248
 249         /* first desc of the last descriptor that contains CTS */
 250         struct ath_desc *axq_lastdsWithCTS;
 251
 252         /* final desc of the gating desc that determines whether
 253            lastdsWithCTS has been DMA'ed or not */
 254         struct ath_desc *axq_gatingds;
 255
 256         struct list_head axq_acq;
 257 };
 258
 259 #define AGGR_CLEANUP         BIT(1)
 260 #define AGGR_ADDBA_COMPLETE  BIT(2)
 261 #define AGGR_ADDBA_PROGRESS  BIT(3)
 262
 263 struct ath_atx_tid {
 264         struct list_head list;
 265         struct list_head buf_q;
 266         struct ath_node *an;
 267         struct ath_atx_ac *ac;
 268         struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
 269         u16 seq_start;
 270         u16 seq_next;
 271         u16 baw_size;
 272         int tidno;
 273         int baw_head;   /* first un-acked tx buffer */
 274         int baw_tail;   /* next unused tx buffer slot */
 275         int sched;
 276         int paused;
 277         u8 state;
 278         int addba_exchangeattempts;
 279 };
 280
 281 struct ath_atx_ac {
 282         int sched;
 283         int qnum;
 284         struct list_head list;
 285         struct list_head tid_q;
 286 };
 287
 288 struct ath_tx_control {
 289         struct ath_txq *txq;
 290         int if_id;
 291         enum ath9k_internal_frame_type frame_type;
 292 };
 293
 294 #define ATH_TX_ERROR        0x01
 295 #define ATH_TX_XRETRY       0x02
 296 #define ATH_TX_BAR          0x04
 297
 298 /* All RSSI values are noise floor adjusted */
 299 struct ath_tx_stat {
 300         int rssi;
 301         int rssictl[ATH_MAX_ANTENNA];
 302         int rssiextn[ATH_MAX_ANTENNA];
 303         int rateieee;
 304         int rateKbps;
 305         int ratecode;
 306         int flags;
 307         u32 airtime;    /* time on air per final tx rate */
 308 };
 309
 310 struct aggr_rifs_param {
 311         int param_max_frames;
 312         int param_max_len;
 313         int param_rl;
 314         int param_al;
 315         struct ath_rc_series *param_rcs;
 316 };
 317
 318 struct ath_node {
 319         struct ath_softc *an_sc;
 320         struct ath_atx_tid tid[WME_NUM_TID];
 321         struct ath_atx_ac ac[WME_NUM_AC];
 322         u16 maxampdu;
 323         u8 mpdudensity;
 324 };
 325
 326 struct ath_tx {
 327         u16 seq_no;
 328         u32 txqsetup;
 329         int hwq_map[ATH9K_WME_AC_VO+1];
 330         spinlock_t txbuflock;
 331         struct list_head txbuf;
 332         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 333         struct ath_descdma txdma;
 334 };
 335
 336 struct ath_rx {
 337         u8 defant;
 338         u8 rxotherant;
 339         u32 *rxlink;
 340         int bufsize;
 341         unsigned int rxfilter;
 342         spinlock_t rxflushlock;
 343         spinlock_t rxbuflock;
 344         struct list_head rxbuf;
 345         struct ath_descdma rxdma;
 346 };
 347
 348 int ath_startrecv(struct ath_softc *sc);
 349 bool ath_stoprecv(struct ath_softc *sc);
 350 void ath_flushrecv(struct ath_softc *sc);
 351 u32 ath_calcrxfilter(struct ath_softc *sc);
 352 int ath_rx_init(struct ath_softc *sc, int nbufs);
 353 void ath_rx_cleanup(struct ath_softc *sc);
 354 int ath_rx_tasklet(struct ath_softc *sc, int flush);
 355 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 356 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 357 int ath_tx_setup(struct ath_softc *sc, int haltype);
 358 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 359 void ath_draintxq(struct ath_softc *sc,
 360                      struct ath_txq *txq, bool retry_tx);
 361 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 362 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 363 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 364 int ath_tx_init(struct ath_softc *sc, int nbufs);
 365 int ath_tx_cleanup(struct ath_softc *sc);
 366 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
 367 int ath_txq_update(struct ath_softc *sc, int qnum,
 368                    struct ath9k_tx_queue_info *q);
 369 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
 370                  struct ath_tx_control *txctl);
 371 void ath_tx_tasklet(struct ath_softc *sc);
 372 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
 373 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
 374 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 375                       u16 tid, u16 *ssn);
 376 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 377 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 378
 379 /********/
 380 /* VIFs */
 381 /********/
 382
 383 struct ath_vif {
 384         int av_bslot;
 385         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
 386         enum nl80211_iftype av_opmode;
 387         struct ath_buf *av_bcbuf;
 388         struct ath_tx_control av_btxctl;
 389         u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
 390 };
 391
 392 /*******************/
 393 /* Beacon Handling */
 394 /*******************/
 395
 396 /*
 397  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 398  * number of BSSIDs) if a given beacon does not go out even after waiting this
 399  * number of beacon intervals, the game's up.
 400  */
 401 #define BSTUCK_THRESH                   (9 * ATH_BCBUF)
 402 #define ATH_BCBUF                       4
 403 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 404 #define ATH_DEFAULT_BMISS_LIMIT         10
 405 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 406
 407 struct ath_beacon_config {
 408         u16 beacon_interval;
 409         u16 listen_interval;
 410         u16 dtim_period;
 411         u16 bmiss_timeout;
 412         u8 dtim_count;
 413 };
 414
 415 struct ath_beacon {
 416         enum {
 417                 OK,             /* no change needed */
 418                 UPDATE,         /* update pending */
 419                 COMMIT          /* beacon sent, commit change */
 420         } updateslot;           /* slot time update fsm */
 421
 422         u32 beaconq;
 423         u32 bmisscnt;
 424         u32 ast_be_xmit;
 425         u64 bc_tstamp;
 426         struct ieee80211_vif *bslot[ATH_BCBUF];
 427         struct ath_wiphy *bslot_aphy[ATH_BCBUF];
 428         int slottime;
 429         int slotupdate;
 430         struct ath9k_tx_queue_info beacon_qi;
 431         struct ath_descdma bdma;
 432         struct ath_txq *cabq;
 433         struct list_head bbuf;
 434 };
 435
 436 void ath_beacon_tasklet(unsigned long data);
 437 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
 438 int ath_beaconq_setup(struct ath_hw *ah);
 439 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
 440 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
 441
 442 /*******/
 443 /* ANI */
 444 /*******/
 445
 446 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
 447 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 448 #define ATH_ANI_POLLINTERVAL      100     /* 100 ms */
 449 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 450 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 451
 452 struct ath_ani {
 453         bool caldone;
 454         int16_t noise_floor;
 455         unsigned int longcal_timer;
 456         unsigned int shortcal_timer;
 457         unsigned int resetcal_timer;
 458         unsigned int checkani_timer;
 459         struct timer_list timer;
 460 };
 461
 462 /********************/
 463 /*   LED Control    */
 464 /********************/
 465
 466 #define ATH_LED_PIN     1
 467 #define ATH_LED_ON_DURATION_IDLE        350     /* in msecs */
 468 #define ATH_LED_OFF_DURATION_IDLE       250     /* in msecs */
 469
 470 enum ath_led_type {
 471         ATH_LED_RADIO,
 472         ATH_LED_ASSOC,
 473         ATH_LED_TX,
 474         ATH_LED_RX
 475 };
 476
 477 struct ath_led {
 478         struct ath_softc *sc;
 479         struct led_classdev led_cdev;
 480         enum ath_led_type led_type;
 481         char name[32];
 482         bool registered;
 483 };
 484
 485 /* Rfkill */
 486 #define ATH_RFKILL_POLL_INTERVAL        2000 /* msecs */
 487
 488 struct ath_rfkill {
 489         struct rfkill *rfkill;
 490         struct delayed_work rfkill_poll;
 491         char rfkill_name[32];
 492 };
 493
 494 /********************/
 495 /* Main driver core */
 496 /********************/
 497
 498 /*
 499  * Default cache line size, in bytes.
 500  * Used when PCI device not fully initialized by bootrom/BIOS
 501 */
 502 #define DEFAULT_CACHELINE       32
 503 #define ATH_DEFAULT_NOISE_FLOOR -95
 504 #define ATH_REGCLASSIDS_MAX     10
 505 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 506 #define ATH_MAX_SW_RETRIES      10
 507 #define ATH_CHAN_MAX            255
 508 #define IEEE80211_WEP_NKID      4       /* number of key ids */
 509
 510 /*
 511  * The key cache is used for h/w cipher state and also for
 512  * tracking station state such as the current tx antenna.
 513  * We also setup a mapping table between key cache slot indices
 514  * and station state to short-circuit node lookups on rx.
 515  * Different parts have different size key caches.  We handle
 516  * up to ATH_KEYMAX entries (could dynamically allocate state).
 517  */
 518 #define ATH_KEYMAX              128     /* max key cache size we handle */
 519
 520 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 521 #define ATH_RSSI_DUMMY_MARKER   0x127
 522 #define ATH_RATE_DUMMY_MARKER   0
 523
 524 #define SC_OP_INVALID           BIT(0)
 525 #define SC_OP_BEACONS           BIT(1)
 526 #define SC_OP_RXAGGR            BIT(2)
 527 #define SC_OP_TXAGGR            BIT(3)
 528 #define SC_OP_FULL_RESET        BIT(4)
 529 #define SC_OP_PREAMBLE_SHORT    BIT(5)
 530 #define SC_OP_PROTECT_ENABLE    BIT(6)
 531 #define SC_OP_RXFLUSH           BIT(7)
 532 #define SC_OP_LED_ASSOCIATED    BIT(8)
 533 #define SC_OP_RFKILL_REGISTERED BIT(9)
 534 #define SC_OP_RFKILL_SW_BLOCKED BIT(10)
 535 #define SC_OP_RFKILL_HW_BLOCKED BIT(11)
 536 #define SC_OP_WAIT_FOR_BEACON   BIT(12)
 537 #define SC_OP_LED_ON            BIT(13)
 538 #define SC_OP_SCANNING          BIT(14)
 539 #define SC_OP_TSF_RESET         BIT(15)
 540
 541 struct ath_bus_ops {
 542         void            (*read_cachesize)(struct ath_softc *sc, int *csz);
 543         void            (*cleanup)(struct ath_softc *sc);
 544         bool            (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data);
 545 };
 546
 547 struct ath_wiphy;
 548
 549 struct ath_softc {
 550         struct ieee80211_hw *hw;
 551         struct device *dev;
 552
 553         spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
 554         struct ath_wiphy *pri_wiphy;
 555         struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
 556                                        * have NULL entries */
 557         int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
 558         int chan_idx;
 559         int chan_is_ht;
 560         struct ath_wiphy *next_wiphy;
 561         struct work_struct chan_work;
 562         int wiphy_select_failures;
 563         unsigned long wiphy_select_first_fail;
 564         struct delayed_work wiphy_work;
 565         unsigned long wiphy_scheduler_int;
 566         int wiphy_scheduler_index;
 567
 568         struct tasklet_struct intr_tq;
 569         struct tasklet_struct bcon_tasklet;
 570         struct ath_hw *sc_ah;
 571         void __iomem *mem;
 572         int irq;
 573         spinlock_t sc_resetlock;
 574         spinlock_t sc_serial_rw;
 575         struct mutex mutex;
 576
 577         u8 curbssid[ETH_ALEN];
 578         u8 bssidmask[ETH_ALEN];
 579         u32 intrstatus;
 580         u32 sc_flags; /* SC_OP_* */
 581         u16 curtxpow;
 582         u16 curaid;
 583         u16 cachelsz;
 584         u8 nbcnvifs;
 585         u16 nvifs;
 586         u8 tx_chainmask;
 587         u8 rx_chainmask;
 588         u32 keymax;
 589         DECLARE_BITMAP(keymap, ATH_KEYMAX);
 590         u8 splitmic;
 591         atomic_t ps_usecount;
 592         enum ath9k_int imask;
 593         enum ath9k_ht_extprotspacing ht_extprotspacing;
 594         enum ath9k_ht_macmode tx_chan_width;
 595
 596         struct ath_config config;
 597         struct ath_rx rx;
 598         struct ath_tx tx;
 599         struct ath_beacon beacon;
 600         struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
 601         struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
 602         struct ath_rate_table *cur_rate_table;
 603         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 604
 605         struct ath_led radio_led;
 606         struct ath_led assoc_led;
 607         struct ath_led tx_led;
 608         struct ath_led rx_led;
 609         struct delayed_work ath_led_blink_work;
 610         int led_on_duration;
 611         int led_off_duration;
 612         int led_on_cnt;
 613         int led_off_cnt;
 614
 615         struct ath_rfkill rf_kill;
 616         struct ath_ani ani;
 617         struct ath9k_node_stats nodestats;
 618 #ifdef CONFIG_ATH9K_DEBUG
 619         struct ath9k_debug debug;
 620 #endif
 621         struct ath_bus_ops *bus_ops;
 622 };
 623
 624 struct ath_wiphy {
 625         struct ath_softc *sc; /* shared for all virtual wiphys */
 626         struct ieee80211_hw *hw;
 627         enum ath_wiphy_state {
 628                 ATH_WIPHY_INACTIVE,
 629                 ATH_WIPHY_ACTIVE,
 630                 ATH_WIPHY_PAUSING,
 631                 ATH_WIPHY_PAUSED,
 632                 ATH_WIPHY_SCAN,
 633         } state;
 634         int chan_idx;
 635         int chan_is_ht;
 636 };
 637
 638 int ath_reset(struct ath_softc *sc, bool retry_tx);
 639 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
 640 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 641 int ath_cabq_update(struct ath_softc *);
 642
 643 static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
 644 {
 645         sc->bus_ops->read_cachesize(sc, csz);
 646 }
 647
 648 static inline void ath_bus_cleanup(struct ath_softc *sc)
 649 {
 650         sc->bus_ops->cleanup(sc);
 651 }
 652
 653 extern struct ieee80211_ops ath9k_ops;
 654
 655 irqreturn_t ath_isr(int irq, void *dev);
 656 void ath_cleanup(struct ath_softc *sc);
 657 int ath_attach(u16 devid, struct ath_softc *sc);
 658 void ath_detach(struct ath_softc *sc);
 659 const char *ath_mac_bb_name(u32 mac_bb_version);
 660 const char *ath_rf_name(u16 rf_version);
 661 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
 662 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
 663                            struct ath9k_channel *ichan);
 664 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 665 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 666                     struct ath9k_channel *hchan);
 667 void ath_radio_enable(struct ath_softc *sc);
 668 void ath_radio_disable(struct ath_softc *sc);
 669
 670 #ifdef CONFIG_PCI
 671 int ath_pci_init(void);
 672 void ath_pci_exit(void);
 673 #else
 674 static inline int ath_pci_init(void) { return 0; };
 675 static inline void ath_pci_exit(void) {};
 676 #endif
 677
 678 #ifdef CONFIG_ATHEROS_AR71XX
 679 int ath_ahb_init(void);
 680 void ath_ahb_exit(void);
 681 #else
 682 static inline int ath_ahb_init(void) { return 0; };
 683 static inline void ath_ahb_exit(void) {};
 684 #endif
 685
 686 static inline void ath9k_ps_wakeup(struct ath_softc *sc)
 687 {
 688         if (atomic_inc_return(&sc->ps_usecount) == 1)
 689                 if (sc->sc_ah->power_mode !=  ATH9K_PM_AWAKE) {
 690                         sc->sc_ah->restore_mode = sc->sc_ah->power_mode;
 691                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 692                 }
 693 }
 694
 695 static inline void ath9k_ps_restore(struct ath_softc *sc)
 696 {
 697         if (atomic_dec_and_test(&sc->ps_usecount))
 698                 if ((sc->hw->conf.flags & IEEE80211_CONF_PS) &&
 699                     !(sc->sc_flags & SC_OP_WAIT_FOR_BEACON))
 700                         ath9k_hw_setpower(sc->sc_ah,
 701                                           sc->sc_ah->restore_mode);
 702 }
 703
 704
 705 void ath9k_set_bssid_mask(struct ieee80211_hw *hw);
 706 int ath9k_wiphy_add(struct ath_softc *sc);
 707 int ath9k_wiphy_del(struct ath_wiphy *aphy);
 708 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
 709 int ath9k_wiphy_pause(struct ath_wiphy *aphy);
 710 int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
 711 int ath9k_wiphy_select(struct ath_wiphy *aphy);
 712 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
 713 void ath9k_wiphy_chan_work(struct work_struct *work);
 714 bool ath9k_wiphy_started(struct ath_softc *sc);
 715 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
 716                                   struct ath_wiphy *selected);
 717 bool ath9k_wiphy_scanning(struct ath_softc *sc);
 718 void ath9k_wiphy_work(struct work_struct *work);
 719
 720 /*
 721  * Read and write, they both share the same lock. We do this to serialize
 722  * reads and writes on Atheros 802.11n PCI devices only. This is required
 723  * as the FIFO on these devices can only accept sanely 2 requests. After
 724  * that the device goes bananas. Serializing the reads/writes prevents this
 725  * from happening.
 726  */
 727
 728 static inline void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
 729 {
 730         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
 731                 unsigned long flags;
 732                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 733                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 734                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 735         } else
 736                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 737 }
 738
 739 static inline unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
 740 {
 741         u32 val;
 742         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
 743                 unsigned long flags;
 744                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 745                 val = ioread32(ah->ah_sc->mem + reg_offset);
 746                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 747         } else
 748                 val = ioread32(ah->ah_sc->mem + reg_offset);
 749         return val;
 750 }
 751
 752 #endif /* ATH9K_H */