arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h

   1 /*
   2  * file:        include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
   3  * based on:
   4  * author:
   5  *
   6  * created:
   7  * description:
   8  *      blackfin serial driver head file
   9  * rev:
  10  *
  11  * modified:
  12  *
  13  *
  14  * bugs:         enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * this program is free software; you can redistribute it and/or modify
  17  * it under the terms of the gnu general public license as published by
  18  * the free software foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * this program is distributed in the hope that it will be useful,
  22  * but without any warranty; without even the implied warranty of
  23  * merchantability or fitness for a particular purpose.  see the
  24  * gnu general public license for more details.
  25  *
  26  * you should have received a copy of the gnu general public license
  27  * along with this program; see the file copying.
  28  * if not, write to the free software foundation,
  29  * 59 temple place - suite 330, boston, ma 02111-1307, usa.
  30  */
  31
  32 #include <linux/serial.h>
  33 #include <asm/dma.h>
  34 #include <asm/portmux.h>
  35
  36 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  37 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  38 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  39 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
  40 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  41 #define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
  42 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  43 #define UART_GET_MSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MSR))
  44 #define UART_GET_MCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MCR))
  45
  46 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  47 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  48 #define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
  49 #define UART_CLEAR_IER(uart,v)  bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
  50 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  51 #define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
  52 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  53 #define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
  54 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  55 #define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
  56 #define UART_CLEAR_SCTS(uart)   bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
  57
  58 #define UART_SET_DLAB(uart)     /* MMRs not muxed on BF54x */
  59 #define UART_CLEAR_DLAB(uart)   /* MMRs not muxed on BF54x */
  60
  61 #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
  62 #define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
  63 #define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
  64 #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
  65 #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
  66
  67 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
  68         defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
  69 # define CONFIG_SERIAL_BFIN_HARD_CTSRTS
  70 #endif
  71
  72 #define BFIN_UART_TX_FIFO_SIZE  2
  73
  74 /*
  75  * The pin configuration is different from schematic
  76  */
  77 struct bfin_serial_port {
  78         struct uart_port        port;
  79         unsigned int            old_status;
  80         int                     status_irq;
  81 #ifdef CONFIG_SERIAL_BFIN_DMA
  82         int                     tx_done;
  83         int                     tx_count;
  84         struct circ_buf         rx_dma_buf;
  85         struct timer_list       rx_dma_timer;
  86         int                     rx_dma_nrows;
  87         unsigned int            tx_dma_channel;
  88         unsigned int            rx_dma_channel;
  89         struct work_struct      tx_dma_workqueue;
  90 #endif
  91 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
  92         int                     scts;
  93         int                     cts_pin;
  94         int                     rts_pin;
  95 #endif
  96 };
  97
  98 struct bfin_serial_res {
  99         unsigned long   uart_base_addr;
 100         int             uart_irq;
 101         int             uart_status_irq;
 102 #ifdef CONFIG_SERIAL_BFIN_DMA
 103         unsigned int    uart_tx_dma_channel;
 104         unsigned int    uart_rx_dma_channel;
 105 #endif
 106 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 107         int             uart_cts_pin;
 108         int             uart_rts_pin;
 109 #endif
 110 };
 111
 112 struct bfin_serial_res bfin_serial_resource[] = {
 113 #ifdef CONFIG_SERIAL_BFIN_UART0
 114         {
 115         0xFFC00400,
 116         IRQ_UART0_RX,
 117         IRQ_UART0_ERROR,
 118 #ifdef CONFIG_SERIAL_BFIN_DMA
 119         CH_UART0_TX,
 120         CH_UART0_RX,
 121 #endif
 122 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 123         0,
 124         0,
 125 #endif
 126         },
 127 #endif
 128 #ifdef CONFIG_SERIAL_BFIN_UART1
 129         {
 130         0xFFC02000,
 131         IRQ_UART1_RX,
 132         IRQ_UART1_ERROR,
 133 #ifdef CONFIG_SERIAL_BFIN_DMA
 134         CH_UART1_TX,
 135         CH_UART1_RX,
 136 #endif
 137 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 138         GPIO_PE10,
 139         GPIO_PE9,
 140 #endif
 141         },
 142 #endif
 143 #ifdef CONFIG_SERIAL_BFIN_UART2
 144         {
 145         0xFFC02100,
 146         IRQ_UART2_RX,
 147         IRQ_UART2_ERROR,
 148 #ifdef CONFIG_SERIAL_BFIN_DMA
 149         CH_UART2_TX,
 150         CH_UART2_RX,
 151 #endif
 152 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 153         0,
 154         0,
 155 #endif
 156         },
 157 #endif
 158 #ifdef CONFIG_SERIAL_BFIN_UART3
 159         {
 160         0xFFC03100,
 161         IRQ_UART3_RX,
 162         IRQ_UART3_ERROR,
 163 #ifdef CONFIG_SERIAL_BFIN_DMA
 164         CH_UART3_TX,
 165         CH_UART3_RX,
 166 #endif
 167 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 168         GPIO_PB3,
 169         GPIO_PB2,
 170 #endif
 171         },
 172 #endif
 173 };
 174
 175 #define DRIVER_NAME "bfin-uart"