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[PATCH] ARM: Fixup missing includes in arch/arm/mm/proc-<cputype>.S
[linux-2.6/kvm.git] / drivers / ide / pci / pdc202xx_old.c
blobb46022a11bef82a2576d0e684282780ba814e0d6
1 /*
2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.36 Sept 11, 2002
3 *
4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
5 *
6 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
7 * compiled into the kernel if you have more than one card installed.
8 * Note that BIOS v1.29 is reported to fix the problem. Since this is
9 * safe chipset tuning, including this support is harmless
10 *
11 * Promise Ultra66 cards with BIOS v1.11 this
12 * compiled into the kernel if you have more than one card installed.
13 *
14 * Promise Ultra100 cards.
15 *
16 * The latest chipset code will support the following ::
17 * Three Ultra33 controllers and 12 drives.
18 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
19 * The 8/4 ratio is a BIOS code limit by promise.
20 *
21 * UNLESS you enable "CONFIG_PDC202XX_BURST"
22 *
23 */
24
25 /*
26 * Portions Copyright (C) 1999 Promise Technology, Inc.
27 * Author: Frank Tiernan (frankt@promise.com)
28 * Released under terms of General Public License
29 */
30
31 #include <linux/types.h>
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/delay.h>
35 #include <linux/timer.h>
36 #include <linux/mm.h>
37 #include <linux/ioport.h>
38 #include <linux/blkdev.h>
39 #include <linux/hdreg.h>
40 #include <linux/interrupt.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/ide.h>
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47
48 #define PDC202_DEBUG_CABLE 0
49 #define PDC202XX_DEBUG_DRIVE_INFO 0
50
51 static const char *pdc_quirk_drives[] = {
52 "QUANTUM FIREBALLlct08 08",
53 "QUANTUM FIREBALLP KA6.4",
54 "QUANTUM FIREBALLP KA9.1",
55 "QUANTUM FIREBALLP LM20.4",
56 "QUANTUM FIREBALLP KX13.6",
57 "QUANTUM FIREBALLP KX20.5",
58 "QUANTUM FIREBALLP KX27.3",
59 "QUANTUM FIREBALLP LM20.5",
60 NULL
61 };
62
63 /* A Register */
64 #define SYNC_ERRDY_EN 0xC0
65
66 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
67 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
68 #define IORDY_EN 0x20 /* PIO: IOREADY */
69 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
70
71 #define PA3 0x08 /* PIO"A" timing */
72 #define PA2 0x04 /* PIO"A" timing */
73 #define PA1 0x02 /* PIO"A" timing */
74 #define PA0 0x01 /* PIO"A" timing */
75
76 /* B Register */
77
78 #define MB2 0x80 /* DMA"B" timing */
79 #define MB1 0x40 /* DMA"B" timing */
80 #define MB0 0x20 /* DMA"B" timing */
81
82 #define PB4 0x10 /* PIO_FORCE 1:0 */
83
84 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
85 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
86 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
87 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
88
89 /* C Register */
90 #define IORDYp_NO_SPEED 0x4F
91 #define SPEED_DIS 0x0F
92
93 #define DMARQp 0x80
94 #define IORDYp 0x40
95 #define DMAR_EN 0x20
96 #define DMAW_EN 0x10
97
98 #define MC3 0x08 /* DMA"C" timing */
99 #define MC2 0x04 /* DMA"C" timing */
100 #define MC1 0x02 /* DMA"C" timing */
101 #define MC0 0x01 /* DMA"C" timing */
102
103 static u8 pdc202xx_ratemask (ide_drive_t *drive)
104 {
105 u8 mode;
106
107 switch(HWIF(drive)->pci_dev->device) {
108 case PCI_DEVICE_ID_PROMISE_20267:
109 case PCI_DEVICE_ID_PROMISE_20265:
110 mode = 3;
111 break;
112 case PCI_DEVICE_ID_PROMISE_20263:
113 case PCI_DEVICE_ID_PROMISE_20262:
114 mode = 2;
115 break;
116 case PCI_DEVICE_ID_PROMISE_20246:
117 return 1;
118 default:
119 return 0;
120 }
121 if (!eighty_ninty_three(drive))
122 mode = min(mode, (u8)1);
123 return mode;
124 }
125
126 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
127 {
128 struct hd_driveid *id = drive->id;
129
130 if (pdc_quirk_drives == list) {
131 while (*list) {
132 if (strstr(id->model, *list++)) {
133 return 2;
134 }
135 }
136 } else {
137 while (*list) {
138 if (!strcmp(*list++,id->model)) {
139 return 1;
140 }
141 }
142 }
143 return 0;
144 }
145
146 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
147 {
148 ide_hwif_t *hwif = HWIF(drive);
149 struct pci_dev *dev = hwif->pci_dev;
150 u8 drive_pci = 0x60 + (drive->dn << 2);
151 u8 speed = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
152
153 u32 drive_conf;
154 u8 AP, BP, CP, DP;
155 u8 TA = 0, TB = 0, TC = 0;
156
157 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
158 return -1;
159
160 pci_read_config_dword(dev, drive_pci, &drive_conf);
161 pci_read_config_byte(dev, (drive_pci), &AP);
162 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
163 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
164 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
165
166 if (speed < XFER_SW_DMA_0) {
167 if ((AP & 0x0F) || (BP & 0x07)) {
168 /* clear PIO modes of lower 8421 bits of A Register */
169 pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
170 pci_read_config_byte(dev, (drive_pci), &AP);
171
172 /* clear PIO modes of lower 421 bits of B Register */
173 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
174 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
175
176 pci_read_config_byte(dev, (drive_pci), &AP);
177 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
178 }
179 } else {
180 if ((BP & 0xF0) && (CP & 0x0F)) {
181 /* clear DMA modes of upper 842 bits of B Register */
182 /* clear PIO forced mode upper 1 bit of B Register */
183 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
184 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
185
186 /* clear DMA modes of lower 8421 bits of C Register */
187 pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
188 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
189 }
190 }
191
192 pci_read_config_byte(dev, (drive_pci), &AP);
193 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
194 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
195
196 switch(speed) {
197 case XFER_UDMA_6: speed = XFER_UDMA_5;
198 case XFER_UDMA_5:
199 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
200 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
201 case XFER_UDMA_3:
202 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
203 case XFER_UDMA_0:
204 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
205 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
206 case XFER_MW_DMA_0:
207 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
208 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
209 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
210 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
211 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
212 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
213 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
214 case XFER_PIO_0:
215 default: TA = 0x09; TB = 0x13; break;
216 }
217
218 if (speed < XFER_SW_DMA_0) {
219 pci_write_config_byte(dev, (drive_pci), AP|TA);
220 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
221 } else {
222 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
223 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
224 }
225
226 #if PDC202XX_DEBUG_DRIVE_INFO
227 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
228 drive->name, ide_xfer_verbose(speed),
229 drive->dn, drive_conf);
230 pci_read_config_dword(dev, drive_pci, &drive_conf);
231 printk("0x%08x\n", drive_conf);
232 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
233
234 return (ide_config_drive_speed(drive, speed));
235 }
236
237
238 /* 0 1 2 3 4 5 6 7 8
239 * 960, 480, 390, 300, 240, 180, 120, 90, 60
240 * 180, 150, 120, 90, 60
241 * DMA_Speed
242 * 180, 120, 90, 90, 90, 60, 30
243 * 11, 5, 4, 3, 2, 1, 0
244 */
245 static void config_chipset_for_pio (ide_drive_t *drive, u8 pio)
246 {
247 u8 speed = 0;
248
249 if (pio == 5) pio = 4;
250 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
251
252 pdc202xx_tune_chipset(drive, speed);
253 }
254
255 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
256 {
257 u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
258 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
259 return (CIS & mask) ? 1 : 0;
260 }
261
262 /*
263 * Set the control register to use the 66MHz system
264 * clock for UDMA 3/4/5 mode operation when necessary.
265 *
266 * It may also be possible to leave the 66MHz clock on
267 * and readjust the timing parameters.
268 */
269 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
270 {
271 unsigned long clock_reg = hwif->dma_master + 0x11;
272 u8 clock = hwif->INB(clock_reg);
273
274 hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
275 }
276
277 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
278 {
279 unsigned long clock_reg = hwif->dma_master + 0x11;
280 u8 clock = hwif->INB(clock_reg);
281
282 hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
283 }
284
285 static int config_chipset_for_dma (ide_drive_t *drive)
286 {
287 struct hd_driveid *id = drive->id;
288 ide_hwif_t *hwif = HWIF(drive);
289 struct pci_dev *dev = hwif->pci_dev;
290 u32 drive_conf = 0;
291 u8 drive_pci = 0x60 + (drive->dn << 2);
292 u8 test1 = 0, test2 = 0, speed = -1;
293 u8 AP = 0, cable = 0;
294
295 u8 ultra_66 = ((id->dma_ultra & 0x0010) ||
296 (id->dma_ultra & 0x0008)) ? 1 : 0;
297
298 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
299 cable = pdc202xx_old_cable_detect(hwif);
300 else
301 ultra_66 = 0;
302
303 if (ultra_66 && cable) {
304 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
305 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
306 }
307
308 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
309 pdc_old_disable_66MHz_clock(drive->hwif);
310
311 drive_pci = 0x60 + (drive->dn << 2);
312 pci_read_config_dword(dev, drive_pci, &drive_conf);
313 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
314 goto chipset_is_set;
315
316 pci_read_config_byte(dev, drive_pci, &test1);
317 if (!(test1 & SYNC_ERRDY_EN)) {
318 if (drive->select.b.unit & 0x01) {
319 pci_read_config_byte(dev, drive_pci - 4, &test2);
320 if ((test2 & SYNC_ERRDY_EN) &&
321 !(test1 & SYNC_ERRDY_EN)) {
322 pci_write_config_byte(dev, drive_pci,
323 test1|SYNC_ERRDY_EN);
324 }
325 } else {
326 pci_write_config_byte(dev, drive_pci,
327 test1|SYNC_ERRDY_EN);
328 }
329 }
330
331 chipset_is_set:
332
333 if (drive->media == ide_disk) {
334 pci_read_config_byte(dev, (drive_pci), &AP);
335 if (id->capability & 4) /* IORDY_EN */
336 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
337 pci_read_config_byte(dev, (drive_pci), &AP);
338 if (drive->media == ide_disk) /* PREFETCH_EN */
339 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
340 }
341
342 speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
343
344 if (!(speed)) {
345 /* restore original pci-config space */
346 pci_write_config_dword(dev, drive_pci, drive_conf);
347 return 0;
348 }
349
350 (void) hwif->speedproc(drive, speed);
351 return ide_dma_enable(drive);
352 }
353
354 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
355 {
356 ide_hwif_t *hwif = HWIF(drive);
357 struct hd_driveid *id = drive->id;
358
359 drive->init_speed = 0;
360
361 if (id && (id->capability & 1) && drive->autodma) {
362
363 if (ide_use_dma(drive)) {
364 if (config_chipset_for_dma(drive))
365 return hwif->ide_dma_on(drive);
366 }
367
368 goto fast_ata_pio;
369
370 } else if ((id->capability & 8) || (id->field_valid & 2)) {
371 fast_ata_pio:
372 hwif->tuneproc(drive, 5);
373 return hwif->ide_dma_off_quietly(drive);
374 }
375 /* IORDY not supported */
376 return 0;
377 }
378
379 static int pdc202xx_quirkproc (ide_drive_t *drive)
380 {
381 return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
382 }
383
384 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
385 {
386 if (drive->current_speed > XFER_UDMA_2)
387 pdc_old_enable_66MHz_clock(drive->hwif);
388 if (drive->addressing == 1) {
389 struct request *rq = HWGROUP(drive)->rq;
390 ide_hwif_t *hwif = HWIF(drive);
391 unsigned long high_16 = hwif->dma_master;
392 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
393 u32 word_count = 0;
394 u8 clock = hwif->INB(high_16 + 0x11);
395
396 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
397 word_count = (rq->nr_sectors << 8);
398 word_count = (rq_data_dir(rq) == READ) ?
399 word_count | 0x05000000 :
400 word_count | 0x06000000;
401 hwif->OUTL(word_count, atapi_reg);
402 }
403 ide_dma_start(drive);
404 }
405
406 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
407 {
408 if (drive->addressing == 1) {
409 ide_hwif_t *hwif = HWIF(drive);
410 unsigned long high_16 = hwif->dma_master;
411 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
412 u8 clock = 0;
413
414 hwif->OUTL(0, atapi_reg); /* zero out extra */
415 clock = hwif->INB(high_16 + 0x11);
416 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
417 }
418 if (drive->current_speed > XFER_UDMA_2)
419 pdc_old_disable_66MHz_clock(drive->hwif);
420 return __ide_dma_end(drive);
421 }
422
423 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
424 {
425 ide_hwif_t *hwif = HWIF(drive);
426 unsigned long high_16 = hwif->dma_master;
427 u8 dma_stat = hwif->INB(hwif->dma_status);
428 u8 sc1d = hwif->INB((high_16 + 0x001d));
429
430 if (hwif->channel) {
431 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
432 if ((sc1d & 0x50) == 0x50)
433 goto somebody_else;
434 else if ((sc1d & 0x40) == 0x40)
435 return (dma_stat & 4) == 4;
436 } else {
437 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
438 if ((sc1d & 0x05) == 0x05)
439 goto somebody_else;
440 else if ((sc1d & 0x04) == 0x04)
441 return (dma_stat & 4) == 4;
442 }
443 somebody_else:
444 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
445 }
446
447 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
448 {
449 if (HWIF(drive)->resetproc != NULL)
450 HWIF(drive)->resetproc(drive);
451 return __ide_dma_lostirq(drive);
452 }
453
454 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
455 {
456 if (HWIF(drive)->resetproc != NULL)
457 HWIF(drive)->resetproc(drive);
458 return __ide_dma_timeout(drive);
459 }
460
461 static void pdc202xx_reset_host (ide_hwif_t *hwif)
462 {
463 unsigned long high_16 = hwif->dma_master;
464 u8 udma_speed_flag = hwif->INB(high_16|0x001f);
465
466 hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
467 mdelay(100);
468 hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
469 mdelay(2000); /* 2 seconds ?! */
470
471 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
472 hwif->channel ? "Secondary" : "Primary");
473 }
474
475 static void pdc202xx_reset (ide_drive_t *drive)
476 {
477 ide_hwif_t *hwif = HWIF(drive);
478 ide_hwif_t *mate = hwif->mate;
479
480 pdc202xx_reset_host(hwif);
481 pdc202xx_reset_host(mate);
482 hwif->tuneproc(drive, 5);
483 }
484
485 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
486 const char *name)
487 {
488 /* This doesn't appear needed */
489 if (dev->resource[PCI_ROM_RESOURCE].start) {
490 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
491 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
492 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
493 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
494 }
495
496 return dev->irq;
497 }
498
499 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
500 {
501 struct pci_dev *dev = hwif->pci_dev;
502
503 /* PDC20265 has problems with large LBA48 requests */
504 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
505 (dev->device == PCI_DEVICE_ID_PROMISE_20265))
506 hwif->rqsize = 256;
507
508 hwif->autodma = 0;
509 hwif->tuneproc = &config_chipset_for_pio;
510 hwif->quirkproc = &pdc202xx_quirkproc;
511
512 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
513 hwif->resetproc = &pdc202xx_reset;
514
515 hwif->speedproc = &pdc202xx_tune_chipset;
516
517 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
518
519 hwif->ultra_mask = 0x3f;
520 hwif->mwdma_mask = 0x07;
521 hwif->swdma_mask = 0x07;
522
523 hwif->err_stops_fifo = 1;
524
525 hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
526 hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
527 hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
528
529 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
530 if (!(hwif->udma_four))
531 hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
532 hwif->dma_start = &pdc202xx_old_ide_dma_start;
533 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
534 }
535 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
536
537 if (!noautodma)
538 hwif->autodma = 1;
539 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
540 #if PDC202_DEBUG_CABLE
541 printk(KERN_DEBUG "%s: %s-pin cable\n",
542 hwif->name, hwif->udma_four ? "80" : "40");
543 #endif /* PDC202_DEBUG_CABLE */
544 }
545
546 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
547 {
548 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
549
550 if (hwif->channel) {
551 ide_setup_dma(hwif, dmabase, 8);
552 return;
553 }
554
555 udma_speed_flag = hwif->INB((dmabase|0x1f));
556 primary_mode = hwif->INB((dmabase|0x1a));
557 secondary_mode = hwif->INB((dmabase|0x1b));
558 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
559 "Primary %s Mode " \
560 "Secondary %s Mode.\n", hwif->cds->name,
561 (udma_speed_flag & 1) ? "EN" : "DIS",
562 (primary_mode & 1) ? "MASTER" : "PCI",
563 (secondary_mode & 1) ? "MASTER" : "PCI" );
564
565 #ifdef CONFIG_PDC202XX_BURST
566 if (!(udma_speed_flag & 1)) {
567 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
568 hwif->cds->name, udma_speed_flag,
569 (udma_speed_flag|1));
570 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
571 printk("%sACTIVE\n",
572 (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
573 }
574 #endif /* CONFIG_PDC202XX_BURST */
575 #ifdef CONFIG_PDC202XX_MASTER
576 if (!(primary_mode & 1)) {
577 printk(KERN_INFO "%s: FORCING PRIMARY MODE BIT "
578 "0x%02x -> 0x%02x ", hwif->cds->name,
579 primary_mode, (primary_mode|1));
580 hwif->OUTB(primary_mode|1, (dmabase|0x1a));
581 printk("%s\n",
582 (hwif->INB((dmabase|0x1a)) & 1) ? "MASTER" : "PCI");
583 }
584
585 if (!(secondary_mode & 1)) {
586 printk(KERN_INFO "%s: FORCING SECONDARY MODE BIT "
587 "0x%02x -> 0x%02x ", hwif->cds->name,
588 secondary_mode, (secondary_mode|1));
589 hwif->OUTB(secondary_mode|1, (dmabase|0x1b));
590 printk("%s\n",
591 (hwif->INB((dmabase|0x1b)) & 1) ? "MASTER" : "PCI");
592 }
593 #endif /* CONFIG_PDC202XX_MASTER */
594
595 ide_setup_dma(hwif, dmabase, 8);
596 }
597
598 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
599 ide_pci_device_t *d)
600 {
601 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
602 u8 irq = 0, irq2 = 0;
603 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
604 /* 0xbc */
605 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
606 if (irq != irq2) {
607 pci_write_config_byte(dev,
608 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
609 printk(KERN_INFO "%s: pci-config space interrupt "
610 "mirror fixed.\n", d->name);
611 }
612 }
613 return ide_setup_pci_device(dev, d);
614 }
615
616 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
617 ide_pci_device_t *d)
618 {
619 if ((dev->bus->self) &&
620 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
621 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
622 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
623 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
624 "attached to I2O RAID controller.\n");
625 return -ENODEV;
626 }
627 return ide_setup_pci_device(dev, d);
628 }
629
630 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
631 ide_pci_device_t *d)
632 {
633 return ide_setup_pci_device(dev, d);
634 }
635
636 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
637 { /* 0 */
638 .name = "PDC20246",
639 .init_setup = init_setup_pdc202ata4,
640 .init_chipset = init_chipset_pdc202xx,
641 .init_hwif = init_hwif_pdc202xx,
642 .init_dma = init_dma_pdc202xx,
643 .channels = 2,
644 .autodma = AUTODMA,
645 .bootable = OFF_BOARD,
646 .extra = 16,
647 },{ /* 1 */
648 .name = "PDC20262",
649 .init_setup = init_setup_pdc202ata4,
650 .init_chipset = init_chipset_pdc202xx,
651 .init_hwif = init_hwif_pdc202xx,
652 .init_dma = init_dma_pdc202xx,
653 .channels = 2,
654 .autodma = AUTODMA,
655 .bootable = OFF_BOARD,
656 .extra = 48,
657 },{ /* 2 */
658 .name = "PDC20263",
659 .init_setup = init_setup_pdc202ata4,
660 .init_chipset = init_chipset_pdc202xx,
661 .init_hwif = init_hwif_pdc202xx,
662 .init_dma = init_dma_pdc202xx,
663 .channels = 2,
664 .autodma = AUTODMA,
665 .bootable = OFF_BOARD,
666 .extra = 48,
667 },{ /* 3 */
668 .name = "PDC20265",
669 .init_setup = init_setup_pdc20265,
670 .init_chipset = init_chipset_pdc202xx,
671 .init_hwif = init_hwif_pdc202xx,
672 .init_dma = init_dma_pdc202xx,
673 .channels = 2,
674 .autodma = AUTODMA,
675 .bootable = OFF_BOARD,
676 .extra = 48,
677 },{ /* 4 */
678 .name = "PDC20267",
679 .init_setup = init_setup_pdc202xx,
680 .init_chipset = init_chipset_pdc202xx,
681 .init_hwif = init_hwif_pdc202xx,
682 .init_dma = init_dma_pdc202xx,
683 .channels = 2,
684 .autodma = AUTODMA,
685 .bootable = OFF_BOARD,
686 .extra = 48,
687 }
688 };
689
690 /**
691 * pdc202xx_init_one - called when a PDC202xx is found
692 * @dev: the pdc202xx device
693 * @id: the matching pci id
694 *
695 * Called when the PCI registration layer (or the IDE initialization)
696 * finds a device matching our IDE device tables.
697 */
698
699 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
700 {
701 ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
702
703 return d->init_setup(dev, d);
704 }
705
706 static struct pci_device_id pdc202xx_pci_tbl[] = {
707 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
708 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
709 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
710 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
711 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
712 { 0, },
713 };
714 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
715
716 static struct pci_driver driver = {
717 .name = "Promise_Old_IDE",
718 .id_table = pdc202xx_pci_tbl,
719 .probe = pdc202xx_init_one,
720 };
721
722 static int pdc202xx_ide_init(void)
723 {
724 return ide_pci_register_driver(&driver);
725 }
726
727 module_init(pdc202xx_ide_init);
728
729 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
730 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
731 MODULE_LICENSE("GPL");
kernel-based virtual machine