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[PATCH] ARM: Fixup missing includes in arch/arm/mm/proc-<cputype>.S
[linux-2.6/kvm.git] / drivers / ide / pci / hpt366.c
blobe993a51f250e5fa026c718d5f66091cd2952a5d2
1 /*
2 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
13 *
14 * Highpoint have their own driver (source except for the raid part)
15 * available from http://www.highpoint-tech.com/hpt3xx-opensource-v131.tgz
16 * This may be useful to anyone wanting to work on the mainstream hpt IDE.
17 *
18 * Note that final HPT370 support was done by force extraction of GPL.
19 *
20 * - add function for getting/setting power status of drive
21 * - the HPT370's state machine can get confused. reset it before each dma
22 * xfer to prevent that from happening.
23 * - reset state engine whenever we get an error.
24 * - check for busmaster state at end of dma.
25 * - use new highpoint timings.
26 * - detect bus speed using highpoint register.
27 * - use pll if we don't have a clock table. added a 66MHz table that's
28 * just 2x the 33MHz table.
29 * - removed turnaround. NOTE: we never want to switch between pll and
30 * pci clocks as the chip can glitch in those cases. the highpoint
31 * approved workaround slows everything down too much to be useful. in
32 * addition, we would have to serialize access to each chip.
33 * Adrian Sun <a.sun@sun.com>
34 *
35 * add drive timings for 66MHz PCI bus,
36 * fix ATA Cable signal detection, fix incorrect /proc info
37 * add /proc display for per-drive PIO/DMA/UDMA mode and
38 * per-channel ATA-33/66 Cable detect.
39 * Duncan Laurie <void@sun.com>
40 *
41 * fixup /proc output for multiple controllers
42 * Tim Hockin <thockin@sun.com>
43 *
44 * On hpt366:
45 * Reset the hpt366 on error, reset on dma
46 * Fix disabling Fast Interrupt hpt366.
47 * Mike Waychison <crlf@sun.com>
48 *
49 * Added support for 372N clocking and clock switching. The 372N needs
50 * different clocks on read/write. This requires overloading rw_disk and
51 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
52 * keeping me sane.
53 * Alan Cox <alan@redhat.com>
54 *
55 */
56
57
58 #include <linux/types.h>
59 #include <linux/module.h>
60 #include <linux/kernel.h>
61 #include <linux/delay.h>
62 #include <linux/timer.h>
63 #include <linux/mm.h>
64 #include <linux/ioport.h>
65 #include <linux/blkdev.h>
66 #include <linux/hdreg.h>
67
68 #include <linux/interrupt.h>
69 #include <linux/pci.h>
70 #include <linux/init.h>
71 #include <linux/ide.h>
72
73 #include <asm/uaccess.h>
74 #include <asm/io.h>
75 #include <asm/irq.h>
76
77 /* various tuning parameters */
78 #define HPT_RESET_STATE_ENGINE
79 #undef HPT_DELAY_INTERRUPT
80 #undef HPT_SERIALIZE_IO
81
82 static const char *quirk_drives[] = {
83 "QUANTUM FIREBALLlct08 08",
84 "QUANTUM FIREBALLP KA6.4",
85 "QUANTUM FIREBALLP LM20.4",
86 "QUANTUM FIREBALLP LM20.5",
87 NULL
88 };
89
90 static const char *bad_ata100_5[] = {
91 "IBM-DTLA-307075",
92 "IBM-DTLA-307060",
93 "IBM-DTLA-307045",
94 "IBM-DTLA-307030",
95 "IBM-DTLA-307020",
96 "IBM-DTLA-307015",
97 "IBM-DTLA-305040",
98 "IBM-DTLA-305030",
99 "IBM-DTLA-305020",
100 "IC35L010AVER07-0",
101 "IC35L020AVER07-0",
102 "IC35L030AVER07-0",
103 "IC35L040AVER07-0",
104 "IC35L060AVER07-0",
105 "WDC AC310200R",
106 NULL
107 };
108
109 static const char *bad_ata66_4[] = {
110 "IBM-DTLA-307075",
111 "IBM-DTLA-307060",
112 "IBM-DTLA-307045",
113 "IBM-DTLA-307030",
114 "IBM-DTLA-307020",
115 "IBM-DTLA-307015",
116 "IBM-DTLA-305040",
117 "IBM-DTLA-305030",
118 "IBM-DTLA-305020",
119 "IC35L010AVER07-0",
120 "IC35L020AVER07-0",
121 "IC35L030AVER07-0",
122 "IC35L040AVER07-0",
123 "IC35L060AVER07-0",
124 "WDC AC310200R",
125 NULL
126 };
127
128 static const char *bad_ata66_3[] = {
129 "WDC AC310200R",
130 NULL
131 };
132
133 static const char *bad_ata33[] = {
134 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
135 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
136 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
137 "Maxtor 90510D4",
138 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
139 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
140 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
141 NULL
142 };
143
144 struct chipset_bus_clock_list_entry {
145 u8 xfer_speed;
146 unsigned int chipset_settings;
147 };
148
149 /* key for bus clock timings
150 * bit
151 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
152 * DMA. cycles = value + 1
153 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
154 * DMA. cycles = value + 1
155 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
156 * register access.
157 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
158 * register access.
159 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
160 * during task file register access.
161 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
162 * xfer.
163 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
164 * register access.
165 * 28 UDMA enable
166 * 29 DMA enable
167 * 30 PIO_MST enable. if set, the chip is in bus master mode during
168 * PIO.
169 * 31 FIFO enable.
170 */
171 static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
172 { XFER_UDMA_4, 0x900fd943 },
173 { XFER_UDMA_3, 0x900ad943 },
174 { XFER_UDMA_2, 0x900bd943 },
175 { XFER_UDMA_1, 0x9008d943 },
176 { XFER_UDMA_0, 0x9008d943 },
177
178 { XFER_MW_DMA_2, 0xa008d943 },
179 { XFER_MW_DMA_1, 0xa010d955 },
180 { XFER_MW_DMA_0, 0xa010d9fc },
181
182 { XFER_PIO_4, 0xc008d963 },
183 { XFER_PIO_3, 0xc010d974 },
184 { XFER_PIO_2, 0xc010d997 },
185 { XFER_PIO_1, 0xc010d9c7 },
186 { XFER_PIO_0, 0xc018d9d9 },
187 { 0, 0x0120d9d9 }
188 };
189
190 static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
191 { XFER_UDMA_4, 0x90c9a731 },
192 { XFER_UDMA_3, 0x90cfa731 },
193 { XFER_UDMA_2, 0x90caa731 },
194 { XFER_UDMA_1, 0x90cba731 },
195 { XFER_UDMA_0, 0x90c8a731 },
196
197 { XFER_MW_DMA_2, 0xa0c8a731 },
198 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
199 { XFER_MW_DMA_0, 0xa0c8a797 },
200
201 { XFER_PIO_4, 0xc0c8a731 },
202 { XFER_PIO_3, 0xc0c8a742 },
203 { XFER_PIO_2, 0xc0d0a753 },
204 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
205 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
206 { 0, 0x0120a7a7 }
207 };
208
209 static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
210 { XFER_UDMA_4, 0x90c98521 },
211 { XFER_UDMA_3, 0x90cf8521 },
212 { XFER_UDMA_2, 0x90cf8521 },
213 { XFER_UDMA_1, 0x90cb8521 },
214 { XFER_UDMA_0, 0x90cb8521 },
215
216 { XFER_MW_DMA_2, 0xa0ca8521 },
217 { XFER_MW_DMA_1, 0xa0ca8532 },
218 { XFER_MW_DMA_0, 0xa0ca8575 },
219
220 { XFER_PIO_4, 0xc0ca8521 },
221 { XFER_PIO_3, 0xc0ca8532 },
222 { XFER_PIO_2, 0xc0ca8542 },
223 { XFER_PIO_1, 0xc0d08572 },
224 { XFER_PIO_0, 0xc0d08585 },
225 { 0, 0x01208585 }
226 };
227
228 /* from highpoint documentation. these are old values */
229 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
230 /* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */
231 { XFER_UDMA_5, 0x16454e31 },
232 { XFER_UDMA_4, 0x16454e31 },
233 { XFER_UDMA_3, 0x166d4e31 },
234 { XFER_UDMA_2, 0x16494e31 },
235 { XFER_UDMA_1, 0x164d4e31 },
236 { XFER_UDMA_0, 0x16514e31 },
237
238 { XFER_MW_DMA_2, 0x26514e21 },
239 { XFER_MW_DMA_1, 0x26514e33 },
240 { XFER_MW_DMA_0, 0x26514e97 },
241
242 { XFER_PIO_4, 0x06514e21 },
243 { XFER_PIO_3, 0x06514e22 },
244 { XFER_PIO_2, 0x06514e33 },
245 { XFER_PIO_1, 0x06914e43 },
246 { XFER_PIO_0, 0x06914e57 },
247 { 0, 0x06514e57 }
248 };
249
250 static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
251 { XFER_UDMA_5, 0x14846231 },
252 { XFER_UDMA_4, 0x14886231 },
253 { XFER_UDMA_3, 0x148c6231 },
254 { XFER_UDMA_2, 0x148c6231 },
255 { XFER_UDMA_1, 0x14906231 },
256 { XFER_UDMA_0, 0x14986231 },
257
258 { XFER_MW_DMA_2, 0x26514e21 },
259 { XFER_MW_DMA_1, 0x26514e33 },
260 { XFER_MW_DMA_0, 0x26514e97 },
261
262 { XFER_PIO_4, 0x06514e21 },
263 { XFER_PIO_3, 0x06514e22 },
264 { XFER_PIO_2, 0x06514e33 },
265 { XFER_PIO_1, 0x06914e43 },
266 { XFER_PIO_0, 0x06914e57 },
267 { 0, 0x06514e57 }
268 };
269
270 /* these are the current (4 sep 2001) timings from highpoint */
271 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
272 { XFER_UDMA_5, 0x12446231 },
273 { XFER_UDMA_4, 0x12446231 },
274 { XFER_UDMA_3, 0x126c6231 },
275 { XFER_UDMA_2, 0x12486231 },
276 { XFER_UDMA_1, 0x124c6233 },
277 { XFER_UDMA_0, 0x12506297 },
278
279 { XFER_MW_DMA_2, 0x22406c31 },
280 { XFER_MW_DMA_1, 0x22406c33 },
281 { XFER_MW_DMA_0, 0x22406c97 },
282
283 { XFER_PIO_4, 0x06414e31 },
284 { XFER_PIO_3, 0x06414e42 },
285 { XFER_PIO_2, 0x06414e53 },
286 { XFER_PIO_1, 0x06814e93 },
287 { XFER_PIO_0, 0x06814ea7 },
288 { 0, 0x06814ea7 }
289 };
290
291 /* 2x 33MHz timings */
292 static struct chipset_bus_clock_list_entry sixty_six_base_hpt370a[] = {
293 { XFER_UDMA_5, 0x1488e673 },
294 { XFER_UDMA_4, 0x1488e673 },
295 { XFER_UDMA_3, 0x1498e673 },
296 { XFER_UDMA_2, 0x1490e673 },
297 { XFER_UDMA_1, 0x1498e677 },
298 { XFER_UDMA_0, 0x14a0e73f },
299
300 { XFER_MW_DMA_2, 0x2480fa73 },
301 { XFER_MW_DMA_1, 0x2480fa77 },
302 { XFER_MW_DMA_0, 0x2480fb3f },
303
304 { XFER_PIO_4, 0x0c82be73 },
305 { XFER_PIO_3, 0x0c82be95 },
306 { XFER_PIO_2, 0x0c82beb7 },
307 { XFER_PIO_1, 0x0d02bf37 },
308 { XFER_PIO_0, 0x0d02bf5f },
309 { 0, 0x0d02bf5f }
310 };
311
312 static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
313 { XFER_UDMA_5, 0x12848242 },
314 { XFER_UDMA_4, 0x12ac8242 },
315 { XFER_UDMA_3, 0x128c8242 },
316 { XFER_UDMA_2, 0x120c8242 },
317 { XFER_UDMA_1, 0x12148254 },
318 { XFER_UDMA_0, 0x121882ea },
319
320 { XFER_MW_DMA_2, 0x22808242 },
321 { XFER_MW_DMA_1, 0x22808254 },
322 { XFER_MW_DMA_0, 0x228082ea },
323
324 { XFER_PIO_4, 0x0a81f442 },
325 { XFER_PIO_3, 0x0a81f443 },
326 { XFER_PIO_2, 0x0a81f454 },
327 { XFER_PIO_1, 0x0ac1f465 },
328 { XFER_PIO_0, 0x0ac1f48a },
329 { 0, 0x0ac1f48a }
330 };
331
332 static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
333 { XFER_UDMA_6, 0x1c81dc62 },
334 { XFER_UDMA_5, 0x1c6ddc62 },
335 { XFER_UDMA_4, 0x1c8ddc62 },
336 { XFER_UDMA_3, 0x1c8edc62 }, /* checkme */
337 { XFER_UDMA_2, 0x1c91dc62 },
338 { XFER_UDMA_1, 0x1c9adc62 }, /* checkme */
339 { XFER_UDMA_0, 0x1c82dc62 }, /* checkme */
340
341 { XFER_MW_DMA_2, 0x2c829262 },
342 { XFER_MW_DMA_1, 0x2c829266 }, /* checkme */
343 { XFER_MW_DMA_0, 0x2c82922e }, /* checkme */
344
345 { XFER_PIO_4, 0x0c829c62 },
346 { XFER_PIO_3, 0x0c829c84 },
347 { XFER_PIO_2, 0x0c829ca6 },
348 { XFER_PIO_1, 0x0d029d26 },
349 { XFER_PIO_0, 0x0d029d5e },
350 { 0, 0x0d029d5e }
351 };
352
353 static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
354 { XFER_UDMA_5, 0x12848242 },
355 { XFER_UDMA_4, 0x12ac8242 },
356 { XFER_UDMA_3, 0x128c8242 },
357 { XFER_UDMA_2, 0x120c8242 },
358 { XFER_UDMA_1, 0x12148254 },
359 { XFER_UDMA_0, 0x121882ea },
360
361 { XFER_MW_DMA_2, 0x22808242 },
362 { XFER_MW_DMA_1, 0x22808254 },
363 { XFER_MW_DMA_0, 0x228082ea },
364
365 { XFER_PIO_4, 0x0a81f442 },
366 { XFER_PIO_3, 0x0a81f443 },
367 { XFER_PIO_2, 0x0a81f454 },
368 { XFER_PIO_1, 0x0ac1f465 },
369 { XFER_PIO_0, 0x0ac1f48a },
370 { 0, 0x0a81f443 }
371 };
372
373 static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
374 { XFER_UDMA_6, 0x1c869c62 },
375 { XFER_UDMA_5, 0x1cae9c62 },
376 { XFER_UDMA_4, 0x1c8a9c62 },
377 { XFER_UDMA_3, 0x1c8e9c62 },
378 { XFER_UDMA_2, 0x1c929c62 },
379 { XFER_UDMA_1, 0x1c9a9c62 },
380 { XFER_UDMA_0, 0x1c829c62 },
381
382 { XFER_MW_DMA_2, 0x2c829c62 },
383 { XFER_MW_DMA_1, 0x2c829c66 },
384 { XFER_MW_DMA_0, 0x2c829d2e },
385
386 { XFER_PIO_4, 0x0c829c62 },
387 { XFER_PIO_3, 0x0c829c84 },
388 { XFER_PIO_2, 0x0c829ca6 },
389 { XFER_PIO_1, 0x0d029d26 },
390 { XFER_PIO_0, 0x0d029d5e },
391 { 0, 0x0d029d26 }
392 };
393
394 static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
395 { XFER_UDMA_6, 0x12808242 },
396 { XFER_UDMA_5, 0x12848242 },
397 { XFER_UDMA_4, 0x12ac8242 },
398 { XFER_UDMA_3, 0x128c8242 },
399 { XFER_UDMA_2, 0x120c8242 },
400 { XFER_UDMA_1, 0x12148254 },
401 { XFER_UDMA_0, 0x121882ea },
402
403 { XFER_MW_DMA_2, 0x22808242 },
404 { XFER_MW_DMA_1, 0x22808254 },
405 { XFER_MW_DMA_0, 0x228082ea },
406
407 { XFER_PIO_4, 0x0a81f442 },
408 { XFER_PIO_3, 0x0a81f443 },
409 { XFER_PIO_2, 0x0a81f454 },
410 { XFER_PIO_1, 0x0ac1f465 },
411 { XFER_PIO_0, 0x0ac1f48a },
412 { 0, 0x06814e93 }
413 };
414
415 /* FIXME: 50MHz timings for HPT374 */
416
417 #if 0
418 static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
419 { XFER_UDMA_6, 0x12406231 }, /* checkme */
420 { XFER_UDMA_5, 0x12446231 }, /* 0x14846231 */
421 { XFER_UDMA_4, 0x16814ea7 }, /* 0x14886231 */
422 { XFER_UDMA_3, 0x16814ea7 }, /* 0x148c6231 */
423 { XFER_UDMA_2, 0x16814ea7 }, /* 0x148c6231 */
424 { XFER_UDMA_1, 0x16814ea7 }, /* 0x14906231 */
425 { XFER_UDMA_0, 0x16814ea7 }, /* 0x14986231 */
426 { XFER_MW_DMA_2, 0x16814ea7 }, /* 0x26514e21 */
427 { XFER_MW_DMA_1, 0x16814ea7 }, /* 0x26514e97 */
428 { XFER_MW_DMA_0, 0x16814ea7 }, /* 0x26514e97 */
429 { XFER_PIO_4, 0x06814ea7 }, /* 0x06514e21 */
430 { XFER_PIO_3, 0x06814ea7 }, /* 0x06514e22 */
431 { XFER_PIO_2, 0x06814ea7 }, /* 0x06514e33 */
432 { XFER_PIO_1, 0x06814ea7 }, /* 0x06914e43 */
433 { XFER_PIO_0, 0x06814ea7 }, /* 0x06914e57 */
434 { 0, 0x06814ea7 }
435 };
436 #endif
437
438 #define HPT366_DEBUG_DRIVE_INFO 0
439 #define HPT374_ALLOW_ATA133_6 0
440 #define HPT371_ALLOW_ATA133_6 0
441 #define HPT302_ALLOW_ATA133_6 0
442 #define HPT372_ALLOW_ATA133_6 1
443 #define HPT370_ALLOW_ATA100_5 1
444 #define HPT366_ALLOW_ATA66_4 1
445 #define HPT366_ALLOW_ATA66_3 1
446 #define HPT366_MAX_DEVS 8
447
448 #define F_LOW_PCI_33 0x23
449 #define F_LOW_PCI_40 0x29
450 #define F_LOW_PCI_50 0x2d
451 #define F_LOW_PCI_66 0x42
452
453 /*
454 * Hold all the highpoint quirks and revision information in one
455 * place.
456 */
457
458 struct hpt_info
459 {
460 u8 max_mode; /* Speeds allowed */
461 int revision; /* Chipset revision */
462 int flags; /* Chipset properties */
463 #define PLL_MODE 1
464 #define IS_372N 2
465 /* Speed table */
466 struct chipset_bus_clock_list_entry *speed;
467 };
468
469 /*
470 * This wants fixing so that we do everything not by classrev
471 * (which breaks on the newest chips) but by creating an
472 * enumeration of chip variants and using that
473 */
474
475 static __devinit u32 hpt_revision (struct pci_dev *dev)
476 {
477 u32 class_rev;
478 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
479 class_rev &= 0xff;
480
481 switch(dev->device) {
482 /* Remap new 372N onto 372 */
483 case PCI_DEVICE_ID_TTI_HPT372N:
484 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
485 case PCI_DEVICE_ID_TTI_HPT374:
486 class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
487 case PCI_DEVICE_ID_TTI_HPT371:
488 class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
489 case PCI_DEVICE_ID_TTI_HPT302:
490 class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
491 case PCI_DEVICE_ID_TTI_HPT372:
492 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
493 default:
494 break;
495 }
496 return class_rev;
497 }
498
499 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
500
501 static u8 hpt3xx_ratemask (ide_drive_t *drive)
502 {
503 ide_hwif_t *hwif = drive->hwif;
504 struct hpt_info *info = ide_get_hwifdata(hwif);
505 u8 mode = 0;
506
507 /* FIXME: TODO - move this to set info->mode once at boot */
508
509 if (info->revision >= 8) { /* HPT374 */
510 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
511 } else if (info->revision >= 7) { /* HPT371 */
512 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
513 } else if (info->revision >= 6) { /* HPT302 */
514 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
515 } else if (info->revision >= 5) { /* HPT372 */
516 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
517 } else if (info->revision >= 4) { /* HPT370A */
518 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
519 } else if (info->revision >= 3) { /* HPT370 */
520 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
521 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
522 } else { /* HPT366 and HPT368 */
523 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
524 }
525 if (!eighty_ninty_three(drive) && mode)
526 mode = min(mode, (u8)1);
527 return mode;
528 }
529
530 /*
531 * Note for the future; the SATA hpt37x we must set
532 * either PIO or UDMA modes 0,4,5
533 */
534
535 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
536 {
537 ide_hwif_t *hwif = drive->hwif;
538 struct hpt_info *info = ide_get_hwifdata(hwif);
539 u8 mode = hpt3xx_ratemask(drive);
540
541 if (drive->media != ide_disk)
542 return min(speed, (u8)XFER_PIO_4);
543
544 switch(mode) {
545 case 0x04:
546 speed = min(speed, (u8)XFER_UDMA_6);
547 break;
548 case 0x03:
549 speed = min(speed, (u8)XFER_UDMA_5);
550 if (info->revision >= 5)
551 break;
552 if (check_in_drive_lists(drive, bad_ata100_5))
553 speed = min(speed, (u8)XFER_UDMA_4);
554 break;
555 case 0x02:
556 speed = min(speed, (u8)XFER_UDMA_4);
557 /*
558 * CHECK ME, Does this need to be set to 5 ??
559 */
560 if (info->revision >= 3)
561 break;
562 if ((check_in_drive_lists(drive, bad_ata66_4)) ||
563 (!(HPT366_ALLOW_ATA66_4)))
564 speed = min(speed, (u8)XFER_UDMA_3);
565 if ((check_in_drive_lists(drive, bad_ata66_3)) ||
566 (!(HPT366_ALLOW_ATA66_3)))
567 speed = min(speed, (u8)XFER_UDMA_2);
568 break;
569 case 0x01:
570 speed = min(speed, (u8)XFER_UDMA_2);
571 /*
572 * CHECK ME, Does this need to be set to 5 ??
573 */
574 if (info->revision >= 3)
575 break;
576 if (check_in_drive_lists(drive, bad_ata33))
577 speed = min(speed, (u8)XFER_MW_DMA_2);
578 break;
579 case 0x00:
580 default:
581 speed = min(speed, (u8)XFER_MW_DMA_2);
582 break;
583 }
584 return speed;
585 }
586
587 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
588 {
589 struct hd_driveid *id = drive->id;
590
591 if (quirk_drives == list) {
592 while (*list)
593 if (strstr(id->model, *list++))
594 return 1;
595 } else {
596 while (*list)
597 if (!strcmp(*list++,id->model))
598 return 1;
599 }
600 return 0;
601 }
602
603 static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
604 {
605 for ( ; chipset_table->xfer_speed ; chipset_table++)
606 if (chipset_table->xfer_speed == speed)
607 return chipset_table->chipset_settings;
608 return chipset_table->chipset_settings;
609 }
610
611 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
612 {
613 ide_hwif_t *hwif = drive->hwif;
614 struct pci_dev *dev = hwif->pci_dev;
615 struct hpt_info *info = ide_get_hwifdata(hwif);
616 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
617 u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
618 u8 regfast = (hwif->channel) ? 0x55 : 0x51;
619 u8 drive_fast = 0;
620 u32 reg1 = 0, reg2 = 0;
621
622 /*
623 * Disable the "fast interrupt" prediction.
624 */
625 pci_read_config_byte(dev, regfast, &drive_fast);
626 if (drive_fast & 0x80)
627 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
628
629 reg2 = pci_bus_clock_list(speed, info->speed);
630
631 /*
632 * Disable on-chip PIO FIFO/buffer
633 * (to avoid problems handling I/O errors later)
634 */
635 pci_read_config_dword(dev, regtime, &reg1);
636 if (speed >= XFER_MW_DMA_0) {
637 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
638 } else {
639 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
640 }
641 reg2 &= ~0x80000000;
642
643 pci_write_config_dword(dev, regtime, reg2);
644
645 return ide_config_drive_speed(drive, speed);
646 }
647
648 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
649 {
650 ide_hwif_t *hwif = drive->hwif;
651 struct pci_dev *dev = hwif->pci_dev;
652 struct hpt_info *info = ide_get_hwifdata(hwif);
653 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
654 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
655 u8 drive_pci = 0x40 + (drive->dn * 4);
656 u8 new_fast = 0, drive_fast = 0;
657 u32 list_conf = 0, drive_conf = 0;
658 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
659
660 /*
661 * Disable the "fast interrupt" prediction.
662 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
663 */
664 pci_read_config_byte(dev, regfast, &drive_fast);
665 new_fast = drive_fast;
666 if (new_fast & 0x02)
667 new_fast &= ~0x02;
668
669 #ifdef HPT_DELAY_INTERRUPT
670 if (new_fast & 0x01)
671 new_fast &= ~0x01;
672 #else
673 if ((new_fast & 0x01) == 0)
674 new_fast |= 0x01;
675 #endif
676 if (new_fast != drive_fast)
677 pci_write_config_byte(dev, regfast, new_fast);
678
679 list_conf = pci_bus_clock_list(speed, info->speed);
680
681 pci_read_config_dword(dev, drive_pci, &drive_conf);
682 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
683
684 if (speed < XFER_MW_DMA_0)
685 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
686 pci_write_config_dword(dev, drive_pci, list_conf);
687
688 return ide_config_drive_speed(drive, speed);
689 }
690
691 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
692 {
693 ide_hwif_t *hwif = drive->hwif;
694 struct pci_dev *dev = hwif->pci_dev;
695 struct hpt_info *info = ide_get_hwifdata(hwif);
696 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
697 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
698 u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4);
699 u32 list_conf = 0, drive_conf = 0;
700 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
701
702 /*
703 * Disable the "fast interrupt" prediction.
704 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
705 */
706 pci_read_config_byte(dev, regfast, &drive_fast);
707 drive_fast &= ~0x07;
708 pci_write_config_byte(dev, regfast, drive_fast);
709
710 list_conf = pci_bus_clock_list(speed, info->speed);
711 pci_read_config_dword(dev, drive_pci, &drive_conf);
712 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
713 if (speed < XFER_MW_DMA_0)
714 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
715 pci_write_config_dword(dev, drive_pci, list_conf);
716
717 return ide_config_drive_speed(drive, speed);
718 }
719
720 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
721 {
722 ide_hwif_t *hwif = drive->hwif;
723 struct hpt_info *info = ide_get_hwifdata(hwif);
724
725 if (info->revision >= 8)
726 return hpt372_tune_chipset(drive, speed); /* not a typo */
727 else if (info->revision >= 5)
728 return hpt372_tune_chipset(drive, speed);
729 else if (info->revision >= 3)
730 return hpt370_tune_chipset(drive, speed);
731 else /* hpt368: hpt_minimum_revision(dev, 2) */
732 return hpt36x_tune_chipset(drive, speed);
733 }
734
735 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
736 {
737 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
738 (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
739 }
740
741 /*
742 * This allows the configuration of ide_pci chipset registers
743 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
744 * after the drive is reported by the OS. Initially for designed for
745 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
746 *
747 * check_in_drive_lists(drive, bad_ata66_4)
748 * check_in_drive_lists(drive, bad_ata66_3)
749 * check_in_drive_lists(drive, bad_ata33)
750 *
751 */
752 static int config_chipset_for_dma (ide_drive_t *drive)
753 {
754 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
755 ide_hwif_t *hwif = drive->hwif;
756 struct hpt_info *info = ide_get_hwifdata(hwif);
757
758 if (!speed)
759 return 0;
760
761 /* If we don't have any timings we can't do a lot */
762 if (info->speed == NULL)
763 return 0;
764
765 (void) hpt3xx_tune_chipset(drive, speed);
766 return ide_dma_enable(drive);
767 }
768
769 static int hpt3xx_quirkproc (ide_drive_t *drive)
770 {
771 return ((int) check_in_drive_lists(drive, quirk_drives));
772 }
773
774 static void hpt3xx_intrproc (ide_drive_t *drive)
775 {
776 ide_hwif_t *hwif = drive->hwif;
777
778 if (drive->quirk_list)
779 return;
780 /* drives in the quirk_list may not like intr setups/cleanups */
781 hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
782 }
783
784 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
785 {
786 ide_hwif_t *hwif = drive->hwif;
787 struct hpt_info *info = ide_get_hwifdata(hwif);
788 struct pci_dev *dev = hwif->pci_dev;
789
790 if (drive->quirk_list) {
791 if (info->revision >= 3) {
792 u8 reg5a = 0;
793 pci_read_config_byte(dev, 0x5a, &reg5a);
794 if (((reg5a & 0x10) >> 4) != mask)
795 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
796 } else {
797 if (mask) {
798 disable_irq(hwif->irq);
799 } else {
800 enable_irq(hwif->irq);
801 }
802 }
803 } else {
804 if (IDE_CONTROL_REG)
805 hwif->OUTB(mask ? (drive->ctl | 2) :
806 (drive->ctl & ~2),
807 IDE_CONTROL_REG);
808 }
809 }
810
811 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
812 {
813 ide_hwif_t *hwif = drive->hwif;
814 struct hd_driveid *id = drive->id;
815
816 drive->init_speed = 0;
817
818 if ((id->capability & 1) && drive->autodma) {
819
820 if (ide_use_dma(drive)) {
821 if (config_chipset_for_dma(drive))
822 return hwif->ide_dma_on(drive);
823 }
824
825 goto fast_ata_pio;
826
827 } else if ((id->capability & 8) || (id->field_valid & 2)) {
828 fast_ata_pio:
829 hpt3xx_tune_drive(drive, 5);
830 return hwif->ide_dma_off_quietly(drive);
831 }
832 /* IORDY not supported */
833 return 0;
834 }
835
836 /*
837 * This is specific to the HPT366 UDMA bios chipset
838 * by HighPoint|Triones Technologies, Inc.
839 */
840 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
841 {
842 struct pci_dev *dev = HWIF(drive)->pci_dev;
843 u8 reg50h = 0, reg52h = 0, reg5ah = 0;
844
845 pci_read_config_byte(dev, 0x50, &reg50h);
846 pci_read_config_byte(dev, 0x52, &reg52h);
847 pci_read_config_byte(dev, 0x5a, &reg5ah);
848 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
849 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
850 if (reg5ah & 0x10)
851 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
852 return __ide_dma_lostirq(drive);
853 }
854
855 static void hpt370_clear_engine (ide_drive_t *drive)
856 {
857 u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
858 pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
859 udelay(10);
860 }
861
862 static void hpt370_ide_dma_start(ide_drive_t *drive)
863 {
864 #ifdef HPT_RESET_STATE_ENGINE
865 hpt370_clear_engine(drive);
866 #endif
867 ide_dma_start(drive);
868 }
869
870 static int hpt370_ide_dma_end (ide_drive_t *drive)
871 {
872 ide_hwif_t *hwif = HWIF(drive);
873 u8 dma_stat = hwif->INB(hwif->dma_status);
874
875 if (dma_stat & 0x01) {
876 /* wait a little */
877 udelay(20);
878 dma_stat = hwif->INB(hwif->dma_status);
879 }
880 if ((dma_stat & 0x01) != 0)
881 /* fallthrough */
882 (void) HWIF(drive)->ide_dma_timeout(drive);
883
884 return __ide_dma_end(drive);
885 }
886
887 static void hpt370_lostirq_timeout (ide_drive_t *drive)
888 {
889 ide_hwif_t *hwif = HWIF(drive);
890 u8 bfifo = 0, reginfo = hwif->channel ? 0x56 : 0x52;
891 u8 dma_stat = 0, dma_cmd = 0;
892
893 pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
894 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
895 hpt370_clear_engine(drive);
896 /* get dma command mode */
897 dma_cmd = hwif->INB(hwif->dma_command);
898 /* stop dma */
899 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
900 dma_stat = hwif->INB(hwif->dma_status);
901 /* clear errors */
902 hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
903 }
904
905 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
906 {
907 hpt370_lostirq_timeout(drive);
908 hpt370_clear_engine(drive);
909 return __ide_dma_timeout(drive);
910 }
911
912 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
913 {
914 hpt370_lostirq_timeout(drive);
915 hpt370_clear_engine(drive);
916 return __ide_dma_lostirq(drive);
917 }
918
919 /* returns 1 if DMA IRQ issued, 0 otherwise */
920 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
921 {
922 ide_hwif_t *hwif = HWIF(drive);
923 u16 bfifo = 0;
924 u8 reginfo = hwif->channel ? 0x56 : 0x52;
925 u8 dma_stat;
926
927 pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
928 if (bfifo & 0x1FF) {
929 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
930 return 0;
931 }
932
933 dma_stat = hwif->INB(hwif->dma_status);
934 /* return 1 if INTR asserted */
935 if ((dma_stat & 4) == 4)
936 return 1;
937
938 if (!drive->waiting_for_dma)
939 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
940 drive->name, __FUNCTION__);
941 return 0;
942 }
943
944 static int hpt374_ide_dma_end (ide_drive_t *drive)
945 {
946 struct pci_dev *dev = HWIF(drive)->pci_dev;
947 ide_hwif_t *hwif = HWIF(drive);
948 u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
949 u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
950
951 pci_read_config_byte(dev, 0x6a, &bwsr_stat);
952 pci_read_config_byte(dev, mscreg, &msc_stat);
953 if ((bwsr_stat & bwsr_mask) == bwsr_mask)
954 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
955 return __ide_dma_end(drive);
956 }
957
958 /**
959 * hpt372n_set_clock - perform clock switching dance
960 * @drive: Drive to switch
961 * @mode: Switching mode (0x21 for write, 0x23 otherwise)
962 *
963 * Switch the DPLL clock on the HPT372N devices. This is a
964 * right mess.
965 */
966
967 static void hpt372n_set_clock(ide_drive_t *drive, int mode)
968 {
969 ide_hwif_t *hwif = HWIF(drive);
970
971 /* FIXME: should we check for DMA active and BUG() */
972 /* Tristate the bus */
973 outb(0x80, hwif->dma_base+0x73);
974 outb(0x80, hwif->dma_base+0x77);
975
976 /* Switch clock and reset channels */
977 outb(mode, hwif->dma_base+0x7B);
978 outb(0xC0, hwif->dma_base+0x79);
979
980 /* Reset state machines */
981 outb(0x37, hwif->dma_base+0x70);
982 outb(0x37, hwif->dma_base+0x74);
983
984 /* Complete reset */
985 outb(0x00, hwif->dma_base+0x79);
986
987 /* Reconnect channels to bus */
988 outb(0x00, hwif->dma_base+0x73);
989 outb(0x00, hwif->dma_base+0x77);
990 }
991
992 /**
993 * hpt372n_rw_disk - prepare for I/O
994 * @drive: drive for command
995 * @rq: block request structure
996 *
997 * This is called when a disk I/O is issued to the 372N.
998 * We need it because of the clock switching.
999 */
1000
1001 static void hpt372n_rw_disk(ide_drive_t *drive, struct request *rq)
1002 {
1003 ide_hwif_t *hwif = drive->hwif;
1004 int wantclock;
1005
1006 wantclock = rq_data_dir(rq) ? 0x23 : 0x21;
1007
1008 if (hwif->config_data != wantclock) {
1009 hpt372n_set_clock(drive, wantclock);
1010 hwif->config_data = wantclock;
1011 }
1012 }
1013
1014 /*
1015 * Since SUN Cobalt is attempting to do this operation, I should disclose
1016 * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
1017 * HOTSWAP ATA Infrastructure.
1018 */
1019
1020 static void hpt3xx_reset (ide_drive_t *drive)
1021 {
1022 }
1023
1024 static int hpt3xx_tristate (ide_drive_t * drive, int state)
1025 {
1026 ide_hwif_t *hwif = HWIF(drive);
1027 struct pci_dev *dev = hwif->pci_dev;
1028 u8 reg59h = 0, reset = (hwif->channel) ? 0x80 : 0x40;
1029 u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
1030
1031 pci_read_config_byte(dev, 0x59, &reg59h);
1032 pci_read_config_byte(dev, state_reg, &regXXh);
1033
1034 if (state) {
1035 (void) ide_do_reset(drive);
1036 pci_write_config_byte(dev, state_reg, regXXh|0x80);
1037 pci_write_config_byte(dev, 0x59, reg59h|reset);
1038 } else {
1039 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
1040 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
1041 (void) ide_do_reset(drive);
1042 }
1043 return 0;
1044 }
1045
1046 /*
1047 * set/get power state for a drive.
1048 * turning the power off does the following things:
1049 * 1) soft-reset the drive
1050 * 2) tri-states the ide bus
1051 *
1052 * when we turn things back on, we need to re-initialize things.
1053 */
1054 #define TRISTATE_BIT 0x8000
1055 static int hpt370_busproc(ide_drive_t * drive, int state)
1056 {
1057 ide_hwif_t *hwif = drive->hwif;
1058 struct pci_dev *dev = hwif->pci_dev;
1059 u8 tristate = 0, resetmask = 0, bus_reg = 0;
1060 u16 tri_reg;
1061
1062 hwif->bus_state = state;
1063
1064 if (hwif->channel) {
1065 /* secondary channel */
1066 tristate = 0x56;
1067 resetmask = 0x80;
1068 } else {
1069 /* primary channel */
1070 tristate = 0x52;
1071 resetmask = 0x40;
1072 }
1073
1074 /* grab status */
1075 pci_read_config_word(dev, tristate, &tri_reg);
1076 pci_read_config_byte(dev, 0x59, &bus_reg);
1077
1078 /* set the state. we don't set it if we don't need to do so.
1079 * make sure that the drive knows that it has failed if it's off */
1080 switch (state) {
1081 case BUSSTATE_ON:
1082 hwif->drives[0].failures = 0;
1083 hwif->drives[1].failures = 0;
1084 if ((bus_reg & resetmask) == 0)
1085 return 0;
1086 tri_reg &= ~TRISTATE_BIT;
1087 bus_reg &= ~resetmask;
1088 break;
1089 case BUSSTATE_OFF:
1090 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1091 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1092 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
1093 return 0;
1094 tri_reg &= ~TRISTATE_BIT;
1095 bus_reg |= resetmask;
1096 break;
1097 case BUSSTATE_TRISTATE:
1098 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1099 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1100 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
1101 return 0;
1102 tri_reg |= TRISTATE_BIT;
1103 bus_reg |= resetmask;
1104 break;
1105 }
1106 pci_write_config_byte(dev, 0x59, bus_reg);
1107 pci_write_config_word(dev, tristate, tri_reg);
1108
1109 return 0;
1110 }
1111
1112 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
1113 {
1114 u32 reg1 = 0;
1115 struct hpt_info *info = ide_get_hwifdata(hwif);
1116
1117 pci_read_config_dword(hwif->pci_dev, 0x40, &reg1);
1118
1119 /* detect bus speed by looking at control reg timing: */
1120 switch((reg1 >> 8) & 7) {
1121 case 5:
1122 info->speed = forty_base_hpt366;
1123 break;
1124 case 9:
1125 info->speed = twenty_five_base_hpt366;
1126 break;
1127 case 7:
1128 default:
1129 info->speed = thirty_three_base_hpt366;
1130 break;
1131 }
1132 }
1133
1134 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1135 {
1136 struct hpt_info *info = ide_get_hwifdata(hwif);
1137 struct pci_dev *dev = hwif->pci_dev;
1138 int adjust, i;
1139 u16 freq;
1140 u32 pll;
1141 u8 reg5bh;
1142
1143 /*
1144 * default to pci clock. make sure MA15/16 are set to output
1145 * to prevent drives having problems with 40-pin cables. Needed
1146 * for some drives such as IBM-DTLA which will not enter ready
1147 * state on reset when PDIAG is a input.
1148 *
1149 * ToDo: should we set 0x21 when using PLL mode ?
1150 */
1151 pci_write_config_byte(dev, 0x5b, 0x23);
1152
1153 /*
1154 * set up the PLL. we need to adjust it so that it's stable.
1155 * freq = Tpll * 192 / Tpci
1156 *
1157 * Todo. For non x86 should probably check the dword is
1158 * set to 0xABCDExxx indicating the BIOS saved f_CNT
1159 */
1160 pci_read_config_word(dev, 0x78, &freq);
1161 freq &= 0x1FF;
1162
1163 /*
1164 * The 372N uses different PCI clock information and has
1165 * some other complications
1166 * On PCI33 timing we must clock switch
1167 * On PCI66 timing we must NOT use the PCI clock
1168 *
1169 * Currently we always set up the PLL for the 372N
1170 */
1171
1172 if(info->flags & IS_372N)
1173 {
1174 printk(KERN_INFO "hpt: HPT372N detected, using 372N timing.\n");
1175 if(freq < 0x55)
1176 pll = F_LOW_PCI_33;
1177 else if(freq < 0x70)
1178 pll = F_LOW_PCI_40;
1179 else if(freq < 0x7F)
1180 pll = F_LOW_PCI_50;
1181 else
1182 pll = F_LOW_PCI_66;
1183
1184 printk(KERN_INFO "FREQ: %d PLL: %d\n", freq, pll);
1185
1186 /* We always use the pll not the PCI clock on 372N */
1187 }
1188 else
1189 {
1190 if(freq < 0x9C)
1191 pll = F_LOW_PCI_33;
1192 else if(freq < 0xb0)
1193 pll = F_LOW_PCI_40;
1194 else if(freq <0xc8)
1195 pll = F_LOW_PCI_50;
1196 else
1197 pll = F_LOW_PCI_66;
1198
1199 if (pll == F_LOW_PCI_33) {
1200 if (info->revision >= 8)
1201 info->speed = thirty_three_base_hpt374;
1202 else if (info->revision >= 5)
1203 info->speed = thirty_three_base_hpt372;
1204 else if (info->revision >= 4)
1205 info->speed = thirty_three_base_hpt370a;
1206 else
1207 info->speed = thirty_three_base_hpt370;
1208 printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n");
1209 } else if (pll == F_LOW_PCI_40) {
1210 /* Unsupported */
1211 } else if (pll == F_LOW_PCI_50) {
1212 if (info->revision >= 8)
1213 info->speed = fifty_base_hpt370a;
1214 else if (info->revision >= 5)
1215 info->speed = fifty_base_hpt372;
1216 else if (info->revision >= 4)
1217 info->speed = fifty_base_hpt370a;
1218 else
1219 info->speed = fifty_base_hpt370a;
1220 printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
1221 } else {
1222 if (info->revision >= 8) {
1223 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
1224 }
1225 else if (info->revision >= 5)
1226 info->speed = sixty_six_base_hpt372;
1227 else if (info->revision >= 4)
1228 info->speed = sixty_six_base_hpt370a;
1229 else
1230 info->speed = sixty_six_base_hpt370;
1231 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1232 }
1233 }
1234
1235 /*
1236 * only try the pll if we don't have a table for the clock
1237 * speed that we're running at. NOTE: the internal PLL will
1238 * result in slow reads when using a 33MHz PCI clock. we also
1239 * don't like to use the PLL because it will cause glitches
1240 * on PRST/SRST when the HPT state engine gets reset.
1241 *
1242 * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1243 * 372 device so we can get ATA133 support
1244 */
1245 if (info->speed)
1246 goto init_hpt37X_done;
1247
1248 info->flags |= PLL_MODE;
1249
1250 /*
1251 * FIXME: make this work correctly, esp with 372N as per
1252 * reference driver code.
1253 *
1254 * adjust PLL based upon PCI clock, enable it, and wait for
1255 * stabilization.
1256 */
1257 adjust = 0;
1258 freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1259 while (adjust++ < 6) {
1260 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1261 pll | 0x100);
1262
1263 /* wait for clock stabilization */
1264 for (i = 0; i < 0x50000; i++) {
1265 pci_read_config_byte(dev, 0x5b, &reg5bh);
1266 if (reg5bh & 0x80) {
1267 /* spin looking for the clock to destabilize */
1268 for (i = 0; i < 0x1000; ++i) {
1269 pci_read_config_byte(dev, 0x5b,
1270 &reg5bh);
1271 if ((reg5bh & 0x80) == 0)
1272 goto pll_recal;
1273 }
1274 pci_read_config_dword(dev, 0x5c, &pll);
1275 pci_write_config_dword(dev, 0x5c,
1276 pll & ~0x100);
1277 pci_write_config_byte(dev, 0x5b, 0x21);
1278 if (info->revision >= 8)
1279 info->speed = fifty_base_hpt370a;
1280 else if (info->revision >= 5)
1281 info->speed = fifty_base_hpt372;
1282 else if (info->revision >= 4)
1283 info->speed = fifty_base_hpt370a;
1284 else
1285 info->speed = fifty_base_hpt370a;
1286 printk("HPT37X: using 50MHz internal PLL\n");
1287 goto init_hpt37X_done;
1288 }
1289 }
1290 if (!pci_get_drvdata(dev)) {
1291 printk("No Clock Stabilization!!!\n");
1292 return;
1293 }
1294 pll_recal:
1295 if (adjust & 1)
1296 pll -= (adjust >> 1);
1297 else
1298 pll += (adjust >> 1);
1299 }
1300
1301 init_hpt37X_done:
1302 if (!info->speed)
1303 printk(KERN_ERR "HPT37X%s: unknown bus timing [%d %d].\n",
1304 (info->flags & IS_372N)?"N":"", pll, freq);
1305 /* reset state engine */
1306 pci_write_config_byte(dev, 0x50, 0x37);
1307 pci_write_config_byte(dev, 0x54, 0x37);
1308 udelay(100);
1309 }
1310
1311 static int __devinit init_hpt37x(struct pci_dev *dev)
1312 {
1313 u8 reg5ah;
1314
1315 pci_read_config_byte(dev, 0x5a, &reg5ah);
1316 /* interrupt force enable */
1317 pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1318 return 0;
1319 }
1320
1321 static int __devinit init_hpt366(struct pci_dev *dev)
1322 {
1323 u32 reg1 = 0;
1324 u8 drive_fast = 0;
1325
1326 /*
1327 * Disable the "fast interrupt" prediction.
1328 */
1329 pci_read_config_byte(dev, 0x51, &drive_fast);
1330 if (drive_fast & 0x80)
1331 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1332 pci_read_config_dword(dev, 0x40, &reg1);
1333
1334 return 0;
1335 }
1336
1337 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1338 {
1339 int ret = 0;
1340
1341 /*
1342 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1343 * We don't seem to be using it.
1344 */
1345 if (dev->resource[PCI_ROM_RESOURCE].start)
1346 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1347 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1348
1349 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1350 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1351 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1352 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1353
1354 if (hpt_revision(dev) >= 3)
1355 ret = init_hpt37x(dev);
1356 else
1357 ret = init_hpt366(dev);
1358
1359 if (ret)
1360 return ret;
1361
1362 return dev->irq;
1363 }
1364
1365 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1366 {
1367 struct pci_dev *dev = hwif->pci_dev;
1368 struct hpt_info *info = ide_get_hwifdata(hwif);
1369 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02;
1370
1371 hwif->tuneproc = &hpt3xx_tune_drive;
1372 hwif->speedproc = &hpt3xx_tune_chipset;
1373 hwif->quirkproc = &hpt3xx_quirkproc;
1374 hwif->intrproc = &hpt3xx_intrproc;
1375 hwif->maskproc = &hpt3xx_maskproc;
1376
1377 if(info->flags & IS_372N)
1378 hwif->rw_disk = &hpt372n_rw_disk;
1379
1380 /*
1381 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1382 * address lines to access an external eeprom. To read valid
1383 * cable detect state the pins must be enabled as inputs.
1384 */
1385 if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1386 /*
1387 * HPT374 PCI function 1
1388 * - set bit 15 of reg 0x52 to enable TCBLID as input
1389 * - set bit 15 of reg 0x56 to enable FCBLID as input
1390 */
1391 u16 mcr3, mcr6;
1392 pci_read_config_word(dev, 0x52, &mcr3);
1393 pci_read_config_word(dev, 0x56, &mcr6);
1394 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1395 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1396 /* now read cable id register */
1397 pci_read_config_byte(dev, 0x5a, &ata66);
1398 pci_write_config_word(dev, 0x52, mcr3);
1399 pci_write_config_word(dev, 0x56, mcr6);
1400 } else if (info->revision >= 3) {
1401 /*
1402 * HPT370/372 and 374 pcifn 0
1403 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1404 */
1405 u8 scr2;
1406 pci_read_config_byte(dev, 0x5b, &scr2);
1407 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1408 /* now read cable id register */
1409 pci_read_config_byte(dev, 0x5a, &ata66);
1410 pci_write_config_byte(dev, 0x5b, scr2);
1411 } else {
1412 pci_read_config_byte(dev, 0x5a, &ata66);
1413 }
1414
1415 #ifdef DEBUG
1416 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1417 ata66, (ata66 & regmask) ? "33" : "66",
1418 PCI_FUNC(hwif->pci_dev->devfn));
1419 #endif /* DEBUG */
1420
1421 #ifdef HPT_SERIALIZE_IO
1422 /* serialize access to this device */
1423 if (hwif->mate)
1424 hwif->serialized = hwif->mate->serialized = 1;
1425 #endif
1426
1427 if (info->revision >= 3) {
1428 u8 reg5ah = 0;
1429 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1430 /*
1431 * set up ioctl for power status.
1432 * note: power affects both
1433 * drives on each channel
1434 */
1435 hwif->resetproc = &hpt3xx_reset;
1436 hwif->busproc = &hpt370_busproc;
1437 } else if (info->revision >= 2) {
1438 hwif->resetproc = &hpt3xx_reset;
1439 hwif->busproc = &hpt3xx_tristate;
1440 } else {
1441 hwif->resetproc = &hpt3xx_reset;
1442 hwif->busproc = &hpt3xx_tristate;
1443 }
1444
1445 if (!hwif->dma_base) {
1446 hwif->drives[0].autotune = 1;
1447 hwif->drives[1].autotune = 1;
1448 return;
1449 }
1450
1451 hwif->ultra_mask = 0x7f;
1452 hwif->mwdma_mask = 0x07;
1453
1454 if (!(hwif->udma_four))
1455 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1456 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1457
1458 if (info->revision >= 8) {
1459 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1460 hwif->ide_dma_end = &hpt374_ide_dma_end;
1461 } else if (info->revision >= 5) {
1462 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1463 hwif->ide_dma_end = &hpt374_ide_dma_end;
1464 } else if (info->revision >= 3) {
1465 hwif->dma_start = &hpt370_ide_dma_start;
1466 hwif->ide_dma_end = &hpt370_ide_dma_end;
1467 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1468 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1469 } else if (info->revision >= 2)
1470 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1471 else
1472 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1473
1474 if (!noautodma)
1475 hwif->autodma = 1;
1476 hwif->drives[0].autodma = hwif->autodma;
1477 hwif->drives[1].autodma = hwif->autodma;
1478 }
1479
1480 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1481 {
1482 struct hpt_info *info = ide_get_hwifdata(hwif);
1483 u8 masterdma = 0, slavedma = 0;
1484 u8 dma_new = 0, dma_old = 0;
1485 u8 primary = hwif->channel ? 0x4b : 0x43;
1486 u8 secondary = hwif->channel ? 0x4f : 0x47;
1487 unsigned long flags;
1488
1489 if (!dmabase)
1490 return;
1491
1492 if(info->speed == NULL) {
1493 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
1494 return;
1495 }
1496
1497 dma_old = hwif->INB(dmabase+2);
1498
1499 local_irq_save(flags);
1500
1501 dma_new = dma_old;
1502 pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1503 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1504
1505 if (masterdma & 0x30) dma_new |= 0x20;
1506 if (slavedma & 0x30) dma_new |= 0x40;
1507 if (dma_new != dma_old)
1508 hwif->OUTB(dma_new, dmabase+2);
1509
1510 local_irq_restore(flags);
1511
1512 ide_setup_dma(hwif, dmabase, 8);
1513 }
1514
1515 /*
1516 * We "borrow" this hook in order to set the data structures
1517 * up early enough before dma or init_hwif calls are made.
1518 */
1519
1520 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1521 {
1522 struct hpt_info *info = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1523 unsigned long dmabase = pci_resource_start(hwif->pci_dev, 4);
1524 u8 did, rid;
1525
1526 if(info == NULL) {
1527 printk(KERN_WARNING "hpt366: out of memory.\n");
1528 return;
1529 }
1530 ide_set_hwifdata(hwif, info);
1531
1532 if(dmabase) {
1533 did = inb(dmabase + 0x22);
1534 rid = inb(dmabase + 0x28);
1535
1536 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1537 info->flags |= IS_372N;
1538 }
1539
1540 info->revision = hpt_revision(hwif->pci_dev);
1541
1542 if (info->revision >= 3)
1543 hpt37x_clocking(hwif);
1544 else
1545 hpt366_clocking(hwif);
1546 }
1547
1548 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1549 {
1550 struct pci_dev *findev = NULL;
1551
1552 if (PCI_FUNC(dev->devfn) & 1)
1553 return -ENODEV;
1554
1555 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1556 if ((findev->vendor == dev->vendor) &&
1557 (findev->device == dev->device) &&
1558 ((findev->devfn - dev->devfn) == 1) &&
1559 (PCI_FUNC(findev->devfn) & 1)) {
1560 if (findev->irq != dev->irq) {
1561 /* FIXME: we need a core pci_set_interrupt() */
1562 findev->irq = dev->irq;
1563 printk(KERN_WARNING "%s: pci-config space interrupt "
1564 "fixed.\n", d->name);
1565 }
1566 return ide_setup_pci_devices(dev, findev, d);
1567 }
1568 }
1569 return ide_setup_pci_device(dev, d);
1570 }
1571
1572 static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1573 {
1574 return ide_setup_pci_device(dev, d);
1575 }
1576
1577 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1578 {
1579 struct pci_dev *findev = NULL;
1580 u8 pin1 = 0, pin2 = 0;
1581 unsigned int class_rev;
1582 char *chipset_names[] = {"HPT366", "HPT366", "HPT368",
1583 "HPT370", "HPT370A", "HPT372",
1584 "HPT372N" };
1585
1586 if (PCI_FUNC(dev->devfn) & 1)
1587 return -ENODEV;
1588
1589 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1590 class_rev &= 0xff;
1591
1592 if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1593 class_rev = 6;
1594
1595 if(class_rev <= 6)
1596 d->name = chipset_names[class_rev];
1597
1598 switch(class_rev) {
1599 case 6:
1600 case 5:
1601 case 4:
1602 case 3:
1603 goto init_single;
1604 default:
1605 break;
1606 }
1607
1608 d->channels = 1;
1609
1610 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1611 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1612 if ((findev->vendor == dev->vendor) &&
1613 (findev->device == dev->device) &&
1614 ((findev->devfn - dev->devfn) == 1) &&
1615 (PCI_FUNC(findev->devfn) & 1)) {
1616 pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1617 if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1618 d->bootable = ON_BOARD;
1619 printk("%s: onboard version of chipset, "
1620 "pin1=%d pin2=%d\n", d->name,
1621 pin1, pin2);
1622 }
1623 return ide_setup_pci_devices(dev, findev, d);
1624 }
1625 }
1626 init_single:
1627 return ide_setup_pci_device(dev, d);
1628 }
1629
1630 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1631 { /* 0 */
1632 .name = "HPT366",
1633 .init_setup = init_setup_hpt366,
1634 .init_chipset = init_chipset_hpt366,
1635 .init_iops = init_iops_hpt366,
1636 .init_hwif = init_hwif_hpt366,
1637 .init_dma = init_dma_hpt366,
1638 .channels = 2,
1639 .autodma = AUTODMA,
1640 .bootable = OFF_BOARD,
1641 .extra = 240
1642 },{ /* 1 */
1643 .name = "HPT372A",
1644 .init_setup = init_setup_hpt37x,
1645 .init_chipset = init_chipset_hpt366,
1646 .init_iops = init_iops_hpt366,
1647 .init_hwif = init_hwif_hpt366,
1648 .init_dma = init_dma_hpt366,
1649 .channels = 2,
1650 .autodma = AUTODMA,
1651 .bootable = OFF_BOARD,
1652 },{ /* 2 */
1653 .name = "HPT302",
1654 .init_setup = init_setup_hpt37x,
1655 .init_chipset = init_chipset_hpt366,
1656 .init_iops = init_iops_hpt366,
1657 .init_hwif = init_hwif_hpt366,
1658 .init_dma = init_dma_hpt366,
1659 .channels = 2,
1660 .autodma = AUTODMA,
1661 .bootable = OFF_BOARD,
1662 },{ /* 3 */
1663 .name = "HPT371",
1664 .init_setup = init_setup_hpt37x,
1665 .init_chipset = init_chipset_hpt366,
1666 .init_iops = init_iops_hpt366,
1667 .init_hwif = init_hwif_hpt366,
1668 .init_dma = init_dma_hpt366,
1669 .channels = 2,
1670 .autodma = AUTODMA,
1671 .bootable = OFF_BOARD,
1672 },{ /* 4 */
1673 .name = "HPT374",
1674 .init_setup = init_setup_hpt374,
1675 .init_chipset = init_chipset_hpt366,
1676 .init_iops = init_iops_hpt366,
1677 .init_hwif = init_hwif_hpt366,
1678 .init_dma = init_dma_hpt366,
1679 .channels = 2, /* 4 */
1680 .autodma = AUTODMA,
1681 .bootable = OFF_BOARD,
1682 },{ /* 5 */
1683 .name = "HPT372N",
1684 .init_setup = init_setup_hpt37x,
1685 .init_chipset = init_chipset_hpt366,
1686 .init_iops = init_iops_hpt366,
1687 .init_hwif = init_hwif_hpt366,
1688 .init_dma = init_dma_hpt366,
1689 .channels = 2, /* 4 */
1690 .autodma = AUTODMA,
1691 .bootable = OFF_BOARD,
1692 }
1693 };
1694
1695 /**
1696 * hpt366_init_one - called when an HPT366 is found
1697 * @dev: the hpt366 device
1698 * @id: the matching pci id
1699 *
1700 * Called when the PCI registration layer (or the IDE initialization)
1701 * finds a device matching our IDE device tables.
1702 */
1703
1704 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1705 {
1706 ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1707
1708 return d->init_setup(dev, d);
1709 }
1710
1711 static struct pci_device_id hpt366_pci_tbl[] = {
1712 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1713 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1714 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1715 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1716 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1717 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1718 { 0, },
1719 };
1720 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1721
1722 static struct pci_driver driver = {
1723 .name = "HPT366_IDE",
1724 .id_table = hpt366_pci_tbl,
1725 .probe = hpt366_init_one,
1726 };
1727
1728 static int hpt366_ide_init(void)
1729 {
1730 return ide_pci_register_driver(&driver);
1731 }
1732
1733 module_init(hpt366_ide_init);
1734
1735 MODULE_AUTHOR("Andre Hedrick");
1736 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1737 MODULE_LICENSE("GPL");
kernel-based virtual machine