2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/pci.h>
35 #include <linux/eeprom_93cx6.h>
38 #include "rt2x00pci.h"
42 * Allow hardware encryption to be disabled.
44 static int modparam_nohwcrypt
= 0;
45 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
46 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attempt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
59 #define WAIT_FOR_BBP(__dev, __reg) \
60 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61 #define WAIT_FOR_RF(__dev, __reg) \
62 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63 #define WAIT_FOR_MCU(__dev, __reg) \
64 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65 H2M_MAILBOX_CSR_OWNER, (__reg))
67 static void rt61pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
68 const unsigned int word
, const u8 value
)
72 mutex_lock(&rt2x00dev
->csr_mutex
);
75 * Wait until the BBP becomes available, afterwards we
76 * can safely write the new data into the register.
78 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
80 rt2x00_set_field32(®
, PHY_CSR3_VALUE
, value
);
81 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
82 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
83 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 0);
85 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
88 mutex_unlock(&rt2x00dev
->csr_mutex
);
91 static void rt61pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
92 const unsigned int word
, u8
*value
)
96 mutex_lock(&rt2x00dev
->csr_mutex
);
99 * Wait until the BBP becomes available, afterwards we
100 * can safely write the read request into the register.
101 * After the data has been written, we wait until hardware
102 * returns the correct value, if at any time the register
103 * doesn't become available in time, reg will be 0xffffffff
104 * which means we return 0xff to the caller.
106 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
108 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
109 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
110 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 1);
112 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
114 WAIT_FOR_BBP(rt2x00dev
, ®
);
117 *value
= rt2x00_get_field32(reg
, PHY_CSR3_VALUE
);
119 mutex_unlock(&rt2x00dev
->csr_mutex
);
122 static void rt61pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
123 const unsigned int word
, const u32 value
)
127 mutex_lock(&rt2x00dev
->csr_mutex
);
130 * Wait until the RF becomes available, afterwards we
131 * can safely write the new data into the register.
133 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
135 rt2x00_set_field32(®
, PHY_CSR4_VALUE
, value
);
136 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
, 21);
137 rt2x00_set_field32(®
, PHY_CSR4_IF_SELECT
, 0);
138 rt2x00_set_field32(®
, PHY_CSR4_BUSY
, 1);
140 rt2x00pci_register_write(rt2x00dev
, PHY_CSR4
, reg
);
141 rt2x00_rf_write(rt2x00dev
, word
, value
);
144 mutex_unlock(&rt2x00dev
->csr_mutex
);
147 static void rt61pci_mcu_request(struct rt2x00_dev
*rt2x00dev
,
148 const u8 command
, const u8 token
,
149 const u8 arg0
, const u8 arg1
)
153 mutex_lock(&rt2x00dev
->csr_mutex
);
156 * Wait until the MCU becomes available, afterwards we
157 * can safely write the new data into the register.
159 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
160 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
161 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
162 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
163 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
164 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
166 rt2x00pci_register_read(rt2x00dev
, HOST_CMD_CSR
, ®
);
167 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
168 rt2x00_set_field32(®
, HOST_CMD_CSR_INTERRUPT_MCU
, 1);
169 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, reg
);
172 mutex_unlock(&rt2x00dev
->csr_mutex
);
176 static void rt61pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
178 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
181 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
183 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_IN
);
184 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_OUT
);
185 eeprom
->reg_data_clock
=
186 !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_CLOCK
);
187 eeprom
->reg_chip_select
=
188 !!rt2x00_get_field32(reg
, E2PROM_CSR_CHIP_SELECT
);
191 static void rt61pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
193 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
196 rt2x00_set_field32(®
, E2PROM_CSR_DATA_IN
, !!eeprom
->reg_data_in
);
197 rt2x00_set_field32(®
, E2PROM_CSR_DATA_OUT
, !!eeprom
->reg_data_out
);
198 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
,
199 !!eeprom
->reg_data_clock
);
200 rt2x00_set_field32(®
, E2PROM_CSR_CHIP_SELECT
,
201 !!eeprom
->reg_chip_select
);
203 rt2x00pci_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
206 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
207 static const struct rt2x00debug rt61pci_rt2x00debug
= {
208 .owner
= THIS_MODULE
,
210 .read
= rt2x00pci_register_read
,
211 .write
= rt2x00pci_register_write
,
212 .flags
= RT2X00DEBUGFS_OFFSET
,
213 .word_base
= CSR_REG_BASE
,
214 .word_size
= sizeof(u32
),
215 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
218 .read
= rt2x00_eeprom_read
,
219 .write
= rt2x00_eeprom_write
,
220 .word_base
= EEPROM_BASE
,
221 .word_size
= sizeof(u16
),
222 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
225 .read
= rt61pci_bbp_read
,
226 .write
= rt61pci_bbp_write
,
227 .word_base
= BBP_BASE
,
228 .word_size
= sizeof(u8
),
229 .word_count
= BBP_SIZE
/ sizeof(u8
),
232 .read
= rt2x00_rf_read
,
233 .write
= rt61pci_rf_write
,
234 .word_base
= RF_BASE
,
235 .word_size
= sizeof(u32
),
236 .word_count
= RF_SIZE
/ sizeof(u32
),
239 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
241 static int rt61pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
245 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
246 return rt2x00_get_field32(reg
, MAC_CSR13_BIT5
);
249 #ifdef CONFIG_RT2X00_LIB_LEDS
250 static void rt61pci_brightness_set(struct led_classdev
*led_cdev
,
251 enum led_brightness brightness
)
253 struct rt2x00_led
*led
=
254 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
255 unsigned int enabled
= brightness
!= LED_OFF
;
256 unsigned int a_mode
=
257 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
258 unsigned int bg_mode
=
259 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
261 if (led
->type
== LED_TYPE_RADIO
) {
262 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
263 MCU_LEDCS_RADIO_STATUS
, enabled
);
265 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
266 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
267 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
268 } else if (led
->type
== LED_TYPE_ASSOC
) {
269 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
270 MCU_LEDCS_LINK_BG_STATUS
, bg_mode
);
271 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
272 MCU_LEDCS_LINK_A_STATUS
, a_mode
);
274 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
275 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
276 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
277 } else if (led
->type
== LED_TYPE_QUALITY
) {
279 * The brightness is divided into 6 levels (0 - 5),
280 * this means we need to convert the brightness
281 * argument into the matching level within that range.
283 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
284 brightness
/ (LED_FULL
/ 6), 0);
288 static int rt61pci_blink_set(struct led_classdev
*led_cdev
,
289 unsigned long *delay_on
,
290 unsigned long *delay_off
)
292 struct rt2x00_led
*led
=
293 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
296 rt2x00pci_register_read(led
->rt2x00dev
, MAC_CSR14
, ®
);
297 rt2x00_set_field32(®
, MAC_CSR14_ON_PERIOD
, *delay_on
);
298 rt2x00_set_field32(®
, MAC_CSR14_OFF_PERIOD
, *delay_off
);
299 rt2x00pci_register_write(led
->rt2x00dev
, MAC_CSR14
, reg
);
304 static void rt61pci_init_led(struct rt2x00_dev
*rt2x00dev
,
305 struct rt2x00_led
*led
,
308 led
->rt2x00dev
= rt2x00dev
;
310 led
->led_dev
.brightness_set
= rt61pci_brightness_set
;
311 led
->led_dev
.blink_set
= rt61pci_blink_set
;
312 led
->flags
= LED_INITIALIZED
;
314 #endif /* CONFIG_RT2X00_LIB_LEDS */
317 * Configuration handlers.
319 static int rt61pci_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
320 struct rt2x00lib_crypto
*crypto
,
321 struct ieee80211_key_conf
*key
)
323 struct hw_key_entry key_entry
;
324 struct rt2x00_field32 field
;
328 if (crypto
->cmd
== SET_KEY
) {
330 * rt2x00lib can't determine the correct free
331 * key_idx for shared keys. We have 1 register
332 * with key valid bits. The goal is simple, read
333 * the register, if that is full we have no slots
335 * Note that each BSS is allowed to have up to 4
336 * shared keys, so put a mask over the allowed
339 mask
= (0xf << crypto
->bssidx
);
341 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
344 if (reg
&& reg
== mask
)
347 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
350 * Upload key to hardware
352 memcpy(key_entry
.key
, crypto
->key
,
353 sizeof(key_entry
.key
));
354 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
355 sizeof(key_entry
.tx_mic
));
356 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
357 sizeof(key_entry
.rx_mic
));
359 reg
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
360 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
361 &key_entry
, sizeof(key_entry
));
364 * The cipher types are stored over 2 registers.
365 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
366 * bssidx 1 and 2 keys are stored in SEC_CSR5.
367 * Using the correct defines correctly will cause overhead,
368 * so just calculate the correct offset.
370 if (key
->hw_key_idx
< 8) {
371 field
.bit_offset
= (3 * key
->hw_key_idx
);
372 field
.bit_mask
= 0x7 << field
.bit_offset
;
374 rt2x00pci_register_read(rt2x00dev
, SEC_CSR1
, ®
);
375 rt2x00_set_field32(®
, field
, crypto
->cipher
);
376 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, reg
);
378 field
.bit_offset
= (3 * (key
->hw_key_idx
- 8));
379 field
.bit_mask
= 0x7 << field
.bit_offset
;
381 rt2x00pci_register_read(rt2x00dev
, SEC_CSR5
, ®
);
382 rt2x00_set_field32(®
, field
, crypto
->cipher
);
383 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, reg
);
387 * The driver does not support the IV/EIV generation
388 * in hardware. However it doesn't support the IV/EIV
389 * inside the ieee80211 frame either, but requires it
390 * to be provided separately for the descriptor.
391 * rt2x00lib will cut the IV/EIV data out of all frames
392 * given to us by mac80211, but we must tell mac80211
393 * to generate the IV/EIV data.
395 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
399 * SEC_CSR0 contains only single-bit fields to indicate
400 * a particular key is valid. Because using the FIELD32()
401 * defines directly will cause a lot of overhead, we use
402 * a calculation to determine the correct bit directly.
404 mask
= 1 << key
->hw_key_idx
;
406 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
407 if (crypto
->cmd
== SET_KEY
)
409 else if (crypto
->cmd
== DISABLE_KEY
)
411 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, reg
);
416 static int rt61pci_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
417 struct rt2x00lib_crypto
*crypto
,
418 struct ieee80211_key_conf
*key
)
420 struct hw_pairwise_ta_entry addr_entry
;
421 struct hw_key_entry key_entry
;
425 if (crypto
->cmd
== SET_KEY
) {
427 * rt2x00lib can't determine the correct free
428 * key_idx for pairwise keys. We have 2 registers
429 * with key valid bits. The goal is simple: read
430 * the first register. If that is full, move to
432 * When both registers are full, we drop the key.
433 * Otherwise, we use the first invalid entry.
435 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
436 if (reg
&& reg
== ~0) {
437 key
->hw_key_idx
= 32;
438 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
439 if (reg
&& reg
== ~0)
443 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
446 * Upload key to hardware
448 memcpy(key_entry
.key
, crypto
->key
,
449 sizeof(key_entry
.key
));
450 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
451 sizeof(key_entry
.tx_mic
));
452 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
453 sizeof(key_entry
.rx_mic
));
455 memset(&addr_entry
, 0, sizeof(addr_entry
));
456 memcpy(&addr_entry
, crypto
->address
, ETH_ALEN
);
457 addr_entry
.cipher
= crypto
->cipher
;
459 reg
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
460 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
461 &key_entry
, sizeof(key_entry
));
463 reg
= PAIRWISE_TA_ENTRY(key
->hw_key_idx
);
464 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
465 &addr_entry
, sizeof(addr_entry
));
468 * Enable pairwise lookup table for given BSS idx.
469 * Without this, received frames will not be decrypted
472 rt2x00pci_register_read(rt2x00dev
, SEC_CSR4
, ®
);
473 reg
|= (1 << crypto
->bssidx
);
474 rt2x00pci_register_write(rt2x00dev
, SEC_CSR4
, reg
);
477 * The driver does not support the IV/EIV generation
478 * in hardware. However it doesn't support the IV/EIV
479 * inside the ieee80211 frame either, but requires it
480 * to be provided separately for the descriptor.
481 * rt2x00lib will cut the IV/EIV data out of all frames
482 * given to us by mac80211, but we must tell mac80211
483 * to generate the IV/EIV data.
485 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
489 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
490 * a particular key is valid. Because using the FIELD32()
491 * defines directly will cause a lot of overhead, we use
492 * a calculation to determine the correct bit directly.
494 if (key
->hw_key_idx
< 32) {
495 mask
= 1 << key
->hw_key_idx
;
497 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
498 if (crypto
->cmd
== SET_KEY
)
500 else if (crypto
->cmd
== DISABLE_KEY
)
502 rt2x00pci_register_write(rt2x00dev
, SEC_CSR2
, reg
);
504 mask
= 1 << (key
->hw_key_idx
- 32);
506 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
507 if (crypto
->cmd
== SET_KEY
)
509 else if (crypto
->cmd
== DISABLE_KEY
)
511 rt2x00pci_register_write(rt2x00dev
, SEC_CSR3
, reg
);
517 static void rt61pci_config_filter(struct rt2x00_dev
*rt2x00dev
,
518 const unsigned int filter_flags
)
523 * Start configuration steps.
524 * Note that the version error will always be dropped
525 * and broadcast frames will always be accepted since
526 * there is no filter for it at this time.
528 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
529 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
,
530 !(filter_flags
& FIF_FCSFAIL
));
531 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
,
532 !(filter_flags
& FIF_PLCPFAIL
));
533 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
,
534 !(filter_flags
& (FIF_CONTROL
| FIF_PSPOLL
)));
535 rt2x00_set_field32(®
, TXRX_CSR0_DROP_NOT_TO_ME
,
536 !(filter_flags
& FIF_PROMISC_IN_BSS
));
537 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
,
538 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
539 !rt2x00dev
->intf_ap_count
);
540 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 1);
541 rt2x00_set_field32(®
, TXRX_CSR0_DROP_MULTICAST
,
542 !(filter_flags
& FIF_ALLMULTI
));
543 rt2x00_set_field32(®
, TXRX_CSR0_DROP_BROADCAST
, 0);
544 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
,
545 !(filter_flags
& FIF_CONTROL
));
546 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
549 static void rt61pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
550 struct rt2x00_intf
*intf
,
551 struct rt2x00intf_conf
*conf
,
552 const unsigned int flags
)
554 unsigned int beacon_base
;
557 if (flags
& CONFIG_UPDATE_TYPE
) {
559 * Clear current synchronisation setup.
560 * For the Beacon base registers, we only need to clear
561 * the first byte since that byte contains the VALID and OWNER
562 * bits which (when set to 0) will invalidate the entire beacon.
564 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
565 rt2x00pci_register_write(rt2x00dev
, beacon_base
, 0);
568 * Enable synchronisation.
570 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
571 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
572 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, conf
->sync
);
573 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
574 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
577 if (flags
& CONFIG_UPDATE_MAC
) {
578 reg
= le32_to_cpu(conf
->mac
[1]);
579 rt2x00_set_field32(®
, MAC_CSR3_UNICAST_TO_ME_MASK
, 0xff);
580 conf
->mac
[1] = cpu_to_le32(reg
);
582 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR2
,
583 conf
->mac
, sizeof(conf
->mac
));
586 if (flags
& CONFIG_UPDATE_BSSID
) {
587 reg
= le32_to_cpu(conf
->bssid
[1]);
588 rt2x00_set_field32(®
, MAC_CSR5_BSS_ID_MASK
, 3);
589 conf
->bssid
[1] = cpu_to_le32(reg
);
591 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR4
,
592 conf
->bssid
, sizeof(conf
->bssid
));
596 static void rt61pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
597 struct rt2x00lib_erp
*erp
)
601 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
602 rt2x00_set_field32(®
, TXRX_CSR0_RX_ACK_TIMEOUT
, 0x32);
603 rt2x00_set_field32(®
, TXRX_CSR0_TSF_OFFSET
, IEEE80211_HEADER
);
604 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
606 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
607 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_ENABLE
, 1);
608 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
,
609 !!erp
->short_preamble
);
610 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
612 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR5
, erp
->basic_rates
);
614 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
615 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
,
616 erp
->beacon_int
* 16);
617 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
619 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
620 rt2x00_set_field32(®
, MAC_CSR9_SLOT_TIME
, erp
->slot_time
);
621 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
623 rt2x00pci_register_read(rt2x00dev
, MAC_CSR8
, ®
);
624 rt2x00_set_field32(®
, MAC_CSR8_SIFS
, erp
->sifs
);
625 rt2x00_set_field32(®
, MAC_CSR8_SIFS_AFTER_RX_OFDM
, 3);
626 rt2x00_set_field32(®
, MAC_CSR8_EIFS
, erp
->eifs
);
627 rt2x00pci_register_write(rt2x00dev
, MAC_CSR8
, reg
);
630 static void rt61pci_config_antenna_5x(struct rt2x00_dev
*rt2x00dev
,
631 struct antenna_setup
*ant
)
637 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
638 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
639 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
641 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, rt2x00_rf(rt2x00dev
, RF5325
));
644 * Configure the RX antenna.
647 case ANTENNA_HW_DIVERSITY
:
648 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
649 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
650 (rt2x00dev
->curr_band
!= IEEE80211_BAND_5GHZ
));
653 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
654 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
655 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
656 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
658 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
662 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
663 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
664 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
665 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
667 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
671 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
672 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
673 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
676 static void rt61pci_config_antenna_2x(struct rt2x00_dev
*rt2x00dev
,
677 struct antenna_setup
*ant
)
683 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
684 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
685 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
687 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, rt2x00_rf(rt2x00dev
, RF2529
));
688 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
689 !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
));
692 * Configure the RX antenna.
695 case ANTENNA_HW_DIVERSITY
:
696 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
699 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
700 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
704 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
705 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
709 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
710 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
711 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
714 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev
*rt2x00dev
,
715 const int p1
, const int p2
)
719 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
721 rt2x00_set_field32(®
, MAC_CSR13_BIT4
, p1
);
722 rt2x00_set_field32(®
, MAC_CSR13_BIT12
, 0);
724 rt2x00_set_field32(®
, MAC_CSR13_BIT3
, !p2
);
725 rt2x00_set_field32(®
, MAC_CSR13_BIT11
, 0);
727 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, reg
);
730 static void rt61pci_config_antenna_2529(struct rt2x00_dev
*rt2x00dev
,
731 struct antenna_setup
*ant
)
737 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
738 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
739 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
742 * Configure the RX antenna.
746 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
747 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
748 rt61pci_config_antenna_2529_rx(rt2x00dev
, 0, 0);
750 case ANTENNA_HW_DIVERSITY
:
752 * FIXME: Antenna selection for the rf 2529 is very confusing
753 * in the legacy driver. Just default to antenna B until the
754 * legacy code can be properly translated into rt2x00 code.
758 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
759 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
760 rt61pci_config_antenna_2529_rx(rt2x00dev
, 1, 1);
764 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
765 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
766 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
772 * value[0] -> non-LNA
778 static const struct antenna_sel antenna_sel_a
[] = {
779 { 96, { 0x58, 0x78 } },
780 { 104, { 0x38, 0x48 } },
781 { 75, { 0xfe, 0x80 } },
782 { 86, { 0xfe, 0x80 } },
783 { 88, { 0xfe, 0x80 } },
784 { 35, { 0x60, 0x60 } },
785 { 97, { 0x58, 0x58 } },
786 { 98, { 0x58, 0x58 } },
789 static const struct antenna_sel antenna_sel_bg
[] = {
790 { 96, { 0x48, 0x68 } },
791 { 104, { 0x2c, 0x3c } },
792 { 75, { 0xfe, 0x80 } },
793 { 86, { 0xfe, 0x80 } },
794 { 88, { 0xfe, 0x80 } },
795 { 35, { 0x50, 0x50 } },
796 { 97, { 0x48, 0x48 } },
797 { 98, { 0x48, 0x48 } },
800 static void rt61pci_config_ant(struct rt2x00_dev
*rt2x00dev
,
801 struct antenna_setup
*ant
)
803 const struct antenna_sel
*sel
;
809 * We should never come here because rt2x00lib is supposed
810 * to catch this and send us the correct antenna explicitely.
812 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
813 ant
->tx
== ANTENNA_SW_DIVERSITY
);
815 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
817 lna
= test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
819 sel
= antenna_sel_bg
;
820 lna
= test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
823 for (i
= 0; i
< ARRAY_SIZE(antenna_sel_a
); i
++)
824 rt61pci_bbp_write(rt2x00dev
, sel
[i
].word
, sel
[i
].value
[lna
]);
826 rt2x00pci_register_read(rt2x00dev
, PHY_CSR0
, ®
);
828 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
,
829 rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
830 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
,
831 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
833 rt2x00pci_register_write(rt2x00dev
, PHY_CSR0
, reg
);
835 if (rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF5325
))
836 rt61pci_config_antenna_5x(rt2x00dev
, ant
);
837 else if (rt2x00_rf(rt2x00dev
, RF2527
))
838 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
839 else if (rt2x00_rf(rt2x00dev
, RF2529
)) {
840 if (test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
))
841 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
843 rt61pci_config_antenna_2529(rt2x00dev
, ant
);
847 static void rt61pci_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
848 struct rt2x00lib_conf
*libconf
)
853 if (libconf
->conf
->channel
->band
== IEEE80211_BAND_2GHZ
) {
854 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
857 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &eeprom
);
858 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_BG_1
);
860 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
863 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &eeprom
);
864 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_A_1
);
867 rt2x00dev
->lna_gain
= lna_gain
;
870 static void rt61pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
871 struct rf_channel
*rf
, const int txpower
)
877 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
878 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
880 smart
= !(rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF2527
));
882 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
883 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, smart
);
884 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
887 if (txpower
> MAX_TXPOWER
&& txpower
<= (MAX_TXPOWER
+ r94
))
888 r94
+= txpower
- MAX_TXPOWER
;
889 else if (txpower
< MIN_TXPOWER
&& txpower
>= (MIN_TXPOWER
- r94
))
891 rt61pci_bbp_write(rt2x00dev
, 94, r94
);
893 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
894 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
895 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
896 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
900 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
901 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
902 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
903 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
907 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
908 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
909 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
910 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
915 static void rt61pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
918 struct rf_channel rf
;
920 rt2x00_rf_read(rt2x00dev
, 1, &rf
.rf1
);
921 rt2x00_rf_read(rt2x00dev
, 2, &rf
.rf2
);
922 rt2x00_rf_read(rt2x00dev
, 3, &rf
.rf3
);
923 rt2x00_rf_read(rt2x00dev
, 4, &rf
.rf4
);
925 rt61pci_config_channel(rt2x00dev
, &rf
, txpower
);
928 static void rt61pci_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
929 struct rt2x00lib_conf
*libconf
)
933 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
934 rt2x00_set_field32(®
, TXRX_CSR4_OFDM_TX_RATE_DOWN
, 1);
935 rt2x00_set_field32(®
, TXRX_CSR4_OFDM_TX_RATE_STEP
, 0);
936 rt2x00_set_field32(®
, TXRX_CSR4_OFDM_TX_FALLBACK_CCK
, 0);
937 rt2x00_set_field32(®
, TXRX_CSR4_LONG_RETRY_LIMIT
,
938 libconf
->conf
->long_frame_max_tx_count
);
939 rt2x00_set_field32(®
, TXRX_CSR4_SHORT_RETRY_LIMIT
,
940 libconf
->conf
->short_frame_max_tx_count
);
941 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
944 static void rt61pci_config_ps(struct rt2x00_dev
*rt2x00dev
,
945 struct rt2x00lib_conf
*libconf
)
947 enum dev_state state
=
948 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
949 STATE_SLEEP
: STATE_AWAKE
;
952 if (state
== STATE_SLEEP
) {
953 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
954 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
,
955 rt2x00dev
->beacon_int
- 10);
956 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
,
957 libconf
->conf
->listen_interval
- 1);
958 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 5);
960 /* We must first disable autowake before it can be enabled */
961 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
962 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
964 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 1);
965 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
967 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000005);
968 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x0000001c);
969 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000060);
971 rt61pci_mcu_request(rt2x00dev
, MCU_SLEEP
, 0xff, 0, 0);
973 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
974 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
, 0);
975 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
, 0);
976 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
977 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 0);
978 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
980 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000007);
981 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x00000018);
982 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000020);
984 rt61pci_mcu_request(rt2x00dev
, MCU_WAKEUP
, 0xff, 0, 0);
988 static void rt61pci_config(struct rt2x00_dev
*rt2x00dev
,
989 struct rt2x00lib_conf
*libconf
,
990 const unsigned int flags
)
992 /* Always recalculate LNA gain before changing configuration */
993 rt61pci_config_lna_gain(rt2x00dev
, libconf
);
995 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
996 rt61pci_config_channel(rt2x00dev
, &libconf
->rf
,
997 libconf
->conf
->power_level
);
998 if ((flags
& IEEE80211_CONF_CHANGE_POWER
) &&
999 !(flags
& IEEE80211_CONF_CHANGE_CHANNEL
))
1000 rt61pci_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
1001 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
1002 rt61pci_config_retry_limit(rt2x00dev
, libconf
);
1003 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1004 rt61pci_config_ps(rt2x00dev
, libconf
);
1010 static void rt61pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
1011 struct link_qual
*qual
)
1016 * Update FCS error count from register.
1018 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1019 qual
->rx_failed
= rt2x00_get_field32(reg
, STA_CSR0_FCS_ERROR
);
1022 * Update False CCA count from register.
1024 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1025 qual
->false_cca
= rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
1028 static inline void rt61pci_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1029 struct link_qual
*qual
, u8 vgc_level
)
1031 if (qual
->vgc_level
!= vgc_level
) {
1032 rt61pci_bbp_write(rt2x00dev
, 17, vgc_level
);
1033 qual
->vgc_level
= vgc_level
;
1034 qual
->vgc_level_reg
= vgc_level
;
1038 static void rt61pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
,
1039 struct link_qual
*qual
)
1041 rt61pci_set_vgc(rt2x00dev
, qual
, 0x20);
1044 static void rt61pci_link_tuner(struct rt2x00_dev
*rt2x00dev
,
1045 struct link_qual
*qual
, const u32 count
)
1051 * Determine r17 bounds.
1053 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1056 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
1063 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
1070 * If we are not associated, we should go straight to the
1071 * dynamic CCA tuning.
1073 if (!rt2x00dev
->intf_associated
)
1074 goto dynamic_cca_tune
;
1077 * Special big-R17 for very short distance
1079 if (qual
->rssi
>= -35) {
1080 rt61pci_set_vgc(rt2x00dev
, qual
, 0x60);
1085 * Special big-R17 for short distance
1087 if (qual
->rssi
>= -58) {
1088 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1093 * Special big-R17 for middle-short distance
1095 if (qual
->rssi
>= -66) {
1096 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x10);
1101 * Special mid-R17 for middle distance
1103 if (qual
->rssi
>= -74) {
1104 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x08);
1109 * Special case: Change up_bound based on the rssi.
1110 * Lower up_bound when rssi is weaker then -74 dBm.
1112 up_bound
-= 2 * (-74 - qual
->rssi
);
1113 if (low_bound
> up_bound
)
1114 up_bound
= low_bound
;
1116 if (qual
->vgc_level
> up_bound
) {
1117 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1124 * r17 does not yet exceed upper limit, continue and base
1125 * the r17 tuning on the false CCA count.
1127 if ((qual
->false_cca
> 512) && (qual
->vgc_level
< up_bound
))
1128 rt61pci_set_vgc(rt2x00dev
, qual
, ++qual
->vgc_level
);
1129 else if ((qual
->false_cca
< 100) && (qual
->vgc_level
> low_bound
))
1130 rt61pci_set_vgc(rt2x00dev
, qual
, --qual
->vgc_level
);
1134 * Firmware functions
1136 static char *rt61pci_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
1141 pci_read_config_word(to_pci_dev(rt2x00dev
->dev
), PCI_DEVICE_ID
, &chip
);
1144 fw_name
= FIRMWARE_RT2561
;
1146 case RT2561s_PCI_ID
:
1147 fw_name
= FIRMWARE_RT2561s
;
1150 fw_name
= FIRMWARE_RT2661
;
1160 static int rt61pci_check_firmware(struct rt2x00_dev
*rt2x00dev
,
1161 const u8
*data
, const size_t len
)
1167 * Only support 8kb firmware files.
1170 return FW_BAD_LENGTH
;
1173 * The last 2 bytes in the firmware array are the crc checksum itself.
1174 * This means that we should never pass those 2 bytes to the crc
1177 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
1180 * Use the crc itu-t algorithm.
1182 crc
= crc_itu_t(0, data
, len
- 2);
1183 crc
= crc_itu_t_byte(crc
, 0);
1184 crc
= crc_itu_t_byte(crc
, 0);
1186 return (fw_crc
== crc
) ? FW_OK
: FW_BAD_CRC
;
1189 static int rt61pci_load_firmware(struct rt2x00_dev
*rt2x00dev
,
1190 const u8
*data
, const size_t len
)
1196 * Wait for stable hardware.
1198 for (i
= 0; i
< 100; i
++) {
1199 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1206 ERROR(rt2x00dev
, "Unstable hardware.\n");
1211 * Prepare MCU and mailbox for firmware loading.
1214 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1215 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1216 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1217 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
1218 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, 0);
1221 * Write firmware to device.
1224 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1225 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 1);
1226 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1228 rt2x00pci_register_multiwrite(rt2x00dev
, FIRMWARE_IMAGE_BASE
,
1231 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 0);
1232 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1234 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 0);
1235 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1237 for (i
= 0; i
< 100; i
++) {
1238 rt2x00pci_register_read(rt2x00dev
, MCU_CNTL_CSR
, ®
);
1239 if (rt2x00_get_field32(reg
, MCU_CNTL_CSR_READY
))
1245 ERROR(rt2x00dev
, "MCU Control register not ready.\n");
1250 * Hardware needs another millisecond before it is ready.
1255 * Reset MAC and BBP registers.
1258 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1259 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1260 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1262 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1263 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1264 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1265 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1267 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1268 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1269 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1275 * Initialization functions.
1277 static bool rt61pci_get_entry_state(struct queue_entry
*entry
)
1279 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1282 if (entry
->queue
->qid
== QID_RX
) {
1283 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1285 return rt2x00_get_field32(word
, RXD_W0_OWNER_NIC
);
1287 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1289 return (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1290 rt2x00_get_field32(word
, TXD_W0_VALID
));
1294 static void rt61pci_clear_entry(struct queue_entry
*entry
)
1296 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1297 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1300 if (entry
->queue
->qid
== QID_RX
) {
1301 rt2x00_desc_read(entry_priv
->desc
, 5, &word
);
1302 rt2x00_set_field32(&word
, RXD_W5_BUFFER_PHYSICAL_ADDRESS
,
1304 rt2x00_desc_write(entry_priv
->desc
, 5, word
);
1306 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1307 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
1308 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1310 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1311 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
1312 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
1313 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1317 static int rt61pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
1319 struct queue_entry_priv_pci
*entry_priv
;
1323 * Initialize registers.
1325 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR0
, ®
);
1326 rt2x00_set_field32(®
, TX_RING_CSR0_AC0_RING_SIZE
,
1327 rt2x00dev
->tx
[0].limit
);
1328 rt2x00_set_field32(®
, TX_RING_CSR0_AC1_RING_SIZE
,
1329 rt2x00dev
->tx
[1].limit
);
1330 rt2x00_set_field32(®
, TX_RING_CSR0_AC2_RING_SIZE
,
1331 rt2x00dev
->tx
[2].limit
);
1332 rt2x00_set_field32(®
, TX_RING_CSR0_AC3_RING_SIZE
,
1333 rt2x00dev
->tx
[3].limit
);
1334 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR0
, reg
);
1336 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR1
, ®
);
1337 rt2x00_set_field32(®
, TX_RING_CSR1_TXD_SIZE
,
1338 rt2x00dev
->tx
[0].desc_size
/ 4);
1339 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR1
, reg
);
1341 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
1342 rt2x00pci_register_read(rt2x00dev
, AC0_BASE_CSR
, ®
);
1343 rt2x00_set_field32(®
, AC0_BASE_CSR_RING_REGISTER
,
1344 entry_priv
->desc_dma
);
1345 rt2x00pci_register_write(rt2x00dev
, AC0_BASE_CSR
, reg
);
1347 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
1348 rt2x00pci_register_read(rt2x00dev
, AC1_BASE_CSR
, ®
);
1349 rt2x00_set_field32(®
, AC1_BASE_CSR_RING_REGISTER
,
1350 entry_priv
->desc_dma
);
1351 rt2x00pci_register_write(rt2x00dev
, AC1_BASE_CSR
, reg
);
1353 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
1354 rt2x00pci_register_read(rt2x00dev
, AC2_BASE_CSR
, ®
);
1355 rt2x00_set_field32(®
, AC2_BASE_CSR_RING_REGISTER
,
1356 entry_priv
->desc_dma
);
1357 rt2x00pci_register_write(rt2x00dev
, AC2_BASE_CSR
, reg
);
1359 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
1360 rt2x00pci_register_read(rt2x00dev
, AC3_BASE_CSR
, ®
);
1361 rt2x00_set_field32(®
, AC3_BASE_CSR_RING_REGISTER
,
1362 entry_priv
->desc_dma
);
1363 rt2x00pci_register_write(rt2x00dev
, AC3_BASE_CSR
, reg
);
1365 rt2x00pci_register_read(rt2x00dev
, RX_RING_CSR
, ®
);
1366 rt2x00_set_field32(®
, RX_RING_CSR_RING_SIZE
, rt2x00dev
->rx
->limit
);
1367 rt2x00_set_field32(®
, RX_RING_CSR_RXD_SIZE
,
1368 rt2x00dev
->rx
->desc_size
/ 4);
1369 rt2x00_set_field32(®
, RX_RING_CSR_RXD_WRITEBACK_SIZE
, 4);
1370 rt2x00pci_register_write(rt2x00dev
, RX_RING_CSR
, reg
);
1372 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
1373 rt2x00pci_register_read(rt2x00dev
, RX_BASE_CSR
, ®
);
1374 rt2x00_set_field32(®
, RX_BASE_CSR_RING_REGISTER
,
1375 entry_priv
->desc_dma
);
1376 rt2x00pci_register_write(rt2x00dev
, RX_BASE_CSR
, reg
);
1378 rt2x00pci_register_read(rt2x00dev
, TX_DMA_DST_CSR
, ®
);
1379 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC0
, 2);
1380 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC1
, 2);
1381 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC2
, 2);
1382 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC3
, 2);
1383 rt2x00pci_register_write(rt2x00dev
, TX_DMA_DST_CSR
, reg
);
1385 rt2x00pci_register_read(rt2x00dev
, LOAD_TX_RING_CSR
, ®
);
1386 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC0
, 1);
1387 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC1
, 1);
1388 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC2
, 1);
1389 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC3
, 1);
1390 rt2x00pci_register_write(rt2x00dev
, LOAD_TX_RING_CSR
, reg
);
1392 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1393 rt2x00_set_field32(®
, RX_CNTL_CSR_LOAD_RXD
, 1);
1394 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1399 static int rt61pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
1403 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1404 rt2x00_set_field32(®
, TXRX_CSR0_AUTO_TX_SEQ
, 1);
1405 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
1406 rt2x00_set_field32(®
, TXRX_CSR0_TX_WITHOUT_WAITING
, 0);
1407 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1409 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR1
, ®
);
1410 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0
, 47); /* CCK Signal */
1411 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0_VALID
, 1);
1412 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1
, 30); /* Rssi */
1413 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1_VALID
, 1);
1414 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2
, 42); /* OFDM Rate */
1415 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2_VALID
, 1);
1416 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3
, 30); /* Rssi */
1417 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3_VALID
, 1);
1418 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR1
, reg
);
1421 * CCK TXD BBP registers
1423 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR2
, ®
);
1424 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0
, 13);
1425 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0_VALID
, 1);
1426 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1
, 12);
1427 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1_VALID
, 1);
1428 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2
, 11);
1429 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2_VALID
, 1);
1430 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3
, 10);
1431 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3_VALID
, 1);
1432 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR2
, reg
);
1435 * OFDM TXD BBP registers
1437 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR3
, ®
);
1438 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0
, 7);
1439 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0_VALID
, 1);
1440 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1
, 6);
1441 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1_VALID
, 1);
1442 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2
, 5);
1443 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2_VALID
, 1);
1444 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR3
, reg
);
1446 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR7
, ®
);
1447 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_6MBS
, 59);
1448 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_9MBS
, 53);
1449 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_12MBS
, 49);
1450 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_18MBS
, 46);
1451 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR7
, reg
);
1453 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR8
, ®
);
1454 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_24MBS
, 44);
1455 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_36MBS
, 42);
1456 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_48MBS
, 42);
1457 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_54MBS
, 42);
1458 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR8
, reg
);
1460 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1461 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
, 0);
1462 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1463 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 0);
1464 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1465 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1466 rt2x00_set_field32(®
, TXRX_CSR9_TIMESTAMP_COMPENSATE
, 0);
1467 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1469 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR15
, 0x0000000f);
1471 rt2x00pci_register_write(rt2x00dev
, MAC_CSR6
, 0x00000fff);
1473 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
1474 rt2x00_set_field32(®
, MAC_CSR9_CW_SELECT
, 0);
1475 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
1477 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x0000071c);
1479 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
1482 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, 0x0000e000);
1485 * Invalidate all Shared Keys (SEC_CSR0),
1486 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1488 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, 0x00000000);
1489 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, 0x00000000);
1490 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, 0x00000000);
1492 rt2x00pci_register_write(rt2x00dev
, PHY_CSR1
, 0x000023b0);
1493 rt2x00pci_register_write(rt2x00dev
, PHY_CSR5
, 0x060a100c);
1494 rt2x00pci_register_write(rt2x00dev
, PHY_CSR6
, 0x00080606);
1495 rt2x00pci_register_write(rt2x00dev
, PHY_CSR7
, 0x00000a08);
1497 rt2x00pci_register_write(rt2x00dev
, PCI_CFG_CSR
, 0x28ca4404);
1499 rt2x00pci_register_write(rt2x00dev
, TEST_MODE_CSR
, 0x00000200);
1501 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1505 * For the Beacon base registers we only need to clear
1506 * the first byte since that byte contains the VALID and OWNER
1507 * bits which (when set to 0) will invalidate the entire beacon.
1509 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1510 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1511 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1512 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1515 * We must clear the error counters.
1516 * These registers are cleared on read,
1517 * so we may pass a useless variable to store the value.
1519 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1520 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1521 rt2x00pci_register_read(rt2x00dev
, STA_CSR2
, ®
);
1524 * Reset MAC and BBP registers.
1526 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1527 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1528 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1529 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1531 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1532 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1533 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1534 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1536 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1537 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1538 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1543 static int rt61pci_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1548 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1549 rt61pci_bbp_read(rt2x00dev
, 0, &value
);
1550 if ((value
!= 0xff) && (value
!= 0x00))
1552 udelay(REGISTER_BUSY_DELAY
);
1555 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1559 static int rt61pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1566 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev
)))
1569 rt61pci_bbp_write(rt2x00dev
, 3, 0x00);
1570 rt61pci_bbp_write(rt2x00dev
, 15, 0x30);
1571 rt61pci_bbp_write(rt2x00dev
, 21, 0xc8);
1572 rt61pci_bbp_write(rt2x00dev
, 22, 0x38);
1573 rt61pci_bbp_write(rt2x00dev
, 23, 0x06);
1574 rt61pci_bbp_write(rt2x00dev
, 24, 0xfe);
1575 rt61pci_bbp_write(rt2x00dev
, 25, 0x0a);
1576 rt61pci_bbp_write(rt2x00dev
, 26, 0x0d);
1577 rt61pci_bbp_write(rt2x00dev
, 34, 0x12);
1578 rt61pci_bbp_write(rt2x00dev
, 37, 0x07);
1579 rt61pci_bbp_write(rt2x00dev
, 39, 0xf8);
1580 rt61pci_bbp_write(rt2x00dev
, 41, 0x60);
1581 rt61pci_bbp_write(rt2x00dev
, 53, 0x10);
1582 rt61pci_bbp_write(rt2x00dev
, 54, 0x18);
1583 rt61pci_bbp_write(rt2x00dev
, 60, 0x10);
1584 rt61pci_bbp_write(rt2x00dev
, 61, 0x04);
1585 rt61pci_bbp_write(rt2x00dev
, 62, 0x04);
1586 rt61pci_bbp_write(rt2x00dev
, 75, 0xfe);
1587 rt61pci_bbp_write(rt2x00dev
, 86, 0xfe);
1588 rt61pci_bbp_write(rt2x00dev
, 88, 0xfe);
1589 rt61pci_bbp_write(rt2x00dev
, 90, 0x0f);
1590 rt61pci_bbp_write(rt2x00dev
, 99, 0x00);
1591 rt61pci_bbp_write(rt2x00dev
, 102, 0x16);
1592 rt61pci_bbp_write(rt2x00dev
, 107, 0x04);
1594 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1595 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1597 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1598 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1599 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1600 rt61pci_bbp_write(rt2x00dev
, reg_id
, value
);
1608 * Device state switch handlers.
1610 static void rt61pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1611 enum dev_state state
)
1615 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1616 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
,
1617 (state
== STATE_RADIO_RX_OFF
) ||
1618 (state
== STATE_RADIO_RX_OFF_LINK
));
1619 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1622 static void rt61pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
1623 enum dev_state state
)
1625 int mask
= (state
== STATE_RADIO_IRQ_OFF
) ||
1626 (state
== STATE_RADIO_IRQ_OFF_ISR
);
1630 * When interrupts are being enabled, the interrupt registers
1631 * should clear the register to assure a clean state.
1633 if (state
== STATE_RADIO_IRQ_ON
) {
1634 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
1635 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
1637 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®
);
1638 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg
);
1642 * Only toggle the interrupts bits we are going to use.
1643 * Non-checked interrupt bits are disabled by default.
1645 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
1646 rt2x00_set_field32(®
, INT_MASK_CSR_TXDONE
, mask
);
1647 rt2x00_set_field32(®
, INT_MASK_CSR_RXDONE
, mask
);
1648 rt2x00_set_field32(®
, INT_MASK_CSR_ENABLE_MITIGATION
, mask
);
1649 rt2x00_set_field32(®
, INT_MASK_CSR_MITIGATION_PERIOD
, 0xff);
1650 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
1652 rt2x00pci_register_read(rt2x00dev
, MCU_INT_MASK_CSR
, ®
);
1653 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_0
, mask
);
1654 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_1
, mask
);
1655 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_2
, mask
);
1656 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_3
, mask
);
1657 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_4
, mask
);
1658 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_5
, mask
);
1659 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_6
, mask
);
1660 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_7
, mask
);
1661 rt2x00pci_register_write(rt2x00dev
, MCU_INT_MASK_CSR
, reg
);
1664 static int rt61pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1669 * Initialize all registers.
1671 if (unlikely(rt61pci_init_queues(rt2x00dev
) ||
1672 rt61pci_init_registers(rt2x00dev
) ||
1673 rt61pci_init_bbp(rt2x00dev
)))
1679 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1680 rt2x00_set_field32(®
, RX_CNTL_CSR_ENABLE_RX_DMA
, 1);
1681 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1686 static void rt61pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1691 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x00001818);
1694 static int rt61pci_set_state(struct rt2x00_dev
*rt2x00dev
, enum dev_state state
)
1700 put_to_sleep
= (state
!= STATE_AWAKE
);
1702 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1703 rt2x00_set_field32(®
, MAC_CSR12_FORCE_WAKEUP
, !put_to_sleep
);
1704 rt2x00_set_field32(®
, MAC_CSR12_PUT_TO_SLEEP
, put_to_sleep
);
1705 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1708 * Device is not guaranteed to be in the requested state yet.
1709 * We must wait until the register indicates that the
1710 * device has entered the correct state.
1712 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1713 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®2
);
1714 state
= rt2x00_get_field32(reg2
, MAC_CSR12_BBP_CURRENT_STATE
);
1715 if (state
== !put_to_sleep
)
1717 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1724 static int rt61pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1725 enum dev_state state
)
1730 case STATE_RADIO_ON
:
1731 retval
= rt61pci_enable_radio(rt2x00dev
);
1733 case STATE_RADIO_OFF
:
1734 rt61pci_disable_radio(rt2x00dev
);
1736 case STATE_RADIO_RX_ON
:
1737 case STATE_RADIO_RX_ON_LINK
:
1738 case STATE_RADIO_RX_OFF
:
1739 case STATE_RADIO_RX_OFF_LINK
:
1740 rt61pci_toggle_rx(rt2x00dev
, state
);
1742 case STATE_RADIO_IRQ_ON
:
1743 case STATE_RADIO_IRQ_ON_ISR
:
1744 case STATE_RADIO_IRQ_OFF
:
1745 case STATE_RADIO_IRQ_OFF_ISR
:
1746 rt61pci_toggle_irq(rt2x00dev
, state
);
1748 case STATE_DEEP_SLEEP
:
1752 retval
= rt61pci_set_state(rt2x00dev
, state
);
1759 if (unlikely(retval
))
1760 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1767 * TX descriptor initialization
1769 static void rt61pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1770 struct sk_buff
*skb
,
1771 struct txentry_desc
*txdesc
)
1773 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1774 struct queue_entry_priv_pci
*entry_priv
= skbdesc
->entry
->priv_data
;
1775 __le32
*txd
= entry_priv
->desc
;
1779 * Start writing the descriptor words.
1781 rt2x00_desc_read(txd
, 1, &word
);
1782 rt2x00_set_field32(&word
, TXD_W1_HOST_Q_ID
, txdesc
->queue
);
1783 rt2x00_set_field32(&word
, TXD_W1_AIFSN
, txdesc
->aifs
);
1784 rt2x00_set_field32(&word
, TXD_W1_CWMIN
, txdesc
->cw_min
);
1785 rt2x00_set_field32(&word
, TXD_W1_CWMAX
, txdesc
->cw_max
);
1786 rt2x00_set_field32(&word
, TXD_W1_IV_OFFSET
, txdesc
->iv_offset
);
1787 rt2x00_set_field32(&word
, TXD_W1_HW_SEQUENCE
,
1788 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
1789 rt2x00_set_field32(&word
, TXD_W1_BUFFER_COUNT
, 1);
1790 rt2x00_desc_write(txd
, 1, word
);
1792 rt2x00_desc_read(txd
, 2, &word
);
1793 rt2x00_set_field32(&word
, TXD_W2_PLCP_SIGNAL
, txdesc
->signal
);
1794 rt2x00_set_field32(&word
, TXD_W2_PLCP_SERVICE
, txdesc
->service
);
1795 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1796 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1797 rt2x00_desc_write(txd
, 2, word
);
1799 if (test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
)) {
1800 _rt2x00_desc_write(txd
, 3, skbdesc
->iv
[0]);
1801 _rt2x00_desc_write(txd
, 4, skbdesc
->iv
[1]);
1804 rt2x00_desc_read(txd
, 5, &word
);
1805 rt2x00_set_field32(&word
, TXD_W5_PID_TYPE
, skbdesc
->entry
->queue
->qid
);
1806 rt2x00_set_field32(&word
, TXD_W5_PID_SUBTYPE
,
1807 skbdesc
->entry
->entry_idx
);
1808 rt2x00_set_field32(&word
, TXD_W5_TX_POWER
,
1809 TXPOWER_TO_DEV(rt2x00dev
->tx_power
));
1810 rt2x00_set_field32(&word
, TXD_W5_WAITING_DMA_DONE_INT
, 1);
1811 rt2x00_desc_write(txd
, 5, word
);
1813 if (txdesc
->queue
!= QID_BEACON
) {
1814 rt2x00_desc_read(txd
, 6, &word
);
1815 rt2x00_set_field32(&word
, TXD_W6_BUFFER_PHYSICAL_ADDRESS
,
1817 rt2x00_desc_write(txd
, 6, word
);
1819 rt2x00_desc_read(txd
, 11, &word
);
1820 rt2x00_set_field32(&word
, TXD_W11_BUFFER_LENGTH0
,
1822 rt2x00_desc_write(txd
, 11, word
);
1826 * Writing TXD word 0 must the last to prevent a race condition with
1827 * the device, whereby the device may take hold of the TXD before we
1828 * finished updating it.
1830 rt2x00_desc_read(txd
, 0, &word
);
1831 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1832 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1833 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1834 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1835 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1836 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1837 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1838 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1839 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1840 (txdesc
->rate_mode
== RATE_MODE_OFDM
));
1841 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1842 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1843 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1844 rt2x00_set_field32(&word
, TXD_W0_TKIP_MIC
,
1845 test_bit(ENTRY_TXD_ENCRYPT_MMIC
, &txdesc
->flags
));
1846 rt2x00_set_field32(&word
, TXD_W0_KEY_TABLE
,
1847 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE
, &txdesc
->flags
));
1848 rt2x00_set_field32(&word
, TXD_W0_KEY_INDEX
, txdesc
->key_idx
);
1849 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, txdesc
->length
);
1850 rt2x00_set_field32(&word
, TXD_W0_BURST
,
1851 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1852 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, txdesc
->cipher
);
1853 rt2x00_desc_write(txd
, 0, word
);
1856 * Register descriptor details in skb frame descriptor.
1858 skbdesc
->desc
= txd
;
1860 (txdesc
->queue
== QID_BEACON
) ? TXINFO_SIZE
: TXD_DESC_SIZE
;
1864 * TX data initialization
1866 static void rt61pci_write_beacon(struct queue_entry
*entry
,
1867 struct txentry_desc
*txdesc
)
1869 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1870 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1871 unsigned int beacon_base
;
1875 * Disable beaconing while we are reloading the beacon data,
1876 * otherwise we might be sending out invalid data.
1878 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1879 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1880 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1883 * Write the TX descriptor for the beacon.
1885 rt61pci_write_tx_desc(rt2x00dev
, entry
->skb
, txdesc
);
1888 * Dump beacon to userspace through debugfs.
1890 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
1893 * Write entire beacon with descriptor to register.
1895 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
1896 rt2x00pci_register_multiwrite(rt2x00dev
, beacon_base
,
1897 entry_priv
->desc
, TXINFO_SIZE
);
1898 rt2x00pci_register_multiwrite(rt2x00dev
, beacon_base
+ TXINFO_SIZE
,
1899 entry
->skb
->data
, entry
->skb
->len
);
1902 * Enable beaconing again.
1904 * For Wi-Fi faily generated beacons between participating
1905 * stations. Set TBTT phase adaptive adjustment step to 8us.
1907 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR10
, 0x00001008);
1909 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
1910 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
1911 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1912 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1915 * Clean up beacon skb.
1917 dev_kfree_skb_any(entry
->skb
);
1921 static void rt61pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1922 const enum data_queue_qid queue
)
1926 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1927 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC0
, (queue
== QID_AC_BE
));
1928 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC1
, (queue
== QID_AC_BK
));
1929 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC2
, (queue
== QID_AC_VI
));
1930 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC3
, (queue
== QID_AC_VO
));
1931 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1934 static void rt61pci_kill_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1935 const enum data_queue_qid qid
)
1939 if (qid
== QID_BEACON
) {
1940 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, 0);
1944 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1945 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC0
, (qid
== QID_AC_BE
));
1946 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC1
, (qid
== QID_AC_BK
));
1947 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC2
, (qid
== QID_AC_VI
));
1948 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC3
, (qid
== QID_AC_VO
));
1949 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1953 * RX control handlers
1955 static int rt61pci_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxd_w1
)
1957 u8 offset
= rt2x00dev
->lna_gain
;
1960 lna
= rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_LNA
);
1975 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1976 if (lna
== 3 || lna
== 2)
1980 return rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_AGC
) * 2 - offset
;
1983 static void rt61pci_fill_rxdone(struct queue_entry
*entry
,
1984 struct rxdone_entry_desc
*rxdesc
)
1986 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1987 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1991 rt2x00_desc_read(entry_priv
->desc
, 0, &word0
);
1992 rt2x00_desc_read(entry_priv
->desc
, 1, &word1
);
1994 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1995 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1997 rxdesc
->cipher
= rt2x00_get_field32(word0
, RXD_W0_CIPHER_ALG
);
1998 rxdesc
->cipher_status
= rt2x00_get_field32(word0
, RXD_W0_CIPHER_ERROR
);
2000 if (rxdesc
->cipher
!= CIPHER_NONE
) {
2001 _rt2x00_desc_read(entry_priv
->desc
, 2, &rxdesc
->iv
[0]);
2002 _rt2x00_desc_read(entry_priv
->desc
, 3, &rxdesc
->iv
[1]);
2003 rxdesc
->dev_flags
|= RXDONE_CRYPTO_IV
;
2005 _rt2x00_desc_read(entry_priv
->desc
, 4, &rxdesc
->icv
);
2006 rxdesc
->dev_flags
|= RXDONE_CRYPTO_ICV
;
2009 * Hardware has stripped IV/EIV data from 802.11 frame during
2010 * decryption. It has provided the data separately but rt2x00lib
2011 * should decide if it should be reinserted.
2013 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
2016 * FIXME: Legacy driver indicates that the frame does
2017 * contain the Michael Mic. Unfortunately, in rt2x00
2018 * the MIC seems to be missing completely...
2020 rxdesc
->flags
|= RX_FLAG_MMIC_STRIPPED
;
2022 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
)
2023 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
2024 else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
)
2025 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
2029 * Obtain the status about this packet.
2030 * When frame was received with an OFDM bitrate,
2031 * the signal is the PLCP value. If it was received with
2032 * a CCK bitrate the signal is the rate in 100kbit/s.
2034 rxdesc
->signal
= rt2x00_get_field32(word1
, RXD_W1_SIGNAL
);
2035 rxdesc
->rssi
= rt61pci_agc_to_rssi(rt2x00dev
, word1
);
2036 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
2038 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
2039 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
2041 rxdesc
->dev_flags
|= RXDONE_SIGNAL_BITRATE
;
2042 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
2043 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
2047 * Interrupt functions.
2049 static void rt61pci_txdone(struct rt2x00_dev
*rt2x00dev
)
2051 struct data_queue
*queue
;
2052 struct queue_entry
*entry
;
2053 struct queue_entry
*entry_done
;
2054 struct queue_entry_priv_pci
*entry_priv
;
2055 struct txdone_entry_desc txdesc
;
2063 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2064 * at most X times and also stop processing once the TX_STA_FIFO_VALID
2065 * flag is not set anymore.
2067 * The legacy drivers use X=TX_RING_SIZE but state in a comment
2068 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2069 * tx ring size for now.
2071 for (i
= 0; i
< TX_ENTRIES
; i
++) {
2072 rt2x00pci_register_read(rt2x00dev
, STA_CSR4
, ®
);
2073 if (!rt2x00_get_field32(reg
, STA_CSR4_VALID
))
2077 * Skip this entry when it contains an invalid
2078 * queue identication number.
2080 type
= rt2x00_get_field32(reg
, STA_CSR4_PID_TYPE
);
2081 queue
= rt2x00queue_get_queue(rt2x00dev
, type
);
2082 if (unlikely(!queue
))
2086 * Skip this entry when it contains an invalid
2089 index
= rt2x00_get_field32(reg
, STA_CSR4_PID_SUBTYPE
);
2090 if (unlikely(index
>= queue
->limit
))
2093 entry
= &queue
->entries
[index
];
2094 entry_priv
= entry
->priv_data
;
2095 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
2097 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
2098 !rt2x00_get_field32(word
, TXD_W0_VALID
))
2101 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2102 while (entry
!= entry_done
) {
2104 * Just report any entries we missed as failed.
2107 "TX status report missed for entry %d\n",
2108 entry_done
->entry_idx
);
2111 __set_bit(TXDONE_UNKNOWN
, &txdesc
.flags
);
2114 rt2x00lib_txdone(entry_done
, &txdesc
);
2115 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2119 * Obtain the status about this packet.
2122 switch (rt2x00_get_field32(reg
, STA_CSR4_TX_RESULT
)) {
2123 case 0: /* Success, maybe with retry */
2124 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
2126 case 6: /* Failure, excessive retries */
2127 __set_bit(TXDONE_EXCESSIVE_RETRY
, &txdesc
.flags
);
2128 /* Don't break, this is a failed frame! */
2129 default: /* Failure */
2130 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
2132 txdesc
.retry
= rt2x00_get_field32(reg
, STA_CSR4_RETRY_COUNT
);
2135 * the frame was retried at least once
2136 * -> hw used fallback rates
2139 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
2141 rt2x00lib_txdone(entry
, &txdesc
);
2145 static void rt61pci_wakeup(struct rt2x00_dev
*rt2x00dev
)
2147 struct ieee80211_conf conf
= { .flags
= 0 };
2148 struct rt2x00lib_conf libconf
= { .conf
= &conf
};
2150 rt61pci_config(rt2x00dev
, &libconf
, IEEE80211_CONF_CHANGE_PS
);
2153 static irqreturn_t
rt61pci_interrupt_thread(int irq
, void *dev_instance
)
2155 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
2156 u32 reg
= rt2x00dev
->irqvalue
[0];
2157 u32 reg_mcu
= rt2x00dev
->irqvalue
[1];
2160 * Handle interrupts, walk through all bits
2161 * and run the tasks, the bits are checked in order of
2166 * 1 - Rx ring done interrupt.
2168 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RXDONE
))
2169 rt2x00pci_rxdone(rt2x00dev
);
2172 * 2 - Tx ring done interrupt.
2174 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TXDONE
))
2175 rt61pci_txdone(rt2x00dev
);
2178 * 3 - Handle MCU command done.
2181 rt2x00pci_register_write(rt2x00dev
,
2182 M2H_CMD_DONE_CSR
, 0xffffffff);
2185 * 4 - MCU Autowakeup interrupt.
2187 if (rt2x00_get_field32(reg_mcu
, MCU_INT_SOURCE_CSR_TWAKEUP
))
2188 rt61pci_wakeup(rt2x00dev
);
2191 * 5 - Beacon done interrupt.
2193 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_BEACON_DONE
))
2194 rt2x00lib_beacondone(rt2x00dev
);
2196 /* Enable interrupts again. */
2197 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
,
2198 STATE_RADIO_IRQ_ON_ISR
);
2203 static irqreturn_t
rt61pci_interrupt(int irq
, void *dev_instance
)
2205 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
2210 * Get the interrupt sources & saved to local variable.
2211 * Write register value back to clear pending interrupts.
2213 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®_mcu
);
2214 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg_mcu
);
2216 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
2217 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
2219 if (!reg
&& !reg_mcu
)
2222 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
2225 /* Store irqvalues for use in the interrupt thread. */
2226 rt2x00dev
->irqvalue
[0] = reg
;
2227 rt2x00dev
->irqvalue
[1] = reg_mcu
;
2229 /* Disable interrupts, will be enabled again in the interrupt thread. */
2230 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
,
2231 STATE_RADIO_IRQ_OFF_ISR
);
2232 return IRQ_WAKE_THREAD
;
2236 * Device probe functions.
2238 static int rt61pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2240 struct eeprom_93cx6 eeprom
;
2246 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
2248 eeprom
.data
= rt2x00dev
;
2249 eeprom
.register_read
= rt61pci_eepromregister_read
;
2250 eeprom
.register_write
= rt61pci_eepromregister_write
;
2251 eeprom
.width
= rt2x00_get_field32(reg
, E2PROM_CSR_TYPE_93C46
) ?
2252 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
2253 eeprom
.reg_data_in
= 0;
2254 eeprom
.reg_data_out
= 0;
2255 eeprom
.reg_data_clock
= 0;
2256 eeprom
.reg_chip_select
= 0;
2258 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
2259 EEPROM_SIZE
/ sizeof(u16
));
2262 * Start validation of the data that has been read.
2264 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2265 if (!is_valid_ether_addr(mac
)) {
2266 random_ether_addr(mac
);
2267 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
2270 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2271 if (word
== 0xffff) {
2272 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
2273 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
2275 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
2277 rt2x00_set_field16(&word
, EEPROM_ANTENNA_FRAME_TYPE
, 0);
2278 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
2279 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
2280 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF5225
);
2281 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2282 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2285 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2286 if (word
== 0xffff) {
2287 rt2x00_set_field16(&word
, EEPROM_NIC_ENABLE_DIVERSITY
, 0);
2288 rt2x00_set_field16(&word
, EEPROM_NIC_TX_DIVERSITY
, 0);
2289 rt2x00_set_field16(&word
, EEPROM_NIC_RX_FIXED
, 0);
2290 rt2x00_set_field16(&word
, EEPROM_NIC_TX_FIXED
, 0);
2291 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2292 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2293 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2294 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2295 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2298 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &word
);
2299 if (word
== 0xffff) {
2300 rt2x00_set_field16(&word
, EEPROM_LED_LED_MODE
,
2302 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED
, word
);
2303 EEPROM(rt2x00dev
, "Led: 0x%04x\n", word
);
2306 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2307 if (word
== 0xffff) {
2308 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2309 rt2x00_set_field16(&word
, EEPROM_FREQ_SEQ
, 0);
2310 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2311 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2314 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &word
);
2315 if (word
== 0xffff) {
2316 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2317 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2318 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2319 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
2321 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_1
);
2322 if (value
< -10 || value
> 10)
2323 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2324 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_2
);
2325 if (value
< -10 || value
> 10)
2326 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2327 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2330 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &word
);
2331 if (word
== 0xffff) {
2332 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2333 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2334 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2335 EEPROM(rt2x00dev
, "RSSI OFFSET A: 0x%04x\n", word
);
2337 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_1
);
2338 if (value
< -10 || value
> 10)
2339 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2340 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_2
);
2341 if (value
< -10 || value
> 10)
2342 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2343 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2349 static int rt61pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2356 * Read EEPROM word for configuration.
2358 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2361 * Identify RF chipset.
2363 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2364 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2365 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
2366 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
2368 if (!rt2x00_rf(rt2x00dev
, RF5225
) &&
2369 !rt2x00_rf(rt2x00dev
, RF5325
) &&
2370 !rt2x00_rf(rt2x00dev
, RF2527
) &&
2371 !rt2x00_rf(rt2x00dev
, RF2529
)) {
2372 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2377 * Determine number of antennas.
2379 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_NUM
) == 2)
2380 __set_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
);
2383 * Identify default antenna configuration.
2385 rt2x00dev
->default_ant
.tx
=
2386 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
2387 rt2x00dev
->default_ant
.rx
=
2388 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
2391 * Read the Frame type.
2393 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_FRAME_TYPE
))
2394 __set_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
);
2397 * Detect if this device has a hardware controlled radio.
2399 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
2400 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
2403 * Read frequency offset and RF programming sequence.
2405 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2406 if (rt2x00_get_field16(eeprom
, EEPROM_FREQ_SEQ
))
2407 __set_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
);
2409 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2412 * Read external LNA informations.
2414 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2416 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2417 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
2418 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2419 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
2422 * When working with a RF2529 chip without double antenna,
2423 * the antenna settings should be gathered from the NIC
2426 if (rt2x00_rf(rt2x00dev
, RF2529
) &&
2427 !test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
)) {
2428 rt2x00dev
->default_ant
.rx
=
2429 ANTENNA_A
+ rt2x00_get_field16(eeprom
, EEPROM_NIC_RX_FIXED
);
2430 rt2x00dev
->default_ant
.tx
=
2431 ANTENNA_B
- rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_FIXED
);
2433 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_DIVERSITY
))
2434 rt2x00dev
->default_ant
.tx
= ANTENNA_SW_DIVERSITY
;
2435 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_ENABLE_DIVERSITY
))
2436 rt2x00dev
->default_ant
.rx
= ANTENNA_SW_DIVERSITY
;
2440 * Store led settings, for correct led behaviour.
2441 * If the eeprom value is invalid,
2442 * switch to default led mode.
2444 #ifdef CONFIG_RT2X00_LIB_LEDS
2445 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &eeprom
);
2446 value
= rt2x00_get_field16(eeprom
, EEPROM_LED_LED_MODE
);
2448 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2449 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2450 if (value
== LED_MODE_SIGNAL_STRENGTH
)
2451 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
2454 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_LED_MODE
, value
);
2455 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_0
,
2456 rt2x00_get_field16(eeprom
,
2457 EEPROM_LED_POLARITY_GPIO_0
));
2458 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_1
,
2459 rt2x00_get_field16(eeprom
,
2460 EEPROM_LED_POLARITY_GPIO_1
));
2461 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_2
,
2462 rt2x00_get_field16(eeprom
,
2463 EEPROM_LED_POLARITY_GPIO_2
));
2464 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_3
,
2465 rt2x00_get_field16(eeprom
,
2466 EEPROM_LED_POLARITY_GPIO_3
));
2467 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_4
,
2468 rt2x00_get_field16(eeprom
,
2469 EEPROM_LED_POLARITY_GPIO_4
));
2470 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_ACT
,
2471 rt2x00_get_field16(eeprom
, EEPROM_LED_POLARITY_ACT
));
2472 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_BG
,
2473 rt2x00_get_field16(eeprom
,
2474 EEPROM_LED_POLARITY_RDY_G
));
2475 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_A
,
2476 rt2x00_get_field16(eeprom
,
2477 EEPROM_LED_POLARITY_RDY_A
));
2478 #endif /* CONFIG_RT2X00_LIB_LEDS */
2484 * RF value list for RF5225 & RF5325
2485 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2487 static const struct rf_channel rf_vals_noseq
[] = {
2488 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2489 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2490 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2491 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2492 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2493 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2494 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2495 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2496 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2497 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2498 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2499 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2500 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2501 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2503 /* 802.11 UNI / HyperLan 2 */
2504 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2505 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2506 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2507 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2508 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2509 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2510 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2511 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2513 /* 802.11 HyperLan 2 */
2514 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2515 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2516 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2517 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2518 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2519 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2520 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2521 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2522 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2523 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2526 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2527 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2528 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2529 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2530 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2531 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2533 /* MMAC(Japan)J52 ch 34,38,42,46 */
2534 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2535 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2536 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2537 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2541 * RF value list for RF5225 & RF5325
2542 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2544 static const struct rf_channel rf_vals_seq
[] = {
2545 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2546 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2547 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2548 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2549 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2550 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2551 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2552 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2553 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2554 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2555 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2556 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2557 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2558 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2560 /* 802.11 UNI / HyperLan 2 */
2561 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2562 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2563 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2564 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2565 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2566 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2567 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2568 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2570 /* 802.11 HyperLan 2 */
2571 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2572 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2573 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2574 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2575 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2576 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2577 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2578 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2579 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2580 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2583 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2584 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2585 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2586 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2587 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2588 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2590 /* MMAC(Japan)J52 ch 34,38,42,46 */
2591 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2592 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2593 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2594 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2597 static int rt61pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2599 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2600 struct channel_info
*info
;
2605 * Disable powersaving as default.
2607 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
2610 * Initialize all hw fields.
2612 rt2x00dev
->hw
->flags
=
2613 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2614 IEEE80211_HW_SIGNAL_DBM
|
2615 IEEE80211_HW_SUPPORTS_PS
|
2616 IEEE80211_HW_PS_NULLFUNC_STACK
;
2618 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2619 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2620 rt2x00_eeprom_addr(rt2x00dev
,
2621 EEPROM_MAC_ADDR_0
));
2624 * As rt61 has a global fallback table we cannot specify
2625 * more then one tx rate per frame but since the hw will
2626 * try several rates (based on the fallback table) we should
2627 * still initialize max_rates to the maximum number of rates
2628 * we are going to try. Otherwise mac80211 will truncate our
2629 * reported tx rates and the rc algortihm will end up with
2632 rt2x00dev
->hw
->max_rates
= 7;
2633 rt2x00dev
->hw
->max_rate_tries
= 1;
2636 * Initialize hw_mode information.
2638 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2639 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2641 if (!test_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
)) {
2642 spec
->num_channels
= 14;
2643 spec
->channels
= rf_vals_noseq
;
2645 spec
->num_channels
= 14;
2646 spec
->channels
= rf_vals_seq
;
2649 if (rt2x00_rf(rt2x00dev
, RF5225
) || rt2x00_rf(rt2x00dev
, RF5325
)) {
2650 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2651 spec
->num_channels
= ARRAY_SIZE(rf_vals_seq
);
2655 * Create channel information array
2657 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
2661 spec
->channels_info
= info
;
2663 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_G_START
);
2664 for (i
= 0; i
< 14; i
++)
2665 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2667 if (spec
->num_channels
> 14) {
2668 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A_START
);
2669 for (i
= 14; i
< spec
->num_channels
; i
++)
2670 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2676 static int rt61pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
2681 * Disable power saving.
2683 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000007);
2686 * Allocate eeprom data.
2688 retval
= rt61pci_validate_eeprom(rt2x00dev
);
2692 retval
= rt61pci_init_eeprom(rt2x00dev
);
2697 * Initialize hw specifications.
2699 retval
= rt61pci_probe_hw_mode(rt2x00dev
);
2704 * This device has multiple filters for control frames,
2705 * but has no a separate filter for PS Poll frames.
2707 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS
, &rt2x00dev
->flags
);
2710 * This device requires firmware and DMA mapped skbs.
2712 __set_bit(DRIVER_REQUIRE_FIRMWARE
, &rt2x00dev
->flags
);
2713 __set_bit(DRIVER_REQUIRE_DMA
, &rt2x00dev
->flags
);
2714 if (!modparam_nohwcrypt
)
2715 __set_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
);
2716 __set_bit(DRIVER_SUPPORT_LINK_TUNING
, &rt2x00dev
->flags
);
2719 * Set the rssi offset.
2721 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
2727 * IEEE80211 stack callback functions.
2729 static int rt61pci_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
2730 const struct ieee80211_tx_queue_params
*params
)
2732 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2733 struct data_queue
*queue
;
2734 struct rt2x00_field32 field
;
2740 * First pass the configuration through rt2x00lib, that will
2741 * update the queue settings and validate the input. After that
2742 * we are free to update the registers based on the value
2743 * in the queue parameter.
2745 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
2750 * We only need to perform additional register initialization
2756 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
2758 /* Update WMM TXOP register */
2759 offset
= AC_TXOP_CSR0
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
2760 field
.bit_offset
= (queue_idx
& 1) * 16;
2761 field
.bit_mask
= 0xffff << field
.bit_offset
;
2763 rt2x00pci_register_read(rt2x00dev
, offset
, ®
);
2764 rt2x00_set_field32(®
, field
, queue
->txop
);
2765 rt2x00pci_register_write(rt2x00dev
, offset
, reg
);
2767 /* Update WMM registers */
2768 field
.bit_offset
= queue_idx
* 4;
2769 field
.bit_mask
= 0xf << field
.bit_offset
;
2771 rt2x00pci_register_read(rt2x00dev
, AIFSN_CSR
, ®
);
2772 rt2x00_set_field32(®
, field
, queue
->aifs
);
2773 rt2x00pci_register_write(rt2x00dev
, AIFSN_CSR
, reg
);
2775 rt2x00pci_register_read(rt2x00dev
, CWMIN_CSR
, ®
);
2776 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2777 rt2x00pci_register_write(rt2x00dev
, CWMIN_CSR
, reg
);
2779 rt2x00pci_register_read(rt2x00dev
, CWMAX_CSR
, ®
);
2780 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2781 rt2x00pci_register_write(rt2x00dev
, CWMAX_CSR
, reg
);
2786 static u64
rt61pci_get_tsf(struct ieee80211_hw
*hw
)
2788 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2792 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR13
, ®
);
2793 tsf
= (u64
) rt2x00_get_field32(reg
, TXRX_CSR13_HIGH_TSFTIMER
) << 32;
2794 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR12
, ®
);
2795 tsf
|= rt2x00_get_field32(reg
, TXRX_CSR12_LOW_TSFTIMER
);
2800 static const struct ieee80211_ops rt61pci_mac80211_ops
= {
2802 .start
= rt2x00mac_start
,
2803 .stop
= rt2x00mac_stop
,
2804 .add_interface
= rt2x00mac_add_interface
,
2805 .remove_interface
= rt2x00mac_remove_interface
,
2806 .config
= rt2x00mac_config
,
2807 .configure_filter
= rt2x00mac_configure_filter
,
2808 .set_key
= rt2x00mac_set_key
,
2809 .sw_scan_start
= rt2x00mac_sw_scan_start
,
2810 .sw_scan_complete
= rt2x00mac_sw_scan_complete
,
2811 .get_stats
= rt2x00mac_get_stats
,
2812 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2813 .conf_tx
= rt61pci_conf_tx
,
2814 .get_tsf
= rt61pci_get_tsf
,
2815 .rfkill_poll
= rt2x00mac_rfkill_poll
,
2818 static const struct rt2x00lib_ops rt61pci_rt2x00_ops
= {
2819 .irq_handler
= rt61pci_interrupt
,
2820 .irq_handler_thread
= rt61pci_interrupt_thread
,
2821 .probe_hw
= rt61pci_probe_hw
,
2822 .get_firmware_name
= rt61pci_get_firmware_name
,
2823 .check_firmware
= rt61pci_check_firmware
,
2824 .load_firmware
= rt61pci_load_firmware
,
2825 .initialize
= rt2x00pci_initialize
,
2826 .uninitialize
= rt2x00pci_uninitialize
,
2827 .get_entry_state
= rt61pci_get_entry_state
,
2828 .clear_entry
= rt61pci_clear_entry
,
2829 .set_device_state
= rt61pci_set_device_state
,
2830 .rfkill_poll
= rt61pci_rfkill_poll
,
2831 .link_stats
= rt61pci_link_stats
,
2832 .reset_tuner
= rt61pci_reset_tuner
,
2833 .link_tuner
= rt61pci_link_tuner
,
2834 .write_tx_desc
= rt61pci_write_tx_desc
,
2835 .write_beacon
= rt61pci_write_beacon
,
2836 .kick_tx_queue
= rt61pci_kick_tx_queue
,
2837 .kill_tx_queue
= rt61pci_kill_tx_queue
,
2838 .fill_rxdone
= rt61pci_fill_rxdone
,
2839 .config_shared_key
= rt61pci_config_shared_key
,
2840 .config_pairwise_key
= rt61pci_config_pairwise_key
,
2841 .config_filter
= rt61pci_config_filter
,
2842 .config_intf
= rt61pci_config_intf
,
2843 .config_erp
= rt61pci_config_erp
,
2844 .config_ant
= rt61pci_config_ant
,
2845 .config
= rt61pci_config
,
2848 static const struct data_queue_desc rt61pci_queue_rx
= {
2849 .entry_num
= RX_ENTRIES
,
2850 .data_size
= DATA_FRAME_SIZE
,
2851 .desc_size
= RXD_DESC_SIZE
,
2852 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2855 static const struct data_queue_desc rt61pci_queue_tx
= {
2856 .entry_num
= TX_ENTRIES
,
2857 .data_size
= DATA_FRAME_SIZE
,
2858 .desc_size
= TXD_DESC_SIZE
,
2859 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2862 static const struct data_queue_desc rt61pci_queue_bcn
= {
2863 .entry_num
= 4 * BEACON_ENTRIES
,
2864 .data_size
= 0, /* No DMA required for beacons */
2865 .desc_size
= TXINFO_SIZE
,
2866 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2869 static const struct rt2x00_ops rt61pci_ops
= {
2870 .name
= KBUILD_MODNAME
,
2873 .eeprom_size
= EEPROM_SIZE
,
2875 .tx_queues
= NUM_TX_QUEUES
,
2876 .extra_tx_headroom
= 0,
2877 .rx
= &rt61pci_queue_rx
,
2878 .tx
= &rt61pci_queue_tx
,
2879 .bcn
= &rt61pci_queue_bcn
,
2880 .lib
= &rt61pci_rt2x00_ops
,
2881 .hw
= &rt61pci_mac80211_ops
,
2882 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2883 .debugfs
= &rt61pci_rt2x00debug
,
2884 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2888 * RT61pci module information.
2890 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table
) = {
2892 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops
) },
2894 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops
) },
2896 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops
) },
2900 MODULE_AUTHOR(DRV_PROJECT
);
2901 MODULE_VERSION(DRV_VERSION
);
2902 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2903 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2904 "PCI & PCMCIA chipset based cards");
2905 MODULE_DEVICE_TABLE(pci
, rt61pci_device_table
);
2906 MODULE_FIRMWARE(FIRMWARE_RT2561
);
2907 MODULE_FIRMWARE(FIRMWARE_RT2561s
);
2908 MODULE_FIRMWARE(FIRMWARE_RT2661
);
2909 MODULE_LICENSE("GPL");
2911 static struct pci_driver rt61pci_driver
= {
2912 .name
= KBUILD_MODNAME
,
2913 .id_table
= rt61pci_device_table
,
2914 .probe
= rt2x00pci_probe
,
2915 .remove
= __devexit_p(rt2x00pci_remove
),
2916 .suspend
= rt2x00pci_suspend
,
2917 .resume
= rt2x00pci_resume
,
2920 static int __init
rt61pci_init(void)
2922 return pci_register_driver(&rt61pci_driver
);
2925 static void __exit
rt61pci_exit(void)
2927 pci_unregister_driver(&rt61pci_driver
);
2930 module_init(rt61pci_init
);
2931 module_exit(rt61pci_exit
);