2 * ahci.c - AHCI SATA support
4 * Copyright 2004 Red Hat, Inc.
6 * The contents of this file are subject to the Open
7 * Software License version 1.1 that can be found at
8 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
11 * Alternatively, the contents of this file may be used under the terms
12 * of the GNU General Public License version 2 (the "GPL") as distributed
13 * in the kernel source COPYING file, in which case the provisions of
14 * the GPL are applicable instead of the above. If you wish to allow
15 * the use of your version of this file only under the terms of the
16 * GPL and not to allow others to use your version of this file under
17 * the OSL, indicate your decision by deleting the provisions above and
18 * replace them with the notice and other provisions required by the GPL.
19 * If you do not delete the provisions above, a recipient may use your
20 * version of this file under either the OSL or the GPL.
22 * Version 1.0 of the AHCI specification:
23 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
35 #include <linux/dma-mapping.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
41 #define DRV_NAME "ahci"
42 #define DRV_VERSION "1.01"
47 AHCI_MAX_SG
= 168, /* hardware max is 64K */
48 AHCI_DMA_BOUNDARY
= 0xffffffff,
49 AHCI_USE_CLUSTERING
= 0,
50 AHCI_CMD_SLOT_SZ
= 32 * 32,
52 AHCI_CMD_TBL_HDR
= 0x80,
53 AHCI_CMD_TBL_CDB
= 0x40,
54 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR
+ (AHCI_MAX_SG
* 16),
55 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_SZ
+
57 AHCI_IRQ_ON_SG
= (1 << 31),
58 AHCI_CMD_ATAPI
= (1 << 5),
59 AHCI_CMD_WRITE
= (1 << 6),
61 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
65 /* global controller registers */
66 HOST_CAP
= 0x00, /* host capabilities */
67 HOST_CTL
= 0x04, /* global host control */
68 HOST_IRQ_STAT
= 0x08, /* interrupt status */
69 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
70 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
73 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
74 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
75 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
78 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
80 /* registers for each SATA port */
81 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
82 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
83 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
84 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
85 PORT_IRQ_STAT
= 0x10, /* interrupt status */
86 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
87 PORT_CMD
= 0x18, /* port command */
88 PORT_TFDATA
= 0x20, /* taskfile data */
89 PORT_SIG
= 0x24, /* device TF signature */
90 PORT_CMD_ISSUE
= 0x38, /* command issue */
91 PORT_SCR
= 0x28, /* SATA phy register block */
92 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
93 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
94 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
95 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
97 /* PORT_IRQ_{STAT,MASK} bits */
98 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
99 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
100 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
101 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
102 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
103 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
104 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
105 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
107 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
108 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
109 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
110 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
111 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
112 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
113 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
114 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
115 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
117 PORT_IRQ_FATAL
= PORT_IRQ_TF_ERR
|
119 PORT_IRQ_HBUS_DATA_ERR
|
121 DEF_PORT_IRQ
= PORT_IRQ_FATAL
| PORT_IRQ_PHYRDY
|
122 PORT_IRQ_CONNECT
| PORT_IRQ_SG_DONE
|
123 PORT_IRQ_UNK_FIS
| PORT_IRQ_SDB_FIS
|
124 PORT_IRQ_DMAS_FIS
| PORT_IRQ_PIOS_FIS
|
125 PORT_IRQ_D2H_REG_FIS
,
128 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
129 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
130 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
131 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
132 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
133 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
135 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
136 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
137 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
139 /* hpriv->flags bits */
140 AHCI_FLAG_MSI
= (1 << 0),
143 struct ahci_cmd_hdr
{
158 struct ahci_host_priv
{
160 u32 cap
; /* cache of HOST_CAP register */
161 u32 port_map
; /* cache of HOST_PORTS_IMPL reg */
164 struct ahci_port_priv
{
165 struct ahci_cmd_hdr
*cmd_slot
;
166 dma_addr_t cmd_slot_dma
;
168 dma_addr_t cmd_tbl_dma
;
169 struct ahci_sg
*cmd_tbl_sg
;
171 dma_addr_t rx_fis_dma
;
174 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
175 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
176 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
177 static int ahci_qc_issue(struct ata_queued_cmd
*qc
);
178 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
179 static void ahci_phy_reset(struct ata_port
*ap
);
180 static void ahci_irq_clear(struct ata_port
*ap
);
181 static void ahci_eng_timeout(struct ata_port
*ap
);
182 static int ahci_port_start(struct ata_port
*ap
);
183 static void ahci_port_stop(struct ata_port
*ap
);
184 static void ahci_host_stop(struct ata_host_set
*host_set
);
185 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
186 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
187 static u8
ahci_check_status(struct ata_port
*ap
);
188 static u8
ahci_check_err(struct ata_port
*ap
);
189 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
);
190 static void ahci_remove_one (struct pci_dev
*pdev
);
192 static Scsi_Host_Template ahci_sht
= {
193 .module
= THIS_MODULE
,
195 .ioctl
= ata_scsi_ioctl
,
196 .queuecommand
= ata_scsi_queuecmd
,
197 .eh_strategy_handler
= ata_scsi_error
,
198 .can_queue
= ATA_DEF_QUEUE
,
199 .this_id
= ATA_SHT_THIS_ID
,
200 .sg_tablesize
= AHCI_MAX_SG
,
201 .max_sectors
= ATA_MAX_SECTORS
,
202 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
203 .emulated
= ATA_SHT_EMULATED
,
204 .use_clustering
= AHCI_USE_CLUSTERING
,
205 .proc_name
= DRV_NAME
,
206 .dma_boundary
= AHCI_DMA_BOUNDARY
,
207 .slave_configure
= ata_scsi_slave_config
,
208 .bios_param
= ata_std_bios_param
,
212 static struct ata_port_operations ahci_ops
= {
213 .port_disable
= ata_port_disable
,
215 .check_status
= ahci_check_status
,
216 .check_altstatus
= ahci_check_status
,
217 .check_err
= ahci_check_err
,
218 .dev_select
= ata_noop_dev_select
,
220 .tf_read
= ahci_tf_read
,
222 .phy_reset
= ahci_phy_reset
,
224 .qc_prep
= ahci_qc_prep
,
225 .qc_issue
= ahci_qc_issue
,
227 .eng_timeout
= ahci_eng_timeout
,
229 .irq_handler
= ahci_interrupt
,
230 .irq_clear
= ahci_irq_clear
,
232 .scr_read
= ahci_scr_read
,
233 .scr_write
= ahci_scr_write
,
235 .port_start
= ahci_port_start
,
236 .port_stop
= ahci_port_stop
,
237 .host_stop
= ahci_host_stop
,
240 static struct ata_port_info ahci_port_info
[] = {
244 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
245 ATA_FLAG_SATA_RESET
| ATA_FLAG_MMIO
|
247 .pio_mask
= 0x03, /* pio3-4 */
248 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
249 .port_ops
= &ahci_ops
,
253 static struct pci_device_id ahci_pci_tbl
[] = {
254 { PCI_VENDOR_ID_INTEL
, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
255 board_ahci
}, /* ICH6 */
256 { PCI_VENDOR_ID_INTEL
, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
257 board_ahci
}, /* ICH6M */
258 { PCI_VENDOR_ID_INTEL
, 0x27c1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
259 board_ahci
}, /* ICH7 */
260 { PCI_VENDOR_ID_INTEL
, 0x27c5, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
261 board_ahci
}, /* ICH7M */
262 { PCI_VENDOR_ID_INTEL
, 0x27c3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
263 board_ahci
}, /* ICH7R */
264 { PCI_VENDOR_ID_AL
, 0x5288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
265 board_ahci
}, /* ULi M5288 */
266 { PCI_VENDOR_ID_INTEL
, 0x2681, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
267 board_ahci
}, /* ESB2 */
268 { PCI_VENDOR_ID_INTEL
, 0x2682, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
269 board_ahci
}, /* ESB2 */
270 { PCI_VENDOR_ID_INTEL
, 0x2683, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
271 board_ahci
}, /* ESB2 */
272 { PCI_VENDOR_ID_INTEL
, 0x27c6, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
273 board_ahci
}, /* ICH7-M DH */
274 { } /* terminate list */
278 static struct pci_driver ahci_pci_driver
= {
280 .id_table
= ahci_pci_tbl
,
281 .probe
= ahci_init_one
,
282 .remove
= ahci_remove_one
,
286 static inline unsigned long ahci_port_base_ul (unsigned long base
, unsigned int port
)
288 return base
+ 0x100 + (port
* 0x80);
291 static inline void *ahci_port_base (void *base
, unsigned int port
)
293 return (void *) ahci_port_base_ul((unsigned long)base
, port
);
296 static void ahci_host_stop(struct ata_host_set
*host_set
)
298 struct ahci_host_priv
*hpriv
= host_set
->private_data
;
301 ata_host_stop(host_set
);
304 static int ahci_port_start(struct ata_port
*ap
)
306 struct device
*dev
= ap
->host_set
->dev
;
307 struct ahci_host_priv
*hpriv
= ap
->host_set
->private_data
;
308 struct ahci_port_priv
*pp
;
309 void *mem
, *mmio
= ap
->host_set
->mmio_base
;
310 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
313 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
316 memset(pp
, 0, sizeof(*pp
));
318 mem
= dma_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
, GFP_KERNEL
);
323 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
326 * First item in chunk of DMA memory: 32-slot command table,
327 * 32 bytes each in size
330 pp
->cmd_slot_dma
= mem_dma
;
332 mem
+= AHCI_CMD_SLOT_SZ
;
333 mem_dma
+= AHCI_CMD_SLOT_SZ
;
336 * Second item: Received-FIS area
339 pp
->rx_fis_dma
= mem_dma
;
341 mem
+= AHCI_RX_FIS_SZ
;
342 mem_dma
+= AHCI_RX_FIS_SZ
;
345 * Third item: data area for storing a single command
346 * and its scatter-gather table
349 pp
->cmd_tbl_dma
= mem_dma
;
351 pp
->cmd_tbl_sg
= mem
+ AHCI_CMD_TBL_HDR
;
353 ap
->private_data
= pp
;
355 if (hpriv
->cap
& HOST_CAP_64
)
356 writel((pp
->cmd_slot_dma
>> 16) >> 16, port_mmio
+ PORT_LST_ADDR_HI
);
357 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
358 readl(port_mmio
+ PORT_LST_ADDR
); /* flush */
360 if (hpriv
->cap
& HOST_CAP_64
)
361 writel((pp
->rx_fis_dma
>> 16) >> 16, port_mmio
+ PORT_FIS_ADDR_HI
);
362 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
363 readl(port_mmio
+ PORT_FIS_ADDR
); /* flush */
365 writel(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
366 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
367 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
368 readl(port_mmio
+ PORT_CMD
); /* flush */
374 static void ahci_port_stop(struct ata_port
*ap
)
376 struct device
*dev
= ap
->host_set
->dev
;
377 struct ahci_port_priv
*pp
= ap
->private_data
;
378 void *mmio
= ap
->host_set
->mmio_base
;
379 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
382 tmp
= readl(port_mmio
+ PORT_CMD
);
383 tmp
&= ~(PORT_CMD_START
| PORT_CMD_FIS_RX
);
384 writel(tmp
, port_mmio
+ PORT_CMD
);
385 readl(port_mmio
+ PORT_CMD
); /* flush */
387 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
388 * this is slightly incorrect.
392 ap
->private_data
= NULL
;
393 dma_free_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
,
394 pp
->cmd_slot
, pp
->cmd_slot_dma
);
398 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
403 case SCR_STATUS
: sc_reg
= 0; break;
404 case SCR_CONTROL
: sc_reg
= 1; break;
405 case SCR_ERROR
: sc_reg
= 2; break;
406 case SCR_ACTIVE
: sc_reg
= 3; break;
411 return readl((void *) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
415 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
421 case SCR_STATUS
: sc_reg
= 0; break;
422 case SCR_CONTROL
: sc_reg
= 1; break;
423 case SCR_ERROR
: sc_reg
= 2; break;
424 case SCR_ACTIVE
: sc_reg
= 3; break;
429 writel(val
, (void *) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
432 static void ahci_phy_reset(struct ata_port
*ap
)
434 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
435 struct ata_taskfile tf
;
436 struct ata_device
*dev
= &ap
->device
[0];
439 __sata_phy_reset(ap
);
441 if (ap
->flags
& ATA_FLAG_PORT_DISABLED
)
444 tmp
= readl(port_mmio
+ PORT_SIG
);
445 tf
.lbah
= (tmp
>> 24) & 0xff;
446 tf
.lbam
= (tmp
>> 16) & 0xff;
447 tf
.lbal
= (tmp
>> 8) & 0xff;
448 tf
.nsect
= (tmp
) & 0xff;
450 dev
->class = ata_dev_classify(&tf
);
451 if (!ata_dev_present(dev
))
452 ata_port_disable(ap
);
455 static u8
ahci_check_status(struct ata_port
*ap
)
457 void *mmio
= (void *) ap
->ioaddr
.cmd_addr
;
459 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
462 static u8
ahci_check_err(struct ata_port
*ap
)
464 void *mmio
= (void *) ap
->ioaddr
.cmd_addr
;
466 return (readl(mmio
+ PORT_TFDATA
) >> 8) & 0xFF;
469 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
471 struct ahci_port_priv
*pp
= ap
->private_data
;
472 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
474 ata_tf_from_fis(d2h_fis
, tf
);
477 static void ahci_fill_sg(struct ata_queued_cmd
*qc
)
479 struct ahci_port_priv
*pp
= qc
->ap
->private_data
;
485 * Next, the S/G list.
487 for (i
= 0; i
< qc
->n_elem
; i
++) {
491 addr
= sg_dma_address(&qc
->sg
[i
]);
492 sg_len
= sg_dma_len(&qc
->sg
[i
]);
494 pp
->cmd_tbl_sg
[i
].addr
= cpu_to_le32(addr
& 0xffffffff);
495 pp
->cmd_tbl_sg
[i
].addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
496 pp
->cmd_tbl_sg
[i
].flags_size
= cpu_to_le32(sg_len
- 1);
500 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
502 struct ata_port
*ap
= qc
->ap
;
503 struct ahci_port_priv
*pp
= ap
->private_data
;
505 const u32 cmd_fis_len
= 5; /* five dwords */
508 * Fill in command slot information (currently only one slot,
509 * slot 0, is currently since we don't do queueing)
512 opts
= (qc
->n_elem
<< 16) | cmd_fis_len
;
513 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
514 opts
|= AHCI_CMD_WRITE
;
515 if (is_atapi_taskfile(&qc
->tf
))
516 opts
|= AHCI_CMD_ATAPI
;
518 pp
->cmd_slot
[0].opts
= cpu_to_le32(opts
);
519 pp
->cmd_slot
[0].status
= 0;
520 pp
->cmd_slot
[0].tbl_addr
= cpu_to_le32(pp
->cmd_tbl_dma
& 0xffffffff);
521 pp
->cmd_slot
[0].tbl_addr_hi
= cpu_to_le32((pp
->cmd_tbl_dma
>> 16) >> 16);
524 * Fill in command table information. First, the header,
525 * a SATA Register - Host to Device command FIS.
527 ata_tf_to_fis(&qc
->tf
, pp
->cmd_tbl
, 0);
528 if (opts
& AHCI_CMD_ATAPI
) {
529 memset(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
530 memcpy(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, ap
->cdb_len
);
533 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
539 static void ahci_intr_error(struct ata_port
*ap
, u32 irq_stat
)
541 void *mmio
= ap
->host_set
->mmio_base
;
542 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
547 tmp
= readl(port_mmio
+ PORT_CMD
);
548 tmp
&= ~PORT_CMD_START
;
549 writel(tmp
, port_mmio
+ PORT_CMD
);
551 /* wait for engine to stop. TODO: this could be
552 * as long as 500 msec
556 tmp
= readl(port_mmio
+ PORT_CMD
);
557 if ((tmp
& PORT_CMD_LIST_ON
) == 0)
562 /* clear SATA phy error, if any */
563 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
564 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
566 /* if DRQ/BSY is set, device needs to be reset.
567 * if so, issue COMRESET
569 tmp
= readl(port_mmio
+ PORT_TFDATA
);
570 if (tmp
& (ATA_BUSY
| ATA_DRQ
)) {
571 writel(0x301, port_mmio
+ PORT_SCR_CTL
);
572 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
574 writel(0x300, port_mmio
+ PORT_SCR_CTL
);
575 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
579 tmp
= readl(port_mmio
+ PORT_CMD
);
580 tmp
|= PORT_CMD_START
;
581 writel(tmp
, port_mmio
+ PORT_CMD
);
582 readl(port_mmio
+ PORT_CMD
); /* flush */
584 printk(KERN_WARNING
"ata%u: error occurred, port reset\n", ap
->id
);
587 static void ahci_eng_timeout(struct ata_port
*ap
)
589 struct ata_host_set
*host_set
= ap
->host_set
;
590 void *mmio
= host_set
->mmio_base
;
591 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
592 struct ata_queued_cmd
*qc
;
597 spin_lock_irqsave(&host_set
->lock
, flags
);
599 ahci_intr_error(ap
, readl(port_mmio
+ PORT_IRQ_STAT
));
601 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
603 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
606 /* hack alert! We cannot use the supplied completion
607 * function from inside the ->eh_strategy_handler() thread.
608 * libata is the only user of ->eh_strategy_handler() in
609 * any kernel, so the default scsi_done() assumes it is
610 * not being called from the SCSI EH.
612 qc
->scsidone
= scsi_finish_command
;
613 ata_qc_complete(qc
, ATA_ERR
);
616 spin_unlock_irqrestore(&host_set
->lock
, flags
);
619 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
)
621 void *mmio
= ap
->host_set
->mmio_base
;
622 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
623 u32 status
, serr
, ci
;
625 serr
= readl(port_mmio
+ PORT_SCR_ERR
);
626 writel(serr
, port_mmio
+ PORT_SCR_ERR
);
628 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
629 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
631 ci
= readl(port_mmio
+ PORT_CMD_ISSUE
);
632 if (likely((ci
& 0x1) == 0)) {
634 ata_qc_complete(qc
, 0);
639 if (status
& PORT_IRQ_FATAL
) {
640 ahci_intr_error(ap
, status
);
642 ata_qc_complete(qc
, ATA_ERR
);
648 static void ahci_irq_clear(struct ata_port
*ap
)
653 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
655 struct ata_host_set
*host_set
= dev_instance
;
656 struct ahci_host_priv
*hpriv
;
657 unsigned int i
, handled
= 0;
659 u32 irq_stat
, irq_ack
= 0;
663 hpriv
= host_set
->private_data
;
664 mmio
= host_set
->mmio_base
;
666 /* sigh. 0xffffffff is a valid return from h/w */
667 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
668 irq_stat
&= hpriv
->port_map
;
672 spin_lock(&host_set
->lock
);
674 for (i
= 0; i
< host_set
->n_ports
; i
++) {
678 VPRINTK("port %u\n", i
);
679 ap
= host_set
->ports
[i
];
680 tmp
= irq_stat
& (1 << i
);
682 struct ata_queued_cmd
*qc
;
683 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
684 if (ahci_host_intr(ap
, qc
))
690 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
694 spin_unlock(&host_set
->lock
);
698 return IRQ_RETVAL(handled
);
701 static int ahci_qc_issue(struct ata_queued_cmd
*qc
)
703 struct ata_port
*ap
= qc
->ap
;
704 void *port_mmio
= (void *) ap
->ioaddr
.cmd_addr
;
706 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
707 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
712 static void ahci_setup_port(struct ata_ioports
*port
, unsigned long base
,
713 unsigned int port_idx
)
715 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base
, port_idx
);
716 base
= ahci_port_base_ul(base
, port_idx
);
717 VPRINTK("base now==0x%lx\n", base
);
719 port
->cmd_addr
= base
;
720 port
->scr_addr
= base
+ PORT_SCR
;
725 static int ahci_host_init(struct ata_probe_ent
*probe_ent
)
727 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
728 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
729 void __iomem
*mmio
= probe_ent
->mmio_base
;
732 unsigned int i
, j
, using_dac
;
734 void __iomem
*port_mmio
;
736 cap_save
= readl(mmio
+ HOST_CAP
);
737 cap_save
&= ( (1<<28) | (1<<17) );
738 cap_save
|= (1 << 27);
740 /* global controller reset */
741 tmp
= readl(mmio
+ HOST_CTL
);
742 if ((tmp
& HOST_RESET
) == 0) {
743 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
744 readl(mmio
+ HOST_CTL
); /* flush */
747 /* reset must complete within 1 second, or
748 * the hardware should be considered fried.
752 tmp
= readl(mmio
+ HOST_CTL
);
753 if (tmp
& HOST_RESET
) {
754 printk(KERN_ERR DRV_NAME
"(%s): controller reset failed (0x%x)\n",
755 pci_name(pdev
), tmp
);
759 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
760 (void) readl(mmio
+ HOST_CTL
); /* flush */
761 writel(cap_save
, mmio
+ HOST_CAP
);
762 writel(0xf, mmio
+ HOST_PORTS_IMPL
);
763 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
765 pci_read_config_word(pdev
, 0x92, &tmp16
);
767 pci_write_config_word(pdev
, 0x92, tmp16
);
769 hpriv
->cap
= readl(mmio
+ HOST_CAP
);
770 hpriv
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
771 probe_ent
->n_ports
= (hpriv
->cap
& 0x1f) + 1;
773 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
774 hpriv
->cap
, hpriv
->port_map
, probe_ent
->n_ports
);
776 using_dac
= hpriv
->cap
& HOST_CAP_64
;
778 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
779 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
781 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
783 printk(KERN_ERR DRV_NAME
"(%s): 64-bit DMA enable failed\n",
789 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
791 printk(KERN_ERR DRV_NAME
"(%s): 32-bit DMA enable failed\n",
795 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
797 printk(KERN_ERR DRV_NAME
"(%s): 32-bit consistent DMA enable failed\n",
803 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
804 #if 0 /* BIOSen initialize this incorrectly */
805 if (!(hpriv
->port_map
& (1 << i
)))
809 port_mmio
= ahci_port_base(mmio
, i
);
810 VPRINTK("mmio %p port_mmio %p\n", mmio
, port_mmio
);
812 ahci_setup_port(&probe_ent
->port
[i
],
813 (unsigned long) mmio
, i
);
815 /* make sure port is not active */
816 tmp
= readl(port_mmio
+ PORT_CMD
);
817 VPRINTK("PORT_CMD 0x%x\n", tmp
);
818 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
819 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
820 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
821 PORT_CMD_FIS_RX
| PORT_CMD_START
);
822 writel(tmp
, port_mmio
+ PORT_CMD
);
823 readl(port_mmio
+ PORT_CMD
); /* flush */
825 /* spec says 500 msecs for each bit, so
826 * this is slightly incorrect.
831 writel(PORT_CMD_SPIN_UP
, port_mmio
+ PORT_CMD
);
836 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
837 if ((tmp
& 0xf) == 0x3)
842 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
843 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
844 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
846 /* ack any pending irq events for this port */
847 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
848 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
850 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
852 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
854 /* set irq mask (enables interrupts) */
855 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
858 tmp
= readl(mmio
+ HOST_CTL
);
859 VPRINTK("HOST_CTL 0x%x\n", tmp
);
860 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
861 tmp
= readl(mmio
+ HOST_CTL
);
862 VPRINTK("HOST_CTL 0x%x\n", tmp
);
864 pci_set_master(pdev
);
869 /* move to PCI layer, integrate w/ MSI stuff */
870 static void pci_intx(struct pci_dev
*pdev
, int enable
)
872 u16 pci_command
, new;
874 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
877 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
879 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
881 if (new != pci_command
)
882 pci_write_config_word(pdev
, PCI_COMMAND
, pci_command
);
885 static void ahci_print_info(struct ata_probe_ent
*probe_ent
)
887 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
888 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
889 void *mmio
= probe_ent
->mmio_base
;
890 u32 vers
, cap
, impl
, speed
;
895 vers
= readl(mmio
+ HOST_VERSION
);
897 impl
= hpriv
->port_map
;
899 speed
= (cap
>> 20) & 0xf;
907 pci_read_config_word(pdev
, 0x0a, &cc
);
910 else if (cc
== 0x0106)
912 else if (cc
== 0x0104)
917 printk(KERN_INFO DRV_NAME
"(%s) AHCI %02x%02x.%02x%02x "
918 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
927 ((cap
>> 8) & 0x1f) + 1,
933 printk(KERN_INFO DRV_NAME
"(%s) flags: "
939 cap
& (1 << 31) ? "64bit " : "",
940 cap
& (1 << 30) ? "ncq " : "",
941 cap
& (1 << 28) ? "ilck " : "",
942 cap
& (1 << 27) ? "stag " : "",
943 cap
& (1 << 26) ? "pm " : "",
944 cap
& (1 << 25) ? "led " : "",
946 cap
& (1 << 24) ? "clo " : "",
947 cap
& (1 << 19) ? "nz " : "",
948 cap
& (1 << 18) ? "only " : "",
949 cap
& (1 << 17) ? "pmp " : "",
950 cap
& (1 << 15) ? "pio " : "",
951 cap
& (1 << 14) ? "slum " : "",
952 cap
& (1 << 13) ? "part " : ""
956 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
958 static int printed_version
;
959 struct ata_probe_ent
*probe_ent
= NULL
;
960 struct ahci_host_priv
*hpriv
;
963 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
964 int have_msi
, pci_dev_busy
= 0;
969 if (!printed_version
++)
970 printk(KERN_DEBUG DRV_NAME
" version " DRV_VERSION
"\n");
972 rc
= pci_enable_device(pdev
);
976 rc
= pci_request_regions(pdev
, DRV_NAME
);
982 if (pci_enable_msi(pdev
) == 0)
989 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
990 if (probe_ent
== NULL
) {
995 memset(probe_ent
, 0, sizeof(*probe_ent
));
996 probe_ent
->dev
= pci_dev_to_dev(pdev
);
997 INIT_LIST_HEAD(&probe_ent
->node
);
999 mmio_base
= ioremap(pci_resource_start(pdev
, AHCI_PCI_BAR
),
1000 pci_resource_len(pdev
, AHCI_PCI_BAR
));
1001 if (mmio_base
== NULL
) {
1003 goto err_out_free_ent
;
1005 base
= (unsigned long) mmio_base
;
1007 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1010 goto err_out_iounmap
;
1012 memset(hpriv
, 0, sizeof(*hpriv
));
1014 probe_ent
->sht
= ahci_port_info
[board_idx
].sht
;
1015 probe_ent
->host_flags
= ahci_port_info
[board_idx
].host_flags
;
1016 probe_ent
->pio_mask
= ahci_port_info
[board_idx
].pio_mask
;
1017 probe_ent
->udma_mask
= ahci_port_info
[board_idx
].udma_mask
;
1018 probe_ent
->port_ops
= ahci_port_info
[board_idx
].port_ops
;
1020 probe_ent
->irq
= pdev
->irq
;
1021 probe_ent
->irq_flags
= SA_SHIRQ
;
1022 probe_ent
->mmio_base
= mmio_base
;
1023 probe_ent
->private_data
= hpriv
;
1026 hpriv
->flags
|= AHCI_FLAG_MSI
;
1028 /* initialize adapter */
1029 rc
= ahci_host_init(probe_ent
);
1033 ahci_print_info(probe_ent
);
1035 /* FIXME: check ata_device_add return value */
1036 ata_device_add(probe_ent
);
1049 pci_disable_msi(pdev
);
1052 pci_release_regions(pdev
);
1055 pci_disable_device(pdev
);
1059 static void ahci_remove_one (struct pci_dev
*pdev
)
1061 struct device
*dev
= pci_dev_to_dev(pdev
);
1062 struct ata_host_set
*host_set
= dev_get_drvdata(dev
);
1063 struct ahci_host_priv
*hpriv
= host_set
->private_data
;
1064 struct ata_port
*ap
;
1068 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1069 ap
= host_set
->ports
[i
];
1071 scsi_remove_host(ap
->host
);
1074 have_msi
= hpriv
->flags
& AHCI_FLAG_MSI
;
1075 free_irq(host_set
->irq
, host_set
);
1077 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1078 ap
= host_set
->ports
[i
];
1080 ata_scsi_release(ap
->host
);
1081 scsi_host_put(ap
->host
);
1084 host_set
->ops
->host_stop(host_set
);
1088 pci_disable_msi(pdev
);
1091 pci_release_regions(pdev
);
1092 pci_disable_device(pdev
);
1093 dev_set_drvdata(dev
, NULL
);
1096 static int __init
ahci_init(void)
1098 return pci_module_init(&ahci_pci_driver
);
1102 static void __exit
ahci_exit(void)
1104 pci_unregister_driver(&ahci_pci_driver
);
1108 MODULE_AUTHOR("Jeff Garzik");
1109 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1110 MODULE_LICENSE("GPL");
1111 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1112 MODULE_VERSION(DRV_VERSION
);
1114 module_init(ahci_init
);
1115 module_exit(ahci_exit
);