2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_proto.h>
29 #include <asm/amd_iommu_types.h>
30 #include <asm/amd_iommu.h>
31 #include <asm/iommu.h>
33 #include <asm/x86_init.h>
36 * definitions for the ACPI scanning code
38 #define IVRS_HEADER_LENGTH 48
40 #define ACPI_IVHD_TYPE 0x10
41 #define ACPI_IVMD_TYPE_ALL 0x20
42 #define ACPI_IVMD_TYPE 0x21
43 #define ACPI_IVMD_TYPE_RANGE 0x22
45 #define IVHD_DEV_ALL 0x01
46 #define IVHD_DEV_SELECT 0x02
47 #define IVHD_DEV_SELECT_RANGE_START 0x03
48 #define IVHD_DEV_RANGE_END 0x04
49 #define IVHD_DEV_ALIAS 0x42
50 #define IVHD_DEV_ALIAS_RANGE 0x43
51 #define IVHD_DEV_EXT_SELECT 0x46
52 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
54 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
55 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
56 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
57 #define IVHD_FLAG_ISOC_EN_MASK 0x08
59 #define IVMD_FLAG_EXCL_RANGE 0x08
60 #define IVMD_FLAG_UNITY_MAP 0x01
62 #define ACPI_DEVFLAG_INITPASS 0x01
63 #define ACPI_DEVFLAG_EXTINT 0x02
64 #define ACPI_DEVFLAG_NMI 0x04
65 #define ACPI_DEVFLAG_SYSMGT1 0x10
66 #define ACPI_DEVFLAG_SYSMGT2 0x20
67 #define ACPI_DEVFLAG_LINT0 0x40
68 #define ACPI_DEVFLAG_LINT1 0x80
69 #define ACPI_DEVFLAG_ATSDIS 0x10000000
72 * ACPI table definitions
74 * These data structures are laid over the table to parse the important values
79 * structure describing one IOMMU in the ACPI table. Typically followed by one
80 * or more ivhd_entrys.
92 } __attribute__((packed
));
95 * A device entry describing which devices a specific IOMMU translates and
96 * which requestor ids they use.
103 } __attribute__((packed
));
106 * An AMD IOMMU memory definition structure. It defines things like exclusion
107 * ranges for devices and regions that should be unity mapped.
118 } __attribute__((packed
));
122 static int __initdata amd_iommu_detected
;
124 u16 amd_iommu_last_bdf
; /* largest PCI device id we have
126 LIST_HEAD(amd_iommu_unity_map
); /* a list of required unity mappings
128 bool amd_iommu_unmap_flush
; /* if true, flush on every unmap */
130 LIST_HEAD(amd_iommu_list
); /* list of all AMD IOMMUs in the
133 /* Array to assign indices to IOMMUs*/
134 struct amd_iommu
*amd_iommus
[MAX_IOMMUS
];
135 int amd_iommus_present
;
137 /* IOMMUs have a non-present cache? */
138 bool amd_iommu_np_cache __read_mostly
;
141 * List of protection domains - used during resume
143 LIST_HEAD(amd_iommu_pd_list
);
144 spinlock_t amd_iommu_pd_lock
;
147 * Pointer to the device table which is shared by all AMD IOMMUs
148 * it is indexed by the PCI device id or the HT unit id and contains
149 * information about the domain the device belongs to as well as the
150 * page table root pointer.
152 struct dev_table_entry
*amd_iommu_dev_table
;
155 * The alias table is a driver specific data structure which contains the
156 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
157 * More than one device can share the same requestor id.
159 u16
*amd_iommu_alias_table
;
162 * The rlookup table is used to find the IOMMU which is responsible
163 * for a specific device. It is also indexed by the PCI device id.
165 struct amd_iommu
**amd_iommu_rlookup_table
;
168 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
169 * to know which ones are already in use.
171 unsigned long *amd_iommu_pd_alloc_bitmap
;
173 static u32 dev_table_size
; /* size of the device table */
174 static u32 alias_table_size
; /* size of the alias table */
175 static u32 rlookup_table_size
; /* size if the rlookup table */
177 static inline void update_last_devid(u16 devid
)
179 if (devid
> amd_iommu_last_bdf
)
180 amd_iommu_last_bdf
= devid
;
183 static inline unsigned long tbl_size(int entry_size
)
185 unsigned shift
= PAGE_SHIFT
+
186 get_order(((int)amd_iommu_last_bdf
+ 1) * entry_size
);
191 /****************************************************************************
193 * AMD IOMMU MMIO register space handling functions
195 * These functions are used to program the IOMMU device registers in
196 * MMIO space required for that driver.
198 ****************************************************************************/
201 * This function set the exclusion range in the IOMMU. DMA accesses to the
202 * exclusion range are passed through untranslated
204 static void iommu_set_exclusion_range(struct amd_iommu
*iommu
)
206 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
207 u64 limit
= (start
+ iommu
->exclusion_length
) & PAGE_MASK
;
210 if (!iommu
->exclusion_start
)
213 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
214 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
215 &entry
, sizeof(entry
));
218 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
219 &entry
, sizeof(entry
));
222 /* Programs the physical address of the device table into the IOMMU hardware */
223 static void __init
iommu_set_device_table(struct amd_iommu
*iommu
)
227 BUG_ON(iommu
->mmio_base
== NULL
);
229 entry
= virt_to_phys(amd_iommu_dev_table
);
230 entry
|= (dev_table_size
>> 12) - 1;
231 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
232 &entry
, sizeof(entry
));
235 /* Generic functions to enable/disable certain features of the IOMMU. */
236 static void iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
240 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
242 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
245 static void iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
249 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
251 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
254 /* Function to enable the hardware */
255 static void iommu_enable(struct amd_iommu
*iommu
)
257 printk(KERN_INFO
"AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n",
258 dev_name(&iommu
->dev
->dev
), iommu
->cap_ptr
);
260 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
263 static void iommu_disable(struct amd_iommu
*iommu
)
265 /* Disable command buffer */
266 iommu_feature_disable(iommu
, CONTROL_CMDBUF_EN
);
268 /* Disable event logging and event interrupts */
269 iommu_feature_disable(iommu
, CONTROL_EVT_INT_EN
);
270 iommu_feature_disable(iommu
, CONTROL_EVT_LOG_EN
);
272 /* Disable IOMMU hardware itself */
273 iommu_feature_disable(iommu
, CONTROL_IOMMU_EN
);
277 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
278 * the system has one.
280 static u8
* __init
iommu_map_mmio_space(u64 address
)
284 if (!request_mem_region(address
, MMIO_REGION_LENGTH
, "amd_iommu"))
287 ret
= ioremap_nocache(address
, MMIO_REGION_LENGTH
);
291 release_mem_region(address
, MMIO_REGION_LENGTH
);
296 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
298 if (iommu
->mmio_base
)
299 iounmap(iommu
->mmio_base
);
300 release_mem_region(iommu
->mmio_phys
, MMIO_REGION_LENGTH
);
303 /****************************************************************************
305 * The functions below belong to the first pass of AMD IOMMU ACPI table
306 * parsing. In this pass we try to find out the highest device id this
307 * code has to handle. Upon this information the size of the shared data
308 * structures is determined later.
310 ****************************************************************************/
313 * This function calculates the length of a given IVHD entry
315 static inline int ivhd_entry_length(u8
*ivhd
)
317 return 0x04 << (*ivhd
>> 6);
321 * This function reads the last device id the IOMMU has to handle from the PCI
322 * capability header for this IOMMU
324 static int __init
find_last_devid_on_pci(int bus
, int dev
, int fn
, int cap_ptr
)
328 cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
329 update_last_devid(calc_devid(MMIO_GET_BUS(cap
), MMIO_GET_LD(cap
)));
335 * After reading the highest device id from the IOMMU PCI capability header
336 * this function looks if there is a higher device id defined in the ACPI table
338 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
340 u8
*p
= (void *)h
, *end
= (void *)h
;
341 struct ivhd_entry
*dev
;
346 find_last_devid_on_pci(PCI_BUS(h
->devid
),
352 dev
= (struct ivhd_entry
*)p
;
354 case IVHD_DEV_SELECT
:
355 case IVHD_DEV_RANGE_END
:
357 case IVHD_DEV_EXT_SELECT
:
358 /* all the above subfield types refer to device ids */
359 update_last_devid(dev
->devid
);
364 p
+= ivhd_entry_length(p
);
373 * Iterate over all IVHD entries in the ACPI table and find the highest device
374 * id which we need to handle. This is the first of three functions which parse
375 * the ACPI table. So we check the checksum here.
377 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
380 u8 checksum
= 0, *p
= (u8
*)table
, *end
= (u8
*)table
;
381 struct ivhd_header
*h
;
384 * Validate checksum here so we don't need to do it when
385 * we actually parse the table
387 for (i
= 0; i
< table
->length
; ++i
)
390 /* ACPI table corrupt */
393 p
+= IVRS_HEADER_LENGTH
;
395 end
+= table
->length
;
397 h
= (struct ivhd_header
*)p
;
400 find_last_devid_from_ivhd(h
);
412 /****************************************************************************
414 * The following functions belong the the code path which parses the ACPI table
415 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
416 * data structures, initialize the device/alias/rlookup table and also
417 * basically initialize the hardware.
419 ****************************************************************************/
422 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
423 * write commands to that buffer later and the IOMMU will execute them
426 static u8
* __init
alloc_command_buffer(struct amd_iommu
*iommu
)
428 u8
*cmd_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
429 get_order(CMD_BUFFER_SIZE
));
434 iommu
->cmd_buf_size
= CMD_BUFFER_SIZE
;
440 * This function resets the command buffer if the IOMMU stopped fetching
443 void amd_iommu_reset_cmd_buffer(struct amd_iommu
*iommu
)
445 iommu_feature_disable(iommu
, CONTROL_CMDBUF_EN
);
447 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
448 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
450 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
454 * This function writes the command buffer address to the hardware and
457 static void iommu_enable_command_buffer(struct amd_iommu
*iommu
)
461 BUG_ON(iommu
->cmd_buf
== NULL
);
463 entry
= (u64
)virt_to_phys(iommu
->cmd_buf
);
464 entry
|= MMIO_CMD_SIZE_512
;
466 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
467 &entry
, sizeof(entry
));
469 amd_iommu_reset_cmd_buffer(iommu
);
472 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
474 free_pages((unsigned long)iommu
->cmd_buf
,
475 get_order(iommu
->cmd_buf_size
));
478 /* allocates the memory where the IOMMU will log its events to */
479 static u8
* __init
alloc_event_buffer(struct amd_iommu
*iommu
)
481 iommu
->evt_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
482 get_order(EVT_BUFFER_SIZE
));
484 if (iommu
->evt_buf
== NULL
)
487 iommu
->evt_buf_size
= EVT_BUFFER_SIZE
;
489 return iommu
->evt_buf
;
492 static void iommu_enable_event_buffer(struct amd_iommu
*iommu
)
496 BUG_ON(iommu
->evt_buf
== NULL
);
498 entry
= (u64
)virt_to_phys(iommu
->evt_buf
) | EVT_LEN_MASK
;
500 memcpy_toio(iommu
->mmio_base
+ MMIO_EVT_BUF_OFFSET
,
501 &entry
, sizeof(entry
));
503 /* set head and tail to zero manually */
504 writel(0x00, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
505 writel(0x00, iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
507 iommu_feature_enable(iommu
, CONTROL_EVT_LOG_EN
);
510 static void __init
free_event_buffer(struct amd_iommu
*iommu
)
512 free_pages((unsigned long)iommu
->evt_buf
, get_order(EVT_BUFFER_SIZE
));
515 /* sets a specific bit in the device table entry. */
516 static void set_dev_entry_bit(u16 devid
, u8 bit
)
518 int i
= (bit
>> 5) & 0x07;
519 int _bit
= bit
& 0x1f;
521 amd_iommu_dev_table
[devid
].data
[i
] |= (1 << _bit
);
524 static int get_dev_entry_bit(u16 devid
, u8 bit
)
526 int i
= (bit
>> 5) & 0x07;
527 int _bit
= bit
& 0x1f;
529 return (amd_iommu_dev_table
[devid
].data
[i
] & (1 << _bit
)) >> _bit
;
533 void amd_iommu_apply_erratum_63(u16 devid
)
537 sysmgt
= get_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
) |
538 (get_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
) << 1);
541 set_dev_entry_bit(devid
, DEV_ENTRY_IW
);
544 /* Writes the specific IOMMU for a device into the rlookup table */
545 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
547 amd_iommu_rlookup_table
[devid
] = iommu
;
551 * This function takes the device specific flags read from the ACPI
552 * table and sets up the device table entry with that information
554 static void __init
set_dev_entry_from_acpi(struct amd_iommu
*iommu
,
555 u16 devid
, u32 flags
, u32 ext_flags
)
557 if (flags
& ACPI_DEVFLAG_INITPASS
)
558 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
559 if (flags
& ACPI_DEVFLAG_EXTINT
)
560 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
561 if (flags
& ACPI_DEVFLAG_NMI
)
562 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
563 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
564 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
565 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
566 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
567 if (flags
& ACPI_DEVFLAG_LINT0
)
568 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
569 if (flags
& ACPI_DEVFLAG_LINT1
)
570 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
572 amd_iommu_apply_erratum_63(devid
);
574 set_iommu_for_device(iommu
, devid
);
578 * Reads the device exclusion range from ACPI and initialize IOMMU with
581 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
583 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
585 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
590 * We only can configure exclusion ranges per IOMMU, not
591 * per device. But we can enable the exclusion range per
592 * device. This is done here
594 set_dev_entry_bit(m
->devid
, DEV_ENTRY_EX
);
595 iommu
->exclusion_start
= m
->range_start
;
596 iommu
->exclusion_length
= m
->range_length
;
601 * This function reads some important data from the IOMMU PCI space and
602 * initializes the driver data structure with it. It reads the hardware
603 * capabilities and the first/last device entries
605 static void __init
init_iommu_from_pci(struct amd_iommu
*iommu
)
607 int cap_ptr
= iommu
->cap_ptr
;
610 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_CAP_HDR_OFFSET
,
612 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_RANGE_OFFSET
,
614 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_MISC_OFFSET
,
617 iommu
->first_device
= calc_devid(MMIO_GET_BUS(range
),
619 iommu
->last_device
= calc_devid(MMIO_GET_BUS(range
),
621 iommu
->evt_msi_num
= MMIO_MSI_NUM(misc
);
625 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
626 * initializes the hardware and our data structures with it.
628 static void __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
629 struct ivhd_header
*h
)
632 u8
*end
= p
, flags
= 0;
633 u16 dev_i
, devid
= 0, devid_start
= 0, devid_to
= 0;
636 struct ivhd_entry
*e
;
639 * First set the recommended feature enable bits from ACPI
640 * into the IOMMU control registers
642 h
->flags
& IVHD_FLAG_HT_TUN_EN_MASK
?
643 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
644 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
646 h
->flags
& IVHD_FLAG_PASSPW_EN_MASK
?
647 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
648 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
650 h
->flags
& IVHD_FLAG_RESPASSPW_EN_MASK
?
651 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
652 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
654 h
->flags
& IVHD_FLAG_ISOC_EN_MASK
?
655 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
656 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
659 * make IOMMU memory accesses cache coherent
661 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
664 * Done. Now parse the device entries
666 p
+= sizeof(struct ivhd_header
);
671 e
= (struct ivhd_entry
*)p
;
675 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
676 " last device %02x:%02x.%x flags: %02x\n",
677 PCI_BUS(iommu
->first_device
),
678 PCI_SLOT(iommu
->first_device
),
679 PCI_FUNC(iommu
->first_device
),
680 PCI_BUS(iommu
->last_device
),
681 PCI_SLOT(iommu
->last_device
),
682 PCI_FUNC(iommu
->last_device
),
685 for (dev_i
= iommu
->first_device
;
686 dev_i
<= iommu
->last_device
; ++dev_i
)
687 set_dev_entry_from_acpi(iommu
, dev_i
,
690 case IVHD_DEV_SELECT
:
692 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
700 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
702 case IVHD_DEV_SELECT_RANGE_START
:
704 DUMP_printk(" DEV_SELECT_RANGE_START\t "
705 "devid: %02x:%02x.%x flags: %02x\n",
711 devid_start
= e
->devid
;
718 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
719 "flags: %02x devid_to: %02x:%02x.%x\n",
724 PCI_BUS(e
->ext
>> 8),
725 PCI_SLOT(e
->ext
>> 8),
726 PCI_FUNC(e
->ext
>> 8));
729 devid_to
= e
->ext
>> 8;
730 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
731 set_dev_entry_from_acpi(iommu
, devid_to
, e
->flags
, 0);
732 amd_iommu_alias_table
[devid
] = devid_to
;
734 case IVHD_DEV_ALIAS_RANGE
:
736 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
737 "devid: %02x:%02x.%x flags: %02x "
738 "devid_to: %02x:%02x.%x\n",
743 PCI_BUS(e
->ext
>> 8),
744 PCI_SLOT(e
->ext
>> 8),
745 PCI_FUNC(e
->ext
>> 8));
747 devid_start
= e
->devid
;
749 devid_to
= e
->ext
>> 8;
753 case IVHD_DEV_EXT_SELECT
:
755 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
756 "flags: %02x ext: %08x\n",
763 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
,
766 case IVHD_DEV_EXT_SELECT_RANGE
:
768 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
769 "%02x:%02x.%x flags: %02x ext: %08x\n",
775 devid_start
= e
->devid
;
780 case IVHD_DEV_RANGE_END
:
782 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
788 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
790 amd_iommu_alias_table
[dev_i
] = devid_to
;
791 set_dev_entry_from_acpi(iommu
,
792 devid_to
, flags
, ext_flags
);
794 set_dev_entry_from_acpi(iommu
, dev_i
,
802 p
+= ivhd_entry_length(p
);
806 /* Initializes the device->iommu mapping for the driver */
807 static int __init
init_iommu_devices(struct amd_iommu
*iommu
)
811 for (i
= iommu
->first_device
; i
<= iommu
->last_device
; ++i
)
812 set_iommu_for_device(iommu
, i
);
817 static void __init
free_iommu_one(struct amd_iommu
*iommu
)
819 free_command_buffer(iommu
);
820 free_event_buffer(iommu
);
821 iommu_unmap_mmio_space(iommu
);
824 static void __init
free_iommu_all(void)
826 struct amd_iommu
*iommu
, *next
;
828 for_each_iommu_safe(iommu
, next
) {
829 list_del(&iommu
->list
);
830 free_iommu_one(iommu
);
836 * This function clues the initialization function for one IOMMU
837 * together and also allocates the command buffer and programs the
838 * hardware. It does NOT enable the IOMMU. This is done afterwards.
840 static int __init
init_iommu_one(struct amd_iommu
*iommu
, struct ivhd_header
*h
)
842 spin_lock_init(&iommu
->lock
);
844 /* Add IOMMU to internal data structures */
845 list_add_tail(&iommu
->list
, &amd_iommu_list
);
846 iommu
->index
= amd_iommus_present
++;
848 if (unlikely(iommu
->index
>= MAX_IOMMUS
)) {
849 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
853 /* Index is fine - add IOMMU to the array */
854 amd_iommus
[iommu
->index
] = iommu
;
857 * Copy data from ACPI table entry to the iommu struct
859 iommu
->dev
= pci_get_bus_and_slot(PCI_BUS(h
->devid
), h
->devid
& 0xff);
863 iommu
->cap_ptr
= h
->cap_ptr
;
864 iommu
->pci_seg
= h
->pci_seg
;
865 iommu
->mmio_phys
= h
->mmio_phys
;
866 iommu
->mmio_base
= iommu_map_mmio_space(h
->mmio_phys
);
867 if (!iommu
->mmio_base
)
870 iommu
->cmd_buf
= alloc_command_buffer(iommu
);
874 iommu
->evt_buf
= alloc_event_buffer(iommu
);
878 iommu
->int_enabled
= false;
880 init_iommu_from_pci(iommu
);
881 init_iommu_from_acpi(iommu
, h
);
882 init_iommu_devices(iommu
);
884 if (iommu
->cap
& (1UL << IOMMU_CAP_NPCACHE
))
885 amd_iommu_np_cache
= true;
887 return pci_enable_device(iommu
->dev
);
891 * Iterates over all IOMMU entries in the ACPI table, allocates the
892 * IOMMU structure and initializes it with init_iommu_one()
894 static int __init
init_iommu_all(struct acpi_table_header
*table
)
896 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
897 struct ivhd_header
*h
;
898 struct amd_iommu
*iommu
;
901 end
+= table
->length
;
902 p
+= IVRS_HEADER_LENGTH
;
905 h
= (struct ivhd_header
*)p
;
909 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
910 "seg: %d flags: %01x info %04x\n",
911 PCI_BUS(h
->devid
), PCI_SLOT(h
->devid
),
912 PCI_FUNC(h
->devid
), h
->cap_ptr
,
913 h
->pci_seg
, h
->flags
, h
->info
);
914 DUMP_printk(" mmio-addr: %016llx\n",
917 iommu
= kzalloc(sizeof(struct amd_iommu
), GFP_KERNEL
);
920 ret
= init_iommu_one(iommu
, h
);
935 /****************************************************************************
937 * The following functions initialize the MSI interrupts for all IOMMUs
938 * in the system. Its a bit challenging because there could be multiple
939 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
942 ****************************************************************************/
944 static int iommu_setup_msi(struct amd_iommu
*iommu
)
948 if (pci_enable_msi(iommu
->dev
))
951 r
= request_irq(iommu
->dev
->irq
, amd_iommu_int_handler
,
957 pci_disable_msi(iommu
->dev
);
961 iommu
->int_enabled
= true;
962 iommu_feature_enable(iommu
, CONTROL_EVT_INT_EN
);
967 static int iommu_init_msi(struct amd_iommu
*iommu
)
969 if (iommu
->int_enabled
)
972 if (pci_find_capability(iommu
->dev
, PCI_CAP_ID_MSI
))
973 return iommu_setup_msi(iommu
);
978 /****************************************************************************
980 * The next functions belong to the third pass of parsing the ACPI
981 * table. In this last pass the memory mapping requirements are
982 * gathered (like exclusion and unity mapping reanges).
984 ****************************************************************************/
986 static void __init
free_unity_maps(void)
988 struct unity_map_entry
*entry
, *next
;
990 list_for_each_entry_safe(entry
, next
, &amd_iommu_unity_map
, list
) {
991 list_del(&entry
->list
);
996 /* called when we find an exclusion range definition in ACPI */
997 static int __init
init_exclusion_range(struct ivmd_header
*m
)
1002 case ACPI_IVMD_TYPE
:
1003 set_device_exclusion_range(m
->devid
, m
);
1005 case ACPI_IVMD_TYPE_ALL
:
1006 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1007 set_device_exclusion_range(i
, m
);
1009 case ACPI_IVMD_TYPE_RANGE
:
1010 for (i
= m
->devid
; i
<= m
->aux
; ++i
)
1011 set_device_exclusion_range(i
, m
);
1020 /* called for unity map ACPI definition */
1021 static int __init
init_unity_map_range(struct ivmd_header
*m
)
1023 struct unity_map_entry
*e
= 0;
1026 e
= kzalloc(sizeof(*e
), GFP_KERNEL
);
1034 case ACPI_IVMD_TYPE
:
1035 s
= "IVMD_TYPEi\t\t\t";
1036 e
->devid_start
= e
->devid_end
= m
->devid
;
1038 case ACPI_IVMD_TYPE_ALL
:
1039 s
= "IVMD_TYPE_ALL\t\t";
1041 e
->devid_end
= amd_iommu_last_bdf
;
1043 case ACPI_IVMD_TYPE_RANGE
:
1044 s
= "IVMD_TYPE_RANGE\t\t";
1045 e
->devid_start
= m
->devid
;
1046 e
->devid_end
= m
->aux
;
1049 e
->address_start
= PAGE_ALIGN(m
->range_start
);
1050 e
->address_end
= e
->address_start
+ PAGE_ALIGN(m
->range_length
);
1051 e
->prot
= m
->flags
>> 1;
1053 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1054 " range_start: %016llx range_end: %016llx flags: %x\n", s
,
1055 PCI_BUS(e
->devid_start
), PCI_SLOT(e
->devid_start
),
1056 PCI_FUNC(e
->devid_start
), PCI_BUS(e
->devid_end
),
1057 PCI_SLOT(e
->devid_end
), PCI_FUNC(e
->devid_end
),
1058 e
->address_start
, e
->address_end
, m
->flags
);
1060 list_add_tail(&e
->list
, &amd_iommu_unity_map
);
1065 /* iterates over all memory definitions we find in the ACPI table */
1066 static int __init
init_memory_definitions(struct acpi_table_header
*table
)
1068 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
1069 struct ivmd_header
*m
;
1071 end
+= table
->length
;
1072 p
+= IVRS_HEADER_LENGTH
;
1075 m
= (struct ivmd_header
*)p
;
1076 if (m
->flags
& IVMD_FLAG_EXCL_RANGE
)
1077 init_exclusion_range(m
);
1078 else if (m
->flags
& IVMD_FLAG_UNITY_MAP
)
1079 init_unity_map_range(m
);
1088 * Init the device table to not allow DMA access for devices and
1089 * suppress all page faults
1091 static void init_device_table(void)
1095 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
1096 set_dev_entry_bit(devid
, DEV_ENTRY_VALID
);
1097 set_dev_entry_bit(devid
, DEV_ENTRY_TRANSLATION
);
1102 * This function finally enables all IOMMUs found in the system after
1103 * they have been initialized
1105 static void enable_iommus(void)
1107 struct amd_iommu
*iommu
;
1109 for_each_iommu(iommu
) {
1110 iommu_disable(iommu
);
1111 iommu_set_device_table(iommu
);
1112 iommu_enable_command_buffer(iommu
);
1113 iommu_enable_event_buffer(iommu
);
1114 iommu_set_exclusion_range(iommu
);
1115 iommu_init_msi(iommu
);
1116 iommu_enable(iommu
);
1120 static void disable_iommus(void)
1122 struct amd_iommu
*iommu
;
1124 for_each_iommu(iommu
)
1125 iommu_disable(iommu
);
1129 * Suspend/Resume support
1130 * disable suspend until real resume implemented
1133 static int amd_iommu_resume(struct sys_device
*dev
)
1135 /* re-load the hardware */
1139 * we have to flush after the IOMMUs are enabled because a
1140 * disabled IOMMU will never execute the commands we send
1142 amd_iommu_flush_all_devices();
1143 amd_iommu_flush_all_domains();
1148 static int amd_iommu_suspend(struct sys_device
*dev
, pm_message_t state
)
1150 /* disable IOMMUs to go out of the way for BIOS */
1156 static struct sysdev_class amd_iommu_sysdev_class
= {
1157 .name
= "amd_iommu",
1158 .suspend
= amd_iommu_suspend
,
1159 .resume
= amd_iommu_resume
,
1162 static struct sys_device device_amd_iommu
= {
1164 .cls
= &amd_iommu_sysdev_class
,
1168 * This is the core init function for AMD IOMMU hardware in the system.
1169 * This function is called from the generic x86 DMA layer initialization
1172 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1175 * 1 pass) Find the highest PCI device id the driver has to handle.
1176 * Upon this information the size of the data structures is
1177 * determined that needs to be allocated.
1179 * 2 pass) Initialize the data structures just allocated with the
1180 * information in the ACPI table about available AMD IOMMUs
1181 * in the system. It also maps the PCI devices in the
1182 * system to specific IOMMUs
1184 * 3 pass) After the basic data structures are allocated and
1185 * initialized we update them with information about memory
1186 * remapping requirements parsed out of the ACPI table in
1189 * After that the hardware is initialized and ready to go. In the last
1190 * step we do some Linux specific things like registering the driver in
1191 * the dma_ops interface and initializing the suspend/resume support
1192 * functions. Finally it prints some information about AMD IOMMUs and
1193 * the driver state and enables the hardware.
1195 static int __init
amd_iommu_init(void)
1200 * First parse ACPI tables to find the largest Bus/Dev/Func
1201 * we need to handle. Upon this information the shared data
1202 * structures for the IOMMUs in the system will be allocated
1204 if (acpi_table_parse("IVRS", find_last_devid_acpi
) != 0)
1207 dev_table_size
= tbl_size(DEV_TABLE_ENTRY_SIZE
);
1208 alias_table_size
= tbl_size(ALIAS_TABLE_ENTRY_SIZE
);
1209 rlookup_table_size
= tbl_size(RLOOKUP_TABLE_ENTRY_SIZE
);
1213 /* Device table - directly used by all IOMMUs */
1214 amd_iommu_dev_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1215 get_order(dev_table_size
));
1216 if (amd_iommu_dev_table
== NULL
)
1220 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1221 * IOMMU see for that device
1223 amd_iommu_alias_table
= (void *)__get_free_pages(GFP_KERNEL
,
1224 get_order(alias_table_size
));
1225 if (amd_iommu_alias_table
== NULL
)
1228 /* IOMMU rlookup table - find the IOMMU for a specific device */
1229 amd_iommu_rlookup_table
= (void *)__get_free_pages(
1230 GFP_KERNEL
| __GFP_ZERO
,
1231 get_order(rlookup_table_size
));
1232 if (amd_iommu_rlookup_table
== NULL
)
1235 amd_iommu_pd_alloc_bitmap
= (void *)__get_free_pages(
1236 GFP_KERNEL
| __GFP_ZERO
,
1237 get_order(MAX_DOMAIN_ID
/8));
1238 if (amd_iommu_pd_alloc_bitmap
== NULL
)
1241 /* init the device table */
1242 init_device_table();
1245 * let all alias entries point to itself
1247 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1248 amd_iommu_alias_table
[i
] = i
;
1251 * never allocate domain 0 because its used as the non-allocated and
1252 * error value placeholder
1254 amd_iommu_pd_alloc_bitmap
[0] = 1;
1256 spin_lock_init(&amd_iommu_pd_lock
);
1259 * now the data structures are allocated and basically initialized
1260 * start the real acpi table scan
1263 if (acpi_table_parse("IVRS", init_iommu_all
) != 0)
1266 if (acpi_table_parse("IVRS", init_memory_definitions
) != 0)
1269 ret
= sysdev_class_register(&amd_iommu_sysdev_class
);
1273 ret
= sysdev_register(&device_amd_iommu
);
1277 ret
= amd_iommu_init_devices();
1281 if (iommu_pass_through
)
1282 ret
= amd_iommu_init_passthrough();
1284 ret
= amd_iommu_init_dma_ops();
1290 if (iommu_pass_through
)
1293 if (amd_iommu_unmap_flush
)
1294 printk(KERN_INFO
"AMD-Vi: IO/TLB flush on unmap enabled\n");
1296 printk(KERN_INFO
"AMD-Vi: Lazy IO/TLB flushing enabled\n");
1298 x86_platform
.iommu_shutdown
= disable_iommus
;
1304 amd_iommu_uninit_devices();
1306 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap
,
1307 get_order(MAX_DOMAIN_ID
/8));
1309 free_pages((unsigned long)amd_iommu_rlookup_table
,
1310 get_order(rlookup_table_size
));
1312 free_pages((unsigned long)amd_iommu_alias_table
,
1313 get_order(alias_table_size
));
1315 free_pages((unsigned long)amd_iommu_dev_table
,
1316 get_order(dev_table_size
));
1325 /****************************************************************************
1327 * Early detect code. This code runs at IOMMU detection time in the DMA
1328 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1331 ****************************************************************************/
1332 static int __init
early_amd_iommu_detect(struct acpi_table_header
*table
)
1337 void __init
amd_iommu_detect(void)
1339 if (no_iommu
|| (iommu_detected
&& !gart_iommu_aperture
))
1342 if (acpi_table_parse("IVRS", early_amd_iommu_detect
) == 0) {
1344 amd_iommu_detected
= 1;
1345 x86_init
.iommu
.iommu_init
= amd_iommu_init
;
1349 /****************************************************************************
1351 * Parsing functions for the AMD IOMMU specific kernel command line
1354 ****************************************************************************/
1356 static int __init
parse_amd_iommu_dump(char *str
)
1358 amd_iommu_dump
= true;
1363 static int __init
parse_amd_iommu_options(char *str
)
1365 for (; *str
; ++str
) {
1366 if (strncmp(str
, "fullflush", 9) == 0)
1367 amd_iommu_unmap_flush
= true;
1373 __setup("amd_iommu_dump", parse_amd_iommu_dump
);
1374 __setup("amd_iommu=", parse_amd_iommu_options
);