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drm: fix some lindent damage
[linux-2.6/kvm.git] / drivers / char / drm / i830_dma.c
blobdc94f1914425b7eabadc538e31c66998e2c08c30
1 /* i830_dma.c -- DMA support for the I830 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Abraham vd Merwe <abraham@2d3d.co.za>
31 *
32 */
33
34 #include "drmP.h"
35 #include "drm.h"
36 #include "i830_drm.h"
37 #include "i830_drv.h"
38 #include <linux/interrupt.h> /* For task queue support */
39 #include <linux/pagemap.h> /* For FASTCALL on unlock_page() */
40 #include <linux/delay.h>
41 #include <asm/uaccess.h>
42
43 #define I830_BUF_FREE 2
44 #define I830_BUF_CLIENT 1
45 #define I830_BUF_HARDWARE 0
46
47 #define I830_BUF_UNMAPPED 0
48 #define I830_BUF_MAPPED 1
49
50 static drm_buf_t *i830_freelist_get(drm_device_t * dev)
51 {
52 drm_device_dma_t *dma = dev->dma;
53 int i;
54 int used;
55
56 /* Linear search might not be the best solution */
57
58 for (i = 0; i < dma->buf_count; i++) {
59 drm_buf_t *buf = dma->buflist[i];
60 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
61 /* In use is already a pointer */
62 used = cmpxchg(buf_priv->in_use, I830_BUF_FREE,
63 I830_BUF_CLIENT);
64 if (used == I830_BUF_FREE) {
65 return buf;
66 }
67 }
68 return NULL;
69 }
70
71 /* This should only be called if the buffer is not sent to the hardware
72 * yet, the hardware updates in use for us once its on the ring buffer.
73 */
74
75 static int i830_freelist_put(drm_device_t * dev, drm_buf_t * buf)
76 {
77 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
78 int used;
79
80 /* In use is already a pointer */
81 used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE);
82 if (used != I830_BUF_CLIENT) {
83 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
84 return -EINVAL;
85 }
86
87 return 0;
88 }
89
90 static int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
91 {
92 drm_file_t *priv = filp->private_data;
93 drm_device_t *dev;
94 drm_i830_private_t *dev_priv;
95 drm_buf_t *buf;
96 drm_i830_buf_priv_t *buf_priv;
97
98 lock_kernel();
99 dev = priv->head->dev;
100 dev_priv = dev->dev_private;
101 buf = dev_priv->mmap_buffer;
102 buf_priv = buf->dev_private;
103
104 vma->vm_flags |= (VM_IO | VM_DONTCOPY);
105 vma->vm_file = filp;
106
107 buf_priv->currently_mapped = I830_BUF_MAPPED;
108 unlock_kernel();
109
110 if (io_remap_pfn_range(vma, vma->vm_start,
111 VM_OFFSET(vma) >> PAGE_SHIFT,
112 vma->vm_end - vma->vm_start, vma->vm_page_prot))
113 return -EAGAIN;
114 return 0;
115 }
116
117 static struct file_operations i830_buffer_fops = {
118 .open = drm_open,
119 .flush = drm_flush,
120 .release = drm_release,
121 .ioctl = drm_ioctl,
122 .mmap = i830_mmap_buffers,
123 .fasync = drm_fasync,
124 };
125
126 static int i830_map_buffer(drm_buf_t * buf, struct file *filp)
127 {
128 drm_file_t *priv = filp->private_data;
129 drm_device_t *dev = priv->head->dev;
130 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
131 drm_i830_private_t *dev_priv = dev->dev_private;
132 struct file_operations *old_fops;
133 unsigned long virtual;
134 int retcode = 0;
135
136 if (buf_priv->currently_mapped == I830_BUF_MAPPED)
137 return -EINVAL;
138
139 down_write(&current->mm->mmap_sem);
140 old_fops = filp->f_op;
141 filp->f_op = &i830_buffer_fops;
142 dev_priv->mmap_buffer = buf;
143 virtual = do_mmap(filp, 0, buf->total, PROT_READ | PROT_WRITE,
144 MAP_SHARED, buf->bus_address);
145 dev_priv->mmap_buffer = NULL;
146 filp->f_op = old_fops;
147 if (IS_ERR((void *)virtual)) { /* ugh */
148 /* Real error */
149 DRM_ERROR("mmap error\n");
150 retcode = virtual;
151 buf_priv->virtual = NULL;
152 } else {
153 buf_priv->virtual = (void __user *)virtual;
154 }
155 up_write(&current->mm->mmap_sem);
156
157 return retcode;
158 }
159
160 static int i830_unmap_buffer(drm_buf_t * buf)
161 {
162 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
163 int retcode = 0;
164
165 if (buf_priv->currently_mapped != I830_BUF_MAPPED)
166 return -EINVAL;
167
168 down_write(&current->mm->mmap_sem);
169 retcode = do_munmap(current->mm,
170 (unsigned long)buf_priv->virtual,
171 (size_t) buf->total);
172 up_write(&current->mm->mmap_sem);
173
174 buf_priv->currently_mapped = I830_BUF_UNMAPPED;
175 buf_priv->virtual = NULL;
176
177 return retcode;
178 }
179
180 static int i830_dma_get_buffer(drm_device_t * dev, drm_i830_dma_t * d,
181 struct file *filp)
182 {
183 drm_buf_t *buf;
184 drm_i830_buf_priv_t *buf_priv;
185 int retcode = 0;
186
187 buf = i830_freelist_get(dev);
188 if (!buf) {
189 retcode = -ENOMEM;
190 DRM_DEBUG("retcode=%d\n", retcode);
191 return retcode;
192 }
193
194 retcode = i830_map_buffer(buf, filp);
195 if (retcode) {
196 i830_freelist_put(dev, buf);
197 DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
198 return retcode;
199 }
200 buf->filp = filp;
201 buf_priv = buf->dev_private;
202 d->granted = 1;
203 d->request_idx = buf->idx;
204 d->request_size = buf->total;
205 d->virtual = buf_priv->virtual;
206
207 return retcode;
208 }
209
210 static int i830_dma_cleanup(drm_device_t * dev)
211 {
212 drm_device_dma_t *dma = dev->dma;
213
214 /* Make sure interrupts are disabled here because the uninstall ioctl
215 * may not have been called from userspace and after dev_private
216 * is freed, it's too late.
217 */
218 if (dev->irq_enabled)
219 drm_irq_uninstall(dev);
220
221 if (dev->dev_private) {
222 int i;
223 drm_i830_private_t *dev_priv =
224 (drm_i830_private_t *) dev->dev_private;
225
226 if (dev_priv->ring.virtual_start) {
227 drm_ioremapfree((void *)dev_priv->ring.virtual_start,
228 dev_priv->ring.Size, dev);
229 }
230 if (dev_priv->hw_status_page) {
231 pci_free_consistent(dev->pdev, PAGE_SIZE,
232 dev_priv->hw_status_page,
233 dev_priv->dma_status_page);
234 /* Need to rewrite hardware status page */
235 I830_WRITE(0x02080, 0x1ffff000);
236 }
237
238 drm_free(dev->dev_private, sizeof(drm_i830_private_t),
239 DRM_MEM_DRIVER);
240 dev->dev_private = NULL;
241
242 for (i = 0; i < dma->buf_count; i++) {
243 drm_buf_t *buf = dma->buflist[i];
244 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
245 if (buf_priv->kernel_virtual && buf->total)
246 drm_ioremapfree(buf_priv->kernel_virtual,
247 buf->total, dev);
248 }
249 }
250 return 0;
251 }
252
253 int i830_wait_ring(drm_device_t * dev, int n, const char *caller)
254 {
255 drm_i830_private_t *dev_priv = dev->dev_private;
256 drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
257 int iters = 0;
258 unsigned long end;
259 unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
260
261 end = jiffies + (HZ * 3);
262 while (ring->space < n) {
263 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
264 ring->space = ring->head - (ring->tail + 8);
265 if (ring->space < 0)
266 ring->space += ring->Size;
267
268 if (ring->head != last_head) {
269 end = jiffies + (HZ * 3);
270 last_head = ring->head;
271 }
272
273 iters++;
274 if (time_before(end, jiffies)) {
275 DRM_ERROR("space: %d wanted %d\n", ring->space, n);
276 DRM_ERROR("lockup\n");
277 goto out_wait_ring;
278 }
279 udelay(1);
280 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT;
281 }
282
283 out_wait_ring:
284 return iters;
285 }
286
287 static void i830_kernel_lost_context(drm_device_t * dev)
288 {
289 drm_i830_private_t *dev_priv = dev->dev_private;
290 drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
291
292 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
293 ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
294 ring->space = ring->head - (ring->tail + 8);
295 if (ring->space < 0)
296 ring->space += ring->Size;
297
298 if (ring->head == ring->tail)
299 dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY;
300 }
301
302 static int i830_freelist_init(drm_device_t * dev, drm_i830_private_t * dev_priv)
303 {
304 drm_device_dma_t *dma = dev->dma;
305 int my_idx = 36;
306 u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
307 int i;
308
309 if (dma->buf_count > 1019) {
310 /* Not enough space in the status page for the freelist */
311 return -EINVAL;
312 }
313
314 for (i = 0; i < dma->buf_count; i++) {
315 drm_buf_t *buf = dma->buflist[i];
316 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
317
318 buf_priv->in_use = hw_status++;
319 buf_priv->my_use_idx = my_idx;
320 my_idx += 4;
321
322 *buf_priv->in_use = I830_BUF_FREE;
323
324 buf_priv->kernel_virtual = drm_ioremap(buf->bus_address,
325 buf->total, dev);
326 }
327 return 0;
328 }
329
330 static int i830_dma_initialize(drm_device_t * dev,
331 drm_i830_private_t * dev_priv,
332 drm_i830_init_t * init)
333 {
334 struct list_head *list;
335
336 memset(dev_priv, 0, sizeof(drm_i830_private_t));
337
338 list_for_each(list, &dev->maplist->head) {
339 drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head);
340 if (r_list->map &&
341 r_list->map->type == _DRM_SHM &&
342 r_list->map->flags & _DRM_CONTAINS_LOCK) {
343 dev_priv->sarea_map = r_list->map;
344 break;
345 }
346 }
347
348 if (!dev_priv->sarea_map) {
349 dev->dev_private = (void *)dev_priv;
350 i830_dma_cleanup(dev);
351 DRM_ERROR("can not find sarea!\n");
352 return -EINVAL;
353 }
354 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
355 if (!dev_priv->mmio_map) {
356 dev->dev_private = (void *)dev_priv;
357 i830_dma_cleanup(dev);
358 DRM_ERROR("can not find mmio map!\n");
359 return -EINVAL;
360 }
361 dev->agp_buffer_token = init->buffers_offset;
362 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
363 if (!dev->agp_buffer_map) {
364 dev->dev_private = (void *)dev_priv;
365 i830_dma_cleanup(dev);
366 DRM_ERROR("can not find dma buffer map!\n");
367 return -EINVAL;
368 }
369
370 dev_priv->sarea_priv = (drm_i830_sarea_t *)
371 ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
372
373 dev_priv->ring.Start = init->ring_start;
374 dev_priv->ring.End = init->ring_end;
375 dev_priv->ring.Size = init->ring_size;
376
377 dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base +
378 init->ring_start,
379 init->ring_size, dev);
380
381 if (dev_priv->ring.virtual_start == NULL) {
382 dev->dev_private = (void *)dev_priv;
383 i830_dma_cleanup(dev);
384 DRM_ERROR("can not ioremap virtual address for"
385 " ring buffer\n");
386 return -ENOMEM;
387 }
388
389 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
390
391 dev_priv->w = init->w;
392 dev_priv->h = init->h;
393 dev_priv->pitch = init->pitch;
394 dev_priv->back_offset = init->back_offset;
395 dev_priv->depth_offset = init->depth_offset;
396 dev_priv->front_offset = init->front_offset;
397
398 dev_priv->front_di1 = init->front_offset | init->pitch_bits;
399 dev_priv->back_di1 = init->back_offset | init->pitch_bits;
400 dev_priv->zi1 = init->depth_offset | init->pitch_bits;
401
402 DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1);
403 DRM_DEBUG("back_offset %x\n", dev_priv->back_offset);
404 DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1);
405 DRM_DEBUG("pitch_bits %x\n", init->pitch_bits);
406
407 dev_priv->cpp = init->cpp;
408 /* We are using separate values as placeholders for mechanisms for
409 * private backbuffer/depthbuffer usage.
410 */
411
412 dev_priv->back_pitch = init->back_pitch;
413 dev_priv->depth_pitch = init->depth_pitch;
414 dev_priv->do_boxes = 0;
415 dev_priv->use_mi_batchbuffer_start = 0;
416
417 /* Program Hardware Status Page */
418 dev_priv->hw_status_page =
419 pci_alloc_consistent(dev->pdev, PAGE_SIZE,
420 &dev_priv->dma_status_page);
421 if (!dev_priv->hw_status_page) {
422 dev->dev_private = (void *)dev_priv;
423 i830_dma_cleanup(dev);
424 DRM_ERROR("Can not allocate hardware status page\n");
425 return -ENOMEM;
426 }
427 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
428 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
429
430 I830_WRITE(0x02080, dev_priv->dma_status_page);
431 DRM_DEBUG("Enabled hardware status page\n");
432
433 /* Now we need to init our freelist */
434 if (i830_freelist_init(dev, dev_priv) != 0) {
435 dev->dev_private = (void *)dev_priv;
436 i830_dma_cleanup(dev);
437 DRM_ERROR("Not enough space in the status page for"
438 " the freelist\n");
439 return -ENOMEM;
440 }
441 dev->dev_private = (void *)dev_priv;
442
443 return 0;
444 }
445
446 static int i830_dma_init(struct inode *inode, struct file *filp,
447 unsigned int cmd, unsigned long arg)
448 {
449 drm_file_t *priv = filp->private_data;
450 drm_device_t *dev = priv->head->dev;
451 drm_i830_private_t *dev_priv;
452 drm_i830_init_t init;
453 int retcode = 0;
454
455 if (copy_from_user(&init, (void *__user)arg, sizeof(init)))
456 return -EFAULT;
457
458 switch (init.func) {
459 case I830_INIT_DMA:
460 dev_priv = drm_alloc(sizeof(drm_i830_private_t),
461 DRM_MEM_DRIVER);
462 if (dev_priv == NULL)
463 return -ENOMEM;
464 retcode = i830_dma_initialize(dev, dev_priv, &init);
465 break;
466 case I830_CLEANUP_DMA:
467 retcode = i830_dma_cleanup(dev);
468 break;
469 default:
470 retcode = -EINVAL;
471 break;
472 }
473
474 return retcode;
475 }
476
477 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
478 #define ST1_ENABLE (1<<16)
479 #define ST1_MASK (0xffff)
480
481 /* Most efficient way to verify state for the i830 is as it is
482 * emitted. Non-conformant state is silently dropped.
483 */
484 static void i830EmitContextVerified(drm_device_t * dev, unsigned int *code)
485 {
486 drm_i830_private_t *dev_priv = dev->dev_private;
487 int i, j = 0;
488 unsigned int tmp;
489 RING_LOCALS;
490
491 BEGIN_LP_RING(I830_CTX_SETUP_SIZE + 4);
492
493 for (i = 0; i < I830_CTXREG_BLENDCOLR0; i++) {
494 tmp = code[i];
495 if ((tmp & (7 << 29)) == CMD_3D &&
496 (tmp & (0x1f << 24)) < (0x1d << 24)) {
497 OUT_RING(tmp);
498 j++;
499 } else {
500 DRM_ERROR("Skipping %d\n", i);
501 }
502 }
503
504 OUT_RING(STATE3D_CONST_BLEND_COLOR_CMD);
505 OUT_RING(code[I830_CTXREG_BLENDCOLR]);
506 j += 2;
507
508 for (i = I830_CTXREG_VF; i < I830_CTXREG_MCSB0; i++) {
509 tmp = code[i];
510 if ((tmp & (7 << 29)) == CMD_3D &&
511 (tmp & (0x1f << 24)) < (0x1d << 24)) {
512 OUT_RING(tmp);
513 j++;
514 } else {
515 DRM_ERROR("Skipping %d\n", i);
516 }
517 }
518
519 OUT_RING(STATE3D_MAP_COORD_SETBIND_CMD);
520 OUT_RING(code[I830_CTXREG_MCSB1]);
521 j += 2;
522
523 if (j & 1)
524 OUT_RING(0);
525
526 ADVANCE_LP_RING();
527 }
528
529 static void i830EmitTexVerified(drm_device_t * dev, unsigned int *code)
530 {
531 drm_i830_private_t *dev_priv = dev->dev_private;
532 int i, j = 0;
533 unsigned int tmp;
534 RING_LOCALS;
535
536 if (code[I830_TEXREG_MI0] == GFX_OP_MAP_INFO ||
537 (code[I830_TEXREG_MI0] & ~(0xf * LOAD_TEXTURE_MAP0)) ==
538 (STATE3D_LOAD_STATE_IMMEDIATE_2 | 4)) {
539
540 BEGIN_LP_RING(I830_TEX_SETUP_SIZE);
541
542 OUT_RING(code[I830_TEXREG_MI0]); /* TM0LI */
543 OUT_RING(code[I830_TEXREG_MI1]); /* TM0S0 */
544 OUT_RING(code[I830_TEXREG_MI2]); /* TM0S1 */
545 OUT_RING(code[I830_TEXREG_MI3]); /* TM0S2 */
546 OUT_RING(code[I830_TEXREG_MI4]); /* TM0S3 */
547 OUT_RING(code[I830_TEXREG_MI5]); /* TM0S4 */
548
549 for (i = 6; i < I830_TEX_SETUP_SIZE; i++) {
550 tmp = code[i];
551 OUT_RING(tmp);
552 j++;
553 }
554
555 if (j & 1)
556 OUT_RING(0);
557
558 ADVANCE_LP_RING();
559 } else
560 printk("rejected packet %x\n", code[0]);
561 }
562
563 static void i830EmitTexBlendVerified(drm_device_t * dev,
564 unsigned int *code, unsigned int num)
565 {
566 drm_i830_private_t *dev_priv = dev->dev_private;
567 int i, j = 0;
568 unsigned int tmp;
569 RING_LOCALS;
570
571 if (!num)
572 return;
573
574 BEGIN_LP_RING(num + 1);
575
576 for (i = 0; i < num; i++) {
577 tmp = code[i];
578 OUT_RING(tmp);
579 j++;
580 }
581
582 if (j & 1)
583 OUT_RING(0);
584
585 ADVANCE_LP_RING();
586 }
587
588 static void i830EmitTexPalette(drm_device_t * dev,
589 unsigned int *palette, int number, int is_shared)
590 {
591 drm_i830_private_t *dev_priv = dev->dev_private;
592 int i;
593 RING_LOCALS;
594
595 return;
596
597 BEGIN_LP_RING(258);
598
599 if (is_shared == 1) {
600 OUT_RING(CMD_OP_MAP_PALETTE_LOAD |
601 MAP_PALETTE_NUM(0) | MAP_PALETTE_BOTH);
602 } else {
603 OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number));
604 }
605 for (i = 0; i < 256; i++) {
606 OUT_RING(palette[i]);
607 }
608 OUT_RING(0);
609 /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop!
610 */
611 }
612
613 /* Need to do some additional checking when setting the dest buffer.
614 */
615 static void i830EmitDestVerified(drm_device_t * dev, unsigned int *code)
616 {
617 drm_i830_private_t *dev_priv = dev->dev_private;
618 unsigned int tmp;
619 RING_LOCALS;
620
621 BEGIN_LP_RING(I830_DEST_SETUP_SIZE + 10);
622
623 tmp = code[I830_DESTREG_CBUFADDR];
624 if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
625 if (((int)outring) & 8) {
626 OUT_RING(0);
627 OUT_RING(0);
628 }
629
630 OUT_RING(CMD_OP_DESTBUFFER_INFO);
631 OUT_RING(BUF_3D_ID_COLOR_BACK |
632 BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) |
633 BUF_3D_USE_FENCE);
634 OUT_RING(tmp);
635 OUT_RING(0);
636
637 OUT_RING(CMD_OP_DESTBUFFER_INFO);
638 OUT_RING(BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE |
639 BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp));
640 OUT_RING(dev_priv->zi1);
641 OUT_RING(0);
642 } else {
643 DRM_ERROR("bad di1 %x (allow %x or %x)\n",
644 tmp, dev_priv->front_di1, dev_priv->back_di1);
645 }
646
647 /* invarient:
648 */
649
650 OUT_RING(GFX_OP_DESTBUFFER_VARS);
651 OUT_RING(code[I830_DESTREG_DV1]);
652
653 OUT_RING(GFX_OP_DRAWRECT_INFO);
654 OUT_RING(code[I830_DESTREG_DR1]);
655 OUT_RING(code[I830_DESTREG_DR2]);
656 OUT_RING(code[I830_DESTREG_DR3]);
657 OUT_RING(code[I830_DESTREG_DR4]);
658
659 /* Need to verify this */
660 tmp = code[I830_DESTREG_SENABLE];
661 if ((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) {
662 OUT_RING(tmp);
663 } else {
664 DRM_ERROR("bad scissor enable\n");
665 OUT_RING(0);
666 }
667
668 OUT_RING(GFX_OP_SCISSOR_RECT);
669 OUT_RING(code[I830_DESTREG_SR1]);
670 OUT_RING(code[I830_DESTREG_SR2]);
671 OUT_RING(0);
672
673 ADVANCE_LP_RING();
674 }
675
676 static void i830EmitStippleVerified(drm_device_t * dev, unsigned int *code)
677 {
678 drm_i830_private_t *dev_priv = dev->dev_private;
679 RING_LOCALS;
680
681 BEGIN_LP_RING(2);
682 OUT_RING(GFX_OP_STIPPLE);
683 OUT_RING(code[1]);
684 ADVANCE_LP_RING();
685 }
686
687 static void i830EmitState(drm_device_t * dev)
688 {
689 drm_i830_private_t *dev_priv = dev->dev_private;
690 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
691 unsigned int dirty = sarea_priv->dirty;
692
693 DRM_DEBUG("%s %x\n", __FUNCTION__, dirty);
694
695 if (dirty & I830_UPLOAD_BUFFERS) {
696 i830EmitDestVerified(dev, sarea_priv->BufferState);
697 sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS;
698 }
699
700 if (dirty & I830_UPLOAD_CTX) {
701 i830EmitContextVerified(dev, sarea_priv->ContextState);
702 sarea_priv->dirty &= ~I830_UPLOAD_CTX;
703 }
704
705 if (dirty & I830_UPLOAD_TEX0) {
706 i830EmitTexVerified(dev, sarea_priv->TexState[0]);
707 sarea_priv->dirty &= ~I830_UPLOAD_TEX0;
708 }
709
710 if (dirty & I830_UPLOAD_TEX1) {
711 i830EmitTexVerified(dev, sarea_priv->TexState[1]);
712 sarea_priv->dirty &= ~I830_UPLOAD_TEX1;
713 }
714
715 if (dirty & I830_UPLOAD_TEXBLEND0) {
716 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[0],
717 sarea_priv->TexBlendStateWordsUsed[0]);
718 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0;
719 }
720
721 if (dirty & I830_UPLOAD_TEXBLEND1) {
722 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[1],
723 sarea_priv->TexBlendStateWordsUsed[1]);
724 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1;
725 }
726
727 if (dirty & I830_UPLOAD_TEX_PALETTE_SHARED) {
728 i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 1);
729 } else {
730 if (dirty & I830_UPLOAD_TEX_PALETTE_N(0)) {
731 i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 0);
732 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(0);
733 }
734 if (dirty & I830_UPLOAD_TEX_PALETTE_N(1)) {
735 i830EmitTexPalette(dev, sarea_priv->Palette[1], 1, 0);
736 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(1);
737 }
738
739 /* 1.3:
740 */
741 #if 0
742 if (dirty & I830_UPLOAD_TEX_PALETTE_N(2)) {
743 i830EmitTexPalette(dev, sarea_priv->Palette2[0], 0, 0);
744 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2);
745 }
746 if (dirty & I830_UPLOAD_TEX_PALETTE_N(3)) {
747 i830EmitTexPalette(dev, sarea_priv->Palette2[1], 1, 0);
748 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2);
749 }
750 #endif
751 }
752
753 /* 1.3:
754 */
755 if (dirty & I830_UPLOAD_STIPPLE) {
756 i830EmitStippleVerified(dev, sarea_priv->StippleState);
757 sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE;
758 }
759
760 if (dirty & I830_UPLOAD_TEX2) {
761 i830EmitTexVerified(dev, sarea_priv->TexState2);
762 sarea_priv->dirty &= ~I830_UPLOAD_TEX2;
763 }
764
765 if (dirty & I830_UPLOAD_TEX3) {
766 i830EmitTexVerified(dev, sarea_priv->TexState3);
767 sarea_priv->dirty &= ~I830_UPLOAD_TEX3;
768 }
769
770 if (dirty & I830_UPLOAD_TEXBLEND2) {
771 i830EmitTexBlendVerified(dev,
772 sarea_priv->TexBlendState2,
773 sarea_priv->TexBlendStateWordsUsed2);
774
775 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2;
776 }
777
778 if (dirty & I830_UPLOAD_TEXBLEND3) {
779 i830EmitTexBlendVerified(dev,
780 sarea_priv->TexBlendState3,
781 sarea_priv->TexBlendStateWordsUsed3);
782 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3;
783 }
784 }
785
786 /* ================================================================
787 * Performance monitoring functions
788 */
789
790 static void i830_fill_box(drm_device_t * dev,
791 int x, int y, int w, int h, int r, int g, int b)
792 {
793 drm_i830_private_t *dev_priv = dev->dev_private;
794 u32 color;
795 unsigned int BR13, CMD;
796 RING_LOCALS;
797
798 BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1 << 24);
799 CMD = XY_COLOR_BLT_CMD;
800 x += dev_priv->sarea_priv->boxes[0].x1;
801 y += dev_priv->sarea_priv->boxes[0].y1;
802
803 if (dev_priv->cpp == 4) {
804 BR13 |= (1 << 25);
805 CMD |= (XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB);
806 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
807 } else {
808 color = (((r & 0xf8) << 8) |
809 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
810 }
811
812 BEGIN_LP_RING(6);
813 OUT_RING(CMD);
814 OUT_RING(BR13);
815 OUT_RING((y << 16) | x);
816 OUT_RING(((y + h) << 16) | (x + w));
817
818 if (dev_priv->current_page == 1) {
819 OUT_RING(dev_priv->front_offset);
820 } else {
821 OUT_RING(dev_priv->back_offset);
822 }
823
824 OUT_RING(color);
825 ADVANCE_LP_RING();
826 }
827
828 static void i830_cp_performance_boxes(drm_device_t * dev)
829 {
830 drm_i830_private_t *dev_priv = dev->dev_private;
831
832 /* Purple box for page flipping
833 */
834 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP)
835 i830_fill_box(dev, 4, 4, 8, 8, 255, 0, 255);
836
837 /* Red box if we have to wait for idle at any point
838 */
839 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT)
840 i830_fill_box(dev, 16, 4, 8, 8, 255, 0, 0);
841
842 /* Blue box: lost context?
843 */
844 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT)
845 i830_fill_box(dev, 28, 4, 8, 8, 0, 0, 255);
846
847 /* Yellow box for texture swaps
848 */
849 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD)
850 i830_fill_box(dev, 40, 4, 8, 8, 255, 255, 0);
851
852 /* Green box if hardware never idles (as far as we can tell)
853 */
854 if (!(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY))
855 i830_fill_box(dev, 64, 4, 8, 8, 0, 255, 0);
856
857 /* Draw bars indicating number of buffers allocated
858 * (not a great measure, easily confused)
859 */
860 if (dev_priv->dma_used) {
861 int bar = dev_priv->dma_used / 10240;
862 if (bar > 100)
863 bar = 100;
864 if (bar < 1)
865 bar = 1;
866 i830_fill_box(dev, 4, 16, bar, 4, 196, 128, 128);
867 dev_priv->dma_used = 0;
868 }
869
870 dev_priv->sarea_priv->perf_boxes = 0;
871 }
872
873 static void i830_dma_dispatch_clear(drm_device_t * dev, int flags,
874 unsigned int clear_color,
875 unsigned int clear_zval,
876 unsigned int clear_depthmask)
877 {
878 drm_i830_private_t *dev_priv = dev->dev_private;
879 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
880 int nbox = sarea_priv->nbox;
881 drm_clip_rect_t *pbox = sarea_priv->boxes;
882 int pitch = dev_priv->pitch;
883 int cpp = dev_priv->cpp;
884 int i;
885 unsigned int BR13, CMD, D_CMD;
886 RING_LOCALS;
887
888 if (dev_priv->current_page == 1) {
889 unsigned int tmp = flags;
890
891 flags &= ~(I830_FRONT | I830_BACK);
892 if (tmp & I830_FRONT)
893 flags |= I830_BACK;
894 if (tmp & I830_BACK)
895 flags |= I830_FRONT;
896 }
897
898 i830_kernel_lost_context(dev);
899
900 switch (cpp) {
901 case 2:
902 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24);
903 D_CMD = CMD = XY_COLOR_BLT_CMD;
904 break;
905 case 4:
906 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24) | (1 << 25);
907 CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA |
908 XY_COLOR_BLT_WRITE_RGB);
909 D_CMD = XY_COLOR_BLT_CMD;
910 if (clear_depthmask & 0x00ffffff)
911 D_CMD |= XY_COLOR_BLT_WRITE_RGB;
912 if (clear_depthmask & 0xff000000)
913 D_CMD |= XY_COLOR_BLT_WRITE_ALPHA;
914 break;
915 default:
916 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24);
917 D_CMD = CMD = XY_COLOR_BLT_CMD;
918 break;
919 }
920
921 if (nbox > I830_NR_SAREA_CLIPRECTS)
922 nbox = I830_NR_SAREA_CLIPRECTS;
923
924 for (i = 0; i < nbox; i++, pbox++) {
925 if (pbox->x1 > pbox->x2 ||
926 pbox->y1 > pbox->y2 ||
927 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
928 continue;
929
930 if (flags & I830_FRONT) {
931 DRM_DEBUG("clear front\n");
932 BEGIN_LP_RING(6);
933 OUT_RING(CMD);
934 OUT_RING(BR13);
935 OUT_RING((pbox->y1 << 16) | pbox->x1);
936 OUT_RING((pbox->y2 << 16) | pbox->x2);
937 OUT_RING(dev_priv->front_offset);
938 OUT_RING(clear_color);
939 ADVANCE_LP_RING();
940 }
941
942 if (flags & I830_BACK) {
943 DRM_DEBUG("clear back\n");
944 BEGIN_LP_RING(6);
945 OUT_RING(CMD);
946 OUT_RING(BR13);
947 OUT_RING((pbox->y1 << 16) | pbox->x1);
948 OUT_RING((pbox->y2 << 16) | pbox->x2);
949 OUT_RING(dev_priv->back_offset);
950 OUT_RING(clear_color);
951 ADVANCE_LP_RING();
952 }
953
954 if (flags & I830_DEPTH) {
955 DRM_DEBUG("clear depth\n");
956 BEGIN_LP_RING(6);
957 OUT_RING(D_CMD);
958 OUT_RING(BR13);
959 OUT_RING((pbox->y1 << 16) | pbox->x1);
960 OUT_RING((pbox->y2 << 16) | pbox->x2);
961 OUT_RING(dev_priv->depth_offset);
962 OUT_RING(clear_zval);
963 ADVANCE_LP_RING();
964 }
965 }
966 }
967
968 static void i830_dma_dispatch_swap(drm_device_t * dev)
969 {
970 drm_i830_private_t *dev_priv = dev->dev_private;
971 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
972 int nbox = sarea_priv->nbox;
973 drm_clip_rect_t *pbox = sarea_priv->boxes;
974 int pitch = dev_priv->pitch;
975 int cpp = dev_priv->cpp;
976 int i;
977 unsigned int CMD, BR13;
978 RING_LOCALS;
979
980 DRM_DEBUG("swapbuffers\n");
981
982 i830_kernel_lost_context(dev);
983
984 if (dev_priv->do_boxes)
985 i830_cp_performance_boxes(dev);
986
987 switch (cpp) {
988 case 2:
989 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
990 CMD = XY_SRC_COPY_BLT_CMD;
991 break;
992 case 4:
993 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25);
994 CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
995 XY_SRC_COPY_BLT_WRITE_RGB);
996 break;
997 default:
998 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
999 CMD = XY_SRC_COPY_BLT_CMD;
1000 break;
1001 }
1002
1003 if (nbox > I830_NR_SAREA_CLIPRECTS)
1004 nbox = I830_NR_SAREA_CLIPRECTS;
1005
1006 for (i = 0; i < nbox; i++, pbox++) {
1007 if (pbox->x1 > pbox->x2 ||
1008 pbox->y1 > pbox->y2 ||
1009 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
1010 continue;
1011
1012 DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
1013 pbox->x1, pbox->y1, pbox->x2, pbox->y2);
1014
1015 BEGIN_LP_RING(8);
1016 OUT_RING(CMD);
1017 OUT_RING(BR13);
1018 OUT_RING((pbox->y1 << 16) | pbox->x1);
1019 OUT_RING((pbox->y2 << 16) | pbox->x2);
1020
1021 if (dev_priv->current_page == 0)
1022 OUT_RING(dev_priv->front_offset);
1023 else
1024 OUT_RING(dev_priv->back_offset);
1025
1026 OUT_RING((pbox->y1 << 16) | pbox->x1);
1027 OUT_RING(BR13 & 0xffff);
1028
1029 if (dev_priv->current_page == 0)
1030 OUT_RING(dev_priv->back_offset);
1031 else
1032 OUT_RING(dev_priv->front_offset);
1033
1034 ADVANCE_LP_RING();
1035 }
1036 }
1037
1038 static void i830_dma_dispatch_flip(drm_device_t * dev)
1039 {
1040 drm_i830_private_t *dev_priv = dev->dev_private;
1041 RING_LOCALS;
1042
1043 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
1044 __FUNCTION__,
1045 dev_priv->current_page,
1046 dev_priv->sarea_priv->pf_current_page);
1047
1048 i830_kernel_lost_context(dev);
1049
1050 if (dev_priv->do_boxes) {
1051 dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP;
1052 i830_cp_performance_boxes(dev);
1053 }
1054
1055 BEGIN_LP_RING(2);
1056 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
1057 OUT_RING(0);
1058 ADVANCE_LP_RING();
1059
1060 BEGIN_LP_RING(6);
1061 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
1062 OUT_RING(0);
1063 if (dev_priv->current_page == 0) {
1064 OUT_RING(dev_priv->back_offset);
1065 dev_priv->current_page = 1;
1066 } else {
1067 OUT_RING(dev_priv->front_offset);
1068 dev_priv->current_page = 0;
1069 }
1070 OUT_RING(0);
1071 ADVANCE_LP_RING();
1072
1073 BEGIN_LP_RING(2);
1074 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
1075 OUT_RING(0);
1076 ADVANCE_LP_RING();
1077
1078 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1079 }
1080
1081 static void i830_dma_dispatch_vertex(drm_device_t * dev,
1082 drm_buf_t * buf, int discard, int used)
1083 {
1084 drm_i830_private_t *dev_priv = dev->dev_private;
1085 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1086 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
1087 drm_clip_rect_t *box = sarea_priv->boxes;
1088 int nbox = sarea_priv->nbox;
1089 unsigned long address = (unsigned long)buf->bus_address;
1090 unsigned long start = address - dev->agp->base;
1091 int i = 0, u;
1092 RING_LOCALS;
1093
1094 i830_kernel_lost_context(dev);
1095
1096 if (nbox > I830_NR_SAREA_CLIPRECTS)
1097 nbox = I830_NR_SAREA_CLIPRECTS;
1098
1099 if (discard) {
1100 u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1101 I830_BUF_HARDWARE);
1102 if (u != I830_BUF_CLIENT) {
1103 DRM_DEBUG("xxxx 2\n");
1104 }
1105 }
1106
1107 if (used > 4 * 1023)
1108 used = 0;
1109
1110 if (sarea_priv->dirty)
1111 i830EmitState(dev);
1112
1113 DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n",
1114 address, used, nbox);
1115
1116 dev_priv->counter++;
1117 DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
1118 DRM_DEBUG("i830_dma_dispatch\n");
1119 DRM_DEBUG("start : %lx\n", start);
1120 DRM_DEBUG("used : %d\n", used);
1121 DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
1122
1123 if (buf_priv->currently_mapped == I830_BUF_MAPPED) {
1124 u32 *vp = buf_priv->kernel_virtual;
1125
1126 vp[0] = (GFX_OP_PRIMITIVE |
1127 sarea_priv->vertex_prim | ((used / 4) - 2));
1128
1129 if (dev_priv->use_mi_batchbuffer_start) {
1130 vp[used / 4] = MI_BATCH_BUFFER_END;
1131 used += 4;
1132 }
1133
1134 if (used & 4) {
1135 vp[used / 4] = 0;
1136 used += 4;
1137 }
1138
1139 i830_unmap_buffer(buf);
1140 }
1141
1142 if (used) {
1143 do {
1144 if (i < nbox) {
1145 BEGIN_LP_RING(6);
1146 OUT_RING(GFX_OP_DRAWRECT_INFO);
1147 OUT_RING(sarea_priv->
1148 BufferState[I830_DESTREG_DR1]);
1149 OUT_RING(box[i].x1 | (box[i].y1 << 16));
1150 OUT_RING(box[i].x2 | (box[i].y2 << 16));
1151 OUT_RING(sarea_priv->
1152 BufferState[I830_DESTREG_DR4]);
1153 OUT_RING(0);
1154 ADVANCE_LP_RING();
1155 }
1156
1157 if (dev_priv->use_mi_batchbuffer_start) {
1158 BEGIN_LP_RING(2);
1159 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
1160 OUT_RING(start | MI_BATCH_NON_SECURE);
1161 ADVANCE_LP_RING();
1162 } else {
1163 BEGIN_LP_RING(4);
1164 OUT_RING(MI_BATCH_BUFFER);
1165 OUT_RING(start | MI_BATCH_NON_SECURE);
1166 OUT_RING(start + used - 4);
1167 OUT_RING(0);
1168 ADVANCE_LP_RING();
1169 }
1170
1171 } while (++i < nbox);
1172 }
1173
1174 if (discard) {
1175 dev_priv->counter++;
1176
1177 (void)cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1178 I830_BUF_HARDWARE);
1179
1180 BEGIN_LP_RING(8);
1181 OUT_RING(CMD_STORE_DWORD_IDX);
1182 OUT_RING(20);
1183 OUT_RING(dev_priv->counter);
1184 OUT_RING(CMD_STORE_DWORD_IDX);
1185 OUT_RING(buf_priv->my_use_idx);
1186 OUT_RING(I830_BUF_FREE);
1187 OUT_RING(CMD_REPORT_HEAD);
1188 OUT_RING(0);
1189 ADVANCE_LP_RING();
1190 }
1191 }
1192
1193 static void i830_dma_quiescent(drm_device_t * dev)
1194 {
1195 drm_i830_private_t *dev_priv = dev->dev_private;
1196 RING_LOCALS;
1197
1198 i830_kernel_lost_context(dev);
1199
1200 BEGIN_LP_RING(4);
1201 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
1202 OUT_RING(CMD_REPORT_HEAD);
1203 OUT_RING(0);
1204 OUT_RING(0);
1205 ADVANCE_LP_RING();
1206
1207 i830_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
1208 }
1209
1210 static int i830_flush_queue(drm_device_t * dev)
1211 {
1212 drm_i830_private_t *dev_priv = dev->dev_private;
1213 drm_device_dma_t *dma = dev->dma;
1214 int i, ret = 0;
1215 RING_LOCALS;
1216
1217 i830_kernel_lost_context(dev);
1218
1219 BEGIN_LP_RING(2);
1220 OUT_RING(CMD_REPORT_HEAD);
1221 OUT_RING(0);
1222 ADVANCE_LP_RING();
1223
1224 i830_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
1225
1226 for (i = 0; i < dma->buf_count; i++) {
1227 drm_buf_t *buf = dma->buflist[i];
1228 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1229
1230 int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE,
1231 I830_BUF_FREE);
1232
1233 if (used == I830_BUF_HARDWARE)
1234 DRM_DEBUG("reclaimed from HARDWARE\n");
1235 if (used == I830_BUF_CLIENT)
1236 DRM_DEBUG("still on client\n");
1237 }
1238
1239 return ret;
1240 }
1241
1242 /* Must be called with the lock held */
1243 void i830_reclaim_buffers(drm_device_t * dev, struct file *filp)
1244 {
1245 drm_device_dma_t *dma = dev->dma;
1246 int i;
1247
1248 if (!dma)
1249 return;
1250 if (!dev->dev_private)
1251 return;
1252 if (!dma->buflist)
1253 return;
1254
1255 i830_flush_queue(dev);
1256
1257 for (i = 0; i < dma->buf_count; i++) {
1258 drm_buf_t *buf = dma->buflist[i];
1259 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1260
1261 if (buf->filp == filp && buf_priv) {
1262 int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1263 I830_BUF_FREE);
1264
1265 if (used == I830_BUF_CLIENT)
1266 DRM_DEBUG("reclaimed from client\n");
1267 if (buf_priv->currently_mapped == I830_BUF_MAPPED)
1268 buf_priv->currently_mapped = I830_BUF_UNMAPPED;
1269 }
1270 }
1271 }
1272
1273 static int i830_flush_ioctl(struct inode *inode, struct file *filp,
1274 unsigned int cmd, unsigned long arg)
1275 {
1276 drm_file_t *priv = filp->private_data;
1277 drm_device_t *dev = priv->head->dev;
1278
1279 LOCK_TEST_WITH_RETURN(dev, filp);
1280
1281 i830_flush_queue(dev);
1282 return 0;
1283 }
1284
1285 static int i830_dma_vertex(struct inode *inode, struct file *filp,
1286 unsigned int cmd, unsigned long arg)
1287 {
1288 drm_file_t *priv = filp->private_data;
1289 drm_device_t *dev = priv->head->dev;
1290 drm_device_dma_t *dma = dev->dma;
1291 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1292 u32 *hw_status = dev_priv->hw_status_page;
1293 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1294 dev_priv->sarea_priv;
1295 drm_i830_vertex_t vertex;
1296
1297 if (copy_from_user
1298 (&vertex, (drm_i830_vertex_t __user *) arg, sizeof(vertex)))
1299 return -EFAULT;
1300
1301 LOCK_TEST_WITH_RETURN(dev, filp);
1302
1303 DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n",
1304 vertex.idx, vertex.used, vertex.discard);
1305
1306 if (vertex.idx < 0 || vertex.idx > dma->buf_count)
1307 return -EINVAL;
1308
1309 i830_dma_dispatch_vertex(dev,
1310 dma->buflist[vertex.idx],
1311 vertex.discard, vertex.used);
1312
1313 sarea_priv->last_enqueue = dev_priv->counter - 1;
1314 sarea_priv->last_dispatch = (int)hw_status[5];
1315
1316 return 0;
1317 }
1318
1319 static int i830_clear_bufs(struct inode *inode, struct file *filp,
1320 unsigned int cmd, unsigned long arg)
1321 {
1322 drm_file_t *priv = filp->private_data;
1323 drm_device_t *dev = priv->head->dev;
1324 drm_i830_clear_t clear;
1325
1326 if (copy_from_user
1327 (&clear, (drm_i830_clear_t __user *) arg, sizeof(clear)))
1328 return -EFAULT;
1329
1330 LOCK_TEST_WITH_RETURN(dev, filp);
1331
1332 /* GH: Someone's doing nasty things... */
1333 if (!dev->dev_private) {
1334 return -EINVAL;
1335 }
1336
1337 i830_dma_dispatch_clear(dev, clear.flags,
1338 clear.clear_color,
1339 clear.clear_depth, clear.clear_depthmask);
1340 return 0;
1341 }
1342
1343 static int i830_swap_bufs(struct inode *inode, struct file *filp,
1344 unsigned int cmd, unsigned long arg)
1345 {
1346 drm_file_t *priv = filp->private_data;
1347 drm_device_t *dev = priv->head->dev;
1348
1349 DRM_DEBUG("i830_swap_bufs\n");
1350
1351 LOCK_TEST_WITH_RETURN(dev, filp);
1352
1353 i830_dma_dispatch_swap(dev);
1354 return 0;
1355 }
1356
1357 /* Not sure why this isn't set all the time:
1358 */
1359 static void i830_do_init_pageflip(drm_device_t * dev)
1360 {
1361 drm_i830_private_t *dev_priv = dev->dev_private;
1362
1363 DRM_DEBUG("%s\n", __FUNCTION__);
1364 dev_priv->page_flipping = 1;
1365 dev_priv->current_page = 0;
1366 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1367 }
1368
1369 static int i830_do_cleanup_pageflip(drm_device_t * dev)
1370 {
1371 drm_i830_private_t *dev_priv = dev->dev_private;
1372
1373 DRM_DEBUG("%s\n", __FUNCTION__);
1374 if (dev_priv->current_page != 0)
1375 i830_dma_dispatch_flip(dev);
1376
1377 dev_priv->page_flipping = 0;
1378 return 0;
1379 }
1380
1381 static int i830_flip_bufs(struct inode *inode, struct file *filp,
1382 unsigned int cmd, unsigned long arg)
1383 {
1384 drm_file_t *priv = filp->private_data;
1385 drm_device_t *dev = priv->head->dev;
1386 drm_i830_private_t *dev_priv = dev->dev_private;
1387
1388 DRM_DEBUG("%s\n", __FUNCTION__);
1389
1390 LOCK_TEST_WITH_RETURN(dev, filp);
1391
1392 if (!dev_priv->page_flipping)
1393 i830_do_init_pageflip(dev);
1394
1395 i830_dma_dispatch_flip(dev);
1396 return 0;
1397 }
1398
1399 static int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd,
1400 unsigned long arg)
1401 {
1402 drm_file_t *priv = filp->private_data;
1403 drm_device_t *dev = priv->head->dev;
1404 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1405 u32 *hw_status = dev_priv->hw_status_page;
1406 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1407 dev_priv->sarea_priv;
1408
1409 sarea_priv->last_dispatch = (int)hw_status[5];
1410 return 0;
1411 }
1412
1413 static int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
1414 unsigned long arg)
1415 {
1416 drm_file_t *priv = filp->private_data;
1417 drm_device_t *dev = priv->head->dev;
1418 int retcode = 0;
1419 drm_i830_dma_t d;
1420 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1421 u32 *hw_status = dev_priv->hw_status_page;
1422 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1423 dev_priv->sarea_priv;
1424
1425 DRM_DEBUG("getbuf\n");
1426 if (copy_from_user(&d, (drm_i830_dma_t __user *) arg, sizeof(d)))
1427 return -EFAULT;
1428
1429 LOCK_TEST_WITH_RETURN(dev, filp);
1430
1431 d.granted = 0;
1432
1433 retcode = i830_dma_get_buffer(dev, &d, filp);
1434
1435 DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n",
1436 current->pid, retcode, d.granted);
1437
1438 if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d)))
1439 return -EFAULT;
1440 sarea_priv->last_dispatch = (int)hw_status[5];
1441
1442 return retcode;
1443 }
1444
1445 static int i830_copybuf(struct inode *inode,
1446 struct file *filp, unsigned int cmd, unsigned long arg)
1447 {
1448 /* Never copy - 2.4.x doesn't need it */
1449 return 0;
1450 }
1451
1452 static int i830_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
1453 unsigned long arg)
1454 {
1455 return 0;
1456 }
1457
1458 static int i830_getparam(struct inode *inode, struct file *filp,
1459 unsigned int cmd, unsigned long arg)
1460 {
1461 drm_file_t *priv = filp->private_data;
1462 drm_device_t *dev = priv->head->dev;
1463 drm_i830_private_t *dev_priv = dev->dev_private;
1464 drm_i830_getparam_t param;
1465 int value;
1466
1467 if (!dev_priv) {
1468 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1469 return -EINVAL;
1470 }
1471
1472 if (copy_from_user
1473 (&param, (drm_i830_getparam_t __user *) arg, sizeof(param)))
1474 return -EFAULT;
1475
1476 switch (param.param) {
1477 case I830_PARAM_IRQ_ACTIVE:
1478 value = dev->irq_enabled;
1479 break;
1480 default:
1481 return -EINVAL;
1482 }
1483
1484 if (copy_to_user(param.value, &value, sizeof(int))) {
1485 DRM_ERROR("copy_to_user\n");
1486 return -EFAULT;
1487 }
1488
1489 return 0;
1490 }
1491
1492 static int i830_setparam(struct inode *inode, struct file *filp,
1493 unsigned int cmd, unsigned long arg)
1494 {
1495 drm_file_t *priv = filp->private_data;
1496 drm_device_t *dev = priv->head->dev;
1497 drm_i830_private_t *dev_priv = dev->dev_private;
1498 drm_i830_setparam_t param;
1499
1500 if (!dev_priv) {
1501 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1502 return -EINVAL;
1503 }
1504
1505 if (copy_from_user
1506 (&param, (drm_i830_setparam_t __user *) arg, sizeof(param)))
1507 return -EFAULT;
1508
1509 switch (param.param) {
1510 case I830_SETPARAM_USE_MI_BATCHBUFFER_START:
1511 dev_priv->use_mi_batchbuffer_start = param.value;
1512 break;
1513 default:
1514 return -EINVAL;
1515 }
1516
1517 return 0;
1518 }
1519
1520 void i830_driver_pretakedown(drm_device_t * dev)
1521 {
1522 i830_dma_cleanup(dev);
1523 }
1524
1525 void i830_driver_prerelease(drm_device_t * dev, DRMFILE filp)
1526 {
1527 if (dev->dev_private) {
1528 drm_i830_private_t *dev_priv = dev->dev_private;
1529 if (dev_priv->page_flipping) {
1530 i830_do_cleanup_pageflip(dev);
1531 }
1532 }
1533 }
1534
1535 void i830_driver_release(drm_device_t * dev, struct file *filp)
1536 {
1537 i830_reclaim_buffers(dev, filp);
1538 }
1539
1540 int i830_driver_dma_quiescent(drm_device_t * dev)
1541 {
1542 i830_dma_quiescent(dev);
1543 return 0;
1544 }
1545
1546 drm_ioctl_desc_t i830_ioctls[] = {
1547 [DRM_IOCTL_NR(DRM_I830_INIT)] = {i830_dma_init, 1, 1},
1548 [DRM_IOCTL_NR(DRM_I830_VERTEX)] = {i830_dma_vertex, 1, 0},
1549 [DRM_IOCTL_NR(DRM_I830_CLEAR)] = {i830_clear_bufs, 1, 0},
1550 [DRM_IOCTL_NR(DRM_I830_FLUSH)] = {i830_flush_ioctl, 1, 0},
1551 [DRM_IOCTL_NR(DRM_I830_GETAGE)] = {i830_getage, 1, 0},
1552 [DRM_IOCTL_NR(DRM_I830_GETBUF)] = {i830_getbuf, 1, 0},
1553 [DRM_IOCTL_NR(DRM_I830_SWAP)] = {i830_swap_bufs, 1, 0},
1554 [DRM_IOCTL_NR(DRM_I830_COPY)] = {i830_copybuf, 1, 0},
1555 [DRM_IOCTL_NR(DRM_I830_DOCOPY)] = {i830_docopy, 1, 0},
1556 [DRM_IOCTL_NR(DRM_I830_FLIP)] = {i830_flip_bufs, 1, 0},
1557 [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT)] = {i830_irq_emit, 1, 0},
1558 [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT)] = {i830_irq_wait, 1, 0},
1559 [DRM_IOCTL_NR(DRM_I830_GETPARAM)] = {i830_getparam, 1, 0},
1560 [DRM_IOCTL_NR(DRM_I830_SETPARAM)] = {i830_setparam, 1, 0}
1561 };
1562
1563 int i830_max_ioctl = DRM_ARRAY_SIZE(i830_ioctls);
1564
1565 /**
1566 * Determine if the device really is AGP or not.
1567 *
1568 * All Intel graphics chipsets are treated as AGP, even if they are really
1569 * PCI-e.
1570 *
1571 * \param dev The device to be tested.
1572 *
1573 * \returns
1574 * A value of 1 is always retured to indictate every i8xx is AGP.
1575 */
1576 int i830_driver_device_is_agp(drm_device_t * dev)
1577 {
1578 return 1;
1579 }
kernel-based virtual machine