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Revert "rt2x00: Fix rt2800usb TX descriptor writing."
[linux-2.6/kvm.git] / drivers / serial / sh-sci.c
blob8d993c4cceac6e92d8aed9a465e956a1139ae3ba
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #define SUPPORT_SYSRQ
24 #endif
25
26 #undef DEBUG
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50 #include <linux/list.h>
51 #include <linux/dmaengine.h>
52 #include <linux/scatterlist.h>
53 #include <linux/slab.h>
54
55 #ifdef CONFIG_SUPERH
56 #include <asm/sh_bios.h>
57 #endif
58
59 #ifdef CONFIG_H8300
60 #include <asm/gpio.h>
61 #endif
62
63 #include "sh-sci.h"
64
65 struct sci_port {
66 struct uart_port port;
67
68 /* Port type */
69 unsigned int type;
70
71 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
72 unsigned int irqs[SCIx_NR_IRQS];
73
74 /* Port enable callback */
75 void (*enable)(struct uart_port *port);
76
77 /* Port disable callback */
78 void (*disable)(struct uart_port *port);
79
80 /* Break timer */
81 struct timer_list break_timer;
82 int break_flag;
83
84 /* Interface clock */
85 struct clk *iclk;
86 /* Function clock */
87 struct clk *fclk;
88
89 struct list_head node;
90 struct dma_chan *chan_tx;
91 struct dma_chan *chan_rx;
92 #ifdef CONFIG_SERIAL_SH_SCI_DMA
93 struct device *dma_dev;
94 unsigned int slave_tx;
95 unsigned int slave_rx;
96 struct dma_async_tx_descriptor *desc_tx;
97 struct dma_async_tx_descriptor *desc_rx[2];
98 dma_cookie_t cookie_tx;
99 dma_cookie_t cookie_rx[2];
100 dma_cookie_t active_rx;
101 struct scatterlist sg_tx;
102 unsigned int sg_len_tx;
103 struct scatterlist sg_rx[2];
104 size_t buf_len_rx;
105 struct sh_dmae_slave param_tx;
106 struct sh_dmae_slave param_rx;
107 struct work_struct work_tx;
108 struct work_struct work_rx;
109 struct timer_list rx_timer;
110 unsigned int rx_timeout;
111 #endif
112 };
113
114 struct sh_sci_priv {
115 spinlock_t lock;
116 struct list_head ports;
117 struct notifier_block clk_nb;
118 };
119
120 /* Function prototypes */
121 static void sci_stop_tx(struct uart_port *port);
122
123 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
124
125 static struct sci_port sci_ports[SCI_NPORTS];
126 static struct uart_driver sci_uart_driver;
127
128 static inline struct sci_port *
129 to_sci_port(struct uart_port *uart)
130 {
131 return container_of(uart, struct sci_port, port);
132 }
133
134 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
135
136 #ifdef CONFIG_CONSOLE_POLL
137 static inline void handle_error(struct uart_port *port)
138 {
139 /* Clear error flags */
140 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
141 }
142
143 static int sci_poll_get_char(struct uart_port *port)
144 {
145 unsigned short status;
146 int c;
147
148 do {
149 status = sci_in(port, SCxSR);
150 if (status & SCxSR_ERRORS(port)) {
151 handle_error(port);
152 continue;
153 }
154 } while (!(status & SCxSR_RDxF(port)));
155
156 c = sci_in(port, SCxRDR);
157
158 /* Dummy read */
159 sci_in(port, SCxSR);
160 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
161
162 return c;
163 }
164 #endif
165
166 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
167 {
168 unsigned short status;
169
170 do {
171 status = sci_in(port, SCxSR);
172 } while (!(status & SCxSR_TDxE(port)));
173
174 sci_out(port, SCxTDR, c);
175 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
176 }
177 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
178
179 #if defined(__H8300H__) || defined(__H8300S__)
180 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
181 {
182 int ch = (port->mapbase - SMR0) >> 3;
183
184 /* set DDR regs */
185 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
186 h8300_sci_pins[ch].rx,
187 H8300_GPIO_INPUT);
188 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
189 h8300_sci_pins[ch].tx,
190 H8300_GPIO_OUTPUT);
191
192 /* tx mark output*/
193 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
194 }
195 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
196 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
197 {
198 if (port->mapbase == 0xA4400000) {
199 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
200 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
201 } else if (port->mapbase == 0xA4410000)
202 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
203 }
204 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
205 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
206 {
207 unsigned short data;
208
209 if (cflag & CRTSCTS) {
210 /* enable RTS/CTS */
211 if (port->mapbase == 0xa4430000) { /* SCIF0 */
212 /* Clear PTCR bit 9-2; enable all scif pins but sck */
213 data = __raw_readw(PORT_PTCR);
214 __raw_writew((data & 0xfc03), PORT_PTCR);
215 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
216 /* Clear PVCR bit 9-2 */
217 data = __raw_readw(PORT_PVCR);
218 __raw_writew((data & 0xfc03), PORT_PVCR);
219 }
220 } else {
221 if (port->mapbase == 0xa4430000) { /* SCIF0 */
222 /* Clear PTCR bit 5-2; enable only tx and rx */
223 data = __raw_readw(PORT_PTCR);
224 __raw_writew((data & 0xffc3), PORT_PTCR);
225 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
226 /* Clear PVCR bit 5-2 */
227 data = __raw_readw(PORT_PVCR);
228 __raw_writew((data & 0xffc3), PORT_PVCR);
229 }
230 }
231 }
232 #elif defined(CONFIG_CPU_SH3)
233 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
234 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
235 {
236 unsigned short data;
237
238 /* We need to set SCPCR to enable RTS/CTS */
239 data = __raw_readw(SCPCR);
240 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
241 __raw_writew(data & 0x0fcf, SCPCR);
242
243 if (!(cflag & CRTSCTS)) {
244 /* We need to set SCPCR to enable RTS/CTS */
245 data = __raw_readw(SCPCR);
246 /* Clear out SCP7MD1,0, SCP4MD1,0,
247 Set SCP6MD1,0 = {01} (output) */
248 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
249
250 data = __raw_readb(SCPDR);
251 /* Set /RTS2 (bit6) = 0 */
252 __raw_writeb(data & 0xbf, SCPDR);
253 }
254 }
255 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
256 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
257 {
258 unsigned short data;
259
260 if (port->mapbase == 0xffe00000) {
261 data = __raw_readw(PSCR);
262 data &= ~0x03cf;
263 if (!(cflag & CRTSCTS))
264 data |= 0x0340;
265
266 __raw_writew(data, PSCR);
267 }
268 }
269 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
270 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
271 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
272 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
273 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
274 defined(CONFIG_CPU_SUBTYPE_SHX3)
275 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
276 {
277 if (!(cflag & CRTSCTS))
278 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
279 }
280 #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
281 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
282 {
283 if (!(cflag & CRTSCTS))
284 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
285 }
286 #else
287 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
288 {
289 /* Nothing to do */
290 }
291 #endif
292
293 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
294 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
295 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
296 defined(CONFIG_CPU_SUBTYPE_SH7786)
297 static int scif_txfill(struct uart_port *port)
298 {
299 return sci_in(port, SCTFDR) & 0xff;
300 }
301
302 static int scif_txroom(struct uart_port *port)
303 {
304 return SCIF_TXROOM_MAX - scif_txfill(port);
305 }
306
307 static int scif_rxfill(struct uart_port *port)
308 {
309 return sci_in(port, SCRFDR) & 0xff;
310 }
311 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
312 static int scif_txfill(struct uart_port *port)
313 {
314 if (port->mapbase == 0xffe00000 ||
315 port->mapbase == 0xffe08000)
316 /* SCIF0/1*/
317 return sci_in(port, SCTFDR) & 0xff;
318 else
319 /* SCIF2 */
320 return sci_in(port, SCFDR) >> 8;
321 }
322
323 static int scif_txroom(struct uart_port *port)
324 {
325 if (port->mapbase == 0xffe00000 ||
326 port->mapbase == 0xffe08000)
327 /* SCIF0/1*/
328 return SCIF_TXROOM_MAX - scif_txfill(port);
329 else
330 /* SCIF2 */
331 return SCIF2_TXROOM_MAX - scif_txfill(port);
332 }
333
334 static int scif_rxfill(struct uart_port *port)
335 {
336 if ((port->mapbase == 0xffe00000) ||
337 (port->mapbase == 0xffe08000)) {
338 /* SCIF0/1*/
339 return sci_in(port, SCRFDR) & 0xff;
340 } else {
341 /* SCIF2 */
342 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
343 }
344 }
345 #else
346 static int scif_txfill(struct uart_port *port)
347 {
348 return sci_in(port, SCFDR) >> 8;
349 }
350
351 static int scif_txroom(struct uart_port *port)
352 {
353 return SCIF_TXROOM_MAX - scif_txfill(port);
354 }
355
356 static int scif_rxfill(struct uart_port *port)
357 {
358 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
359 }
360 #endif
361
362 static int sci_txfill(struct uart_port *port)
363 {
364 return !(sci_in(port, SCxSR) & SCI_TDRE);
365 }
366
367 static int sci_txroom(struct uart_port *port)
368 {
369 return !sci_txfill(port);
370 }
371
372 static int sci_rxfill(struct uart_port *port)
373 {
374 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
375 }
376
377 /* ********************************************************************** *
378 * the interrupt related routines *
379 * ********************************************************************** */
380
381 static void sci_transmit_chars(struct uart_port *port)
382 {
383 struct circ_buf *xmit = &port->state->xmit;
384 unsigned int stopped = uart_tx_stopped(port);
385 unsigned short status;
386 unsigned short ctrl;
387 int count;
388
389 status = sci_in(port, SCxSR);
390 if (!(status & SCxSR_TDxE(port))) {
391 ctrl = sci_in(port, SCSCR);
392 if (uart_circ_empty(xmit))
393 ctrl &= ~SCI_CTRL_FLAGS_TIE;
394 else
395 ctrl |= SCI_CTRL_FLAGS_TIE;
396 sci_out(port, SCSCR, ctrl);
397 return;
398 }
399
400 if (port->type == PORT_SCI)
401 count = sci_txroom(port);
402 else
403 count = scif_txroom(port);
404
405 do {
406 unsigned char c;
407
408 if (port->x_char) {
409 c = port->x_char;
410 port->x_char = 0;
411 } else if (!uart_circ_empty(xmit) && !stopped) {
412 c = xmit->buf[xmit->tail];
413 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
414 } else {
415 break;
416 }
417
418 sci_out(port, SCxTDR, c);
419
420 port->icount.tx++;
421 } while (--count > 0);
422
423 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
424
425 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
426 uart_write_wakeup(port);
427 if (uart_circ_empty(xmit)) {
428 sci_stop_tx(port);
429 } else {
430 ctrl = sci_in(port, SCSCR);
431
432 if (port->type != PORT_SCI) {
433 sci_in(port, SCxSR); /* Dummy read */
434 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
435 }
436
437 ctrl |= SCI_CTRL_FLAGS_TIE;
438 sci_out(port, SCSCR, ctrl);
439 }
440 }
441
442 /* On SH3, SCIF may read end-of-break as a space->mark char */
443 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
444
445 static inline void sci_receive_chars(struct uart_port *port)
446 {
447 struct sci_port *sci_port = to_sci_port(port);
448 struct tty_struct *tty = port->state->port.tty;
449 int i, count, copied = 0;
450 unsigned short status;
451 unsigned char flag;
452
453 status = sci_in(port, SCxSR);
454 if (!(status & SCxSR_RDxF(port)))
455 return;
456
457 while (1) {
458 if (port->type == PORT_SCI)
459 count = sci_rxfill(port);
460 else
461 count = scif_rxfill(port);
462
463 /* Don't copy more bytes than there is room for in the buffer */
464 count = tty_buffer_request_room(tty, count);
465
466 /* If for any reason we can't copy more data, we're done! */
467 if (count == 0)
468 break;
469
470 if (port->type == PORT_SCI) {
471 char c = sci_in(port, SCxRDR);
472 if (uart_handle_sysrq_char(port, c) ||
473 sci_port->break_flag)
474 count = 0;
475 else
476 tty_insert_flip_char(tty, c, TTY_NORMAL);
477 } else {
478 for (i = 0; i < count; i++) {
479 char c = sci_in(port, SCxRDR);
480 status = sci_in(port, SCxSR);
481 #if defined(CONFIG_CPU_SH3)
482 /* Skip "chars" during break */
483 if (sci_port->break_flag) {
484 if ((c == 0) &&
485 (status & SCxSR_FER(port))) {
486 count--; i--;
487 continue;
488 }
489
490 /* Nonzero => end-of-break */
491 dev_dbg(port->dev, "debounce<%02x>\n", c);
492 sci_port->break_flag = 0;
493
494 if (STEPFN(c)) {
495 count--; i--;
496 continue;
497 }
498 }
499 #endif /* CONFIG_CPU_SH3 */
500 if (uart_handle_sysrq_char(port, c)) {
501 count--; i--;
502 continue;
503 }
504
505 /* Store data and status */
506 if (status & SCxSR_FER(port)) {
507 flag = TTY_FRAME;
508 dev_notice(port->dev, "frame error\n");
509 } else if (status & SCxSR_PER(port)) {
510 flag = TTY_PARITY;
511 dev_notice(port->dev, "parity error\n");
512 } else
513 flag = TTY_NORMAL;
514
515 tty_insert_flip_char(tty, c, flag);
516 }
517 }
518
519 sci_in(port, SCxSR); /* dummy read */
520 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
521
522 copied += count;
523 port->icount.rx += count;
524 }
525
526 if (copied) {
527 /* Tell the rest of the system the news. New characters! */
528 tty_flip_buffer_push(tty);
529 } else {
530 sci_in(port, SCxSR); /* dummy read */
531 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
532 }
533 }
534
535 #define SCI_BREAK_JIFFIES (HZ/20)
536 /* The sci generates interrupts during the break,
537 * 1 per millisecond or so during the break period, for 9600 baud.
538 * So dont bother disabling interrupts.
539 * But dont want more than 1 break event.
540 * Use a kernel timer to periodically poll the rx line until
541 * the break is finished.
542 */
543 static void sci_schedule_break_timer(struct sci_port *port)
544 {
545 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
546 add_timer(&port->break_timer);
547 }
548 /* Ensure that two consecutive samples find the break over. */
549 static void sci_break_timer(unsigned long data)
550 {
551 struct sci_port *port = (struct sci_port *)data;
552
553 if (sci_rxd_in(&port->port) == 0) {
554 port->break_flag = 1;
555 sci_schedule_break_timer(port);
556 } else if (port->break_flag == 1) {
557 /* break is over. */
558 port->break_flag = 2;
559 sci_schedule_break_timer(port);
560 } else
561 port->break_flag = 0;
562 }
563
564 static inline int sci_handle_errors(struct uart_port *port)
565 {
566 int copied = 0;
567 unsigned short status = sci_in(port, SCxSR);
568 struct tty_struct *tty = port->state->port.tty;
569
570 if (status & SCxSR_ORER(port)) {
571 /* overrun error */
572 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
573 copied++;
574
575 dev_notice(port->dev, "overrun error");
576 }
577
578 if (status & SCxSR_FER(port)) {
579 if (sci_rxd_in(port) == 0) {
580 /* Notify of BREAK */
581 struct sci_port *sci_port = to_sci_port(port);
582
583 if (!sci_port->break_flag) {
584 sci_port->break_flag = 1;
585 sci_schedule_break_timer(sci_port);
586
587 /* Do sysrq handling. */
588 if (uart_handle_break(port))
589 return 0;
590
591 dev_dbg(port->dev, "BREAK detected\n");
592
593 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
594 copied++;
595 }
596
597 } else {
598 /* frame error */
599 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
600 copied++;
601
602 dev_notice(port->dev, "frame error\n");
603 }
604 }
605
606 if (status & SCxSR_PER(port)) {
607 /* parity error */
608 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
609 copied++;
610
611 dev_notice(port->dev, "parity error");
612 }
613
614 if (copied)
615 tty_flip_buffer_push(tty);
616
617 return copied;
618 }
619
620 static inline int sci_handle_fifo_overrun(struct uart_port *port)
621 {
622 struct tty_struct *tty = port->state->port.tty;
623 int copied = 0;
624
625 if (port->type != PORT_SCIF)
626 return 0;
627
628 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
629 sci_out(port, SCLSR, 0);
630
631 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
632 tty_flip_buffer_push(tty);
633
634 dev_notice(port->dev, "overrun error\n");
635 copied++;
636 }
637
638 return copied;
639 }
640
641 static inline int sci_handle_breaks(struct uart_port *port)
642 {
643 int copied = 0;
644 unsigned short status = sci_in(port, SCxSR);
645 struct tty_struct *tty = port->state->port.tty;
646 struct sci_port *s = to_sci_port(port);
647
648 if (uart_handle_break(port))
649 return 0;
650
651 if (!s->break_flag && status & SCxSR_BRK(port)) {
652 #if defined(CONFIG_CPU_SH3)
653 /* Debounce break */
654 s->break_flag = 1;
655 #endif
656 /* Notify of BREAK */
657 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
658 copied++;
659
660 dev_dbg(port->dev, "BREAK detected\n");
661 }
662
663 if (copied)
664 tty_flip_buffer_push(tty);
665
666 copied += sci_handle_fifo_overrun(port);
667
668 return copied;
669 }
670
671 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
672 {
673 #ifdef CONFIG_SERIAL_SH_SCI_DMA
674 struct uart_port *port = ptr;
675 struct sci_port *s = to_sci_port(port);
676
677 if (s->chan_rx) {
678 u16 scr = sci_in(port, SCSCR);
679 u16 ssr = sci_in(port, SCxSR);
680
681 /* Disable future Rx interrupts */
682 if (port->type == PORT_SCIFA) {
683 disable_irq_nosync(irq);
684 scr |= 0x4000;
685 } else {
686 scr &= ~SCI_CTRL_FLAGS_RIE;
687 }
688 sci_out(port, SCSCR, scr);
689 /* Clear current interrupt */
690 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
691 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
692 jiffies, s->rx_timeout);
693 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
694
695 return IRQ_HANDLED;
696 }
697 #endif
698
699 /* I think sci_receive_chars has to be called irrespective
700 * of whether the I_IXOFF is set, otherwise, how is the interrupt
701 * to be disabled?
702 */
703 sci_receive_chars(ptr);
704
705 return IRQ_HANDLED;
706 }
707
708 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
709 {
710 struct uart_port *port = ptr;
711 unsigned long flags;
712
713 spin_lock_irqsave(&port->lock, flags);
714 sci_transmit_chars(port);
715 spin_unlock_irqrestore(&port->lock, flags);
716
717 return IRQ_HANDLED;
718 }
719
720 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
721 {
722 struct uart_port *port = ptr;
723
724 /* Handle errors */
725 if (port->type == PORT_SCI) {
726 if (sci_handle_errors(port)) {
727 /* discard character in rx buffer */
728 sci_in(port, SCxSR);
729 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
730 }
731 } else {
732 sci_handle_fifo_overrun(port);
733 sci_rx_interrupt(irq, ptr);
734 }
735
736 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
737
738 /* Kick the transmission */
739 sci_tx_interrupt(irq, ptr);
740
741 return IRQ_HANDLED;
742 }
743
744 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
745 {
746 struct uart_port *port = ptr;
747
748 /* Handle BREAKs */
749 sci_handle_breaks(port);
750 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
751
752 return IRQ_HANDLED;
753 }
754
755 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
756 {
757 unsigned short ssr_status, scr_status, err_enabled;
758 struct uart_port *port = ptr;
759 struct sci_port *s = to_sci_port(port);
760 irqreturn_t ret = IRQ_NONE;
761
762 ssr_status = sci_in(port, SCxSR);
763 scr_status = sci_in(port, SCSCR);
764 err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE);
765
766 /* Tx Interrupt */
767 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) &&
768 !s->chan_tx)
769 ret = sci_tx_interrupt(irq, ptr);
770 /*
771 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
772 * DR flags
773 */
774 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
775 (scr_status & SCI_CTRL_FLAGS_RIE))
776 ret = sci_rx_interrupt(irq, ptr);
777 /* Error Interrupt */
778 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
779 ret = sci_er_interrupt(irq, ptr);
780 /* Break Interrupt */
781 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
782 ret = sci_br_interrupt(irq, ptr);
783
784 return ret;
785 }
786
787 /*
788 * Here we define a transistion notifier so that we can update all of our
789 * ports' baud rate when the peripheral clock changes.
790 */
791 static int sci_notifier(struct notifier_block *self,
792 unsigned long phase, void *p)
793 {
794 struct sh_sci_priv *priv = container_of(self,
795 struct sh_sci_priv, clk_nb);
796 struct sci_port *sci_port;
797 unsigned long flags;
798
799 if ((phase == CPUFREQ_POSTCHANGE) ||
800 (phase == CPUFREQ_RESUMECHANGE)) {
801 spin_lock_irqsave(&priv->lock, flags);
802 list_for_each_entry(sci_port, &priv->ports, node)
803 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
804 spin_unlock_irqrestore(&priv->lock, flags);
805 }
806
807 return NOTIFY_OK;
808 }
809
810 static void sci_clk_enable(struct uart_port *port)
811 {
812 struct sci_port *sci_port = to_sci_port(port);
813
814 clk_enable(sci_port->iclk);
815 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
816 clk_enable(sci_port->fclk);
817 }
818
819 static void sci_clk_disable(struct uart_port *port)
820 {
821 struct sci_port *sci_port = to_sci_port(port);
822
823 clk_disable(sci_port->fclk);
824 clk_disable(sci_port->iclk);
825 }
826
827 static int sci_request_irq(struct sci_port *port)
828 {
829 int i;
830 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
831 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
832 sci_br_interrupt,
833 };
834 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
835 "SCI Transmit Data Empty", "SCI Break" };
836
837 if (port->irqs[0] == port->irqs[1]) {
838 if (unlikely(!port->irqs[0]))
839 return -ENODEV;
840
841 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
842 IRQF_DISABLED, "sci", port)) {
843 dev_err(port->port.dev, "Can't allocate IRQ\n");
844 return -ENODEV;
845 }
846 } else {
847 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
848 if (unlikely(!port->irqs[i]))
849 continue;
850
851 if (request_irq(port->irqs[i], handlers[i],
852 IRQF_DISABLED, desc[i], port)) {
853 dev_err(port->port.dev, "Can't allocate IRQ\n");
854 return -ENODEV;
855 }
856 }
857 }
858
859 return 0;
860 }
861
862 static void sci_free_irq(struct sci_port *port)
863 {
864 int i;
865
866 if (port->irqs[0] == port->irqs[1])
867 free_irq(port->irqs[0], port);
868 else {
869 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
870 if (!port->irqs[i])
871 continue;
872
873 free_irq(port->irqs[i], port);
874 }
875 }
876 }
877
878 static unsigned int sci_tx_empty(struct uart_port *port)
879 {
880 unsigned short status = sci_in(port, SCxSR);
881 unsigned short in_tx_fifo = scif_txfill(port);
882
883 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
884 }
885
886 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
887 {
888 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
889 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
890 /* If you have signals for DTR and DCD, please implement here. */
891 }
892
893 static unsigned int sci_get_mctrl(struct uart_port *port)
894 {
895 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
896 and CTS/RTS */
897
898 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
899 }
900
901 #ifdef CONFIG_SERIAL_SH_SCI_DMA
902 static void sci_dma_tx_complete(void *arg)
903 {
904 struct sci_port *s = arg;
905 struct uart_port *port = &s->port;
906 struct circ_buf *xmit = &port->state->xmit;
907 unsigned long flags;
908
909 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
910
911 spin_lock_irqsave(&port->lock, flags);
912
913 xmit->tail += sg_dma_len(&s->sg_tx);
914 xmit->tail &= UART_XMIT_SIZE - 1;
915
916 port->icount.tx += sg_dma_len(&s->sg_tx);
917
918 async_tx_ack(s->desc_tx);
919 s->cookie_tx = -EINVAL;
920 s->desc_tx = NULL;
921
922 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
923 uart_write_wakeup(port);
924
925 if (!uart_circ_empty(xmit)) {
926 schedule_work(&s->work_tx);
927 } else if (port->type == PORT_SCIFA) {
928 u16 ctrl = sci_in(port, SCSCR);
929 sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE);
930 }
931
932 spin_unlock_irqrestore(&port->lock, flags);
933 }
934
935 /* Locking: called with port lock held */
936 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
937 size_t count)
938 {
939 struct uart_port *port = &s->port;
940 int i, active, room;
941
942 room = tty_buffer_request_room(tty, count);
943
944 if (s->active_rx == s->cookie_rx[0]) {
945 active = 0;
946 } else if (s->active_rx == s->cookie_rx[1]) {
947 active = 1;
948 } else {
949 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
950 return 0;
951 }
952
953 if (room < count)
954 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
955 count - room);
956 if (!room)
957 return room;
958
959 for (i = 0; i < room; i++)
960 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
961 TTY_NORMAL);
962
963 port->icount.rx += room;
964
965 return room;
966 }
967
968 static void sci_dma_rx_complete(void *arg)
969 {
970 struct sci_port *s = arg;
971 struct uart_port *port = &s->port;
972 struct tty_struct *tty = port->state->port.tty;
973 unsigned long flags;
974 int count;
975
976 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
977
978 spin_lock_irqsave(&port->lock, flags);
979
980 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
981
982 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
983
984 spin_unlock_irqrestore(&port->lock, flags);
985
986 if (count)
987 tty_flip_buffer_push(tty);
988
989 schedule_work(&s->work_rx);
990 }
991
992 static void sci_start_rx(struct uart_port *port);
993 static void sci_start_tx(struct uart_port *port);
994
995 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
996 {
997 struct dma_chan *chan = s->chan_rx;
998 struct uart_port *port = &s->port;
999
1000 s->chan_rx = NULL;
1001 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1002 dma_release_channel(chan);
1003 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1004 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1005 if (enable_pio)
1006 sci_start_rx(port);
1007 }
1008
1009 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1010 {
1011 struct dma_chan *chan = s->chan_tx;
1012 struct uart_port *port = &s->port;
1013
1014 s->chan_tx = NULL;
1015 s->cookie_tx = -EINVAL;
1016 dma_release_channel(chan);
1017 if (enable_pio)
1018 sci_start_tx(port);
1019 }
1020
1021 static void sci_submit_rx(struct sci_port *s)
1022 {
1023 struct dma_chan *chan = s->chan_rx;
1024 int i;
1025
1026 for (i = 0; i < 2; i++) {
1027 struct scatterlist *sg = &s->sg_rx[i];
1028 struct dma_async_tx_descriptor *desc;
1029
1030 desc = chan->device->device_prep_slave_sg(chan,
1031 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1032
1033 if (desc) {
1034 s->desc_rx[i] = desc;
1035 desc->callback = sci_dma_rx_complete;
1036 desc->callback_param = s;
1037 s->cookie_rx[i] = desc->tx_submit(desc);
1038 }
1039
1040 if (!desc || s->cookie_rx[i] < 0) {
1041 if (i) {
1042 async_tx_ack(s->desc_rx[0]);
1043 s->cookie_rx[0] = -EINVAL;
1044 }
1045 if (desc) {
1046 async_tx_ack(desc);
1047 s->cookie_rx[i] = -EINVAL;
1048 }
1049 dev_warn(s->port.dev,
1050 "failed to re-start DMA, using PIO\n");
1051 sci_rx_dma_release(s, true);
1052 return;
1053 }
1054 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1055 s->cookie_rx[i], i);
1056 }
1057
1058 s->active_rx = s->cookie_rx[0];
1059
1060 dma_async_issue_pending(chan);
1061 }
1062
1063 static void work_fn_rx(struct work_struct *work)
1064 {
1065 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1066 struct uart_port *port = &s->port;
1067 struct dma_async_tx_descriptor *desc;
1068 int new;
1069
1070 if (s->active_rx == s->cookie_rx[0]) {
1071 new = 0;
1072 } else if (s->active_rx == s->cookie_rx[1]) {
1073 new = 1;
1074 } else {
1075 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1076 return;
1077 }
1078 desc = s->desc_rx[new];
1079
1080 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1081 DMA_SUCCESS) {
1082 /* Handle incomplete DMA receive */
1083 struct tty_struct *tty = port->state->port.tty;
1084 struct dma_chan *chan = s->chan_rx;
1085 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1086 async_tx);
1087 unsigned long flags;
1088 int count;
1089
1090 chan->device->device_terminate_all(chan);
1091 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1092 sh_desc->partial, sh_desc->cookie);
1093
1094 spin_lock_irqsave(&port->lock, flags);
1095 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1096 spin_unlock_irqrestore(&port->lock, flags);
1097
1098 if (count)
1099 tty_flip_buffer_push(tty);
1100
1101 sci_submit_rx(s);
1102
1103 return;
1104 }
1105
1106 s->cookie_rx[new] = desc->tx_submit(desc);
1107 if (s->cookie_rx[new] < 0) {
1108 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1109 sci_rx_dma_release(s, true);
1110 return;
1111 }
1112
1113 s->active_rx = s->cookie_rx[!new];
1114
1115 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1116 s->cookie_rx[new], new, s->active_rx);
1117 }
1118
1119 static void work_fn_tx(struct work_struct *work)
1120 {
1121 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1122 struct dma_async_tx_descriptor *desc;
1123 struct dma_chan *chan = s->chan_tx;
1124 struct uart_port *port = &s->port;
1125 struct circ_buf *xmit = &port->state->xmit;
1126 struct scatterlist *sg = &s->sg_tx;
1127
1128 /*
1129 * DMA is idle now.
1130 * Port xmit buffer is already mapped, and it is one page... Just adjust
1131 * offsets and lengths. Since it is a circular buffer, we have to
1132 * transmit till the end, and then the rest. Take the port lock to get a
1133 * consistent xmit buffer state.
1134 */
1135 spin_lock_irq(&port->lock);
1136 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1137 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1138 sg->offset;
1139 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1140 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1141 spin_unlock_irq(&port->lock);
1142
1143 BUG_ON(!sg_dma_len(sg));
1144
1145 desc = chan->device->device_prep_slave_sg(chan,
1146 sg, s->sg_len_tx, DMA_TO_DEVICE,
1147 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1148 if (!desc) {
1149 /* switch to PIO */
1150 sci_tx_dma_release(s, true);
1151 return;
1152 }
1153
1154 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1155
1156 spin_lock_irq(&port->lock);
1157 s->desc_tx = desc;
1158 desc->callback = sci_dma_tx_complete;
1159 desc->callback_param = s;
1160 spin_unlock_irq(&port->lock);
1161 s->cookie_tx = desc->tx_submit(desc);
1162 if (s->cookie_tx < 0) {
1163 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1164 /* switch to PIO */
1165 sci_tx_dma_release(s, true);
1166 return;
1167 }
1168
1169 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1170 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1171
1172 dma_async_issue_pending(chan);
1173 }
1174 #endif
1175
1176 static void sci_start_tx(struct uart_port *port)
1177 {
1178 struct sci_port *s = to_sci_port(port);
1179 unsigned short ctrl;
1180
1181 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1182 if (port->type == PORT_SCIFA) {
1183 u16 new, scr = sci_in(port, SCSCR);
1184 if (s->chan_tx)
1185 new = scr | 0x8000;
1186 else
1187 new = scr & ~0x8000;
1188 if (new != scr)
1189 sci_out(port, SCSCR, new);
1190 }
1191 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1192 s->cookie_tx < 0)
1193 schedule_work(&s->work_tx);
1194 #endif
1195 if (!s->chan_tx || port->type == PORT_SCIFA) {
1196 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1197 ctrl = sci_in(port, SCSCR);
1198 sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE);
1199 }
1200 }
1201
1202 static void sci_stop_tx(struct uart_port *port)
1203 {
1204 unsigned short ctrl;
1205
1206 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1207 ctrl = sci_in(port, SCSCR);
1208 if (port->type == PORT_SCIFA)
1209 ctrl &= ~0x8000;
1210 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1211 sci_out(port, SCSCR, ctrl);
1212 }
1213
1214 static void sci_start_rx(struct uart_port *port)
1215 {
1216 unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
1217
1218 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1219 ctrl |= sci_in(port, SCSCR);
1220 if (port->type == PORT_SCIFA)
1221 ctrl &= ~0x4000;
1222 sci_out(port, SCSCR, ctrl);
1223 }
1224
1225 static void sci_stop_rx(struct uart_port *port)
1226 {
1227 unsigned short ctrl;
1228
1229 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1230 ctrl = sci_in(port, SCSCR);
1231 if (port->type == PORT_SCIFA)
1232 ctrl &= ~0x4000;
1233 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1234 sci_out(port, SCSCR, ctrl);
1235 }
1236
1237 static void sci_enable_ms(struct uart_port *port)
1238 {
1239 /* Nothing here yet .. */
1240 }
1241
1242 static void sci_break_ctl(struct uart_port *port, int break_state)
1243 {
1244 /* Nothing here yet .. */
1245 }
1246
1247 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1248 static bool filter(struct dma_chan *chan, void *slave)
1249 {
1250 struct sh_dmae_slave *param = slave;
1251
1252 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1253 param->slave_id);
1254
1255 if (param->dma_dev == chan->device->dev) {
1256 chan->private = param;
1257 return true;
1258 } else {
1259 return false;
1260 }
1261 }
1262
1263 static void rx_timer_fn(unsigned long arg)
1264 {
1265 struct sci_port *s = (struct sci_port *)arg;
1266 struct uart_port *port = &s->port;
1267 u16 scr = sci_in(port, SCSCR);
1268
1269 if (port->type == PORT_SCIFA) {
1270 scr &= ~0x4000;
1271 enable_irq(s->irqs[1]);
1272 }
1273 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
1274 dev_dbg(port->dev, "DMA Rx timed out\n");
1275 schedule_work(&s->work_rx);
1276 }
1277
1278 static void sci_request_dma(struct uart_port *port)
1279 {
1280 struct sci_port *s = to_sci_port(port);
1281 struct sh_dmae_slave *param;
1282 struct dma_chan *chan;
1283 dma_cap_mask_t mask;
1284 int nent;
1285
1286 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1287 port->line, s->dma_dev);
1288
1289 if (!s->dma_dev)
1290 return;
1291
1292 dma_cap_zero(mask);
1293 dma_cap_set(DMA_SLAVE, mask);
1294
1295 param = &s->param_tx;
1296
1297 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1298 param->slave_id = s->slave_tx;
1299 param->dma_dev = s->dma_dev;
1300
1301 s->cookie_tx = -EINVAL;
1302 chan = dma_request_channel(mask, filter, param);
1303 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1304 if (chan) {
1305 s->chan_tx = chan;
1306 sg_init_table(&s->sg_tx, 1);
1307 /* UART circular tx buffer is an aligned page. */
1308 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1309 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1310 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1311 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1312 if (!nent)
1313 sci_tx_dma_release(s, false);
1314 else
1315 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1316 sg_dma_len(&s->sg_tx),
1317 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1318
1319 s->sg_len_tx = nent;
1320
1321 INIT_WORK(&s->work_tx, work_fn_tx);
1322 }
1323
1324 param = &s->param_rx;
1325
1326 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1327 param->slave_id = s->slave_rx;
1328 param->dma_dev = s->dma_dev;
1329
1330 chan = dma_request_channel(mask, filter, param);
1331 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1332 if (chan) {
1333 dma_addr_t dma[2];
1334 void *buf[2];
1335 int i;
1336
1337 s->chan_rx = chan;
1338
1339 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1340 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1341 &dma[0], GFP_KERNEL);
1342
1343 if (!buf[0]) {
1344 dev_warn(port->dev,
1345 "failed to allocate dma buffer, using PIO\n");
1346 sci_rx_dma_release(s, true);
1347 return;
1348 }
1349
1350 buf[1] = buf[0] + s->buf_len_rx;
1351 dma[1] = dma[0] + s->buf_len_rx;
1352
1353 for (i = 0; i < 2; i++) {
1354 struct scatterlist *sg = &s->sg_rx[i];
1355
1356 sg_init_table(sg, 1);
1357 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1358 (int)buf[i] & ~PAGE_MASK);
1359 sg_dma_address(sg) = dma[i];
1360 }
1361
1362 INIT_WORK(&s->work_rx, work_fn_rx);
1363 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1364
1365 sci_submit_rx(s);
1366 }
1367 }
1368
1369 static void sci_free_dma(struct uart_port *port)
1370 {
1371 struct sci_port *s = to_sci_port(port);
1372
1373 if (!s->dma_dev)
1374 return;
1375
1376 if (s->chan_tx)
1377 sci_tx_dma_release(s, false);
1378 if (s->chan_rx)
1379 sci_rx_dma_release(s, false);
1380 }
1381 #endif
1382
1383 static int sci_startup(struct uart_port *port)
1384 {
1385 struct sci_port *s = to_sci_port(port);
1386
1387 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1388
1389 if (s->enable)
1390 s->enable(port);
1391
1392 sci_request_irq(s);
1393 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1394 sci_request_dma(port);
1395 #endif
1396 sci_start_tx(port);
1397 sci_start_rx(port);
1398
1399 return 0;
1400 }
1401
1402 static void sci_shutdown(struct uart_port *port)
1403 {
1404 struct sci_port *s = to_sci_port(port);
1405
1406 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1407
1408 sci_stop_rx(port);
1409 sci_stop_tx(port);
1410 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1411 sci_free_dma(port);
1412 #endif
1413 sci_free_irq(s);
1414
1415 if (s->disable)
1416 s->disable(port);
1417 }
1418
1419 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1420 struct ktermios *old)
1421 {
1422 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1423 struct sci_port *s = to_sci_port(port);
1424 #endif
1425 unsigned int status, baud, smr_val, max_baud;
1426 int t = -1;
1427 u16 scfcr = 0;
1428
1429 /*
1430 * earlyprintk comes here early on with port->uartclk set to zero.
1431 * the clock framework is not up and running at this point so here
1432 * we assume that 115200 is the maximum baud rate. please note that
1433 * the baud rate is not programmed during earlyprintk - it is assumed
1434 * that the previous boot loader has enabled required clocks and
1435 * setup the baud rate generator hardware for us already.
1436 */
1437 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1438
1439 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1440 if (likely(baud && port->uartclk))
1441 t = SCBRR_VALUE(baud, port->uartclk);
1442
1443 do {
1444 status = sci_in(port, SCxSR);
1445 } while (!(status & SCxSR_TEND(port)));
1446
1447 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1448
1449 if (port->type != PORT_SCI)
1450 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1451
1452 smr_val = sci_in(port, SCSMR) & 3;
1453 if ((termios->c_cflag & CSIZE) == CS7)
1454 smr_val |= 0x40;
1455 if (termios->c_cflag & PARENB)
1456 smr_val |= 0x20;
1457 if (termios->c_cflag & PARODD)
1458 smr_val |= 0x30;
1459 if (termios->c_cflag & CSTOPB)
1460 smr_val |= 0x08;
1461
1462 uart_update_timeout(port, termios->c_cflag, baud);
1463
1464 sci_out(port, SCSMR, smr_val);
1465
1466 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1467 SCSCR_INIT(port));
1468
1469 if (t > 0) {
1470 if (t >= 256) {
1471 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1472 t >>= 2;
1473 } else
1474 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1475
1476 sci_out(port, SCBRR, t);
1477 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1478 }
1479
1480 sci_init_pins(port, termios->c_cflag);
1481 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
1482
1483 sci_out(port, SCSCR, SCSCR_INIT(port));
1484
1485 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1486 /*
1487 * Calculate delay for 1.5 DMA buffers: see
1488 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1489 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1490 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1491 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1492 * sizes), but it has been found out experimentally, that this is not
1493 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1494 * as a minimum seem to work perfectly.
1495 */
1496 if (s->chan_rx) {
1497 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1498 port->fifosize / 2;
1499 dev_dbg(port->dev,
1500 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1501 s->rx_timeout * 1000 / HZ, port->timeout);
1502 if (s->rx_timeout < msecs_to_jiffies(20))
1503 s->rx_timeout = msecs_to_jiffies(20);
1504 }
1505 #endif
1506
1507 if ((termios->c_cflag & CREAD) != 0)
1508 sci_start_rx(port);
1509 }
1510
1511 static const char *sci_type(struct uart_port *port)
1512 {
1513 switch (port->type) {
1514 case PORT_IRDA:
1515 return "irda";
1516 case PORT_SCI:
1517 return "sci";
1518 case PORT_SCIF:
1519 return "scif";
1520 case PORT_SCIFA:
1521 return "scifa";
1522 }
1523
1524 return NULL;
1525 }
1526
1527 static void sci_release_port(struct uart_port *port)
1528 {
1529 /* Nothing here yet .. */
1530 }
1531
1532 static int sci_request_port(struct uart_port *port)
1533 {
1534 /* Nothing here yet .. */
1535 return 0;
1536 }
1537
1538 static void sci_config_port(struct uart_port *port, int flags)
1539 {
1540 struct sci_port *s = to_sci_port(port);
1541
1542 port->type = s->type;
1543
1544 if (port->membase)
1545 return;
1546
1547 if (port->flags & UPF_IOREMAP) {
1548 port->membase = ioremap_nocache(port->mapbase, 0x40);
1549
1550 if (IS_ERR(port->membase))
1551 dev_err(port->dev, "can't remap port#%d\n", port->line);
1552 } else {
1553 /*
1554 * For the simple (and majority of) cases where we don't
1555 * need to do any remapping, just cast the cookie
1556 * directly.
1557 */
1558 port->membase = (void __iomem *)port->mapbase;
1559 }
1560 }
1561
1562 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1563 {
1564 struct sci_port *s = to_sci_port(port);
1565
1566 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1567 return -EINVAL;
1568 if (ser->baud_base < 2400)
1569 /* No paper tape reader for Mitch.. */
1570 return -EINVAL;
1571
1572 return 0;
1573 }
1574
1575 static struct uart_ops sci_uart_ops = {
1576 .tx_empty = sci_tx_empty,
1577 .set_mctrl = sci_set_mctrl,
1578 .get_mctrl = sci_get_mctrl,
1579 .start_tx = sci_start_tx,
1580 .stop_tx = sci_stop_tx,
1581 .stop_rx = sci_stop_rx,
1582 .enable_ms = sci_enable_ms,
1583 .break_ctl = sci_break_ctl,
1584 .startup = sci_startup,
1585 .shutdown = sci_shutdown,
1586 .set_termios = sci_set_termios,
1587 .type = sci_type,
1588 .release_port = sci_release_port,
1589 .request_port = sci_request_port,
1590 .config_port = sci_config_port,
1591 .verify_port = sci_verify_port,
1592 #ifdef CONFIG_CONSOLE_POLL
1593 .poll_get_char = sci_poll_get_char,
1594 .poll_put_char = sci_poll_put_char,
1595 #endif
1596 };
1597
1598 static int __devinit sci_init_single(struct platform_device *dev,
1599 struct sci_port *sci_port,
1600 unsigned int index,
1601 struct plat_sci_port *p)
1602 {
1603 struct uart_port *port = &sci_port->port;
1604
1605 port->ops = &sci_uart_ops;
1606 port->iotype = UPIO_MEM;
1607 port->line = index;
1608
1609 switch (p->type) {
1610 case PORT_SCIFA:
1611 port->fifosize = 64;
1612 break;
1613 case PORT_SCIF:
1614 port->fifosize = 16;
1615 break;
1616 default:
1617 port->fifosize = 1;
1618 break;
1619 }
1620
1621 if (dev) {
1622 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1623 if (IS_ERR(sci_port->iclk)) {
1624 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1625 if (IS_ERR(sci_port->iclk)) {
1626 dev_err(&dev->dev, "can't get iclk\n");
1627 return PTR_ERR(sci_port->iclk);
1628 }
1629 }
1630
1631 /*
1632 * The function clock is optional, ignore it if we can't
1633 * find it.
1634 */
1635 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1636 if (IS_ERR(sci_port->fclk))
1637 sci_port->fclk = NULL;
1638
1639 sci_port->enable = sci_clk_enable;
1640 sci_port->disable = sci_clk_disable;
1641 port->dev = &dev->dev;
1642 }
1643
1644 sci_port->break_timer.data = (unsigned long)sci_port;
1645 sci_port->break_timer.function = sci_break_timer;
1646 init_timer(&sci_port->break_timer);
1647
1648 port->mapbase = p->mapbase;
1649 port->membase = p->membase;
1650
1651 port->irq = p->irqs[SCIx_TXI_IRQ];
1652 port->flags = p->flags;
1653 sci_port->type = port->type = p->type;
1654
1655 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1656 sci_port->dma_dev = p->dma_dev;
1657 sci_port->slave_tx = p->dma_slave_tx;
1658 sci_port->slave_rx = p->dma_slave_rx;
1659
1660 dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__,
1661 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1662 #endif
1663
1664 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
1665 return 0;
1666 }
1667
1668 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1669 static struct tty_driver *serial_console_device(struct console *co, int *index)
1670 {
1671 struct uart_driver *p = &sci_uart_driver;
1672 *index = co->index;
1673 return p->tty_driver;
1674 }
1675
1676 static void serial_console_putchar(struct uart_port *port, int ch)
1677 {
1678 sci_poll_put_char(port, ch);
1679 }
1680
1681 /*
1682 * Print a string to the serial port trying not to disturb
1683 * any possible real use of the port...
1684 */
1685 static void serial_console_write(struct console *co, const char *s,
1686 unsigned count)
1687 {
1688 struct uart_port *port = co->data;
1689 struct sci_port *sci_port = to_sci_port(port);
1690 unsigned short bits;
1691
1692 if (sci_port->enable)
1693 sci_port->enable(port);
1694
1695 uart_console_write(port, s, count, serial_console_putchar);
1696
1697 /* wait until fifo is empty and last bit has been transmitted */
1698 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1699 while ((sci_in(port, SCxSR) & bits) != bits)
1700 cpu_relax();
1701
1702 if (sci_port->disable)
1703 sci_port->disable(port);
1704 }
1705
1706 static int __devinit serial_console_setup(struct console *co, char *options)
1707 {
1708 struct sci_port *sci_port;
1709 struct uart_port *port;
1710 int baud = 115200;
1711 int bits = 8;
1712 int parity = 'n';
1713 int flow = 'n';
1714 int ret;
1715
1716 /*
1717 * Check whether an invalid uart number has been specified, and
1718 * if so, search for the first available port that does have
1719 * console support.
1720 */
1721 if (co->index >= SCI_NPORTS)
1722 co->index = 0;
1723
1724 if (co->data) {
1725 port = co->data;
1726 sci_port = to_sci_port(port);
1727 } else {
1728 sci_port = &sci_ports[co->index];
1729 port = &sci_port->port;
1730 co->data = port;
1731 }
1732
1733 /*
1734 * Also need to check port->type, we don't actually have any
1735 * UPIO_PORT ports, but uart_report_port() handily misreports
1736 * it anyways if we don't have a port available by the time this is
1737 * called.
1738 */
1739 if (!port->type)
1740 return -ENODEV;
1741
1742 sci_config_port(port, 0);
1743
1744 if (sci_port->enable)
1745 sci_port->enable(port);
1746
1747 if (options)
1748 uart_parse_options(options, &baud, &parity, &bits, &flow);
1749
1750 ret = uart_set_options(port, co, baud, parity, bits, flow);
1751 #if defined(__H8300H__) || defined(__H8300S__)
1752 /* disable rx interrupt */
1753 if (ret == 0)
1754 sci_stop_rx(port);
1755 #endif
1756 /* TODO: disable clock */
1757 return ret;
1758 }
1759
1760 static struct console serial_console = {
1761 .name = "ttySC",
1762 .device = serial_console_device,
1763 .write = serial_console_write,
1764 .setup = serial_console_setup,
1765 .flags = CON_PRINTBUFFER,
1766 .index = -1,
1767 };
1768
1769 static int __init sci_console_init(void)
1770 {
1771 register_console(&serial_console);
1772 return 0;
1773 }
1774 console_initcall(sci_console_init);
1775
1776 static struct sci_port early_serial_port;
1777 static struct console early_serial_console = {
1778 .name = "early_ttySC",
1779 .write = serial_console_write,
1780 .flags = CON_PRINTBUFFER,
1781 };
1782 static char early_serial_buf[32];
1783
1784 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1785
1786 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1787 #define SCI_CONSOLE (&serial_console)
1788 #else
1789 #define SCI_CONSOLE 0
1790 #endif
1791
1792 static char banner[] __initdata =
1793 KERN_INFO "SuperH SCI(F) driver initialized\n";
1794
1795 static struct uart_driver sci_uart_driver = {
1796 .owner = THIS_MODULE,
1797 .driver_name = "sci",
1798 .dev_name = "ttySC",
1799 .major = SCI_MAJOR,
1800 .minor = SCI_MINOR_START,
1801 .nr = SCI_NPORTS,
1802 .cons = SCI_CONSOLE,
1803 };
1804
1805
1806 static int sci_remove(struct platform_device *dev)
1807 {
1808 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1809 struct sci_port *p;
1810 unsigned long flags;
1811
1812 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1813
1814 spin_lock_irqsave(&priv->lock, flags);
1815 list_for_each_entry(p, &priv->ports, node) {
1816 uart_remove_one_port(&sci_uart_driver, &p->port);
1817 clk_put(p->iclk);
1818 clk_put(p->fclk);
1819 }
1820 spin_unlock_irqrestore(&priv->lock, flags);
1821
1822 kfree(priv);
1823 return 0;
1824 }
1825
1826 static int __devinit sci_probe_single(struct platform_device *dev,
1827 unsigned int index,
1828 struct plat_sci_port *p,
1829 struct sci_port *sciport)
1830 {
1831 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1832 unsigned long flags;
1833 int ret;
1834
1835 /* Sanity check */
1836 if (unlikely(index >= SCI_NPORTS)) {
1837 dev_notice(&dev->dev, "Attempting to register port "
1838 "%d when only %d are available.\n",
1839 index+1, SCI_NPORTS);
1840 dev_notice(&dev->dev, "Consider bumping "
1841 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1842 return 0;
1843 }
1844
1845 ret = sci_init_single(dev, sciport, index, p);
1846 if (ret)
1847 return ret;
1848
1849 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
1850 if (ret)
1851 return ret;
1852
1853 INIT_LIST_HEAD(&sciport->node);
1854
1855 spin_lock_irqsave(&priv->lock, flags);
1856 list_add(&sciport->node, &priv->ports);
1857 spin_unlock_irqrestore(&priv->lock, flags);
1858
1859 return 0;
1860 }
1861
1862 /*
1863 * Register a set of serial devices attached to a platform device. The
1864 * list is terminated with a zero flags entry, which means we expect
1865 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1866 * remapping (such as sh64) should also set UPF_IOREMAP.
1867 */
1868 static int __devinit sci_probe(struct platform_device *dev)
1869 {
1870 struct plat_sci_port *p = dev->dev.platform_data;
1871 struct sh_sci_priv *priv;
1872 int i, ret = -EINVAL;
1873
1874 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1875 if (is_early_platform_device(dev)) {
1876 if (dev->id == -1)
1877 return -ENOTSUPP;
1878 early_serial_console.index = dev->id;
1879 early_serial_console.data = &early_serial_port.port;
1880 sci_init_single(NULL, &early_serial_port, dev->id, p);
1881 serial_console_setup(&early_serial_console, early_serial_buf);
1882 if (!strstr(early_serial_buf, "keep"))
1883 early_serial_console.flags |= CON_BOOT;
1884 register_console(&early_serial_console);
1885 return 0;
1886 }
1887 #endif
1888
1889 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1890 if (!priv)
1891 return -ENOMEM;
1892
1893 INIT_LIST_HEAD(&priv->ports);
1894 spin_lock_init(&priv->lock);
1895 platform_set_drvdata(dev, priv);
1896
1897 priv->clk_nb.notifier_call = sci_notifier;
1898 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1899
1900 if (dev->id != -1) {
1901 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1902 if (ret)
1903 goto err_unreg;
1904 } else {
1905 for (i = 0; p && p->flags != 0; p++, i++) {
1906 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1907 if (ret)
1908 goto err_unreg;
1909 }
1910 }
1911
1912 #ifdef CONFIG_SH_STANDARD_BIOS
1913 sh_bios_gdb_detach();
1914 #endif
1915
1916 return 0;
1917
1918 err_unreg:
1919 sci_remove(dev);
1920 return ret;
1921 }
1922
1923 static int sci_suspend(struct device *dev)
1924 {
1925 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1926 struct sci_port *p;
1927 unsigned long flags;
1928
1929 spin_lock_irqsave(&priv->lock, flags);
1930 list_for_each_entry(p, &priv->ports, node)
1931 uart_suspend_port(&sci_uart_driver, &p->port);
1932 spin_unlock_irqrestore(&priv->lock, flags);
1933
1934 return 0;
1935 }
1936
1937 static int sci_resume(struct device *dev)
1938 {
1939 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1940 struct sci_port *p;
1941 unsigned long flags;
1942
1943 spin_lock_irqsave(&priv->lock, flags);
1944 list_for_each_entry(p, &priv->ports, node)
1945 uart_resume_port(&sci_uart_driver, &p->port);
1946 spin_unlock_irqrestore(&priv->lock, flags);
1947
1948 return 0;
1949 }
1950
1951 static const struct dev_pm_ops sci_dev_pm_ops = {
1952 .suspend = sci_suspend,
1953 .resume = sci_resume,
1954 };
1955
1956 static struct platform_driver sci_driver = {
1957 .probe = sci_probe,
1958 .remove = sci_remove,
1959 .driver = {
1960 .name = "sh-sci",
1961 .owner = THIS_MODULE,
1962 .pm = &sci_dev_pm_ops,
1963 },
1964 };
1965
1966 static int __init sci_init(void)
1967 {
1968 int ret;
1969
1970 printk(banner);
1971
1972 ret = uart_register_driver(&sci_uart_driver);
1973 if (likely(ret == 0)) {
1974 ret = platform_driver_register(&sci_driver);
1975 if (unlikely(ret))
1976 uart_unregister_driver(&sci_uart_driver);
1977 }
1978
1979 return ret;
1980 }
1981
1982 static void __exit sci_exit(void)
1983 {
1984 platform_driver_unregister(&sci_driver);
1985 uart_unregister_driver(&sci_uart_driver);
1986 }
1987
1988 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1989 early_platform_init_buffer("earlyprintk", &sci_driver,
1990 early_serial_buf, ARRAY_SIZE(early_serial_buf));
1991 #endif
1992 module_init(sci_init);
1993 module_exit(sci_exit);
1994
1995 MODULE_LICENSE("GPL");
1996 MODULE_ALIAS("platform:sh-sci");
kernel-based virtual machine