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Revert "rt2x00: Fix rt2800usb TX descriptor writing."
[linux-2.6/kvm.git] / drivers / serial / bfin_sport_uart.c
blobc88f8ad3ff821d16fef218c5021adede8c9c6cf1
1 /*
2 * Blackfin On-Chip Sport Emulated UART Driver
3 *
4 * Copyright 2006-2009 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 /*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
13 * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
16 * Transmit Frame Sync is not used by this driver to transfer data out.
17 */
18
19 /* #define DEBUG */
20
21 #define DRV_NAME "bfin-sport-uart"
22 #define DEVICE_NAME "ttySS"
23 #define pr_fmt(fmt) DRV_NAME ": " fmt
24
25 #include <linux/module.h>
26 #include <linux/ioport.h>
27 #include <linux/io.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/slab.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_core.h>
36
37 #include <asm/delay.h>
38 #include <asm/portmux.h>
39
40 #include "bfin_sport_uart.h"
41
42 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
43 unsigned short bfin_uart_pin_req_sport0[] =
44 {P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, \
45 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0};
46 #endif
47 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
48 unsigned short bfin_uart_pin_req_sport1[] =
49 {P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, \
50 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0};
51 #endif
52 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
53 unsigned short bfin_uart_pin_req_sport2[] =
54 {P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, \
55 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0};
56 #endif
57 #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
58 unsigned short bfin_uart_pin_req_sport3[] =
59 {P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, \
60 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0};
61 #endif
62
63 struct sport_uart_port {
64 struct uart_port port;
65 int err_irq;
66 unsigned short csize;
67 unsigned short rxmask;
68 unsigned short txmask1;
69 unsigned short txmask2;
70 unsigned char stopb;
71 /* unsigned char parib; */
72 };
73
74 static void sport_uart_tx_chars(struct sport_uart_port *up);
75 static void sport_stop_tx(struct uart_port *port);
76
77 static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
78 {
79 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
80 up->txmask1, up->txmask2);
81
82 /* Place Start and Stop bits */
83 __asm__ __volatile__ (
84 "%[val] <<= 1;"
85 "%[val] = %[val] & %[mask1];"
86 "%[val] = %[val] | %[mask2];"
87 : [val]"+d"(value)
88 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
89 : "ASTAT"
90 );
91 pr_debug("%s value:%x\n", __func__, value);
92
93 SPORT_PUT_TX(up, value);
94 }
95
96 static inline unsigned char rx_one_byte(struct sport_uart_port *up)
97 {
98 unsigned int value;
99 unsigned char extract;
100 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
101
102 if ((up->csize + up->stopb) > 7)
103 value = SPORT_GET_RX32(up);
104 else
105 value = SPORT_GET_RX(up);
106
107 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
108 up->csize, up->rxmask);
109
110 /* Extract data */
111 __asm__ __volatile__ (
112 "%[extr] = 0;"
113 "%[mask1] = %[rxmask];"
114 "%[mask2] = 0x0200(Z);"
115 "%[shift] = 0;"
116 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
117 ".Lloop_s:"
118 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
119 "%[tmp] <<= %[shift];"
120 "%[extr] = %[extr] | %[tmp];"
121 "%[mask1] = %[mask1] - %[mask2];"
122 ".Lloop_e:"
123 "%[shift] += 1;"
124 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
125 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
126 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
127 : "ASTAT", "LB0", "LC0", "LT0"
128 );
129
130 pr_debug(" extract:%x\n", extract);
131 return extract;
132 }
133
134 static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
135 {
136 int tclkdiv, rclkdiv;
137 unsigned int sclk = get_sclk();
138
139 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
140 SPORT_PUT_TCR1(up, (ITFS | TLSBIT | ITCLK));
141 SPORT_PUT_TCR2(up, size + 1);
142 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
143
144 /* Set RCR1 and RCR2 */
145 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
146 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
147 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
148
149 tclkdiv = sclk / (2 * baud_rate) - 1;
150 rclkdiv = sclk / (2 * baud_rate * 2) - 1;
151 SPORT_PUT_TCLKDIV(up, tclkdiv);
152 SPORT_PUT_RCLKDIV(up, rclkdiv);
153 SSYNC();
154 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
155 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
156
157 return 0;
158 }
159
160 static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
161 {
162 struct sport_uart_port *up = dev_id;
163 struct tty_struct *tty = up->port.state->port.tty;
164 unsigned int ch;
165
166 spin_lock(&up->port.lock);
167
168 while (SPORT_GET_STAT(up) & RXNE) {
169 ch = rx_one_byte(up);
170 up->port.icount.rx++;
171
172 if (!uart_handle_sysrq_char(&up->port, ch))
173 tty_insert_flip_char(tty, ch, TTY_NORMAL);
174 }
175 tty_flip_buffer_push(tty);
176
177 spin_unlock(&up->port.lock);
178
179 return IRQ_HANDLED;
180 }
181
182 static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
183 {
184 struct sport_uart_port *up = dev_id;
185
186 spin_lock(&up->port.lock);
187 sport_uart_tx_chars(up);
188 spin_unlock(&up->port.lock);
189
190 return IRQ_HANDLED;
191 }
192
193 static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
194 {
195 struct sport_uart_port *up = dev_id;
196 struct tty_struct *tty = up->port.state->port.tty;
197 unsigned int stat = SPORT_GET_STAT(up);
198
199 spin_lock(&up->port.lock);
200
201 /* Overflow in RX FIFO */
202 if (stat & ROVF) {
203 up->port.icount.overrun++;
204 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
205 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
206 }
207 /* These should not happen */
208 if (stat & (TOVF | TUVF | RUVF)) {
209 pr_err("SPORT Error:%s %s %s\n",
210 (stat & TOVF) ? "TX overflow" : "",
211 (stat & TUVF) ? "TX underflow" : "",
212 (stat & RUVF) ? "RX underflow" : "");
213 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
214 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
215 }
216 SSYNC();
217
218 spin_unlock(&up->port.lock);
219 return IRQ_HANDLED;
220 }
221
222 /* Reqeust IRQ, Setup clock */
223 static int sport_startup(struct uart_port *port)
224 {
225 struct sport_uart_port *up = (struct sport_uart_port *)port;
226 int ret;
227
228 pr_debug("%s enter\n", __func__);
229 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
230 "SPORT_UART_RX", up);
231 if (ret) {
232 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
233 return ret;
234 }
235
236 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
237 "SPORT_UART_TX", up);
238 if (ret) {
239 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
240 goto fail1;
241 }
242
243 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
244 "SPORT_UART_STATUS", up);
245 if (ret) {
246 dev_err(port->dev, "unable to request SPORT status interrupt\n");
247 goto fail2;
248 }
249
250 return 0;
251 fail2:
252 free_irq(up->port.irq+1, up);
253 fail1:
254 free_irq(up->port.irq, up);
255
256 return ret;
257 }
258
259 static void sport_uart_tx_chars(struct sport_uart_port *up)
260 {
261 struct circ_buf *xmit = &up->port.state->xmit;
262
263 if (SPORT_GET_STAT(up) & TXF)
264 return;
265
266 if (up->port.x_char) {
267 tx_one_byte(up, up->port.x_char);
268 up->port.icount.tx++;
269 up->port.x_char = 0;
270 return;
271 }
272
273 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
274 sport_stop_tx(&up->port);
275 return;
276 }
277
278 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
279 tx_one_byte(up, xmit->buf[xmit->tail]);
280 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
281 up->port.icount.tx++;
282 }
283
284 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
285 uart_write_wakeup(&up->port);
286 }
287
288 static unsigned int sport_tx_empty(struct uart_port *port)
289 {
290 struct sport_uart_port *up = (struct sport_uart_port *)port;
291 unsigned int stat;
292
293 stat = SPORT_GET_STAT(up);
294 pr_debug("%s stat:%04x\n", __func__, stat);
295 if (stat & TXHRE) {
296 return TIOCSER_TEMT;
297 } else
298 return 0;
299 }
300
301 static unsigned int sport_get_mctrl(struct uart_port *port)
302 {
303 pr_debug("%s enter\n", __func__);
304 return (TIOCM_CTS | TIOCM_CD | TIOCM_DSR);
305 }
306
307 static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
308 {
309 pr_debug("%s enter\n", __func__);
310 }
311
312 static void sport_stop_tx(struct uart_port *port)
313 {
314 struct sport_uart_port *up = (struct sport_uart_port *)port;
315
316 pr_debug("%s enter\n", __func__);
317
318 /* Although the hold register is empty, last byte is still in shift
319 * register and not sent out yet. So, put a dummy data into TX FIFO.
320 * Then, sport tx stops when last byte is shift out and the dummy
321 * data is moved into the shift register.
322 */
323 SPORT_PUT_TX(up, 0xffff);
324 while (!(SPORT_GET_STAT(up) & TXHRE))
325 cpu_relax();
326
327 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
328 SSYNC();
329
330 return;
331 }
332
333 static void sport_start_tx(struct uart_port *port)
334 {
335 struct sport_uart_port *up = (struct sport_uart_port *)port;
336
337 pr_debug("%s enter\n", __func__);
338
339 /* Write data into SPORT FIFO before enable SPROT to transmit */
340 sport_uart_tx_chars(up);
341
342 /* Enable transmit, then an interrupt will generated */
343 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
344 SSYNC();
345 pr_debug("%s exit\n", __func__);
346 }
347
348 static void sport_stop_rx(struct uart_port *port)
349 {
350 struct sport_uart_port *up = (struct sport_uart_port *)port;
351
352 pr_debug("%s enter\n", __func__);
353 /* Disable sport to stop rx */
354 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
355 SSYNC();
356 }
357
358 static void sport_enable_ms(struct uart_port *port)
359 {
360 pr_debug("%s enter\n", __func__);
361 }
362
363 static void sport_break_ctl(struct uart_port *port, int break_state)
364 {
365 pr_debug("%s enter\n", __func__);
366 }
367
368 static void sport_shutdown(struct uart_port *port)
369 {
370 struct sport_uart_port *up = (struct sport_uart_port *)port;
371
372 dev_dbg(port->dev, "%s enter\n", __func__);
373
374 /* Disable sport */
375 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
376 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
377 SSYNC();
378
379 free_irq(up->port.irq, up);
380 free_irq(up->port.irq+1, up);
381 free_irq(up->err_irq, up);
382 }
383
384 static const char *sport_type(struct uart_port *port)
385 {
386 struct sport_uart_port *up = (struct sport_uart_port *)port;
387
388 pr_debug("%s enter\n", __func__);
389 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
390 }
391
392 static void sport_release_port(struct uart_port *port)
393 {
394 pr_debug("%s enter\n", __func__);
395 }
396
397 static int sport_request_port(struct uart_port *port)
398 {
399 pr_debug("%s enter\n", __func__);
400 return 0;
401 }
402
403 static void sport_config_port(struct uart_port *port, int flags)
404 {
405 struct sport_uart_port *up = (struct sport_uart_port *)port;
406
407 pr_debug("%s enter\n", __func__);
408 up->port.type = PORT_BFIN_SPORT;
409 }
410
411 static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
412 {
413 pr_debug("%s enter\n", __func__);
414 return 0;
415 }
416
417 static void sport_set_termios(struct uart_port *port,
418 struct ktermios *termios, struct ktermios *old)
419 {
420 struct sport_uart_port *up = (struct sport_uart_port *)port;
421 unsigned long flags;
422 int i;
423
424 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
425
426 switch (termios->c_cflag & CSIZE) {
427 case CS8:
428 up->csize = 8;
429 break;
430 case CS7:
431 up->csize = 7;
432 break;
433 case CS6:
434 up->csize = 6;
435 break;
436 case CS5:
437 up->csize = 5;
438 break;
439 default:
440 pr_warning("requested word length not supported\n");
441 }
442
443 if (termios->c_cflag & CSTOPB) {
444 up->stopb = 1;
445 }
446 if (termios->c_cflag & PARENB) {
447 pr_warning("PAREN bits is not supported yet\n");
448 /* up->parib = 1; */
449 }
450
451 port->read_status_mask = OE;
452 if (termios->c_iflag & INPCK)
453 port->read_status_mask |= (FE | PE);
454 if (termios->c_iflag & (BRKINT | PARMRK))
455 port->read_status_mask |= BI;
456
457 /*
458 * Characters to ignore
459 */
460 port->ignore_status_mask = 0;
461 if (termios->c_iflag & IGNPAR)
462 port->ignore_status_mask |= FE | PE;
463 if (termios->c_iflag & IGNBRK) {
464 port->ignore_status_mask |= BI;
465 /*
466 * If we're ignoring parity and break indicators,
467 * ignore overruns too (for real raw support).
468 */
469 if (termios->c_iflag & IGNPAR)
470 port->ignore_status_mask |= OE;
471 }
472
473 /* RX extract mask */
474 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
475 /* TX masks, 8 bit data and 1 bit stop for example:
476 * mask1 = b#0111111110
477 * mask2 = b#1000000000
478 */
479 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
480 up->txmask1 |= (1<<i);
481 up->txmask2 = (1<<i);
482 if (up->stopb) {
483 ++i;
484 up->txmask2 |= (1<<i);
485 }
486 up->txmask1 <<= 1;
487 up->txmask2 <<= 1;
488 /* uart baud rate */
489 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
490
491 spin_lock_irqsave(&up->port.lock, flags);
492
493 /* Disable UART */
494 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
495 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
496
497 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
498
499 /* driver TX line high after config, one dummy data is
500 * necessary to stop sport after shift one byte
501 */
502 SPORT_PUT_TX(up, 0xffff);
503 SPORT_PUT_TX(up, 0xffff);
504 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
505 SSYNC();
506 while (!(SPORT_GET_STAT(up) & TXHRE))
507 cpu_relax();
508 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
509 SSYNC();
510
511 /* Port speed changed, update the per-port timeout. */
512 uart_update_timeout(port, termios->c_cflag, port->uartclk);
513
514 /* Enable sport rx */
515 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
516 SSYNC();
517
518 spin_unlock_irqrestore(&up->port.lock, flags);
519 }
520
521 struct uart_ops sport_uart_ops = {
522 .tx_empty = sport_tx_empty,
523 .set_mctrl = sport_set_mctrl,
524 .get_mctrl = sport_get_mctrl,
525 .stop_tx = sport_stop_tx,
526 .start_tx = sport_start_tx,
527 .stop_rx = sport_stop_rx,
528 .enable_ms = sport_enable_ms,
529 .break_ctl = sport_break_ctl,
530 .startup = sport_startup,
531 .shutdown = sport_shutdown,
532 .set_termios = sport_set_termios,
533 .type = sport_type,
534 .release_port = sport_release_port,
535 .request_port = sport_request_port,
536 .config_port = sport_config_port,
537 .verify_port = sport_verify_port,
538 };
539
540 #define BFIN_SPORT_UART_MAX_PORTS 4
541
542 static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
543
544 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
545 static int __init
546 sport_uart_console_setup(struct console *co, char *options)
547 {
548 struct sport_uart_port *up;
549 int baud = 57600;
550 int bits = 8;
551 int parity = 'n';
552 int flow = 'n';
553
554 /* Check whether an invalid uart number has been specified */
555 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
556 return -ENODEV;
557
558 up = bfin_sport_uart_ports[co->index];
559 if (!up)
560 return -ENODEV;
561
562 if (options)
563 uart_parse_options(options, &baud, &parity, &bits, &flow);
564
565 return uart_set_options(&up->port, co, baud, parity, bits, flow);
566 }
567
568 static void sport_uart_console_putchar(struct uart_port *port, int ch)
569 {
570 struct sport_uart_port *up = (struct sport_uart_port *)port;
571
572 while (SPORT_GET_STAT(up) & TXF)
573 barrier();
574
575 tx_one_byte(up, ch);
576 }
577
578 /*
579 * Interrupts are disabled on entering
580 */
581 static void
582 sport_uart_console_write(struct console *co, const char *s, unsigned int count)
583 {
584 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
585 unsigned long flags;
586
587 spin_lock_irqsave(&up->port.lock, flags);
588
589 if (SPORT_GET_TCR1(up) & TSPEN)
590 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
591 else {
592 /* dummy data to start sport */
593 while (SPORT_GET_STAT(up) & TXF)
594 barrier();
595 SPORT_PUT_TX(up, 0xffff);
596 /* Enable transmit, then an interrupt will generated */
597 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
598 SSYNC();
599
600 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
601
602 /* Although the hold register is empty, last byte is still in shift
603 * register and not sent out yet. So, put a dummy data into TX FIFO.
604 * Then, sport tx stops when last byte is shift out and the dummy
605 * data is moved into the shift register.
606 */
607 while (SPORT_GET_STAT(up) & TXF)
608 barrier();
609 SPORT_PUT_TX(up, 0xffff);
610 while (!(SPORT_GET_STAT(up) & TXHRE))
611 barrier();
612
613 /* Stop sport tx transfer */
614 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
615 SSYNC();
616 }
617
618 spin_unlock_irqrestore(&up->port.lock, flags);
619 }
620
621 static struct uart_driver sport_uart_reg;
622
623 static struct console sport_uart_console = {
624 .name = DEVICE_NAME,
625 .write = sport_uart_console_write,
626 .device = uart_console_device,
627 .setup = sport_uart_console_setup,
628 .flags = CON_PRINTBUFFER,
629 .index = -1,
630 .data = &sport_uart_reg,
631 };
632
633 #define SPORT_UART_CONSOLE (&sport_uart_console)
634 #else
635 #define SPORT_UART_CONSOLE NULL
636 #endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
637
638
639 static struct uart_driver sport_uart_reg = {
640 .owner = THIS_MODULE,
641 .driver_name = DRV_NAME,
642 .dev_name = DEVICE_NAME,
643 .major = 204,
644 .minor = 84,
645 .nr = BFIN_SPORT_UART_MAX_PORTS,
646 .cons = SPORT_UART_CONSOLE,
647 };
648
649 #ifdef CONFIG_PM
650 static int sport_uart_suspend(struct device *dev)
651 {
652 struct sport_uart_port *sport = dev_get_drvdata(dev);
653
654 dev_dbg(dev, "%s enter\n", __func__);
655 if (sport)
656 uart_suspend_port(&sport_uart_reg, &sport->port);
657
658 return 0;
659 }
660
661 static int sport_uart_resume(struct device *dev)
662 {
663 struct sport_uart_port *sport = dev_get_drvdata(dev);
664
665 dev_dbg(dev, "%s enter\n", __func__);
666 if (sport)
667 uart_resume_port(&sport_uart_reg, &sport->port);
668
669 return 0;
670 }
671
672 static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
673 .suspend = sport_uart_suspend,
674 .resume = sport_uart_resume,
675 };
676 #endif
677
678 static int __devinit sport_uart_probe(struct platform_device *pdev)
679 {
680 struct resource *res;
681 struct sport_uart_port *sport;
682 int ret = 0;
683
684 dev_dbg(&pdev->dev, "%s enter\n", __func__);
685
686 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
687 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
688 return -ENOENT;
689 }
690
691 if (bfin_sport_uart_ports[pdev->id] == NULL) {
692 bfin_sport_uart_ports[pdev->id] =
693 kmalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
694 sport = bfin_sport_uart_ports[pdev->id];
695 if (!sport) {
696 dev_err(&pdev->dev,
697 "Fail to kmalloc sport_uart_port\n");
698 return -ENOMEM;
699 }
700
701 ret = peripheral_request_list(
702 (unsigned short *)pdev->dev.platform_data, DRV_NAME);
703 if (ret) {
704 dev_err(&pdev->dev,
705 "Fail to request SPORT peripherals\n");
706 goto out_error_free_mem;
707 }
708
709 spin_lock_init(&sport->port.lock);
710 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
711 sport->port.ops = &sport_uart_ops;
712 sport->port.line = pdev->id;
713 sport->port.iotype = UPIO_MEM;
714 sport->port.flags = UPF_BOOT_AUTOCONF;
715
716 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
717 if (res == NULL) {
718 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
719 ret = -ENOENT;
720 goto out_error_free_peripherals;
721 }
722
723 sport->port.membase = ioremap(res->start,
724 res->end - res->start);
725 if (!sport->port.membase) {
726 dev_err(&pdev->dev, "Cannot map sport IO\n");
727 ret = -ENXIO;
728 goto out_error_free_peripherals;
729 }
730
731 sport->port.irq = platform_get_irq(pdev, 0);
732 if (sport->port.irq < 0) {
733 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
734 ret = -ENOENT;
735 goto out_error_unmap;
736 }
737
738 sport->err_irq = platform_get_irq(pdev, 1);
739 if (sport->err_irq < 0) {
740 dev_err(&pdev->dev, "No sport status IRQ specified\n");
741 ret = -ENOENT;
742 goto out_error_unmap;
743 }
744 }
745
746 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
747 if (!is_early_platform_device(pdev)) {
748 #endif
749 sport = bfin_sport_uart_ports[pdev->id];
750 sport->port.dev = &pdev->dev;
751 dev_set_drvdata(&pdev->dev, sport);
752 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
753 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
754 }
755 #endif
756 if (!ret)
757 return 0;
758
759 if (sport) {
760 out_error_unmap:
761 iounmap(sport->port.membase);
762 out_error_free_peripherals:
763 peripheral_free_list(
764 (unsigned short *)pdev->dev.platform_data);
765 out_error_free_mem:
766 kfree(sport);
767 bfin_sport_uart_ports[pdev->id] = NULL;
768 }
769
770 return ret;
771 }
772
773 static int __devexit sport_uart_remove(struct platform_device *pdev)
774 {
775 struct sport_uart_port *sport = platform_get_drvdata(pdev);
776
777 dev_dbg(&pdev->dev, "%s enter\n", __func__);
778 dev_set_drvdata(&pdev->dev, NULL);
779
780 if (sport) {
781 uart_remove_one_port(&sport_uart_reg, &sport->port);
782 iounmap(sport->port.membase);
783 peripheral_free_list(
784 (unsigned short *)pdev->dev.platform_data);
785 kfree(sport);
786 bfin_sport_uart_ports[pdev->id] = NULL;
787 }
788
789 return 0;
790 }
791
792 static struct platform_driver sport_uart_driver = {
793 .probe = sport_uart_probe,
794 .remove = __devexit_p(sport_uart_remove),
795 .driver = {
796 .name = DRV_NAME,
797 #ifdef CONFIG_PM
798 .pm = &bfin_sport_uart_dev_pm_ops,
799 #endif
800 },
801 };
802
803 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
804 static __initdata struct early_platform_driver early_sport_uart_driver = {
805 .class_str = DRV_NAME,
806 .pdrv = &sport_uart_driver,
807 .requested_id = EARLY_PLATFORM_ID_UNSET,
808 };
809
810 static int __init sport_uart_rs_console_init(void)
811 {
812 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
813
814 early_platform_driver_probe(DRV_NAME, BFIN_SPORT_UART_MAX_PORTS, 0);
815
816 register_console(&sport_uart_console);
817
818 return 0;
819 }
820 console_initcall(sport_uart_rs_console_init);
821 #endif
822
823 static int __init sport_uart_init(void)
824 {
825 int ret;
826
827 pr_info("Serial: Blackfin uart over sport driver\n");
828
829 ret = uart_register_driver(&sport_uart_reg);
830 if (ret) {
831 pr_err("failed to register %s:%d\n",
832 sport_uart_reg.driver_name, ret);
833 return ret;
834 }
835
836 ret = platform_driver_register(&sport_uart_driver);
837 if (ret) {
838 pr_err("failed to register sport uart driver:%d\n", ret);
839 uart_unregister_driver(&sport_uart_reg);
840 }
841
842 return ret;
843 }
844 module_init(sport_uart_init);
845
846 static void __exit sport_uart_exit(void)
847 {
848 platform_driver_unregister(&sport_uart_driver);
849 uart_unregister_driver(&sport_uart_reg);
850 }
851 module_exit(sport_uart_exit);
852
853 MODULE_AUTHOR("Sonic Zhang, Roy Huang");
854 MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
855 MODULE_LICENSE("GPL");
kernel-based virtual machine