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arch/x86/pci: use kasprintf
[linux-2.6/kvm.git] / drivers / usb / musb / tusb6010.c
blob05c077f8f9acbd3c87fe99a945aa61878ca7471f
1 /*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Notes:
12 * - Driver assumes that interface to external host (main CPU) is
13 * configured for NOR FLASH interface instead of VLYNQ serial
14 * interface.
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/init.h>
21 #include <linux/usb.h>
22 #include <linux/irq.h>
23 #include <linux/platform_device.h>
24
25 #include "musb_core.h"
26
27 static void tusb_source_power(struct musb *musb, int is_on);
28
29 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
30 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
31
32 #ifdef CONFIG_PM
33 /* REVISIT: These should be only needed if somebody implements off idle */
34 void musb_platform_save_context(struct musb *musb,
35 struct musb_context_registers *musb_context)
36 {
37 }
38
39 void musb_platform_restore_context(struct musb *musb,
40 struct musb_context_registers *musb_context)
41 {
42 }
43 #endif
44
45 /*
46 * Checks the revision. We need to use the DMA register as 3.0 does not
47 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
48 */
49 u8 tusb_get_revision(struct musb *musb)
50 {
51 void __iomem *tbase = musb->ctrl_base;
52 u32 die_id;
53 u8 rev;
54
55 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
56 if (TUSB_REV_MAJOR(rev) == 3) {
57 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
58 TUSB_DIDR1_HI));
59 if (die_id >= TUSB_DIDR1_HI_REV_31)
60 rev |= 1;
61 }
62
63 return rev;
64 }
65
66 static int __init tusb_print_revision(struct musb *musb)
67 {
68 void __iomem *tbase = musb->ctrl_base;
69 u8 rev;
70
71 rev = tusb_get_revision(musb);
72
73 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
74 "prcm",
75 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
76 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
77 "int",
78 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
79 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
80 "gpio",
81 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
82 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
83 "dma",
84 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
85 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
86 "dieid",
87 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
88 "rev",
89 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
90
91 return tusb_get_revision(musb);
92 }
93
94 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
95 | TUSB_PHY_OTG_CTRL_TESTM0)
96
97 /*
98 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
99 * Disables power detection in PHY for the duration of idle.
100 */
101 static void tusb_wbus_quirk(struct musb *musb, int enabled)
102 {
103 void __iomem *tbase = musb->ctrl_base;
104 static u32 phy_otg_ctrl, phy_otg_ena;
105 u32 tmp;
106
107 if (enabled) {
108 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
109 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
110 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
111 | phy_otg_ena | WBUS_QUIRK_MASK;
112 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
113 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
114 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
115 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
116 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
117 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
118 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
119 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
120 & TUSB_PHY_OTG_CTRL_TESTM2) {
121 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
122 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
123 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
124 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
125 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
126 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
127 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
128 phy_otg_ctrl = 0;
129 phy_otg_ena = 0;
130 }
131 }
132
133 /*
134 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
135 * so both loading and unloading FIFOs need explicit byte counts.
136 */
137
138 static inline void
139 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
140 {
141 u32 val;
142 int i;
143
144 if (len > 4) {
145 for (i = 0; i < (len >> 2); i++) {
146 memcpy(&val, buf, 4);
147 musb_writel(fifo, 0, val);
148 buf += 4;
149 }
150 len %= 4;
151 }
152 if (len > 0) {
153 /* Write the rest 1 - 3 bytes to FIFO */
154 memcpy(&val, buf, len);
155 musb_writel(fifo, 0, val);
156 }
157 }
158
159 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
160 void __iomem *buf, u16 len)
161 {
162 u32 val;
163 int i;
164
165 if (len > 4) {
166 for (i = 0; i < (len >> 2); i++) {
167 val = musb_readl(fifo, 0);
168 memcpy(buf, &val, 4);
169 buf += 4;
170 }
171 len %= 4;
172 }
173 if (len > 0) {
174 /* Read the rest 1 - 3 bytes from FIFO */
175 val = musb_readl(fifo, 0);
176 memcpy(buf, &val, len);
177 }
178 }
179
180 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
181 {
182 void __iomem *ep_conf = hw_ep->conf;
183 void __iomem *fifo = hw_ep->fifo;
184 u8 epnum = hw_ep->epnum;
185
186 prefetch(buf);
187
188 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
189 'T', epnum, fifo, len, buf);
190
191 if (epnum)
192 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
193 TUSB_EP_CONFIG_XFR_SIZE(len));
194 else
195 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
196 TUSB_EP0_CONFIG_XFR_SIZE(len));
197
198 if (likely((0x01 & (unsigned long) buf) == 0)) {
199
200 /* Best case is 32bit-aligned destination address */
201 if ((0x02 & (unsigned long) buf) == 0) {
202 if (len >= 4) {
203 writesl(fifo, buf, len >> 2);
204 buf += (len & ~0x03);
205 len &= 0x03;
206 }
207 } else {
208 if (len >= 2) {
209 u32 val;
210 int i;
211
212 /* Cannot use writesw, fifo is 32-bit */
213 for (i = 0; i < (len >> 2); i++) {
214 val = (u32)(*(u16 *)buf);
215 buf += 2;
216 val |= (*(u16 *)buf) << 16;
217 buf += 2;
218 musb_writel(fifo, 0, val);
219 }
220 len &= 0x03;
221 }
222 }
223 }
224
225 if (len > 0)
226 tusb_fifo_write_unaligned(fifo, buf, len);
227 }
228
229 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
230 {
231 void __iomem *ep_conf = hw_ep->conf;
232 void __iomem *fifo = hw_ep->fifo;
233 u8 epnum = hw_ep->epnum;
234
235 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
236 'R', epnum, fifo, len, buf);
237
238 if (epnum)
239 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
240 TUSB_EP_CONFIG_XFR_SIZE(len));
241 else
242 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
243
244 if (likely((0x01 & (unsigned long) buf) == 0)) {
245
246 /* Best case is 32bit-aligned destination address */
247 if ((0x02 & (unsigned long) buf) == 0) {
248 if (len >= 4) {
249 readsl(fifo, buf, len >> 2);
250 buf += (len & ~0x03);
251 len &= 0x03;
252 }
253 } else {
254 if (len >= 2) {
255 u32 val;
256 int i;
257
258 /* Cannot use readsw, fifo is 32-bit */
259 for (i = 0; i < (len >> 2); i++) {
260 val = musb_readl(fifo, 0);
261 *(u16 *)buf = (u16)(val & 0xffff);
262 buf += 2;
263 *(u16 *)buf = (u16)(val >> 16);
264 buf += 2;
265 }
266 len &= 0x03;
267 }
268 }
269 }
270
271 if (len > 0)
272 tusb_fifo_read_unaligned(fifo, buf, len);
273 }
274
275 static struct musb *the_musb;
276
277 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
278
279 /* This is used by gadget drivers, and OTG transceiver logic, allowing
280 * at most mA current to be drawn from VBUS during a Default-B session
281 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
282 * mode), or low power Default-B sessions, something else supplies power.
283 * Caller must take care of locking.
284 */
285 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
286 {
287 struct musb *musb = the_musb;
288 void __iomem *tbase = musb->ctrl_base;
289 u32 reg;
290
291 /*
292 * Keep clock active when enabled. Note that this is not tied to
293 * drawing VBUS, as with OTG mA can be less than musb->min_power.
294 */
295 if (musb->set_clock) {
296 if (mA)
297 musb->set_clock(musb->clock, 1);
298 else
299 musb->set_clock(musb->clock, 0);
300 }
301
302 /* tps65030 seems to consume max 100mA, with maybe 60mA available
303 * (measured on one board) for things other than tps and tusb.
304 *
305 * Boards sharing the CPU clock with CLKIN will need to prevent
306 * certain idle sleep states while the USB link is active.
307 *
308 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
309 * The actual current usage would be very board-specific. For now,
310 * it's simpler to just use an aggregate (also board-specific).
311 */
312 if (x->default_a || mA < (musb->min_power << 1))
313 mA = 0;
314
315 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
316 if (mA) {
317 musb->is_bus_powered = 1;
318 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
319 } else {
320 musb->is_bus_powered = 0;
321 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
322 }
323 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
324
325 DBG(2, "draw max %d mA VBUS\n", mA);
326 return 0;
327 }
328
329 #else
330 #define tusb_draw_power NULL
331 #endif
332
333 /* workaround for issue 13: change clock during chip idle
334 * (to be fixed in rev3 silicon) ... symptoms include disconnect
335 * or looping suspend/resume cycles
336 */
337 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
338 {
339 void __iomem *tbase = musb->ctrl_base;
340 u32 reg;
341
342 reg = musb_readl(tbase, TUSB_PRCM_CONF);
343 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
344
345 /* 0 = refclk (clkin, XI)
346 * 1 = PHY 60 MHz (internal PLL)
347 * 2 = not supported
348 * 3 = what?
349 */
350 if (mode > 0)
351 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
352
353 musb_writel(tbase, TUSB_PRCM_CONF, reg);
354
355 /* FIXME tusb6010_platform_retime(mode == 0); */
356 }
357
358 /*
359 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
360 * Other code ensures that we idle unless we're connected _and_ the
361 * USB link is not suspended ... and tells us the relevant wakeup
362 * events. SW_EN for voltage is handled separately.
363 */
364 void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
365 {
366 void __iomem *tbase = musb->ctrl_base;
367 u32 reg;
368
369 if ((wakeup_enables & TUSB_PRCM_WBUS)
370 && (tusb_get_revision(musb) == TUSB_REV_30))
371 tusb_wbus_quirk(musb, 1);
372
373 tusb_set_clock_source(musb, 0);
374
375 wakeup_enables |= TUSB_PRCM_WNORCS;
376 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
377
378 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
379 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
380 * Presumably that's mostly to save power, hence WID is immaterial ...
381 */
382
383 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
384 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
385 if (is_host_active(musb)) {
386 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
387 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
388 } else {
389 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
390 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
391 }
392 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
393 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
394
395 DBG(6, "idle, wake on %02x\n", wakeup_enables);
396 }
397
398 /*
399 * Updates cable VBUS status. Caller must take care of locking.
400 */
401 int musb_platform_get_vbus_status(struct musb *musb)
402 {
403 void __iomem *tbase = musb->ctrl_base;
404 u32 otg_stat, prcm_mngmt;
405 int ret = 0;
406
407 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
408 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
409
410 /* Temporarily enable VBUS detection if it was disabled for
411 * suspend mode. Unless it's enabled otg_stat and devctl will
412 * not show correct VBUS state.
413 */
414 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
415 u32 tmp = prcm_mngmt;
416 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
417 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
418 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
419 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
420 }
421
422 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
423 ret = 1;
424
425 return ret;
426 }
427
428 static struct timer_list musb_idle_timer;
429
430 static void musb_do_idle(unsigned long _musb)
431 {
432 struct musb *musb = (void *)_musb;
433 unsigned long flags;
434
435 spin_lock_irqsave(&musb->lock, flags);
436
437 switch (musb->xceiv->state) {
438 case OTG_STATE_A_WAIT_BCON:
439 if ((musb->a_wait_bcon != 0)
440 && (musb->idle_timeout == 0
441 || time_after(jiffies, musb->idle_timeout))) {
442 DBG(4, "Nothing connected %s, turning off VBUS\n",
443 otg_state_string(musb));
444 }
445 /* FALLTHROUGH */
446 case OTG_STATE_A_IDLE:
447 tusb_source_power(musb, 0);
448 default:
449 break;
450 }
451
452 if (!musb->is_active) {
453 u32 wakeups;
454
455 /* wait until khubd handles port change status */
456 if (is_host_active(musb) && (musb->port1_status >> 16))
457 goto done;
458
459 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
460 if (is_peripheral_enabled(musb) && !musb->gadget_driver)
461 wakeups = 0;
462 else {
463 wakeups = TUSB_PRCM_WHOSTDISCON
464 | TUSB_PRCM_WBUS
465 | TUSB_PRCM_WVBUS;
466 if (is_otg_enabled(musb))
467 wakeups |= TUSB_PRCM_WID;
468 }
469 #else
470 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS;
471 #endif
472 tusb_allow_idle(musb, wakeups);
473 }
474 done:
475 spin_unlock_irqrestore(&musb->lock, flags);
476 }
477
478 /*
479 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
480 * like "disconnected" or "suspended". We'll be woken out of it by
481 * connect, resume, or disconnect.
482 *
483 * Needs to be called as the last function everywhere where there is
484 * register access to TUSB6010 because of NOR flash wake-up.
485 * Caller should own controller spinlock.
486 *
487 * Delay because peripheral enables D+ pullup 3msec after SE0, and
488 * we don't want to treat that full speed J as a wakeup event.
489 * ... peripherals must draw only suspend current after 10 msec.
490 */
491 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
492 {
493 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
494 static unsigned long last_timer;
495
496 if (timeout == 0)
497 timeout = default_timeout;
498
499 /* Never idle if active, or when VBUS timeout is not set as host */
500 if (musb->is_active || ((musb->a_wait_bcon == 0)
501 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
502 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
503 del_timer(&musb_idle_timer);
504 last_timer = jiffies;
505 return;
506 }
507
508 if (time_after(last_timer, timeout)) {
509 if (!timer_pending(&musb_idle_timer))
510 last_timer = timeout;
511 else {
512 DBG(4, "Longer idle timer already pending, ignoring\n");
513 return;
514 }
515 }
516 last_timer = timeout;
517
518 DBG(4, "%s inactive, for idle timer for %lu ms\n",
519 otg_state_string(musb),
520 (unsigned long)jiffies_to_msecs(timeout - jiffies));
521 mod_timer(&musb_idle_timer, timeout);
522 }
523
524 /* ticks of 60 MHz clock */
525 #define DEVCLOCK 60000000
526 #define OTG_TIMER_MS(msecs) ((msecs) \
527 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
528 | TUSB_DEV_OTG_TIMER_ENABLE) \
529 : 0)
530
531 static void tusb_source_power(struct musb *musb, int is_on)
532 {
533 void __iomem *tbase = musb->ctrl_base;
534 u32 conf, prcm, timer;
535 u8 devctl;
536
537 /* HDRC controls CPEN, but beware current surges during device
538 * connect. They can trigger transient overcurrent conditions
539 * that must be ignored.
540 */
541
542 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
543 conf = musb_readl(tbase, TUSB_DEV_CONF);
544 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
545
546 if (is_on) {
547 if (musb->set_clock)
548 musb->set_clock(musb->clock, 1);
549 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
550 musb->xceiv->default_a = 1;
551 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
552 devctl |= MUSB_DEVCTL_SESSION;
553
554 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
555 MUSB_HST_MODE(musb);
556 } else {
557 u32 otg_stat;
558
559 timer = 0;
560
561 /* If ID pin is grounded, we want to be a_idle */
562 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
563 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
564 switch (musb->xceiv->state) {
565 case OTG_STATE_A_WAIT_VRISE:
566 case OTG_STATE_A_WAIT_BCON:
567 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
568 break;
569 case OTG_STATE_A_WAIT_VFALL:
570 musb->xceiv->state = OTG_STATE_A_IDLE;
571 break;
572 default:
573 musb->xceiv->state = OTG_STATE_A_IDLE;
574 }
575 musb->is_active = 0;
576 musb->xceiv->default_a = 1;
577 MUSB_HST_MODE(musb);
578 } else {
579 musb->is_active = 0;
580 musb->xceiv->default_a = 0;
581 musb->xceiv->state = OTG_STATE_B_IDLE;
582 MUSB_DEV_MODE(musb);
583 }
584
585 devctl &= ~MUSB_DEVCTL_SESSION;
586 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
587 if (musb->set_clock)
588 musb->set_clock(musb->clock, 0);
589 }
590 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
591
592 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
593 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
594 musb_writel(tbase, TUSB_DEV_CONF, conf);
595 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
596
597 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
598 otg_state_string(musb),
599 musb_readb(musb->mregs, MUSB_DEVCTL),
600 musb_readl(tbase, TUSB_DEV_OTG_STAT),
601 conf, prcm);
602 }
603
604 /*
605 * Sets the mode to OTG, peripheral or host by changing the ID detection.
606 * Caller must take care of locking.
607 *
608 * Note that if a mini-A cable is plugged in the ID line will stay down as
609 * the weak ID pull-up is not able to pull the ID up.
610 *
611 * REVISIT: It would be possible to add support for changing between host
612 * and peripheral modes in non-OTG configurations by reconfiguring hardware
613 * and then setting musb->board_mode. For now, only support OTG mode.
614 */
615 int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
616 {
617 void __iomem *tbase = musb->ctrl_base;
618 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
619
620 if (musb->board_mode != MUSB_OTG) {
621 ERR("Changing mode currently only supported in OTG mode\n");
622 return -EINVAL;
623 }
624
625 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
626 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
627 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
628 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
629
630 switch (musb_mode) {
631
632 #ifdef CONFIG_USB_MUSB_HDRC_HCD
633 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
634 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
635 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
636 dev_conf |= TUSB_DEV_CONF_ID_SEL;
637 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
638 break;
639 #endif
640
641 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
642 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
643 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
644 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
645 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
646 break;
647 #endif
648
649 #ifdef CONFIG_USB_MUSB_OTG
650 case MUSB_OTG: /* Use PHY ID detection */
651 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
652 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
653 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
654 break;
655 #endif
656
657 default:
658 DBG(2, "Trying to set mode %i\n", musb_mode);
659 return -EINVAL;
660 }
661
662 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
663 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
664 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
665 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
666 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
667
668 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
669 if ((musb_mode == MUSB_PERIPHERAL) &&
670 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
671 INFO("Cannot be peripheral with mini-A cable "
672 "otg_stat: %08x\n", otg_stat);
673
674 return 0;
675 }
676
677 static inline unsigned long
678 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
679 {
680 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
681 unsigned long idle_timeout = 0;
682
683 /* ID pin */
684 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
685 int default_a;
686
687 if (is_otg_enabled(musb))
688 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
689 else
690 default_a = is_host_enabled(musb);
691 DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
692 musb->xceiv->default_a = default_a;
693 tusb_source_power(musb, default_a);
694
695 /* Don't allow idling immediately */
696 if (default_a)
697 idle_timeout = jiffies + (HZ * 3);
698 }
699
700 /* VBUS state change */
701 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
702
703 /* B-dev state machine: no vbus ~= disconnect */
704 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
705 || !is_host_enabled(musb)) {
706 #ifdef CONFIG_USB_MUSB_HDRC_HCD
707 /* ? musb_root_disconnect(musb); */
708 musb->port1_status &=
709 ~(USB_PORT_STAT_CONNECTION
710 | USB_PORT_STAT_ENABLE
711 | USB_PORT_STAT_LOW_SPEED
712 | USB_PORT_STAT_HIGH_SPEED
713 | USB_PORT_STAT_TEST
714 );
715 #endif
716
717 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
718 DBG(1, "Forcing disconnect (no interrupt)\n");
719 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
720 /* INTR_DISCONNECT can hide... */
721 musb->xceiv->state = OTG_STATE_B_IDLE;
722 musb->int_usb |= MUSB_INTR_DISCONNECT;
723 }
724 musb->is_active = 0;
725 }
726 DBG(2, "vbus change, %s, otg %03x\n",
727 otg_state_string(musb), otg_stat);
728 idle_timeout = jiffies + (1 * HZ);
729 schedule_work(&musb->irq_work);
730
731 } else /* A-dev state machine */ {
732 DBG(2, "vbus change, %s, otg %03x\n",
733 otg_state_string(musb), otg_stat);
734
735 switch (musb->xceiv->state) {
736 case OTG_STATE_A_IDLE:
737 DBG(2, "Got SRP, turning on VBUS\n");
738 musb_set_vbus(musb, 1);
739
740 /* CONNECT can wake if a_wait_bcon is set */
741 if (musb->a_wait_bcon != 0)
742 musb->is_active = 0;
743 else
744 musb->is_active = 1;
745
746 /*
747 * OPT FS A TD.4.6 needs few seconds for
748 * A_WAIT_VRISE
749 */
750 idle_timeout = jiffies + (2 * HZ);
751
752 break;
753 case OTG_STATE_A_WAIT_VRISE:
754 /* ignore; A-session-valid < VBUS_VALID/2,
755 * we monitor this with the timer
756 */
757 break;
758 case OTG_STATE_A_WAIT_VFALL:
759 /* REVISIT this irq triggers during short
760 * spikes caused by enumeration ...
761 */
762 if (musb->vbuserr_retry) {
763 musb->vbuserr_retry--;
764 tusb_source_power(musb, 1);
765 } else {
766 musb->vbuserr_retry
767 = VBUSERR_RETRY_COUNT;
768 tusb_source_power(musb, 0);
769 }
770 break;
771 default:
772 break;
773 }
774 }
775 }
776
777 /* OTG timer expiration */
778 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
779 u8 devctl;
780
781 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
782
783 switch (musb->xceiv->state) {
784 case OTG_STATE_A_WAIT_VRISE:
785 /* VBUS has probably been valid for a while now,
786 * but may well have bounced out of range a bit
787 */
788 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
789 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
790 if ((devctl & MUSB_DEVCTL_VBUS)
791 != MUSB_DEVCTL_VBUS) {
792 DBG(2, "devctl %02x\n", devctl);
793 break;
794 }
795 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
796 musb->is_active = 0;
797 idle_timeout = jiffies
798 + msecs_to_jiffies(musb->a_wait_bcon);
799 } else {
800 /* REVISIT report overcurrent to hub? */
801 ERR("vbus too slow, devctl %02x\n", devctl);
802 tusb_source_power(musb, 0);
803 }
804 break;
805 case OTG_STATE_A_WAIT_BCON:
806 if (musb->a_wait_bcon != 0)
807 idle_timeout = jiffies
808 + msecs_to_jiffies(musb->a_wait_bcon);
809 break;
810 case OTG_STATE_A_SUSPEND:
811 break;
812 case OTG_STATE_B_WAIT_ACON:
813 break;
814 default:
815 break;
816 }
817 }
818 schedule_work(&musb->irq_work);
819
820 return idle_timeout;
821 }
822
823 static irqreturn_t tusb_interrupt(int irq, void *__hci)
824 {
825 struct musb *musb = __hci;
826 void __iomem *tbase = musb->ctrl_base;
827 unsigned long flags, idle_timeout = 0;
828 u32 int_mask, int_src;
829
830 spin_lock_irqsave(&musb->lock, flags);
831
832 /* Mask all interrupts to allow using both edge and level GPIO irq */
833 int_mask = musb_readl(tbase, TUSB_INT_MASK);
834 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
835
836 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
837 DBG(3, "TUSB IRQ %08x\n", int_src);
838
839 musb->int_usb = (u8) int_src;
840
841 /* Acknowledge wake-up source interrupts */
842 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
843 u32 reg;
844 u32 i;
845
846 if (tusb_get_revision(musb) == TUSB_REV_30)
847 tusb_wbus_quirk(musb, 0);
848
849 /* there are issues re-locking the PLL on wakeup ... */
850
851 /* work around issue 8 */
852 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
853 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
854 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
855 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
856 if (reg == i)
857 break;
858 DBG(6, "TUSB NOR not ready\n");
859 }
860
861 /* work around issue 13 (2nd half) */
862 tusb_set_clock_source(musb, 1);
863
864 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
865 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
866 if (reg & ~TUSB_PRCM_WNORCS) {
867 musb->is_active = 1;
868 schedule_work(&musb->irq_work);
869 }
870 DBG(3, "wake %sactive %02x\n",
871 musb->is_active ? "" : "in", reg);
872
873 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
874 }
875
876 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
877 del_timer(&musb_idle_timer);
878
879 /* OTG state change reports (annoyingly) not issued by Mentor core */
880 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
881 | TUSB_INT_SRC_OTG_TIMEOUT
882 | TUSB_INT_SRC_ID_STATUS_CHNG))
883 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
884
885 /* TX dma callback must be handled here, RX dma callback is
886 * handled in tusb_omap_dma_cb.
887 */
888 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
889 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
890 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
891
892 DBG(3, "DMA IRQ %08x\n", dma_src);
893 real_dma_src = ~real_dma_src & dma_src;
894 if (tusb_dma_omap() && real_dma_src) {
895 int tx_source = (real_dma_src & 0xffff);
896 int i;
897
898 for (i = 1; i <= 15; i++) {
899 if (tx_source & (1 << i)) {
900 DBG(3, "completing ep%i %s\n", i, "tx");
901 musb_dma_completion(musb, i, 1);
902 }
903 }
904 }
905 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
906 }
907
908 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
909 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
910 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
911
912 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
913 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
914 musb->int_tx = (musb_src & 0xffff);
915 } else {
916 musb->int_rx = 0;
917 musb->int_tx = 0;
918 }
919
920 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
921 musb_interrupt(musb);
922
923 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
924 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
925 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
926
927 musb_platform_try_idle(musb, idle_timeout);
928
929 musb_writel(tbase, TUSB_INT_MASK, int_mask);
930 spin_unlock_irqrestore(&musb->lock, flags);
931
932 return IRQ_HANDLED;
933 }
934
935 static int dma_off;
936
937 /*
938 * Enables TUSB6010. Caller must take care of locking.
939 * REVISIT:
940 * - Check what is unnecessary in MGC_HdrcStart()
941 */
942 void musb_platform_enable(struct musb *musb)
943 {
944 void __iomem *tbase = musb->ctrl_base;
945
946 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
947 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
948 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
949
950 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
951 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
952 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
953 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
954
955 /* Clear all subsystem interrups */
956 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
957 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
958 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
959
960 /* Acknowledge pending interrupt(s) */
961 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
962
963 /* Only 0 clock cycles for minimum interrupt de-assertion time and
964 * interrupt polarity active low seems to work reliably here */
965 musb_writel(tbase, TUSB_INT_CTRL_CONF,
966 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
967
968 set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
969
970 /* maybe force into the Default-A OTG state machine */
971 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
972 & TUSB_DEV_OTG_STAT_ID_STATUS))
973 musb_writel(tbase, TUSB_INT_SRC_SET,
974 TUSB_INT_SRC_ID_STATUS_CHNG);
975
976 if (is_dma_capable() && dma_off)
977 printk(KERN_WARNING "%s %s: dma not reactivated\n",
978 __FILE__, __func__);
979 else
980 dma_off = 1;
981 }
982
983 /*
984 * Disables TUSB6010. Caller must take care of locking.
985 */
986 void musb_platform_disable(struct musb *musb)
987 {
988 void __iomem *tbase = musb->ctrl_base;
989
990 /* FIXME stop DMA, IRQs, timers, ... */
991
992 /* disable all IRQs */
993 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
994 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
995 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
996 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
997
998 del_timer(&musb_idle_timer);
999
1000 if (is_dma_capable() && !dma_off) {
1001 printk(KERN_WARNING "%s %s: dma still active\n",
1002 __FILE__, __func__);
1003 dma_off = 1;
1004 }
1005 }
1006
1007 /*
1008 * Sets up TUSB6010 CPU interface specific signals and registers
1009 * Note: Settings optimized for OMAP24xx
1010 */
1011 static void __init tusb_setup_cpu_interface(struct musb *musb)
1012 {
1013 void __iomem *tbase = musb->ctrl_base;
1014
1015 /*
1016 * Disable GPIO[5:0] pullups (used as output DMA requests)
1017 * Don't disable GPIO[7:6] as they are needed for wake-up.
1018 */
1019 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1020
1021 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1022 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1023
1024 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1025 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1026
1027 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1028 * de-assertion time 2 system clocks p 62 */
1029 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1030 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1031 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1032 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1033
1034 /* Set 0 wait count for synchronous burst access */
1035 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1036 }
1037
1038 static int __init tusb_start(struct musb *musb)
1039 {
1040 void __iomem *tbase = musb->ctrl_base;
1041 int ret = 0;
1042 unsigned long flags;
1043 u32 reg;
1044
1045 if (musb->board_set_power)
1046 ret = musb->board_set_power(1);
1047 if (ret != 0) {
1048 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1049 return ret;
1050 }
1051
1052 spin_lock_irqsave(&musb->lock, flags);
1053
1054 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1055 TUSB_PROD_TEST_RESET_VAL) {
1056 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1057 goto err;
1058 }
1059
1060 ret = tusb_print_revision(musb);
1061 if (ret < 2) {
1062 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1063 ret);
1064 goto err;
1065 }
1066
1067 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1068 * NOR FLASH interface is used */
1069 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1070
1071 /* Select PHY free running 60MHz as a system clock */
1072 tusb_set_clock_source(musb, 1);
1073
1074 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1075 * power saving, enable VBus detect and session end comparators,
1076 * enable IDpullup, enable VBus charging */
1077 musb_writel(tbase, TUSB_PRCM_MNGMT,
1078 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1079 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1080 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1081 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1082 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1083 tusb_setup_cpu_interface(musb);
1084
1085 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1086 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1087 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1088 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1089
1090 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1091 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1092 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1093
1094 spin_unlock_irqrestore(&musb->lock, flags);
1095
1096 return 0;
1097
1098 err:
1099 spin_unlock_irqrestore(&musb->lock, flags);
1100
1101 if (musb->board_set_power)
1102 musb->board_set_power(0);
1103
1104 return -ENODEV;
1105 }
1106
1107 int __init musb_platform_init(struct musb *musb, void *board_data)
1108 {
1109 struct platform_device *pdev;
1110 struct resource *mem;
1111 void __iomem *sync = NULL;
1112 int ret;
1113
1114 usb_nop_xceiv_register();
1115 musb->xceiv = otg_get_transceiver();
1116 if (!musb->xceiv)
1117 return -ENODEV;
1118
1119 pdev = to_platform_device(musb->controller);
1120
1121 /* dma address for async dma */
1122 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1123 musb->async = mem->start;
1124
1125 /* dma address for sync dma */
1126 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1127 if (!mem) {
1128 pr_debug("no sync dma resource?\n");
1129 ret = -ENODEV;
1130 goto done;
1131 }
1132 musb->sync = mem->start;
1133
1134 sync = ioremap(mem->start, resource_size(mem));
1135 if (!sync) {
1136 pr_debug("ioremap for sync failed\n");
1137 ret = -ENOMEM;
1138 goto done;
1139 }
1140 musb->sync_va = sync;
1141
1142 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1143 * FIFOs at 0x600, TUSB at 0x800
1144 */
1145 musb->mregs += TUSB_BASE_OFFSET;
1146
1147 ret = tusb_start(musb);
1148 if (ret) {
1149 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1150 ret);
1151 goto done;
1152 }
1153 musb->isr = tusb_interrupt;
1154
1155 if (is_host_enabled(musb))
1156 musb->board_set_vbus = tusb_source_power;
1157 if (is_peripheral_enabled(musb)) {
1158 musb->xceiv->set_power = tusb_draw_power;
1159 the_musb = musb;
1160 }
1161
1162 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1163
1164 done:
1165 if (ret < 0) {
1166 if (sync)
1167 iounmap(sync);
1168 usb_nop_xceiv_unregister();
1169 }
1170 return ret;
1171 }
1172
1173 int musb_platform_exit(struct musb *musb)
1174 {
1175 del_timer_sync(&musb_idle_timer);
1176 the_musb = NULL;
1177
1178 if (musb->board_set_power)
1179 musb->board_set_power(0);
1180
1181 iounmap(musb->sync_va);
1182 usb_nop_xceiv_unregister();
1183 return 0;
1184 }
kernel-based virtual machine