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[SPARC64]: Avoid membar instructions in delay slots.
[linux-2.6/kvm.git] / arch / sparc64 / mm / init.c
blob8fc413cb6acd9116763ce2eb4edcf12d0d765f3c
1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/fs.h>
21 #include <linux/seq_file.h>
22
23 #include <asm/head.h>
24 #include <asm/system.h>
25 #include <asm/page.h>
26 #include <asm/pgalloc.h>
27 #include <asm/pgtable.h>
28 #include <asm/oplib.h>
29 #include <asm/iommu.h>
30 #include <asm/io.h>
31 #include <asm/uaccess.h>
32 #include <asm/mmu_context.h>
33 #include <asm/tlbflush.h>
34 #include <asm/dma.h>
35 #include <asm/starfire.h>
36 #include <asm/tlb.h>
37 #include <asm/spitfire.h>
38 #include <asm/sections.h>
39
40 extern void device_scan(void);
41
42 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
43
44 unsigned long *sparc64_valid_addr_bitmap;
45
46 /* Ugly, but necessary... -DaveM */
47 unsigned long phys_base;
48 unsigned long kern_base;
49 unsigned long kern_size;
50 unsigned long pfn_base;
51
52 /* This is even uglier. We have a problem where the kernel may not be
53 * located at phys_base. However, initial __alloc_bootmem() calls need to
54 * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
55 * those page mappings wont work. Things are ok after inherit_prom_mappings
56 * is called though. Dave says he'll clean this up some other time.
57 * -- BenC
58 */
59 static unsigned long bootmap_base;
60
61 /* get_new_mmu_context() uses "cache + 1". */
62 DEFINE_SPINLOCK(ctx_alloc_lock);
63 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
64 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
65 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
66
67 /* References to special section boundaries */
68 extern char _start[], _end[];
69
70 /* Initial ramdisk setup */
71 extern unsigned long sparc_ramdisk_image64;
72 extern unsigned int sparc_ramdisk_image;
73 extern unsigned int sparc_ramdisk_size;
74
75 struct page *mem_map_zero;
76
77 int bigkernel = 0;
78
79 /* XXX Tune this... */
80 #define PGT_CACHE_LOW 25
81 #define PGT_CACHE_HIGH 50
82
83 void check_pgt_cache(void)
84 {
85 preempt_disable();
86 if (pgtable_cache_size > PGT_CACHE_HIGH) {
87 do {
88 if (pgd_quicklist)
89 free_pgd_slow(get_pgd_fast());
90 if (pte_quicklist[0])
91 free_pte_slow(pte_alloc_one_fast(NULL, 0));
92 if (pte_quicklist[1])
93 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
94 } while (pgtable_cache_size > PGT_CACHE_LOW);
95 }
96 preempt_enable();
97 }
98
99 #ifdef CONFIG_DEBUG_DCFLUSH
100 atomic_t dcpage_flushes = ATOMIC_INIT(0);
101 #ifdef CONFIG_SMP
102 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
103 #endif
104 #endif
105
106 __inline__ void flush_dcache_page_impl(struct page *page)
107 {
108 #ifdef CONFIG_DEBUG_DCFLUSH
109 atomic_inc(&dcpage_flushes);
110 #endif
111
112 #ifdef DCACHE_ALIASING_POSSIBLE
113 __flush_dcache_page(page_address(page),
114 ((tlb_type == spitfire) &&
115 page_mapping(page) != NULL));
116 #else
117 if (page_mapping(page) != NULL &&
118 tlb_type == spitfire)
119 __flush_icache_page(__pa(page_address(page)));
120 #endif
121 }
122
123 #define PG_dcache_dirty PG_arch_1
124
125 #define dcache_dirty_cpu(page) \
126 (((page)->flags >> 24) & (NR_CPUS - 1UL))
127
128 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
129 {
130 unsigned long mask = this_cpu;
131 unsigned long non_cpu_bits = ~((NR_CPUS - 1UL) << 24UL);
132 mask = (mask << 24) | (1UL << PG_dcache_dirty);
133 __asm__ __volatile__("1:\n\t"
134 "ldx [%2], %%g7\n\t"
135 "and %%g7, %1, %%g1\n\t"
136 "or %%g1, %0, %%g1\n\t"
137 "casx [%2], %%g7, %%g1\n\t"
138 "cmp %%g7, %%g1\n\t"
139 "membar #StoreLoad | #StoreStore\n\t"
140 "bne,pn %%xcc, 1b\n\t"
141 " nop"
142 : /* no outputs */
143 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
144 : "g1", "g7");
145 }
146
147 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
148 {
149 unsigned long mask = (1UL << PG_dcache_dirty);
150
151 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
152 "1:\n\t"
153 "ldx [%2], %%g7\n\t"
154 "srlx %%g7, 24, %%g1\n\t"
155 "and %%g1, %3, %%g1\n\t"
156 "cmp %%g1, %0\n\t"
157 "bne,pn %%icc, 2f\n\t"
158 " andn %%g7, %1, %%g1\n\t"
159 "casx [%2], %%g7, %%g1\n\t"
160 "cmp %%g7, %%g1\n\t"
161 "membar #StoreLoad | #StoreStore\n\t"
162 "bne,pn %%xcc, 1b\n\t"
163 " nop\n"
164 "2:"
165 : /* no outputs */
166 : "r" (cpu), "r" (mask), "r" (&page->flags),
167 "i" (NR_CPUS - 1UL)
168 : "g1", "g7");
169 }
170
171 extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
172
173 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
174 {
175 struct page *page;
176 unsigned long pfn;
177 unsigned long pg_flags;
178
179 pfn = pte_pfn(pte);
180 if (pfn_valid(pfn) &&
181 (page = pfn_to_page(pfn), page_mapping(page)) &&
182 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
183 int cpu = ((pg_flags >> 24) & (NR_CPUS - 1UL));
184 int this_cpu = get_cpu();
185
186 /* This is just to optimize away some function calls
187 * in the SMP case.
188 */
189 if (cpu == this_cpu)
190 flush_dcache_page_impl(page);
191 else
192 smp_flush_dcache_page_impl(page, cpu);
193
194 clear_dcache_dirty_cpu(page, cpu);
195
196 put_cpu();
197 }
198
199 if (get_thread_fault_code())
200 __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),
201 address, pte, get_thread_fault_code());
202 }
203
204 void flush_dcache_page(struct page *page)
205 {
206 struct address_space *mapping;
207 int this_cpu;
208
209 /* Do not bother with the expensive D-cache flush if it
210 * is merely the zero page. The 'bigcore' testcase in GDB
211 * causes this case to run millions of times.
212 */
213 if (page == ZERO_PAGE(0))
214 return;
215
216 this_cpu = get_cpu();
217
218 mapping = page_mapping(page);
219 if (mapping && !mapping_mapped(mapping)) {
220 int dirty = test_bit(PG_dcache_dirty, &page->flags);
221 if (dirty) {
222 int dirty_cpu = dcache_dirty_cpu(page);
223
224 if (dirty_cpu == this_cpu)
225 goto out;
226 smp_flush_dcache_page_impl(page, dirty_cpu);
227 }
228 set_dcache_dirty(page, this_cpu);
229 } else {
230 /* We could delay the flush for the !page_mapping
231 * case too. But that case is for exec env/arg
232 * pages and those are %99 certainly going to get
233 * faulted into the tlb (and thus flushed) anyways.
234 */
235 flush_dcache_page_impl(page);
236 }
237
238 out:
239 put_cpu();
240 }
241
242 void flush_icache_range(unsigned long start, unsigned long end)
243 {
244 /* Cheetah has coherent I-cache. */
245 if (tlb_type == spitfire) {
246 unsigned long kaddr;
247
248 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
249 __flush_icache_page(__get_phys(kaddr));
250 }
251 }
252
253 unsigned long page_to_pfn(struct page *page)
254 {
255 return (unsigned long) ((page - mem_map) + pfn_base);
256 }
257
258 struct page *pfn_to_page(unsigned long pfn)
259 {
260 return (mem_map + (pfn - pfn_base));
261 }
262
263 void show_mem(void)
264 {
265 printk("Mem-info:\n");
266 show_free_areas();
267 printk("Free swap: %6ldkB\n",
268 nr_swap_pages << (PAGE_SHIFT-10));
269 printk("%ld pages of RAM\n", num_physpages);
270 printk("%d free pages\n", nr_free_pages());
271 printk("%d pages in page table cache\n",pgtable_cache_size);
272 }
273
274 void mmu_info(struct seq_file *m)
275 {
276 if (tlb_type == cheetah)
277 seq_printf(m, "MMU Type\t: Cheetah\n");
278 else if (tlb_type == cheetah_plus)
279 seq_printf(m, "MMU Type\t: Cheetah+\n");
280 else if (tlb_type == spitfire)
281 seq_printf(m, "MMU Type\t: Spitfire\n");
282 else
283 seq_printf(m, "MMU Type\t: ???\n");
284
285 #ifdef CONFIG_DEBUG_DCFLUSH
286 seq_printf(m, "DCPageFlushes\t: %d\n",
287 atomic_read(&dcpage_flushes));
288 #ifdef CONFIG_SMP
289 seq_printf(m, "DCPageFlushesXC\t: %d\n",
290 atomic_read(&dcpage_flushes_xcall));
291 #endif /* CONFIG_SMP */
292 #endif /* CONFIG_DEBUG_DCFLUSH */
293 }
294
295 struct linux_prom_translation {
296 unsigned long virt;
297 unsigned long size;
298 unsigned long data;
299 };
300
301 extern unsigned long prom_boot_page;
302 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
303 extern int prom_get_mmu_ihandle(void);
304 extern void register_prom_callbacks(void);
305
306 /* Exported for SMP bootup purposes. */
307 unsigned long kern_locked_tte_data;
308
309 void __init early_pgtable_allocfail(char *type)
310 {
311 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
312 prom_halt();
313 }
314
315 #define BASE_PAGE_SIZE 8192
316 static pmd_t *prompmd;
317
318 /*
319 * Translate PROM's mapping we capture at boot time into physical address.
320 * The second parameter is only set from prom_callback() invocations.
321 */
322 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
323 {
324 pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
325 pte_t *ptep;
326 unsigned long base;
327
328 if (pmd_none(*pmdp)) {
329 if (error)
330 *error = 1;
331 return(0);
332 }
333 ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
334 if (!pte_present(*ptep)) {
335 if (error)
336 *error = 1;
337 return(0);
338 }
339 if (error) {
340 *error = 0;
341 return(pte_val(*ptep));
342 }
343 base = pte_val(*ptep) & _PAGE_PADDR;
344 return(base + (promva & (BASE_PAGE_SIZE - 1)));
345 }
346
347 static void inherit_prom_mappings(void)
348 {
349 struct linux_prom_translation *trans;
350 unsigned long phys_page, tte_vaddr, tte_data;
351 void (*remap_func)(unsigned long, unsigned long, int);
352 pmd_t *pmdp;
353 pte_t *ptep;
354 int node, n, i, tsz;
355 extern unsigned int obp_iaddr_patch[2], obp_daddr_patch[2];
356
357 node = prom_finddevice("/virtual-memory");
358 n = prom_getproplen(node, "translations");
359 if (n == 0 || n == -1) {
360 prom_printf("Couldn't get translation property\n");
361 prom_halt();
362 }
363 n += 5 * sizeof(struct linux_prom_translation);
364 for (tsz = 1; tsz < n; tsz <<= 1)
365 /* empty */;
366 trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
367 if (trans == NULL) {
368 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
369 prom_halt();
370 }
371 memset(trans, 0, tsz);
372
373 if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
374 prom_printf("Couldn't get translation property\n");
375 prom_halt();
376 }
377 n = n / sizeof(*trans);
378
379 /*
380 * The obp translations are saved based on 8k pagesize, since obp can
381 * use a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000,
382 * ie obp range, are handled in entry.S and do not use the vpte scheme
383 * (see rant in inherit_locked_prom_mappings()).
384 */
385 #define OBP_PMD_SIZE 2048
386 prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
387 if (prompmd == NULL)
388 early_pgtable_allocfail("pmd");
389 memset(prompmd, 0, OBP_PMD_SIZE);
390 for (i = 0; i < n; i++) {
391 unsigned long vaddr;
392
393 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
394 for (vaddr = trans[i].virt;
395 ((vaddr < trans[i].virt + trans[i].size) &&
396 (vaddr < HI_OBP_ADDRESS));
397 vaddr += BASE_PAGE_SIZE) {
398 unsigned long val;
399
400 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
401 if (pmd_none(*pmdp)) {
402 ptep = __alloc_bootmem(BASE_PAGE_SIZE,
403 BASE_PAGE_SIZE,
404 bootmap_base);
405 if (ptep == NULL)
406 early_pgtable_allocfail("pte");
407 memset(ptep, 0, BASE_PAGE_SIZE);
408 pmd_set(pmdp, ptep);
409 }
410 ptep = (pte_t *)__pmd_page(*pmdp) +
411 ((vaddr >> 13) & 0x3ff);
412
413 val = trans[i].data;
414
415 /* Clear diag TTE bits. */
416 if (tlb_type == spitfire)
417 val &= ~0x0003fe0000000000UL;
418
419 set_pte_at(&init_mm, vaddr,
420 ptep, __pte(val | _PAGE_MODIFIED));
421 trans[i].data += BASE_PAGE_SIZE;
422 }
423 }
424 }
425 phys_page = __pa(prompmd);
426 obp_iaddr_patch[0] |= (phys_page >> 10);
427 obp_iaddr_patch[1] |= (phys_page & 0x3ff);
428 flushi((long)&obp_iaddr_patch[0]);
429 obp_daddr_patch[0] |= (phys_page >> 10);
430 obp_daddr_patch[1] |= (phys_page & 0x3ff);
431 flushi((long)&obp_daddr_patch[0]);
432
433 /* Now fixup OBP's idea about where we really are mapped. */
434 prom_printf("Remapping the kernel... ");
435
436 /* Spitfire Errata #32 workaround */
437 /* NOTE: Using plain zero for the context value is
438 * correct here, we are not using the Linux trap
439 * tables yet so we should not use the special
440 * UltraSPARC-III+ page size encodings yet.
441 */
442 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
443 "flush %%g6"
444 : /* No outputs */
445 : "r" (0), "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
446
447 switch (tlb_type) {
448 default:
449 case spitfire:
450 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
451 break;
452
453 case cheetah:
454 case cheetah_plus:
455 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
456 break;
457 };
458
459 phys_page &= _PAGE_PADDR;
460 phys_page += ((unsigned long)&prom_boot_page -
461 (unsigned long)KERNBASE);
462
463 if (tlb_type == spitfire) {
464 /* Lock this into i/d tlb entry 59 */
465 __asm__ __volatile__(
466 "stxa %%g0, [%2] %3\n\t"
467 "stxa %0, [%1] %4\n\t"
468 "membar #Sync\n\t"
469 "flush %%g6\n\t"
470 "stxa %%g0, [%2] %5\n\t"
471 "stxa %0, [%1] %6\n\t"
472 "membar #Sync\n\t"
473 "flush %%g6"
474 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
475 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
476 "r" (59 << 3), "r" (TLB_TAG_ACCESS),
477 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
478 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
479 : "memory");
480 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
481 /* Lock this into i/d tlb-0 entry 11 */
482 __asm__ __volatile__(
483 "stxa %%g0, [%2] %3\n\t"
484 "stxa %0, [%1] %4\n\t"
485 "membar #Sync\n\t"
486 "flush %%g6\n\t"
487 "stxa %%g0, [%2] %5\n\t"
488 "stxa %0, [%1] %6\n\t"
489 "membar #Sync\n\t"
490 "flush %%g6"
491 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
492 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
493 "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
494 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
495 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
496 : "memory");
497 } else {
498 /* Implement me :-) */
499 BUG();
500 }
501
502 tte_vaddr = (unsigned long) KERNBASE;
503
504 /* Spitfire Errata #32 workaround */
505 /* NOTE: Using plain zero for the context value is
506 * correct here, we are not using the Linux trap
507 * tables yet so we should not use the special
508 * UltraSPARC-III+ page size encodings yet.
509 */
510 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
511 "flush %%g6"
512 : /* No outputs */
513 : "r" (0),
514 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
515
516 if (tlb_type == spitfire)
517 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
518 else
519 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
520
521 kern_locked_tte_data = tte_data;
522
523 remap_func = (void *) ((unsigned long) &prom_remap -
524 (unsigned long) &prom_boot_page);
525
526
527 /* Spitfire Errata #32 workaround */
528 /* NOTE: Using plain zero for the context value is
529 * correct here, we are not using the Linux trap
530 * tables yet so we should not use the special
531 * UltraSPARC-III+ page size encodings yet.
532 */
533 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
534 "flush %%g6"
535 : /* No outputs */
536 : "r" (0),
537 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
538
539 remap_func((tlb_type == spitfire ?
540 (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
541 (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
542 (unsigned long) KERNBASE,
543 prom_get_mmu_ihandle());
544
545 if (bigkernel)
546 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
547 (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
548
549 /* Flush out that temporary mapping. */
550 spitfire_flush_dtlb_nucleus_page(0x0);
551 spitfire_flush_itlb_nucleus_page(0x0);
552
553 /* Now lock us back into the TLBs via OBP. */
554 prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
555 prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
556 if (bigkernel) {
557 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
558 tte_vaddr + 0x400000);
559 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
560 tte_vaddr + 0x400000);
561 }
562
563 /* Re-read translations property. */
564 if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
565 prom_printf("Couldn't get translation property\n");
566 prom_halt();
567 }
568 n = n / sizeof(*trans);
569
570 for (i = 0; i < n; i++) {
571 unsigned long vaddr = trans[i].virt;
572 unsigned long size = trans[i].size;
573
574 if (vaddr < 0xf0000000UL) {
575 unsigned long avoid_start = (unsigned long) KERNBASE;
576 unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
577
578 if (bigkernel)
579 avoid_end += (4 * 1024 * 1024);
580 if (vaddr < avoid_start) {
581 unsigned long top = vaddr + size;
582
583 if (top > avoid_start)
584 top = avoid_start;
585 prom_unmap(top - vaddr, vaddr);
586 }
587 if ((vaddr + size) > avoid_end) {
588 unsigned long bottom = vaddr;
589
590 if (bottom < avoid_end)
591 bottom = avoid_end;
592 prom_unmap((vaddr + size) - bottom, bottom);
593 }
594 }
595 }
596
597 prom_printf("done.\n");
598
599 register_prom_callbacks();
600 }
601
602 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
603 * upwards as reserved for use by the firmware (I wonder if this
604 * will be the same on Cheetah...). We use this virtual address
605 * range for the VPTE table mappings of the nucleus so we need
606 * to zap them when we enter the PROM. -DaveM
607 */
608 static void __flush_nucleus_vptes(void)
609 {
610 unsigned long prom_reserved_base = 0xfffffffc00000000UL;
611 int i;
612
613 /* Only DTLB must be checked for VPTE entries. */
614 if (tlb_type == spitfire) {
615 for (i = 0; i < 63; i++) {
616 unsigned long tag;
617
618 /* Spitfire Errata #32 workaround */
619 /* NOTE: Always runs on spitfire, so no cheetah+
620 * page size encodings.
621 */
622 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
623 "flush %%g6"
624 : /* No outputs */
625 : "r" (0),
626 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
627
628 tag = spitfire_get_dtlb_tag(i);
629 if (((tag & ~(PAGE_MASK)) == 0) &&
630 ((tag & (PAGE_MASK)) >= prom_reserved_base)) {
631 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
632 "membar #Sync"
633 : /* no outputs */
634 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
635 spitfire_put_dtlb_data(i, 0x0UL);
636 }
637 }
638 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
639 for (i = 0; i < 512; i++) {
640 unsigned long tag = cheetah_get_dtlb_tag(i, 2);
641
642 if ((tag & ~PAGE_MASK) == 0 &&
643 (tag & PAGE_MASK) >= prom_reserved_base) {
644 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
645 "membar #Sync"
646 : /* no outputs */
647 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
648 cheetah_put_dtlb_data(i, 0x0UL, 2);
649 }
650
651 if (tlb_type != cheetah_plus)
652 continue;
653
654 tag = cheetah_get_dtlb_tag(i, 3);
655
656 if ((tag & ~PAGE_MASK) == 0 &&
657 (tag & PAGE_MASK) >= prom_reserved_base) {
658 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
659 "membar #Sync"
660 : /* no outputs */
661 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
662 cheetah_put_dtlb_data(i, 0x0UL, 3);
663 }
664 }
665 } else {
666 /* Implement me :-) */
667 BUG();
668 }
669 }
670
671 static int prom_ditlb_set;
672 struct prom_tlb_entry {
673 int tlb_ent;
674 unsigned long tlb_tag;
675 unsigned long tlb_data;
676 };
677 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
678
679 void prom_world(int enter)
680 {
681 unsigned long pstate;
682 int i;
683
684 if (!enter)
685 set_fs((mm_segment_t) { get_thread_current_ds() });
686
687 if (!prom_ditlb_set)
688 return;
689
690 /* Make sure the following runs atomically. */
691 __asm__ __volatile__("flushw\n\t"
692 "rdpr %%pstate, %0\n\t"
693 "wrpr %0, %1, %%pstate"
694 : "=r" (pstate)
695 : "i" (PSTATE_IE));
696
697 if (enter) {
698 /* Kick out nucleus VPTEs. */
699 __flush_nucleus_vptes();
700
701 /* Install PROM world. */
702 for (i = 0; i < 16; i++) {
703 if (prom_dtlb[i].tlb_ent != -1) {
704 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
705 "membar #Sync"
706 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
707 "i" (ASI_DMMU));
708 if (tlb_type == spitfire)
709 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
710 prom_dtlb[i].tlb_data);
711 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
712 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
713 prom_dtlb[i].tlb_data);
714 }
715 if (prom_itlb[i].tlb_ent != -1) {
716 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
717 "membar #Sync"
718 : : "r" (prom_itlb[i].tlb_tag),
719 "r" (TLB_TAG_ACCESS),
720 "i" (ASI_IMMU));
721 if (tlb_type == spitfire)
722 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
723 prom_itlb[i].tlb_data);
724 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
725 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
726 prom_itlb[i].tlb_data);
727 }
728 }
729 } else {
730 for (i = 0; i < 16; i++) {
731 if (prom_dtlb[i].tlb_ent != -1) {
732 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
733 "membar #Sync"
734 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
735 if (tlb_type == spitfire)
736 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
737 else
738 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
739 }
740 if (prom_itlb[i].tlb_ent != -1) {
741 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
742 "membar #Sync"
743 : : "r" (TLB_TAG_ACCESS),
744 "i" (ASI_IMMU));
745 if (tlb_type == spitfire)
746 spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
747 else
748 cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
749 }
750 }
751 }
752 __asm__ __volatile__("wrpr %0, 0, %%pstate"
753 : : "r" (pstate));
754 }
755
756 void inherit_locked_prom_mappings(int save_p)
757 {
758 int i;
759 int dtlb_seen = 0;
760 int itlb_seen = 0;
761
762 /* Fucking losing PROM has more mappings in the TLB, but
763 * it (conveniently) fails to mention any of these in the
764 * translations property. The only ones that matter are
765 * the locked PROM tlb entries, so we impose the following
766 * irrecovable rule on the PROM, it is allowed 8 locked
767 * entries in the ITLB and 8 in the DTLB.
768 *
769 * Supposedly the upper 16GB of the address space is
770 * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
771 * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface
772 * used between the client program and the firmware on sun5
773 * systems to coordinate mmu mappings is also COMPLETELY
774 * UNDOCUMENTED!!!!!! Thanks S(t)un!
775 */
776 if (save_p) {
777 for (i = 0; i < 16; i++) {
778 prom_itlb[i].tlb_ent = -1;
779 prom_dtlb[i].tlb_ent = -1;
780 }
781 }
782 if (tlb_type == spitfire) {
783 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
784 for (i = 0; i < high; i++) {
785 unsigned long data;
786
787 /* Spitfire Errata #32 workaround */
788 /* NOTE: Always runs on spitfire, so no cheetah+
789 * page size encodings.
790 */
791 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
792 "flush %%g6"
793 : /* No outputs */
794 : "r" (0),
795 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
796
797 data = spitfire_get_dtlb_data(i);
798 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
799 unsigned long tag;
800
801 /* Spitfire Errata #32 workaround */
802 /* NOTE: Always runs on spitfire, so no
803 * cheetah+ page size encodings.
804 */
805 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
806 "flush %%g6"
807 : /* No outputs */
808 : "r" (0),
809 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
810
811 tag = spitfire_get_dtlb_tag(i);
812 if (save_p) {
813 prom_dtlb[dtlb_seen].tlb_ent = i;
814 prom_dtlb[dtlb_seen].tlb_tag = tag;
815 prom_dtlb[dtlb_seen].tlb_data = data;
816 }
817 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
818 "membar #Sync"
819 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
820 spitfire_put_dtlb_data(i, 0x0UL);
821
822 dtlb_seen++;
823 if (dtlb_seen > 15)
824 break;
825 }
826 }
827
828 for (i = 0; i < high; i++) {
829 unsigned long data;
830
831 /* Spitfire Errata #32 workaround */
832 /* NOTE: Always runs on spitfire, so no
833 * cheetah+ page size encodings.
834 */
835 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
836 "flush %%g6"
837 : /* No outputs */
838 : "r" (0),
839 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
840
841 data = spitfire_get_itlb_data(i);
842 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
843 unsigned long tag;
844
845 /* Spitfire Errata #32 workaround */
846 /* NOTE: Always runs on spitfire, so no
847 * cheetah+ page size encodings.
848 */
849 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
850 "flush %%g6"
851 : /* No outputs */
852 : "r" (0),
853 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
854
855 tag = spitfire_get_itlb_tag(i);
856 if (save_p) {
857 prom_itlb[itlb_seen].tlb_ent = i;
858 prom_itlb[itlb_seen].tlb_tag = tag;
859 prom_itlb[itlb_seen].tlb_data = data;
860 }
861 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
862 "membar #Sync"
863 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
864 spitfire_put_itlb_data(i, 0x0UL);
865
866 itlb_seen++;
867 if (itlb_seen > 15)
868 break;
869 }
870 }
871 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
872 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
873
874 for (i = 0; i < high; i++) {
875 unsigned long data;
876
877 data = cheetah_get_ldtlb_data(i);
878 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
879 unsigned long tag;
880
881 tag = cheetah_get_ldtlb_tag(i);
882 if (save_p) {
883 prom_dtlb[dtlb_seen].tlb_ent = i;
884 prom_dtlb[dtlb_seen].tlb_tag = tag;
885 prom_dtlb[dtlb_seen].tlb_data = data;
886 }
887 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
888 "membar #Sync"
889 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
890 cheetah_put_ldtlb_data(i, 0x0UL);
891
892 dtlb_seen++;
893 if (dtlb_seen > 15)
894 break;
895 }
896 }
897
898 for (i = 0; i < high; i++) {
899 unsigned long data;
900
901 data = cheetah_get_litlb_data(i);
902 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
903 unsigned long tag;
904
905 tag = cheetah_get_litlb_tag(i);
906 if (save_p) {
907 prom_itlb[itlb_seen].tlb_ent = i;
908 prom_itlb[itlb_seen].tlb_tag = tag;
909 prom_itlb[itlb_seen].tlb_data = data;
910 }
911 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
912 "membar #Sync"
913 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
914 cheetah_put_litlb_data(i, 0x0UL);
915
916 itlb_seen++;
917 if (itlb_seen > 15)
918 break;
919 }
920 }
921 } else {
922 /* Implement me :-) */
923 BUG();
924 }
925 if (save_p)
926 prom_ditlb_set = 1;
927 }
928
929 /* Give PROM back his world, done during reboots... */
930 void prom_reload_locked(void)
931 {
932 int i;
933
934 for (i = 0; i < 16; i++) {
935 if (prom_dtlb[i].tlb_ent != -1) {
936 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
937 "membar #Sync"
938 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
939 "i" (ASI_DMMU));
940 if (tlb_type == spitfire)
941 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
942 prom_dtlb[i].tlb_data);
943 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
944 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
945 prom_dtlb[i].tlb_data);
946 }
947
948 if (prom_itlb[i].tlb_ent != -1) {
949 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
950 "membar #Sync"
951 : : "r" (prom_itlb[i].tlb_tag),
952 "r" (TLB_TAG_ACCESS),
953 "i" (ASI_IMMU));
954 if (tlb_type == spitfire)
955 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
956 prom_itlb[i].tlb_data);
957 else
958 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
959 prom_itlb[i].tlb_data);
960 }
961 }
962 }
963
964 #ifdef DCACHE_ALIASING_POSSIBLE
965 void __flush_dcache_range(unsigned long start, unsigned long end)
966 {
967 unsigned long va;
968
969 if (tlb_type == spitfire) {
970 int n = 0;
971
972 for (va = start; va < end; va += 32) {
973 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
974 if (++n >= 512)
975 break;
976 }
977 } else {
978 start = __pa(start);
979 end = __pa(end);
980 for (va = start; va < end; va += 32)
981 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
982 "membar #Sync"
983 : /* no outputs */
984 : "r" (va),
985 "i" (ASI_DCACHE_INVALIDATE));
986 }
987 }
988 #endif /* DCACHE_ALIASING_POSSIBLE */
989
990 /* If not locked, zap it. */
991 void __flush_tlb_all(void)
992 {
993 unsigned long pstate;
994 int i;
995
996 __asm__ __volatile__("flushw\n\t"
997 "rdpr %%pstate, %0\n\t"
998 "wrpr %0, %1, %%pstate"
999 : "=r" (pstate)
1000 : "i" (PSTATE_IE));
1001 if (tlb_type == spitfire) {
1002 for (i = 0; i < 64; i++) {
1003 /* Spitfire Errata #32 workaround */
1004 /* NOTE: Always runs on spitfire, so no
1005 * cheetah+ page size encodings.
1006 */
1007 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1008 "flush %%g6"
1009 : /* No outputs */
1010 : "r" (0),
1011 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1012
1013 if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1014 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1015 "membar #Sync"
1016 : /* no outputs */
1017 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1018 spitfire_put_dtlb_data(i, 0x0UL);
1019 }
1020
1021 /* Spitfire Errata #32 workaround */
1022 /* NOTE: Always runs on spitfire, so no
1023 * cheetah+ page size encodings.
1024 */
1025 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1026 "flush %%g6"
1027 : /* No outputs */
1028 : "r" (0),
1029 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1030
1031 if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1032 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1033 "membar #Sync"
1034 : /* no outputs */
1035 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1036 spitfire_put_itlb_data(i, 0x0UL);
1037 }
1038 }
1039 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1040 cheetah_flush_dtlb_all();
1041 cheetah_flush_itlb_all();
1042 }
1043 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1044 : : "r" (pstate));
1045 }
1046
1047 /* Caller does TLB context flushing on local CPU if necessary.
1048 * The caller also ensures that CTX_VALID(mm->context) is false.
1049 *
1050 * We must be careful about boundary cases so that we never
1051 * let the user have CTX 0 (nucleus) or we ever use a CTX
1052 * version of zero (and thus NO_CONTEXT would not be caught
1053 * by version mis-match tests in mmu_context.h).
1054 */
1055 void get_new_mmu_context(struct mm_struct *mm)
1056 {
1057 unsigned long ctx, new_ctx;
1058 unsigned long orig_pgsz_bits;
1059
1060
1061 spin_lock(&ctx_alloc_lock);
1062 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1063 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1064 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1065 if (new_ctx >= (1 << CTX_NR_BITS)) {
1066 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1067 if (new_ctx >= ctx) {
1068 int i;
1069 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1070 CTX_FIRST_VERSION;
1071 if (new_ctx == 1)
1072 new_ctx = CTX_FIRST_VERSION;
1073
1074 /* Don't call memset, for 16 entries that's just
1075 * plain silly...
1076 */
1077 mmu_context_bmap[0] = 3;
1078 mmu_context_bmap[1] = 0;
1079 mmu_context_bmap[2] = 0;
1080 mmu_context_bmap[3] = 0;
1081 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1082 mmu_context_bmap[i + 0] = 0;
1083 mmu_context_bmap[i + 1] = 0;
1084 mmu_context_bmap[i + 2] = 0;
1085 mmu_context_bmap[i + 3] = 0;
1086 }
1087 goto out;
1088 }
1089 }
1090 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1091 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1092 out:
1093 tlb_context_cache = new_ctx;
1094 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1095 spin_unlock(&ctx_alloc_lock);
1096 }
1097
1098 #ifndef CONFIG_SMP
1099 struct pgtable_cache_struct pgt_quicklists;
1100 #endif
1101
1102 /* OK, we have to color these pages. The page tables are accessed
1103 * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1104 * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1105 * other parts of the kernel. By coloring, we make sure that the tlbmiss
1106 * fast handlers do not get data from old/garbage dcache lines that
1107 * correspond to an old/stale virtual address (user/kernel) that
1108 * previously mapped the pagetable page while accessing vpte range
1109 * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1110 * color is the same, then when the kernel initializes the pagetable
1111 * using the later address range, accesses with the first address
1112 * range will see the newly initialized data rather than the garbage.
1113 */
1114 #ifdef DCACHE_ALIASING_POSSIBLE
1115 #define DC_ALIAS_SHIFT 1
1116 #else
1117 #define DC_ALIAS_SHIFT 0
1118 #endif
1119 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1120 {
1121 struct page *page;
1122 unsigned long color;
1123
1124 {
1125 pte_t *ptep = pte_alloc_one_fast(mm, address);
1126
1127 if (ptep)
1128 return ptep;
1129 }
1130
1131 color = VPTE_COLOR(address);
1132 page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1133 if (page) {
1134 unsigned long *to_free;
1135 unsigned long paddr;
1136 pte_t *pte;
1137
1138 #ifdef DCACHE_ALIASING_POSSIBLE
1139 set_page_count(page, 1);
1140 ClearPageCompound(page);
1141
1142 set_page_count((page + 1), 1);
1143 ClearPageCompound(page + 1);
1144 #endif
1145 paddr = (unsigned long) page_address(page);
1146 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1147
1148 if (!color) {
1149 pte = (pte_t *) paddr;
1150 to_free = (unsigned long *) (paddr + PAGE_SIZE);
1151 } else {
1152 pte = (pte_t *) (paddr + PAGE_SIZE);
1153 to_free = (unsigned long *) paddr;
1154 }
1155
1156 #ifdef DCACHE_ALIASING_POSSIBLE
1157 /* Now free the other one up, adjust cache size. */
1158 preempt_disable();
1159 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1160 pte_quicklist[color ^ 0x1] = to_free;
1161 pgtable_cache_size++;
1162 preempt_enable();
1163 #endif
1164
1165 return pte;
1166 }
1167 return NULL;
1168 }
1169
1170 void sparc_ultra_dump_itlb(void)
1171 {
1172 int slot;
1173
1174 if (tlb_type == spitfire) {
1175 printk ("Contents of itlb: ");
1176 for (slot = 0; slot < 14; slot++) printk (" ");
1177 printk ("%2x:%016lx,%016lx\n",
1178 0,
1179 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1180 for (slot = 1; slot < 64; slot+=3) {
1181 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1182 slot,
1183 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1184 slot+1,
1185 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1186 slot+2,
1187 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1188 }
1189 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1190 printk ("Contents of itlb0:\n");
1191 for (slot = 0; slot < 16; slot+=2) {
1192 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1193 slot,
1194 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1195 slot+1,
1196 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1197 }
1198 printk ("Contents of itlb2:\n");
1199 for (slot = 0; slot < 128; slot+=2) {
1200 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1201 slot,
1202 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1203 slot+1,
1204 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1205 }
1206 }
1207 }
1208
1209 void sparc_ultra_dump_dtlb(void)
1210 {
1211 int slot;
1212
1213 if (tlb_type == spitfire) {
1214 printk ("Contents of dtlb: ");
1215 for (slot = 0; slot < 14; slot++) printk (" ");
1216 printk ("%2x:%016lx,%016lx\n", 0,
1217 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1218 for (slot = 1; slot < 64; slot+=3) {
1219 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1220 slot,
1221 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1222 slot+1,
1223 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1224 slot+2,
1225 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1226 }
1227 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1228 printk ("Contents of dtlb0:\n");
1229 for (slot = 0; slot < 16; slot+=2) {
1230 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1231 slot,
1232 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1233 slot+1,
1234 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1235 }
1236 printk ("Contents of dtlb2:\n");
1237 for (slot = 0; slot < 512; slot+=2) {
1238 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1239 slot,
1240 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1241 slot+1,
1242 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1243 }
1244 if (tlb_type == cheetah_plus) {
1245 printk ("Contents of dtlb3:\n");
1246 for (slot = 0; slot < 512; slot+=2) {
1247 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1248 slot,
1249 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1250 slot+1,
1251 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1252 }
1253 }
1254 }
1255 }
1256
1257 extern unsigned long cmdline_memory_size;
1258
1259 unsigned long __init bootmem_init(unsigned long *pages_avail)
1260 {
1261 unsigned long bootmap_size, start_pfn, end_pfn;
1262 unsigned long end_of_phys_memory = 0UL;
1263 unsigned long bootmap_pfn, bytes_avail, size;
1264 int i;
1265
1266 #ifdef CONFIG_DEBUG_BOOTMEM
1267 prom_printf("bootmem_init: Scan sp_banks, ");
1268 #endif
1269
1270 bytes_avail = 0UL;
1271 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1272 end_of_phys_memory = sp_banks[i].base_addr +
1273 sp_banks[i].num_bytes;
1274 bytes_avail += sp_banks[i].num_bytes;
1275 if (cmdline_memory_size) {
1276 if (bytes_avail > cmdline_memory_size) {
1277 unsigned long slack = bytes_avail - cmdline_memory_size;
1278
1279 bytes_avail -= slack;
1280 end_of_phys_memory -= slack;
1281
1282 sp_banks[i].num_bytes -= slack;
1283 if (sp_banks[i].num_bytes == 0) {
1284 sp_banks[i].base_addr = 0xdeadbeef;
1285 } else {
1286 sp_banks[i+1].num_bytes = 0;
1287 sp_banks[i+1].base_addr = 0xdeadbeef;
1288 }
1289 break;
1290 }
1291 }
1292 }
1293
1294 *pages_avail = bytes_avail >> PAGE_SHIFT;
1295
1296 /* Start with page aligned address of last symbol in kernel
1297 * image. The kernel is hard mapped below PAGE_OFFSET in a
1298 * 4MB locked TLB translation.
1299 */
1300 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1301
1302 bootmap_pfn = start_pfn;
1303
1304 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1305
1306 #ifdef CONFIG_BLK_DEV_INITRD
1307 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1308 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1309 unsigned long ramdisk_image = sparc_ramdisk_image ?
1310 sparc_ramdisk_image : sparc_ramdisk_image64;
1311 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1312 ramdisk_image -= KERNBASE;
1313 initrd_start = ramdisk_image + phys_base;
1314 initrd_end = initrd_start + sparc_ramdisk_size;
1315 if (initrd_end > end_of_phys_memory) {
1316 printk(KERN_CRIT "initrd extends beyond end of memory "
1317 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1318 initrd_end, end_of_phys_memory);
1319 initrd_start = 0;
1320 }
1321 if (initrd_start) {
1322 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1323 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1324 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1325 }
1326 }
1327 #endif
1328 /* Initialize the boot-time allocator. */
1329 max_pfn = max_low_pfn = end_pfn;
1330 min_low_pfn = pfn_base;
1331
1332 #ifdef CONFIG_DEBUG_BOOTMEM
1333 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1334 min_low_pfn, bootmap_pfn, max_low_pfn);
1335 #endif
1336 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1337
1338 bootmap_base = bootmap_pfn << PAGE_SHIFT;
1339
1340 /* Now register the available physical memory with the
1341 * allocator.
1342 */
1343 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1344 #ifdef CONFIG_DEBUG_BOOTMEM
1345 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1346 i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1347 #endif
1348 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1349 }
1350
1351 #ifdef CONFIG_BLK_DEV_INITRD
1352 if (initrd_start) {
1353 size = initrd_end - initrd_start;
1354
1355 /* Resert the initrd image area. */
1356 #ifdef CONFIG_DEBUG_BOOTMEM
1357 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1358 initrd_start, initrd_end);
1359 #endif
1360 reserve_bootmem(initrd_start, size);
1361 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1362
1363 initrd_start += PAGE_OFFSET;
1364 initrd_end += PAGE_OFFSET;
1365 }
1366 #endif
1367 /* Reserve the kernel text/data/bss. */
1368 #ifdef CONFIG_DEBUG_BOOTMEM
1369 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1370 #endif
1371 reserve_bootmem(kern_base, kern_size);
1372 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1373
1374 /* Reserve the bootmem map. We do not account for it
1375 * in pages_avail because we will release that memory
1376 * in free_all_bootmem.
1377 */
1378 size = bootmap_size;
1379 #ifdef CONFIG_DEBUG_BOOTMEM
1380 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1381 (bootmap_pfn << PAGE_SHIFT), size);
1382 #endif
1383 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1384 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1385
1386 return end_pfn;
1387 }
1388
1389 /* paging_init() sets up the page tables */
1390
1391 extern void cheetah_ecache_flush_init(void);
1392
1393 static unsigned long last_valid_pfn;
1394
1395 void __init paging_init(void)
1396 {
1397 extern pmd_t swapper_pmd_dir[1024];
1398 extern unsigned int sparc64_vpte_patchme1[1];
1399 extern unsigned int sparc64_vpte_patchme2[1];
1400 unsigned long alias_base = kern_base + PAGE_OFFSET;
1401 unsigned long second_alias_page = 0;
1402 unsigned long pt, flags, end_pfn, pages_avail;
1403 unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1404 unsigned long real_end;
1405
1406 set_bit(0, mmu_context_bmap);
1407
1408 real_end = (unsigned long)_end;
1409 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1410 bigkernel = 1;
1411 #ifdef CONFIG_BLK_DEV_INITRD
1412 if (sparc_ramdisk_image || sparc_ramdisk_image64)
1413 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1414 #endif
1415
1416 /* We assume physical memory starts at some 4mb multiple,
1417 * if this were not true we wouldn't boot up to this point
1418 * anyways.
1419 */
1420 pt = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1421 pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1422 local_irq_save(flags);
1423 if (tlb_type == spitfire) {
1424 __asm__ __volatile__(
1425 " stxa %1, [%0] %3\n"
1426 " stxa %2, [%5] %4\n"
1427 " membar #Sync\n"
1428 " flush %%g6\n"
1429 " nop\n"
1430 " nop\n"
1431 " nop\n"
1432 : /* No outputs */
1433 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1434 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1435 : "memory");
1436 if (real_end >= KERNBASE + 0x340000) {
1437 second_alias_page = alias_base + 0x400000;
1438 __asm__ __volatile__(
1439 " stxa %1, [%0] %3\n"
1440 " stxa %2, [%5] %4\n"
1441 " membar #Sync\n"
1442 " flush %%g6\n"
1443 " nop\n"
1444 " nop\n"
1445 " nop\n"
1446 : /* No outputs */
1447 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1448 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1449 : "memory");
1450 }
1451 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1452 __asm__ __volatile__(
1453 " stxa %1, [%0] %3\n"
1454 " stxa %2, [%5] %4\n"
1455 " membar #Sync\n"
1456 " flush %%g6\n"
1457 " nop\n"
1458 " nop\n"
1459 " nop\n"
1460 : /* No outputs */
1461 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1462 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1463 : "memory");
1464 if (real_end >= KERNBASE + 0x340000) {
1465 second_alias_page = alias_base + 0x400000;
1466 __asm__ __volatile__(
1467 " stxa %1, [%0] %3\n"
1468 " stxa %2, [%5] %4\n"
1469 " membar #Sync\n"
1470 " flush %%g6\n"
1471 " nop\n"
1472 " nop\n"
1473 " nop\n"
1474 : /* No outputs */
1475 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1476 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1477 : "memory");
1478 }
1479 }
1480 local_irq_restore(flags);
1481
1482 /* Now set kernel pgd to upper alias so physical page computations
1483 * work.
1484 */
1485 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1486
1487 memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1488
1489 /* Now can init the kernel/bad page tables. */
1490 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1491 swapper_pmd_dir + (shift / sizeof(pgd_t)));
1492
1493 sparc64_vpte_patchme1[0] |=
1494 (((unsigned long)pgd_val(init_mm.pgd[0])) >> 10);
1495 sparc64_vpte_patchme2[0] |=
1496 (((unsigned long)pgd_val(init_mm.pgd[0])) & 0x3ff);
1497 flushi((long)&sparc64_vpte_patchme1[0]);
1498
1499 /* Setup bootmem... */
1500 pages_avail = 0;
1501 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1502
1503 /* Inherit non-locked OBP mappings. */
1504 inherit_prom_mappings();
1505
1506 /* Ok, we can use our TLB miss and window trap handlers safely.
1507 * We need to do a quick peek here to see if we are on StarFire
1508 * or not, so setup_tba can setup the IRQ globals correctly (it
1509 * needs to get the hard smp processor id correctly).
1510 */
1511 {
1512 extern void setup_tba(int);
1513 setup_tba(this_is_starfire);
1514 }
1515
1516 inherit_locked_prom_mappings(1);
1517
1518 /* We only created DTLB mapping of this stuff. */
1519 spitfire_flush_dtlb_nucleus_page(alias_base);
1520 if (second_alias_page)
1521 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1522
1523 __flush_tlb_all();
1524
1525 {
1526 unsigned long zones_size[MAX_NR_ZONES];
1527 unsigned long zholes_size[MAX_NR_ZONES];
1528 unsigned long npages;
1529 int znum;
1530
1531 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1532 zones_size[znum] = zholes_size[znum] = 0;
1533
1534 npages = end_pfn - pfn_base;
1535 zones_size[ZONE_DMA] = npages;
1536 zholes_size[ZONE_DMA] = npages - pages_avail;
1537
1538 free_area_init_node(0, &contig_page_data, zones_size,
1539 phys_base >> PAGE_SHIFT, zholes_size);
1540 }
1541
1542 device_scan();
1543 }
1544
1545 /* Ok, it seems that the prom can allocate some more memory chunks
1546 * as a side effect of some prom calls we perform during the
1547 * boot sequence. My most likely theory is that it is from the
1548 * prom_set_traptable() call, and OBP is allocating a scratchpad
1549 * for saving client program register state etc.
1550 */
1551 static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1552 {
1553 int swapi = 0;
1554 int i, mitr;
1555 unsigned long tmpaddr, tmpsize;
1556 unsigned long lowest;
1557
1558 for (i = 0; thislist[i].theres_more != 0; i++) {
1559 lowest = thislist[i].start_adr;
1560 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1561 if (thislist[mitr].start_adr < lowest) {
1562 lowest = thislist[mitr].start_adr;
1563 swapi = mitr;
1564 }
1565 if (lowest == thislist[i].start_adr)
1566 continue;
1567 tmpaddr = thislist[swapi].start_adr;
1568 tmpsize = thislist[swapi].num_bytes;
1569 for (mitr = swapi; mitr > i; mitr--) {
1570 thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1571 thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1572 }
1573 thislist[i].start_adr = tmpaddr;
1574 thislist[i].num_bytes = tmpsize;
1575 }
1576 }
1577
1578 void __init rescan_sp_banks(void)
1579 {
1580 struct linux_prom64_registers memlist[64];
1581 struct linux_mlist_p1275 avail[64], *mlist;
1582 unsigned long bytes, base_paddr;
1583 int num_regs, node = prom_finddevice("/memory");
1584 int i;
1585
1586 num_regs = prom_getproperty(node, "available",
1587 (char *) memlist, sizeof(memlist));
1588 num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1589 for (i = 0; i < num_regs; i++) {
1590 avail[i].start_adr = memlist[i].phys_addr;
1591 avail[i].num_bytes = memlist[i].reg_size;
1592 avail[i].theres_more = &avail[i + 1];
1593 }
1594 avail[i - 1].theres_more = NULL;
1595 sort_memlist(avail);
1596
1597 mlist = &avail[0];
1598 i = 0;
1599 bytes = mlist->num_bytes;
1600 base_paddr = mlist->start_adr;
1601
1602 sp_banks[0].base_addr = base_paddr;
1603 sp_banks[0].num_bytes = bytes;
1604
1605 while (mlist->theres_more != NULL){
1606 i++;
1607 mlist = mlist->theres_more;
1608 bytes = mlist->num_bytes;
1609 if (i >= SPARC_PHYS_BANKS-1) {
1610 printk ("The machine has more banks than "
1611 "this kernel can support\n"
1612 "Increase the SPARC_PHYS_BANKS "
1613 "setting (currently %d)\n",
1614 SPARC_PHYS_BANKS);
1615 i = SPARC_PHYS_BANKS-1;
1616 break;
1617 }
1618
1619 sp_banks[i].base_addr = mlist->start_adr;
1620 sp_banks[i].num_bytes = mlist->num_bytes;
1621 }
1622
1623 i++;
1624 sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1625 sp_banks[i].num_bytes = 0;
1626
1627 for (i = 0; sp_banks[i].num_bytes != 0; i++)
1628 sp_banks[i].num_bytes &= PAGE_MASK;
1629 }
1630
1631 static void __init taint_real_pages(void)
1632 {
1633 struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1634 int i;
1635
1636 for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1637 saved_sp_banks[i].base_addr =
1638 sp_banks[i].base_addr;
1639 saved_sp_banks[i].num_bytes =
1640 sp_banks[i].num_bytes;
1641 }
1642
1643 rescan_sp_banks();
1644
1645 /* Find changes discovered in the sp_bank rescan and
1646 * reserve the lost portions in the bootmem maps.
1647 */
1648 for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1649 unsigned long old_start, old_end;
1650
1651 old_start = saved_sp_banks[i].base_addr;
1652 old_end = old_start +
1653 saved_sp_banks[i].num_bytes;
1654 while (old_start < old_end) {
1655 int n;
1656
1657 for (n = 0; sp_banks[n].num_bytes; n++) {
1658 unsigned long new_start, new_end;
1659
1660 new_start = sp_banks[n].base_addr;
1661 new_end = new_start + sp_banks[n].num_bytes;
1662
1663 if (new_start <= old_start &&
1664 new_end >= (old_start + PAGE_SIZE)) {
1665 set_bit (old_start >> 22,
1666 sparc64_valid_addr_bitmap);
1667 goto do_next_page;
1668 }
1669 }
1670 reserve_bootmem(old_start, PAGE_SIZE);
1671
1672 do_next_page:
1673 old_start += PAGE_SIZE;
1674 }
1675 }
1676 }
1677
1678 void __init mem_init(void)
1679 {
1680 unsigned long codepages, datapages, initpages;
1681 unsigned long addr, last;
1682 int i;
1683
1684 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1685 i += 1;
1686 sparc64_valid_addr_bitmap = (unsigned long *)
1687 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1688 if (sparc64_valid_addr_bitmap == NULL) {
1689 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1690 prom_halt();
1691 }
1692 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1693
1694 addr = PAGE_OFFSET + kern_base;
1695 last = PAGE_ALIGN(kern_size) + addr;
1696 while (addr < last) {
1697 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1698 addr += PAGE_SIZE;
1699 }
1700
1701 taint_real_pages();
1702
1703 max_mapnr = last_valid_pfn - pfn_base;
1704 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1705
1706 #ifdef CONFIG_DEBUG_BOOTMEM
1707 prom_printf("mem_init: Calling free_all_bootmem().\n");
1708 #endif
1709 totalram_pages = num_physpages = free_all_bootmem() - 1;
1710
1711 /*
1712 * Set up the zero page, mark it reserved, so that page count
1713 * is not manipulated when freeing the page from user ptes.
1714 */
1715 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1716 if (mem_map_zero == NULL) {
1717 prom_printf("paging_init: Cannot alloc zero page.\n");
1718 prom_halt();
1719 }
1720 SetPageReserved(mem_map_zero);
1721
1722 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1723 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1724 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1725 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1726 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1727 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1728
1729 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1730 nr_free_pages() << (PAGE_SHIFT-10),
1731 codepages << (PAGE_SHIFT-10),
1732 datapages << (PAGE_SHIFT-10),
1733 initpages << (PAGE_SHIFT-10),
1734 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1735
1736 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1737 cheetah_ecache_flush_init();
1738 }
1739
1740 void free_initmem (void)
1741 {
1742 unsigned long addr, initend;
1743
1744 /*
1745 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1746 */
1747 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1748 initend = (unsigned long)(__init_end) & PAGE_MASK;
1749 for (; addr < initend; addr += PAGE_SIZE) {
1750 unsigned long page;
1751 struct page *p;
1752
1753 page = (addr +
1754 ((unsigned long) __va(kern_base)) -
1755 ((unsigned long) KERNBASE));
1756 memset((void *)addr, 0xcc, PAGE_SIZE);
1757 p = virt_to_page(page);
1758
1759 ClearPageReserved(p);
1760 set_page_count(p, 1);
1761 __free_page(p);
1762 num_physpages++;
1763 totalram_pages++;
1764 }
1765 }
1766
1767 #ifdef CONFIG_BLK_DEV_INITRD
1768 void free_initrd_mem(unsigned long start, unsigned long end)
1769 {
1770 if (start < end)
1771 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1772 for (; start < end; start += PAGE_SIZE) {
1773 struct page *p = virt_to_page(start);
1774
1775 ClearPageReserved(p);
1776 set_page_count(p, 1);
1777 __free_page(p);
1778 num_physpages++;
1779 totalram_pages++;
1780 }
1781 }
1782 #endif
kernel-based virtual machine