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[PATCH] ppc64 boot: remove global initializers
[linux-2.6/kvm.git] / arch / ppc / platforms / katana.c
bloba301c5ac58ddf985244fa5fd8e8fe55f93a614c3
1 /*
2 * arch/ppc/platforms/katana.c
3 *
4 * Board setup routines for the Artesyn Katana cPCI boards.
5 *
6 * Author: Tim Montgomery <timm@artesyncp.com>
7 * Maintained by: Mark A. Greer <mgreer@mvista.com>
8 *
9 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
10 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17 /*
18 * Supports the Artesyn 750i, 752i, and 3750. The 752i is virtually identical
19 * to the 750i except that it has an mv64460 bridge.
20 */
21 #include <linux/config.h>
22 #include <linux/kernel.h>
23 #include <linux/pci.h>
24 #include <linux/kdev_t.h>
25 #include <linux/console.h>
26 #include <linux/initrd.h>
27 #include <linux/root_dev.h>
28 #include <linux/delay.h>
29 #include <linux/seq_file.h>
30 #include <linux/mtd/physmap.h>
31 #include <linux/mv643xx.h>
32 #ifdef CONFIG_BOOTIMG
33 #include <linux/bootimg.h>
34 #endif
35 #include <asm/io.h>
36 #include <asm/unistd.h>
37 #include <asm/page.h>
38 #include <asm/time.h>
39 #include <asm/smp.h>
40 #include <asm/todc.h>
41 #include <asm/bootinfo.h>
42 #include <asm/ppcboot.h>
43 #include <asm/mv64x60.h>
44 #include <platforms/katana.h>
45 #include <asm/machdep.h>
46
47 static struct mv64x60_handle bh;
48 static katana_id_t katana_id;
49 static void __iomem *cpld_base;
50 static void __iomem *sram_base;
51 static u32 katana_flash_size_0;
52 static u32 katana_flash_size_1;
53 static u32 katana_bus_frequency;
54 static struct pci_controller katana_hose_a;
55
56 unsigned char __res[sizeof(bd_t)];
57
58 /* PCI Interrupt routing */
59 static int __init
60 katana_irq_lookup_750i(unsigned char idsel, unsigned char pin)
61 {
62 static char pci_irq_table[][4] = {
63 /*
64 * PCI IDSEL/INTPIN->INTLINE
65 * A B C D
66 */
67 /* IDSEL 4 (PMC 1) */
68 { KATANA_PCI_INTB_IRQ_750i, KATANA_PCI_INTC_IRQ_750i,
69 KATANA_PCI_INTD_IRQ_750i, KATANA_PCI_INTA_IRQ_750i },
70 /* IDSEL 5 (PMC 2) */
71 { KATANA_PCI_INTC_IRQ_750i, KATANA_PCI_INTD_IRQ_750i,
72 KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i },
73 /* IDSEL 6 (T8110) */
74 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
75 /* IDSEL 7 (unused) */
76 {0, 0, 0, 0 },
77 /* IDSEL 8 (Intel 82544) (752i only but doesn't harm 750i) */
78 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
79 };
80 const long min_idsel = 4, max_idsel = 8, irqs_per_slot = 4;
81
82 return PCI_IRQ_TABLE_LOOKUP;
83 }
84
85 static int __init
86 katana_irq_lookup_3750(unsigned char idsel, unsigned char pin)
87 {
88 static char pci_irq_table[][4] = {
89 /*
90 * PCI IDSEL/INTPIN->INTLINE
91 * A B C D
92 */
93 { KATANA_PCI_INTA_IRQ_3750, 0, 0, 0 }, /* IDSEL 3 (BCM5691) */
94 { KATANA_PCI_INTB_IRQ_3750, 0, 0, 0 }, /* IDSEL 4 (MV64360 #2)*/
95 { KATANA_PCI_INTC_IRQ_3750, 0, 0, 0 }, /* IDSEL 5 (MV64360 #3)*/
96 };
97 const long min_idsel = 3, max_idsel = 5, irqs_per_slot = 4;
98
99 return PCI_IRQ_TABLE_LOOKUP;
100 }
101
102 static int __init
103 katana_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
104 {
105 switch (katana_id) {
106 case KATANA_ID_750I:
107 case KATANA_ID_752I:
108 return katana_irq_lookup_750i(idsel, pin);
109
110 case KATANA_ID_3750:
111 return katana_irq_lookup_3750(idsel, pin);
112
113 default:
114 printk(KERN_ERR "Bogus board ID\n");
115 return 0;
116 }
117 }
118
119 /* Board info retrieval routines */
120 void __init
121 katana_get_board_id(void)
122 {
123 switch (in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)) {
124 case KATANA_PRODUCT_ID_3750:
125 katana_id = KATANA_ID_3750;
126 break;
127
128 case KATANA_PRODUCT_ID_750i:
129 katana_id = KATANA_ID_750I;
130 break;
131
132 case KATANA_PRODUCT_ID_752i:
133 katana_id = KATANA_ID_752I;
134 break;
135
136 default:
137 printk(KERN_ERR "Unsupported board\n");
138 }
139 }
140
141 int __init
142 katana_get_proc_num(void)
143 {
144 u16 val;
145 u8 save_exclude;
146 static int proc = -1;
147 static u8 first_time = 1;
148
149 if (first_time) {
150 if (katana_id != KATANA_ID_3750)
151 proc = 0;
152 else {
153 save_exclude = mv64x60_pci_exclude_bridge;
154 mv64x60_pci_exclude_bridge = 0;
155
156 early_read_config_word(bh.hose_b, 0,
157 PCI_DEVFN(0,0), PCI_DEVICE_ID, &val);
158
159 mv64x60_pci_exclude_bridge = save_exclude;
160
161 switch(val) {
162 case PCI_DEVICE_ID_KATANA_3750_PROC0:
163 proc = 0;
164 break;
165
166 case PCI_DEVICE_ID_KATANA_3750_PROC1:
167 proc = 1;
168 break;
169
170 case PCI_DEVICE_ID_KATANA_3750_PROC2:
171 proc = 2;
172 break;
173
174 default:
175 printk(KERN_ERR "Bogus Device ID\n");
176 }
177 }
178
179 first_time = 0;
180 }
181
182 return proc;
183 }
184
185 static inline int
186 katana_is_monarch(void)
187 {
188 return in_8(cpld_base + KATANA_CPLD_BD_CFG_3) &
189 KATANA_CPLD_BD_CFG_3_MONARCH;
190 }
191
192 static void __init
193 katana_setup_bridge(void)
194 {
195 struct pci_controller hose;
196 struct mv64x60_setup_info si;
197 void __iomem *vaddr;
198 int i;
199 u32 v;
200 u16 val, type;
201 u8 save_exclude;
202
203 /*
204 * Some versions of the Katana firmware mistakenly change the vendor
205 * & device id fields in the bridge's pci device (visible via pci
206 * config accesses). This breaks mv64x60_init() because those values
207 * are used to identify the type of bridge that's there. Artesyn
208 * claims that the subsystem vendor/device id's will have the correct
209 * Marvell values so this code puts back the correct values from there.
210 */
211 memset(&hose, 0, sizeof(hose));
212 vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
213 setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
214 vaddr + MV64x60_PCI0_CONFIG_DATA);
215 save_exclude = mv64x60_pci_exclude_bridge;
216 mv64x60_pci_exclude_bridge = 0;
217
218 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
219
220 if (val != PCI_VENDOR_ID_MARVELL) {
221 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
222 PCI_SUBSYSTEM_VENDOR_ID, &val);
223 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
224 PCI_VENDOR_ID, val);
225 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
226 PCI_SUBSYSTEM_ID, &val);
227 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
228 PCI_DEVICE_ID, val);
229 }
230
231 /*
232 * While we're in here, set the hotswap register correctly.
233 * Turn off blue LED; mask ENUM#, clear insertion & extraction bits.
234 */
235 early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0),
236 MV64360_PCICFG_CPCI_HOTSWAP, &v);
237 v &= ~(1<<19);
238 v |= ((1<<17) | (1<<22) | (1<<23));
239 early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0),
240 MV64360_PCICFG_CPCI_HOTSWAP, v);
241
242 /* While we're at it, grab the bridge type for later */
243 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type);
244
245 mv64x60_pci_exclude_bridge = save_exclude;
246 iounmap(vaddr);
247
248 memset(&si, 0, sizeof(si));
249
250 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
251
252 si.pci_1.enable_bus = 1;
253 si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
254 si.pci_1.pci_io.pci_base_hi = 0;
255 si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
256 si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
257 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
258 si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
259 si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
260 si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
261 si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
262 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
263 si.pci_1.pci_cmd_bits = 0;
264 si.pci_1.latency_timer = 0x80;
265
266 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
267 #if defined(CONFIG_NOT_COHERENT_CACHE)
268 si.cpu_prot_options[i] = 0;
269 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
270 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
271 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
272
273 si.pci_1.acc_cntl_options[i] =
274 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
275 MV64360_PCI_ACC_CNTL_SWAP_NONE |
276 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
277 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
278 #else
279 si.cpu_prot_options[i] = 0;
280 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
281 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
282 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
283
284 si.pci_1.acc_cntl_options[i] =
285 MV64360_PCI_ACC_CNTL_SNOOP_WB |
286 MV64360_PCI_ACC_CNTL_SWAP_NONE |
287 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
288 ((type == PCI_DEVICE_ID_MARVELL_MV64360) ?
289 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES :
290 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES);
291 #endif
292 }
293
294 /* Lookup PCI host bridges */
295 if (mv64x60_init(&bh, &si))
296 printk(KERN_WARNING "Bridge initialization failed.\n");
297
298 pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
299 ppc_md.pci_swizzle = common_swizzle;
300 ppc_md.pci_map_irq = katana_map_irq;
301 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
302
303 mv64x60_set_bus(&bh, 1, 0);
304 bh.hose_b->first_busno = 0;
305 bh.hose_b->last_busno = 0xff;
306
307 /*
308 * Need to access hotswap reg which is in the pci config area of the
309 * bridge's hose 0. Note that pcibios_alloc_controller() can't be used
310 * to alloc hose_a b/c that would make hose 0 known to the generic
311 * pci code which we don't want.
312 */
313 bh.hose_a = &katana_hose_a;
314 setup_indirect_pci_nomap(bh.hose_a,
315 bh.v_base + MV64x60_PCI0_CONFIG_ADDR,
316 bh.v_base + MV64x60_PCI0_CONFIG_DATA);
317 }
318
319 /* Bridge & platform setup routines */
320 void __init
321 katana_intr_setup(void)
322 {
323 if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */
324 mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15);
325
326 /* MPP 8, 9, and 10 */
327 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
328
329 /* MPP 14 */
330 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I))
331 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000);
332
333 /*
334 * Define GPP 8,9,and 10 interrupt polarity as active low
335 * input signal and level triggered
336 */
337 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
338 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
339
340 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
341 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14));
342 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14));
343 }
344
345 /* Config GPP intr ctlr to respond to level trigger */
346 mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
347
348 if (bh.type == MV64x60_TYPE_MV64360) {
349 /* Erratum FEr PCI-#9 */
350 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD,
351 (1<<4) | (1<<5) | (1<<6) | (1<<7));
352 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9));
353 } else {
354 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7));
355 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD,
356 (1<<4) | (1<<5) | (1<<8) | (1<<9));
357 }
358
359 /*
360 * Dismiss and then enable interrupt on GPP interrupt cause
361 * for CPU #0
362 */
363 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
364 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
365
366 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
367 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14));
368 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14));
369 }
370
371 /*
372 * Dismiss and then enable interrupt on CPU #0 high cause reg
373 * BIT25 summarizes GPP interrupts 8-15
374 */
375 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
376 }
377
378 void __init
379 katana_setup_peripherals(void)
380 {
381 u32 base;
382
383 /* Set up windows for boot CS, soldered & socketed flash, and CPLD */
384 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
385 KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
386 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
387
388 /* Assume firmware set up window sizes correctly for dev 0 & 1 */
389 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base,
390 &katana_flash_size_0);
391
392 if (katana_flash_size_0 > 0) {
393 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
394 KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0);
395 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
396 }
397
398 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base,
399 &katana_flash_size_1);
400
401 if (katana_flash_size_1 > 0) {
402 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
403 (KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0),
404 katana_flash_size_1, 0);
405 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
406 }
407
408 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
409 KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
410 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
411
412 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
413 KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
414 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
415 cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
416
417 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
418 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
419 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
420 sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
421
422 /* Set up Enet->SRAM window */
423 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
424 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
425 bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
426
427 /* Give enet r/w access to memory region */
428 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
429 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
430 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
431
432 mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
433 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
434 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
435
436 /* Must wait until window set up before retrieving board id */
437 katana_get_board_id();
438
439 /* Enumerate pci bus (must know board id before getting proc number) */
440 if (katana_get_proc_num() == 0)
441 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
442
443 #if defined(CONFIG_NOT_COHERENT_CACHE)
444 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
445 #else
446 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
447 #endif
448
449 /*
450 * Setting the SRAM to 0. Note that this generates parity errors on
451 * internal data path in SRAM since it's first time accessing it
452 * while after reset it's not configured.
453 */
454 memset(sram_base, 0, MV64360_SRAM_SIZE);
455
456 /* Only processor zero [on 3750] is an PCI interrupt controller */
457 if (katana_get_proc_num() == 0)
458 katana_intr_setup();
459 }
460
461 static void __init
462 katana_enable_ipmi(void)
463 {
464 u8 reset_out;
465
466 /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
467 reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT);
468 reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
469 out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out);
470 }
471
472 static void __init
473 katana_setup_arch(void)
474 {
475 if (ppc_md.progress)
476 ppc_md.progress("katana_setup_arch: enter", 0);
477
478 set_tb(0, 0);
479
480 #ifdef CONFIG_BLK_DEV_INITRD
481 if (initrd_start)
482 ROOT_DEV = Root_RAM0;
483 else
484 #endif
485 #ifdef CONFIG_ROOT_NFS
486 ROOT_DEV = Root_NFS;
487 #else
488 ROOT_DEV = Root_SDA2;
489 #endif
490
491 /*
492 * Set up the L2CR register.
493 *
494 * 750FX has only L2E, L2PE (bits 2-8 are reserved)
495 * DD2.0 has bug that requires the L2 to be in WRT mode
496 * avoid dirty data in cache
497 */
498 if (PVR_REV(mfspr(SPRN_PVR)) == 0x0200) {
499 printk(KERN_INFO "DD2.0 detected. Setting L2 cache"
500 "to Writethrough mode\n");
501 _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT);
502 } else
503 _set_L2CR(L2CR_L2E | L2CR_L2PE);
504
505 if (ppc_md.progress)
506 ppc_md.progress("katana_setup_arch: calling setup_bridge", 0);
507
508 katana_setup_bridge();
509 katana_setup_peripherals();
510 katana_enable_ipmi();
511
512 katana_bus_frequency = katana_bus_freq(cpld_base);
513
514 printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
515 if (ppc_md.progress)
516 ppc_md.progress("katana_setup_arch: exit", 0);
517 }
518
519 void
520 katana_fixup_resources(struct pci_dev *dev)
521 {
522 u16 v16;
523
524 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES>>2);
525
526 pci_read_config_word(dev, PCI_COMMAND, &v16);
527 v16 |= PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK;
528 pci_write_config_word(dev, PCI_COMMAND, v16);
529 }
530
531 static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
532 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/
533 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/
534 };
535
536 static int
537 katana_get_cpu_freq(void)
538 {
539 unsigned long pll_cfg;
540
541 pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
542 return katana_bus_frequency * cpu_750xx[pll_cfg]/2;
543 }
544
545 /* Platform device data fixup routines. */
546 #if defined(CONFIG_SERIAL_MPSC)
547 static void __init
548 katana_fixup_mpsc_pdata(struct platform_device *pdev)
549 {
550 struct mpsc_pdata *pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
551 bd_t *bdp = (bd_t *)__res;
552
553 if (bdp->bi_baudrate)
554 pdata->default_baud = bdp->bi_baudrate;
555 else
556 pdata->default_baud = KATANA_DEFAULT_BAUD;
557
558 pdata->max_idle = 40;
559 pdata->brg_clk_src = KATANA_MPSC_CLK_SRC;
560 /*
561 * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts,
562 * TCLK == SysCLK but on 64460, they are separate pins.
563 * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
564 */
565 pdata->brg_clk_freq = min(katana_bus_frequency, MV64x60_TCLK_FREQ_MAX);
566 }
567 #endif
568
569 #if defined(CONFIG_MV643XX_ETH)
570 static void __init
571 katana_fixup_eth_pdata(struct platform_device *pdev)
572 {
573 struct mv643xx_eth_platform_data *eth_pd;
574 static u16 phy_addr[] = {
575 KATANA_ETH0_PHY_ADDR,
576 KATANA_ETH1_PHY_ADDR,
577 KATANA_ETH2_PHY_ADDR,
578 };
579
580 eth_pd = pdev->dev.platform_data;
581 eth_pd->force_phy_addr = 1;
582 eth_pd->phy_addr = phy_addr[pdev->id];
583 eth_pd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE;
584 eth_pd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE;
585 }
586 #endif
587
588 #if defined(CONFIG_SYSFS)
589 static void __init
590 katana_fixup_mv64xxx_pdata(struct platform_device *pdev)
591 {
592 struct mv64xxx_pdata *pdata = (struct mv64xxx_pdata *)
593 pdev->dev.platform_data;
594
595 /* Katana supports the mv64xxx hotswap register */
596 pdata->hs_reg_valid = 1;
597 }
598 #endif
599
600 static int __init
601 katana_platform_notify(struct device *dev)
602 {
603 static struct {
604 char *bus_id;
605 void ((*rtn)(struct platform_device *pdev));
606 } dev_map[] = {
607 #if defined(CONFIG_SERIAL_MPSC)
608 { MPSC_CTLR_NAME ".0", katana_fixup_mpsc_pdata },
609 { MPSC_CTLR_NAME ".1", katana_fixup_mpsc_pdata },
610 #endif
611 #if defined(CONFIG_MV643XX_ETH)
612 { MV643XX_ETH_NAME ".0", katana_fixup_eth_pdata },
613 { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata },
614 { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata },
615 #endif
616 #if defined(CONFIG_SYSFS)
617 { MV64XXX_DEV_NAME ".0", katana_fixup_mv64xxx_pdata },
618 #endif
619 };
620 struct platform_device *pdev;
621 int i;
622
623 if (dev && dev->bus_id)
624 for (i=0; i<ARRAY_SIZE(dev_map); i++)
625 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
626 BUS_ID_SIZE)) {
627 pdev = container_of(dev,
628 struct platform_device, dev);
629 dev_map[i].rtn(pdev);
630 }
631
632 return 0;
633 }
634
635 #ifdef CONFIG_MTD_PHYSMAP
636
637 #ifndef MB
638 #define MB (1 << 20)
639 #endif
640
641 /*
642 * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB.
643 *
644 * FLASH Amount: 128 64 32 16
645 * ------------- --- -- -- --
646 * Monitor: 1 1 1 1
647 * Primary Kernel: 1.5 1.5 1.5 1.5
648 * Primary fs: 30 30 <end> <end>
649 * Secondary Kernel: 1.5 1.5 N/A N/A
650 * Secondary fs: <end> <end> N/A N/A
651 * User: <overlays entire FLASH except for "Monitor" section>
652 */
653 static int __init
654 katana_setup_mtd(void)
655 {
656 u32 size;
657 int ptbl_entries;
658 static struct mtd_partition *ptbl;
659
660 size = katana_flash_size_0 + katana_flash_size_1;
661 if (!size)
662 return -ENOMEM;
663
664 ptbl_entries = (size >= (64*MB)) ? 6 : 4;
665
666 if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
667 GFP_KERNEL)) == NULL) {
668 printk(KERN_WARNING "Can't alloc MTD partition table\n");
669 return -ENOMEM;
670 }
671 memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
672
673 ptbl[0].name = "Monitor";
674 ptbl[0].size = KATANA_MTD_MONITOR_SIZE;
675 ptbl[1].name = "Primary Kernel";
676 ptbl[1].offset = MTDPART_OFS_NXTBLK;
677 ptbl[1].size = 0x00180000; /* 1.5 MB */
678 ptbl[2].name = "Primary Filesystem";
679 ptbl[2].offset = MTDPART_OFS_APPEND;
680 ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */
681 ptbl[ptbl_entries-1].name = "User FLASH";
682 ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE;
683 ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL;
684
685 if (size >= (64*MB)) {
686 ptbl[2].size = 30*MB;
687 ptbl[3].name = "Secondary Kernel";
688 ptbl[3].offset = MTDPART_OFS_NXTBLK;
689 ptbl[3].size = 0x00180000; /* 1.5 MB */
690 ptbl[4].name = "Secondary Filesystem";
691 ptbl[4].offset = MTDPART_OFS_APPEND;
692 ptbl[4].size = MTDPART_SIZ_FULL;
693 }
694
695 physmap_map.size = size;
696 physmap_set_partitions(ptbl, ptbl_entries);
697 return 0;
698 }
699 arch_initcall(katana_setup_mtd);
700 #endif
701
702 static void
703 katana_restart(char *cmd)
704 {
705 ulong i = 10000000;
706
707 /* issue hard reset to the reset command register */
708 out_8(cpld_base + KATANA_CPLD_RST_CMD, KATANA_CPLD_RST_CMD_HR);
709
710 while (i-- > 0) ;
711 panic("restart failed\n");
712 }
713
714 static void
715 katana_halt(void)
716 {
717 u8 v;
718
719 /* Turn on blue LED to indicate its okay to remove */
720 if (katana_id == KATANA_ID_750I) {
721 u32 v;
722 u8 save_exclude;
723
724 /* Set LOO bit in cPCI HotSwap reg of hose 0 to turn on LED. */
725 save_exclude = mv64x60_pci_exclude_bridge;
726 mv64x60_pci_exclude_bridge = 0;
727 early_read_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
728 MV64360_PCICFG_CPCI_HOTSWAP, &v);
729 v &= 0xff;
730 v |= (1 << 19);
731 early_write_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
732 MV64360_PCICFG_CPCI_HOTSWAP, v);
733 mv64x60_pci_exclude_bridge = save_exclude;
734 } else if (katana_id == KATANA_ID_752I) {
735 v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF);
736 v |= HSL_PLD_HOT_SWAP_LED_BIT;
737 out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v);
738 }
739
740 while (1) ;
741 /* NOTREACHED */
742 }
743
744 static void
745 katana_power_off(void)
746 {
747 katana_halt();
748 /* NOTREACHED */
749 }
750
751 static int
752 katana_show_cpuinfo(struct seq_file *m)
753 {
754 char *s;
755
756 seq_printf(m, "cpu freq\t: %dMHz\n",
757 (katana_get_cpu_freq() + 500000) / 1000000);
758 seq_printf(m, "bus freq\t: %ldMHz\n",
759 ((long)katana_bus_frequency + 500000) / 1000000);
760 seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n");
761
762 seq_printf(m, "board\t\t: ");
763 switch (katana_id) {
764 case KATANA_ID_3750:
765 seq_printf(m, "Katana 3750");
766 break;
767
768 case KATANA_ID_750I:
769 seq_printf(m, "Katana 750i");
770 break;
771
772 case KATANA_ID_752I:
773 seq_printf(m, "Katana 752i");
774 break;
775
776 default:
777 seq_printf(m, "Unknown");
778 break;
779 }
780 seq_printf(m, " (product id: 0x%x)\n",
781 in_8(cpld_base + KATANA_CPLD_PRODUCT_ID));
782
783 seq_printf(m, "pci mode\t: %sMonarch\n",
784 katana_is_monarch()? "" : "Non-");
785 seq_printf(m, "hardware rev\t: 0x%x\n",
786 in_8(cpld_base+KATANA_CPLD_HARDWARE_VER));
787 seq_printf(m, "pld rev\t\t: 0x%x\n",
788 in_8(cpld_base + KATANA_CPLD_PLD_VER));
789
790 switch(bh.type) {
791 case MV64x60_TYPE_GT64260A:
792 s = "gt64260a";
793 break;
794 case MV64x60_TYPE_GT64260B:
795 s = "gt64260b";
796 break;
797 case MV64x60_TYPE_MV64360:
798 s = "mv64360";
799 break;
800 case MV64x60_TYPE_MV64460:
801 s = "mv64460";
802 break;
803 default:
804 s = "Unknown";
805 }
806 seq_printf(m, "bridge type\t: %s\n", s);
807 seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
808 #if defined(CONFIG_NOT_COHERENT_CACHE)
809 seq_printf(m, "coherency\t: %s\n", "off");
810 #else
811 seq_printf(m, "coherency\t: %s\n", "on");
812 #endif
813
814 return 0;
815 }
816
817 static void __init
818 katana_calibrate_decr(void)
819 {
820 u32 freq;
821
822 freq = katana_bus_frequency / 4;
823
824 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
825 (long)freq / 1000000, (long)freq % 1000000);
826
827 tb_ticks_per_jiffy = freq / HZ;
828 tb_to_us = mulhwu_scale_factor(freq, 1000000);
829 }
830
831 /*
832 * The katana supports both uImage and zImage. If uImage, get the mem size
833 * from the bd info. If zImage, the bootwrapper adds a BI_MEMSIZE entry in
834 * the bi_rec data which is sucked out and put into boot_mem_size by
835 * parse_bootinfo(). MMU_init() will then use the boot_mem_size for the mem
836 * size and not call this routine. The only way this will fail is when a uImage
837 * is used but the fw doesn't pass in a valid bi_memsize. This should never
838 * happen, though.
839 */
840 unsigned long __init
841 katana_find_end_of_memory(void)
842 {
843 bd_t *bdp = (bd_t *)__res;
844 return bdp->bi_memsize;
845 }
846
847 #if defined(CONFIG_I2C_MV64XXX) && defined(CONFIG_SENSORS_M41T00)
848 extern ulong m41t00_get_rtc_time(void);
849 extern int m41t00_set_rtc_time(ulong);
850
851 static int __init
852 katana_rtc_hookup(void)
853 {
854 struct timespec tv;
855
856 ppc_md.get_rtc_time = m41t00_get_rtc_time;
857 ppc_md.set_rtc_time = m41t00_set_rtc_time;
858
859 tv.tv_nsec = 0;
860 tv.tv_sec = (ppc_md.get_rtc_time)();
861 do_settimeofday(&tv);
862
863 return 0;
864 }
865 late_initcall(katana_rtc_hookup);
866 #endif
867
868 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
869 static void __init
870 katana_map_io(void)
871 {
872 io_block_mapping(0xf8100000, 0xf8100000, 0x00020000, _PAGE_IO);
873 }
874 #endif
875
876 void __init
877 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
878 unsigned long r6, unsigned long r7)
879 {
880 parse_bootinfo(find_bootinfo());
881
882 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
883 * are non-zero, then we should use the board info from the bd_t
884 * structure and the cmdline pointed to by r6 instead of the
885 * information from birecs, if any. Otherwise, use the information
886 * from birecs as discovered by the preceeding call to
887 * parse_bootinfo(). This rule should work with both PPCBoot, which
888 * uses a bd_t board info structure, and the kernel boot wrapper,
889 * which uses birecs.
890 */
891 if (r3 && r6) {
892 /* copy board info structure */
893 memcpy((void *)__res, (void *)(r3+KERNELBASE), sizeof(bd_t));
894 /* copy command line */
895 *(char *)(r7+KERNELBASE) = 0;
896 strcpy(cmd_line, (char *)(r6+KERNELBASE));
897 }
898
899 #ifdef CONFIG_BLK_DEV_INITRD
900 /* take care of initrd if we have one */
901 if (r4) {
902 initrd_start = r4 + KERNELBASE;
903 initrd_end = r5 + KERNELBASE;
904 }
905 #endif /* CONFIG_BLK_DEV_INITRD */
906
907 isa_mem_base = 0;
908
909 ppc_md.setup_arch = katana_setup_arch;
910 ppc_md.pcibios_fixup_resources = katana_fixup_resources;
911 ppc_md.show_cpuinfo = katana_show_cpuinfo;
912 ppc_md.init_IRQ = mv64360_init_irq;
913 ppc_md.get_irq = mv64360_get_irq;
914 ppc_md.restart = katana_restart;
915 ppc_md.power_off = katana_power_off;
916 ppc_md.halt = katana_halt;
917 ppc_md.find_end_of_memory = katana_find_end_of_memory;
918 ppc_md.calibrate_decr = katana_calibrate_decr;
919
920 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
921 ppc_md.setup_io_mappings = katana_map_io;
922 ppc_md.progress = mv64x60_mpsc_progress;
923 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
924 #endif
925
926 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
927 platform_notify = katana_platform_notify;
928 #endif
929 }
kernel-based virtual machine