arch/arm/mach-spear3xx/clock.c

   1 /*
   2  * arch/arm/mach-spear3xx/clock.c
   3  *
   4  * SPEAr3xx machines clock framework source file
   5  *
   6  * Copyright (C) 2009 ST Microelectronics
   7  * Viresh Kumar<viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <mach/misc_regs.h>
  17 #include <plat/clock.h>
  18
  19 /* root clks */
  20 /* 32 KHz oscillator clock */
  21 static struct clk osc_32k_clk = {
  22         .flags = ALWAYS_ENABLED,
  23         .rate = 32000,
  24 };
  25
  26 /* 24 MHz oscillator clock */
  27 static struct clk osc_24m_clk = {
  28         .flags = ALWAYS_ENABLED,
  29         .rate = 24000000,
  30 };
  31
  32 /* clock derived from 32 KHz osc clk */
  33 /* rtc clock */
  34 static struct clk rtc_clk = {
  35         .pclk = &osc_32k_clk,
  36         .en_reg = PERIP1_CLK_ENB,
  37         .en_reg_bit = RTC_CLK_ENB,
  38         .recalc = &follow_parent,
  39 };
  40
  41 /* clock derived from 24 MHz osc clk */
  42 /* pll masks structure */
  43 static struct pll_clk_masks pll1_masks = {
  44         .mode_mask = PLL_MODE_MASK,
  45         .mode_shift = PLL_MODE_SHIFT,
  46         .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
  47         .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
  48         .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
  49         .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
  50         .div_p_mask = PLL_DIV_P_MASK,
  51         .div_p_shift = PLL_DIV_P_SHIFT,
  52         .div_n_mask = PLL_DIV_N_MASK,
  53         .div_n_shift = PLL_DIV_N_SHIFT,
  54 };
  55
  56 /* pll1 configuration structure */
  57 static struct pll_clk_config pll1_config = {
  58         .mode_reg = PLL1_CTR,
  59         .cfg_reg = PLL1_FRQ,
  60         .masks = &pll1_masks,
  61 };
  62
  63 /* pll rate configuration table, in ascending order of rates */
  64 struct pll_rate_tbl pll_rtbl[] = {
  65         {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
  66         {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
  67 };
  68
  69 /* PLL1 clock */
  70 static struct clk pll1_clk = {
  71         .flags = ENABLED_ON_INIT,
  72         .pclk = &osc_24m_clk,
  73         .en_reg = PLL1_CTR,
  74         .en_reg_bit = PLL_ENABLE,
  75         .calc_rate = &pll_calc_rate,
  76         .recalc = &pll_clk_recalc,
  77         .set_rate = &pll_clk_set_rate,
  78         .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
  79         .private_data = &pll1_config,
  80 };
  81
  82 /* PLL3 48 MHz clock */
  83 static struct clk pll3_48m_clk = {
  84         .flags = ALWAYS_ENABLED,
  85         .pclk = &osc_24m_clk,
  86         .rate = 48000000,
  87 };
  88
  89 /* watch dog timer clock */
  90 static struct clk wdt_clk = {
  91         .flags = ALWAYS_ENABLED,
  92         .pclk = &osc_24m_clk,
  93         .recalc = &follow_parent,
  94 };
  95
  96 /* clock derived from pll1 clk */
  97 /* cpu clock */
  98 static struct clk cpu_clk = {
  99         .flags = ALWAYS_ENABLED,
 100         .pclk = &pll1_clk,
 101         .recalc = &follow_parent,
 102 };
 103
 104 /* ahb masks structure */
 105 static struct bus_clk_masks ahb_masks = {
 106         .mask = PLL_HCLK_RATIO_MASK,
 107         .shift = PLL_HCLK_RATIO_SHIFT,
 108 };
 109
 110 /* ahb configuration structure */
 111 static struct bus_clk_config ahb_config = {
 112         .reg = CORE_CLK_CFG,
 113         .masks = &ahb_masks,
 114 };
 115
 116 /* ahb rate configuration table, in ascending order of rates */
 117 struct bus_rate_tbl bus_rtbl[] = {
 118         {.div = 3}, /* == parent divided by 4 */
 119         {.div = 2}, /* == parent divided by 3 */
 120         {.div = 1}, /* == parent divided by 2 */
 121         {.div = 0}, /* == parent divided by 1 */
 122 };
 123
 124 /* ahb clock */
 125 static struct clk ahb_clk = {
 126         .flags = ALWAYS_ENABLED,
 127         .pclk = &pll1_clk,
 128         .calc_rate = &bus_calc_rate,
 129         .recalc = &bus_clk_recalc,
 130         .set_rate = &bus_clk_set_rate,
 131         .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
 132         .private_data = &ahb_config,
 133 };
 134
 135 /* auxiliary synthesizers masks */
 136 static struct aux_clk_masks aux_masks = {
 137         .eq_sel_mask = AUX_EQ_SEL_MASK,
 138         .eq_sel_shift = AUX_EQ_SEL_SHIFT,
 139         .eq1_mask = AUX_EQ1_SEL,
 140         .eq2_mask = AUX_EQ2_SEL,
 141         .xscale_sel_mask = AUX_XSCALE_MASK,
 142         .xscale_sel_shift = AUX_XSCALE_SHIFT,
 143         .yscale_sel_mask = AUX_YSCALE_MASK,
 144         .yscale_sel_shift = AUX_YSCALE_SHIFT,
 145 };
 146
 147 /* uart synth configurations */
 148 static struct aux_clk_config uart_synth_config = {
 149         .synth_reg = UART_CLK_SYNT,
 150         .masks = &aux_masks,
 151 };
 152
 153 /* aux rate configuration table, in ascending order of rates */
 154 struct aux_rate_tbl aux_rtbl[] = {
 155         /* For PLL1 = 332 MHz */
 156         {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
 157         {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
 158         {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
 159 };
 160
 161 /* uart synth clock */
 162 static struct clk uart_synth_clk = {
 163         .en_reg = UART_CLK_SYNT,
 164         .en_reg_bit = AUX_SYNT_ENB,
 165         .pclk = &pll1_clk,
 166         .calc_rate = &aux_calc_rate,
 167         .recalc = &aux_clk_recalc,
 168         .set_rate = &aux_clk_set_rate,
 169         .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
 170         .private_data = &uart_synth_config,
 171 };
 172
 173 /* uart parents */
 174 static struct pclk_info uart_pclk_info[] = {
 175         {
 176                 .pclk = &uart_synth_clk,
 177                 .pclk_val = AUX_CLK_PLL1_VAL,
 178         }, {
 179                 .pclk = &pll3_48m_clk,
 180                 .pclk_val = AUX_CLK_PLL3_VAL,
 181         },
 182 };
 183
 184 /* uart parent select structure */
 185 static struct pclk_sel uart_pclk_sel = {
 186         .pclk_info = uart_pclk_info,
 187         .pclk_count = ARRAY_SIZE(uart_pclk_info),
 188         .pclk_sel_reg = PERIP_CLK_CFG,
 189         .pclk_sel_mask = UART_CLK_MASK,
 190 };
 191
 192 /* uart clock */
 193 static struct clk uart_clk = {
 194         .en_reg = PERIP1_CLK_ENB,
 195         .en_reg_bit = UART_CLK_ENB,
 196         .pclk_sel = &uart_pclk_sel,
 197         .pclk_sel_shift = UART_CLK_SHIFT,
 198         .recalc = &follow_parent,
 199 };
 200
 201 /* firda configurations */
 202 static struct aux_clk_config firda_synth_config = {
 203         .synth_reg = FIRDA_CLK_SYNT,
 204         .masks = &aux_masks,
 205 };
 206
 207 /* firda synth clock */
 208 static struct clk firda_synth_clk = {
 209         .en_reg = FIRDA_CLK_SYNT,
 210         .en_reg_bit = AUX_SYNT_ENB,
 211         .pclk = &pll1_clk,
 212         .calc_rate = &aux_calc_rate,
 213         .recalc = &aux_clk_recalc,
 214         .set_rate = &aux_clk_set_rate,
 215         .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
 216         .private_data = &firda_synth_config,
 217 };
 218
 219 /* firda parents */
 220 static struct pclk_info firda_pclk_info[] = {
 221         {
 222                 .pclk = &firda_synth_clk,
 223                 .pclk_val = AUX_CLK_PLL1_VAL,
 224         }, {
 225                 .pclk = &pll3_48m_clk,
 226                 .pclk_val = AUX_CLK_PLL3_VAL,
 227         },
 228 };
 229
 230 /* firda parent select structure */
 231 static struct pclk_sel firda_pclk_sel = {
 232         .pclk_info = firda_pclk_info,
 233         .pclk_count = ARRAY_SIZE(firda_pclk_info),
 234         .pclk_sel_reg = PERIP_CLK_CFG,
 235         .pclk_sel_mask = FIRDA_CLK_MASK,
 236 };
 237
 238 /* firda clock */
 239 static struct clk firda_clk = {
 240         .en_reg = PERIP1_CLK_ENB,
 241         .en_reg_bit = FIRDA_CLK_ENB,
 242         .pclk_sel = &firda_pclk_sel,
 243         .pclk_sel_shift = FIRDA_CLK_SHIFT,
 244         .recalc = &follow_parent,
 245 };
 246
 247 /* gpt synthesizer masks */
 248 static struct gpt_clk_masks gpt_masks = {
 249         .mscale_sel_mask = GPT_MSCALE_MASK,
 250         .mscale_sel_shift = GPT_MSCALE_SHIFT,
 251         .nscale_sel_mask = GPT_NSCALE_MASK,
 252         .nscale_sel_shift = GPT_NSCALE_SHIFT,
 253 };
 254
 255 /* gpt rate configuration table, in ascending order of rates */
 256 struct gpt_rate_tbl gpt_rtbl[] = {
 257         /* For pll1 = 332 MHz */
 258         {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
 259         {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
 260         {.mscale = 1, .nscale = 0}, /* 83 MHz */
 261 };
 262
 263 /* gpt0 synth clk config*/
 264 static struct gpt_clk_config gpt0_synth_config = {
 265         .synth_reg = PRSC1_CLK_CFG,
 266         .masks = &gpt_masks,
 267 };
 268
 269 /* gpt synth clock */
 270 static struct clk gpt0_synth_clk = {
 271         .flags = ALWAYS_ENABLED,
 272         .pclk = &pll1_clk,
 273         .calc_rate = &gpt_calc_rate,
 274         .recalc = &gpt_clk_recalc,
 275         .set_rate = &gpt_clk_set_rate,
 276         .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
 277         .private_data = &gpt0_synth_config,
 278 };
 279
 280 /* gpt parents */
 281 static struct pclk_info gpt0_pclk_info[] = {
 282         {
 283                 .pclk = &gpt0_synth_clk,
 284                 .pclk_val = AUX_CLK_PLL1_VAL,
 285         }, {
 286                 .pclk = &pll3_48m_clk,
 287                 .pclk_val = AUX_CLK_PLL3_VAL,
 288         },
 289 };
 290
 291 /* gpt parent select structure */
 292 static struct pclk_sel gpt0_pclk_sel = {
 293         .pclk_info = gpt0_pclk_info,
 294         .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
 295         .pclk_sel_reg = PERIP_CLK_CFG,
 296         .pclk_sel_mask = GPT_CLK_MASK,
 297 };
 298
 299 /* gpt0 timer clock */
 300 static struct clk gpt0_clk = {
 301         .flags = ALWAYS_ENABLED,
 302         .pclk_sel = &gpt0_pclk_sel,
 303         .pclk_sel_shift = GPT0_CLK_SHIFT,
 304         .recalc = &follow_parent,
 305 };
 306
 307 /* gpt1 synth clk configurations */
 308 static struct gpt_clk_config gpt1_synth_config = {
 309         .synth_reg = PRSC2_CLK_CFG,
 310         .masks = &gpt_masks,
 311 };
 312
 313 /* gpt1 synth clock */
 314 static struct clk gpt1_synth_clk = {
 315         .flags = ALWAYS_ENABLED,
 316         .pclk = &pll1_clk,
 317         .calc_rate = &gpt_calc_rate,
 318         .recalc = &gpt_clk_recalc,
 319         .set_rate = &gpt_clk_set_rate,
 320         .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
 321         .private_data = &gpt1_synth_config,
 322 };
 323
 324 static struct pclk_info gpt1_pclk_info[] = {
 325         {
 326                 .pclk = &gpt1_synth_clk,
 327                 .pclk_val = AUX_CLK_PLL1_VAL,
 328         }, {
 329                 .pclk = &pll3_48m_clk,
 330                 .pclk_val = AUX_CLK_PLL3_VAL,
 331         },
 332 };
 333
 334 /* gpt parent select structure */
 335 static struct pclk_sel gpt1_pclk_sel = {
 336         .pclk_info = gpt1_pclk_info,
 337         .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
 338         .pclk_sel_reg = PERIP_CLK_CFG,
 339         .pclk_sel_mask = GPT_CLK_MASK,
 340 };
 341
 342 /* gpt1 timer clock */
 343 static struct clk gpt1_clk = {
 344         .en_reg = PERIP1_CLK_ENB,
 345         .en_reg_bit = GPT1_CLK_ENB,
 346         .pclk_sel = &gpt1_pclk_sel,
 347         .pclk_sel_shift = GPT1_CLK_SHIFT,
 348         .recalc = &follow_parent,
 349 };
 350
 351 /* gpt2 synth clk configurations */
 352 static struct gpt_clk_config gpt2_synth_config = {
 353         .synth_reg = PRSC3_CLK_CFG,
 354         .masks = &gpt_masks,
 355 };
 356
 357 /* gpt1 synth clock */
 358 static struct clk gpt2_synth_clk = {
 359         .flags = ALWAYS_ENABLED,
 360         .pclk = &pll1_clk,
 361         .calc_rate = &gpt_calc_rate,
 362         .recalc = &gpt_clk_recalc,
 363         .set_rate = &gpt_clk_set_rate,
 364         .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
 365         .private_data = &gpt2_synth_config,
 366 };
 367
 368 static struct pclk_info gpt2_pclk_info[] = {
 369         {
 370                 .pclk = &gpt2_synth_clk,
 371                 .pclk_val = AUX_CLK_PLL1_VAL,
 372         }, {
 373                 .pclk = &pll3_48m_clk,
 374                 .pclk_val = AUX_CLK_PLL3_VAL,
 375         },
 376 };
 377
 378 /* gpt parent select structure */
 379 static struct pclk_sel gpt2_pclk_sel = {
 380         .pclk_info = gpt2_pclk_info,
 381         .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
 382         .pclk_sel_reg = PERIP_CLK_CFG,
 383         .pclk_sel_mask = GPT_CLK_MASK,
 384 };
 385
 386 /* gpt2 timer clock */
 387 static struct clk gpt2_clk = {
 388         .en_reg = PERIP1_CLK_ENB,
 389         .en_reg_bit = GPT2_CLK_ENB,
 390         .pclk_sel = &gpt2_pclk_sel,
 391         .pclk_sel_shift = GPT2_CLK_SHIFT,
 392         .recalc = &follow_parent,
 393 };
 394
 395 /* clock derived from pll3 clk */
 396 /* usbh clock */
 397 static struct clk usbh_clk = {
 398         .pclk = &pll3_48m_clk,
 399         .en_reg = PERIP1_CLK_ENB,
 400         .en_reg_bit = USBH_CLK_ENB,
 401         .recalc = &follow_parent,
 402 };
 403
 404 /* usbd clock */
 405 static struct clk usbd_clk = {
 406         .pclk = &pll3_48m_clk,
 407         .en_reg = PERIP1_CLK_ENB,
 408         .en_reg_bit = USBD_CLK_ENB,
 409         .recalc = &follow_parent,
 410 };
 411
 412 /* clock derived from ahb clk */
 413 /* apb masks structure */
 414 static struct bus_clk_masks apb_masks = {
 415         .mask = HCLK_PCLK_RATIO_MASK,
 416         .shift = HCLK_PCLK_RATIO_SHIFT,
 417 };
 418
 419 /* apb configuration structure */
 420 static struct bus_clk_config apb_config = {
 421         .reg = CORE_CLK_CFG,
 422         .masks = &apb_masks,
 423 };
 424
 425 /* apb clock */
 426 static struct clk apb_clk = {
 427         .flags = ALWAYS_ENABLED,
 428         .pclk = &ahb_clk,
 429         .calc_rate = &bus_calc_rate,
 430         .recalc = &bus_clk_recalc,
 431         .set_rate = &bus_clk_set_rate,
 432         .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
 433         .private_data = &apb_config,
 434 };
 435
 436 /* i2c clock */
 437 static struct clk i2c_clk = {
 438         .pclk = &ahb_clk,
 439         .en_reg = PERIP1_CLK_ENB,
 440         .en_reg_bit = I2C_CLK_ENB,
 441         .recalc = &follow_parent,
 442 };
 443
 444 /* dma clock */
 445 static struct clk dma_clk = {
 446         .pclk = &ahb_clk,
 447         .en_reg = PERIP1_CLK_ENB,
 448         .en_reg_bit = DMA_CLK_ENB,
 449         .recalc = &follow_parent,
 450 };
 451
 452 /* jpeg clock */
 453 static struct clk jpeg_clk = {
 454         .pclk = &ahb_clk,
 455         .en_reg = PERIP1_CLK_ENB,
 456         .en_reg_bit = JPEG_CLK_ENB,
 457         .recalc = &follow_parent,
 458 };
 459
 460 /* gmac clock */
 461 static struct clk gmac_clk = {
 462         .pclk = &ahb_clk,
 463         .en_reg = PERIP1_CLK_ENB,
 464         .en_reg_bit = GMAC_CLK_ENB,
 465         .recalc = &follow_parent,
 466 };
 467
 468 /* smi clock */
 469 static struct clk smi_clk = {
 470         .pclk = &ahb_clk,
 471         .en_reg = PERIP1_CLK_ENB,
 472         .en_reg_bit = SMI_CLK_ENB,
 473         .recalc = &follow_parent,
 474 };
 475
 476 /* c3 clock */
 477 static struct clk c3_clk = {
 478         .pclk = &ahb_clk,
 479         .en_reg = PERIP1_CLK_ENB,
 480         .en_reg_bit = C3_CLK_ENB,
 481         .recalc = &follow_parent,
 482 };
 483
 484 /* clock derived from apb clk */
 485 /* adc clock */
 486 static struct clk adc_clk = {
 487         .pclk = &apb_clk,
 488         .en_reg = PERIP1_CLK_ENB,
 489         .en_reg_bit = ADC_CLK_ENB,
 490         .recalc = &follow_parent,
 491 };
 492
 493 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
 494 /* emi clock */
 495 static struct clk emi_clk = {
 496         .flags = ALWAYS_ENABLED,
 497         .pclk = &ahb_clk,
 498         .recalc = &follow_parent,
 499 };
 500 #endif
 501
 502 /* ssp clock */
 503 static struct clk ssp0_clk = {
 504         .pclk = &apb_clk,
 505         .en_reg = PERIP1_CLK_ENB,
 506         .en_reg_bit = SSP_CLK_ENB,
 507         .recalc = &follow_parent,
 508 };
 509
 510 /* gpio clock */
 511 static struct clk gpio_clk = {
 512         .pclk = &apb_clk,
 513         .en_reg = PERIP1_CLK_ENB,
 514         .en_reg_bit = GPIO_CLK_ENB,
 515         .recalc = &follow_parent,
 516 };
 517
 518 static struct clk dummy_apb_pclk;
 519
 520 #if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
 521         defined(CONFIG_MACH_SPEAR320)
 522 /* fsmc clock */
 523 static struct clk fsmc_clk = {
 524         .flags = ALWAYS_ENABLED,
 525         .pclk = &ahb_clk,
 526         .recalc = &follow_parent,
 527 };
 528 #endif
 529
 530 /* common clocks to spear310 and spear320 */
 531 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
 532 /* uart1 clock */
 533 static struct clk uart1_clk = {
 534         .flags = ALWAYS_ENABLED,
 535         .pclk = &apb_clk,
 536         .recalc = &follow_parent,
 537 };
 538
 539 /* uart2 clock */
 540 static struct clk uart2_clk = {
 541         .flags = ALWAYS_ENABLED,
 542         .pclk = &apb_clk,
 543         .recalc = &follow_parent,
 544 };
 545 #endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
 546
 547 /* common clocks to spear300 and spear320 */
 548 #if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
 549 /* clcd clock */
 550 static struct clk clcd_clk = {
 551         .flags = ALWAYS_ENABLED,
 552         .pclk = &pll3_48m_clk,
 553         .recalc = &follow_parent,
 554 };
 555
 556 /* sdhci clock */
 557 static struct clk sdhci_clk = {
 558         .flags = ALWAYS_ENABLED,
 559         .pclk = &ahb_clk,
 560         .recalc = &follow_parent,
 561 };
 562 #endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
 563
 564 /* spear300 machine specific clock structures */
 565 #ifdef CONFIG_MACH_SPEAR300
 566 /* gpio1 clock */
 567 static struct clk gpio1_clk = {
 568         .flags = ALWAYS_ENABLED,
 569         .pclk = &apb_clk,
 570         .recalc = &follow_parent,
 571 };
 572
 573 /* keyboard clock */
 574 static struct clk kbd_clk = {
 575         .flags = ALWAYS_ENABLED,
 576         .pclk = &apb_clk,
 577         .recalc = &follow_parent,
 578 };
 579
 580 #endif
 581
 582 /* spear310 machine specific clock structures */
 583 #ifdef CONFIG_MACH_SPEAR310
 584 /* uart3 clock */
 585 static struct clk uart3_clk = {
 586         .flags = ALWAYS_ENABLED,
 587         .pclk = &apb_clk,
 588         .recalc = &follow_parent,
 589 };
 590
 591 /* uart4 clock */
 592 static struct clk uart4_clk = {
 593         .flags = ALWAYS_ENABLED,
 594         .pclk = &apb_clk,
 595         .recalc = &follow_parent,
 596 };
 597
 598 /* uart5 clock */
 599 static struct clk uart5_clk = {
 600         .flags = ALWAYS_ENABLED,
 601         .pclk = &apb_clk,
 602         .recalc = &follow_parent,
 603 };
 604 #endif
 605
 606 /* spear320 machine specific clock structures */
 607 #ifdef CONFIG_MACH_SPEAR320
 608 /* can0 clock */
 609 static struct clk can0_clk = {
 610         .flags = ALWAYS_ENABLED,
 611         .pclk = &apb_clk,
 612         .recalc = &follow_parent,
 613 };
 614
 615 /* can1 clock */
 616 static struct clk can1_clk = {
 617         .flags = ALWAYS_ENABLED,
 618         .pclk = &apb_clk,
 619         .recalc = &follow_parent,
 620 };
 621
 622 /* i2c1 clock */
 623 static struct clk i2c1_clk = {
 624         .flags = ALWAYS_ENABLED,
 625         .pclk = &ahb_clk,
 626         .recalc = &follow_parent,
 627 };
 628
 629 /* ssp1 clock */
 630 static struct clk ssp1_clk = {
 631         .flags = ALWAYS_ENABLED,
 632         .pclk = &apb_clk,
 633         .recalc = &follow_parent,
 634 };
 635
 636 /* ssp2 clock */
 637 static struct clk ssp2_clk = {
 638         .flags = ALWAYS_ENABLED,
 639         .pclk = &apb_clk,
 640         .recalc = &follow_parent,
 641 };
 642
 643 /* pwm clock */
 644 static struct clk pwm_clk = {
 645         .flags = ALWAYS_ENABLED,
 646         .pclk = &apb_clk,
 647         .recalc = &follow_parent,
 648 };
 649 #endif
 650
 651 /* array of all spear 3xx clock lookups */
 652 static struct clk_lookup spear_clk_lookups[] = {
 653         { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
 654         /* root clks */
 655         { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
 656         { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},
 657         /* clock derived from 32 KHz osc clk */
 658         { .dev_id = "rtc-spear",        .clk = &rtc_clk},
 659         /* clock derived from 24 MHz osc clk */
 660         { .con_id = "pll1_clk",         .clk = &pll1_clk},
 661         { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
 662         { .dev_id = "wdt",              .clk = &wdt_clk},
 663         /* clock derived from pll1 clk */
 664         { .con_id = "cpu_clk",          .clk = &cpu_clk},
 665         { .con_id = "ahb_clk",          .clk = &ahb_clk},
 666         { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
 667         { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
 668         { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
 669         { .con_id = "gpt1_synth_clk",   .clk = &gpt1_synth_clk},
 670         { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
 671         { .dev_id = "uart",             .clk = &uart_clk},
 672         { .dev_id = "firda",            .clk = &firda_clk},
 673         { .dev_id = "gpt0",             .clk = &gpt0_clk},
 674         { .dev_id = "gpt1",             .clk = &gpt1_clk},
 675         { .dev_id = "gpt2",             .clk = &gpt2_clk},
 676         /* clock derived from pll3 clk */
 677         { .con_id = "usbh_clk",         .clk = &usbh_clk},
 678         { .dev_id = "usbd",             .clk = &usbd_clk},
 679         /* clock derived from ahb clk */
 680         { .con_id = "apb_clk",          .clk = &apb_clk},
 681         { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
 682         { .dev_id = "dma",              .clk = &dma_clk},
 683         { .dev_id = "jpeg",             .clk = &jpeg_clk},
 684         { .dev_id = "gmac",             .clk = &gmac_clk},
 685         { .dev_id = "smi",              .clk = &smi_clk},
 686         { .dev_id = "c3",               .clk = &c3_clk},
 687         /* clock derived from apb clk */
 688         { .dev_id = "adc",              .clk = &adc_clk},
 689         { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
 690         { .dev_id = "gpio",             .clk = &gpio_clk},
 691 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
 692         { .dev_id = "physmap-flash",    .clk = &emi_clk},
 693 #endif
 694 #if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
 695         defined(CONFIG_MACH_SPEAR320)
 696         { .con_id = "fsmc",             .clk = &fsmc_clk},
 697 #endif
 698
 699 /* common clocks to spear310 and spear320 */
 700 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
 701         { .dev_id = "uart1",            .clk = &uart1_clk},
 702         { .dev_id = "uart2",            .clk = &uart2_clk},
 703 #endif
 704
 705         /* common clock to spear300 and spear320 */
 706 #if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
 707         { .dev_id = "clcd",             .clk = &clcd_clk},
 708         { .dev_id = "sdhci",            .clk = &sdhci_clk},
 709 #endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
 710
 711         /* spear300 machine specific clock structures */
 712 #ifdef CONFIG_MACH_SPEAR300
 713         { .dev_id = "gpio1",            .clk = &gpio1_clk},
 714         { .dev_id = "keyboard",         .clk = &kbd_clk},
 715 #endif
 716
 717         /* spear310 machine specific clock structures */
 718 #ifdef CONFIG_MACH_SPEAR310
 719         { .dev_id = "uart3",            .clk = &uart3_clk},
 720         { .dev_id = "uart4",            .clk = &uart4_clk},
 721         { .dev_id = "uart5",            .clk = &uart5_clk},
 722
 723 #endif
 724         /* spear320 machine specific clock structures */
 725 #ifdef CONFIG_MACH_SPEAR320
 726         { .dev_id = "c_can_platform.0", .clk = &can0_clk},
 727         { .dev_id = "c_can_platform.1", .clk = &can1_clk},
 728         { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
 729         { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
 730         { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
 731         { .dev_id = "pwm",              .clk = &pwm_clk},
 732 #endif
 733 };
 734
 735 void __init clk_init(void)
 736 {
 737         int i;
 738
 739         for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
 740                 clk_register(&spear_clk_lookups[i]);
 741
 742         recalc_root_clocks();
 743 }