include/asm-x86/processor.h

   1 #ifndef __ASM_X86_PROCESSOR_H
   2 #define __ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/page.h>
  14 #include <asm/types.h>
  15 #include <asm/sigcontext.h>
  16 #include <asm/current.h>
  17 #include <asm/cpufeature.h>
  18 #include <asm/system.h>
  19 #include <asm/page.h>
  20 #include <asm/percpu.h>
  21 #include <asm/msr.h>
  22 #include <asm/desc_defs.h>
  23 #include <asm/nops.h>
  24 #include <linux/personality.h>
  25 #include <linux/cpumask.h>
  26 #include <linux/cache.h>
  27 #include <linux/threads.h>
  28 #include <linux/init.h>
  29
  30 /*
  31  * Default implementation of macro that returns current
  32  * instruction pointer ("program counter").
  33  */
  34 static inline void *current_text_addr(void)
  35 {
  36         void *pc;
  37         asm volatile("mov $1f,%0\n1:":"=r" (pc));
  38         return pc;
  39 }
  40
  41 #ifdef CONFIG_X86_VSMP
  42 #define ARCH_MIN_TASKALIGN      (1 << INTERNODE_CACHE_SHIFT)
  43 #define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
  44 #else
  45 #define ARCH_MIN_TASKALIGN      16
  46 #define ARCH_MIN_MMSTRUCT_ALIGN 0
  47 #endif
  48
  49 /*
  50  *  CPU type and hardware bug flags. Kept separately for each CPU.
  51  *  Members of this structure are referenced in head.S, so think twice
  52  *  before touching them. [mj]
  53  */
  54
  55 struct cpuinfo_x86 {
  56         __u8    x86;            /* CPU family */
  57         __u8    x86_vendor;     /* CPU vendor */
  58         __u8    x86_model;
  59         __u8    x86_mask;
  60 #ifdef CONFIG_X86_32
  61         char    wp_works_ok;    /* It doesn't on 386's */
  62         char    hlt_works_ok;   /* Problems on some 486Dx4's and old 386's */
  63         char    hard_math;
  64         char    rfu;
  65         char    fdiv_bug;
  66         char    f00f_bug;
  67         char    coma_bug;
  68         char    pad0;
  69 #else
  70         /* number of 4K pages in DTLB/ITLB combined(in pages)*/
  71         int     x86_tlbsize;
  72         __u8    x86_virt_bits, x86_phys_bits;
  73         /* cpuid returned core id bits */
  74         __u8    x86_coreid_bits;
  75         /* Max extended CPUID function supported */
  76         __u32   extended_cpuid_level;
  77 #endif
  78         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  79         __u32   x86_capability[NCAPINTS];
  80         char    x86_vendor_id[16];
  81         char    x86_model_id[64];
  82         int     x86_cache_size;  /* in KB - valid for CPUS which support this
  83                                     call  */
  84         int     x86_cache_alignment;    /* In bytes */
  85         int     x86_power;
  86         unsigned long loops_per_jiffy;
  87 #ifdef CONFIG_SMP
  88         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
  89 #endif
  90         unsigned char x86_max_cores;    /* cpuid returned max cores value */
  91         unsigned char apicid;
  92         unsigned short x86_clflush_size;
  93 #ifdef CONFIG_SMP
  94         unsigned char booted_cores;     /* number of cores as seen by OS */
  95         __u8 phys_proc_id;              /* Physical processor id. */
  96         __u8 cpu_core_id;               /* Core id */
  97         __u8 cpu_index;                 /* index into per_cpu list */
  98 #endif
  99 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 100
 101 #define X86_VENDOR_INTEL 0
 102 #define X86_VENDOR_CYRIX 1
 103 #define X86_VENDOR_AMD 2
 104 #define X86_VENDOR_UMC 3
 105 #define X86_VENDOR_NEXGEN 4
 106 #define X86_VENDOR_CENTAUR 5
 107 #define X86_VENDOR_TRANSMETA 7
 108 #define X86_VENDOR_NSC 8
 109 #define X86_VENDOR_NUM 9
 110 #define X86_VENDOR_UNKNOWN 0xff
 111
 112 /*
 113  * capabilities of CPUs
 114  */
 115 extern struct cpuinfo_x86 boot_cpu_data;
 116 extern struct cpuinfo_x86 new_cpu_data;
 117 extern struct tss_struct doublefault_tss;
 118
 119 #ifdef CONFIG_SMP
 120 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
 121 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 122 #define current_cpu_data        cpu_data(smp_processor_id())
 123 #else
 124 #define cpu_data(cpu)           boot_cpu_data
 125 #define current_cpu_data        boot_cpu_data
 126 #endif
 127
 128 void cpu_detect(struct cpuinfo_x86 *c);
 129
 130 extern void identify_cpu(struct cpuinfo_x86 *);
 131 extern void identify_boot_cpu(void);
 132 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 133 extern void print_cpu_info(struct cpuinfo_x86 *);
 134 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 135 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 136 extern unsigned short num_cache_leaves;
 137
 138 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
 139 extern void detect_ht(struct cpuinfo_x86 *c);
 140 #else
 141 static inline void detect_ht(struct cpuinfo_x86 *c) {}
 142 #endif
 143
 144 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 145                                          unsigned int *ecx, unsigned int *edx)
 146 {
 147         /* ecx is often an input as well as an output. */
 148         __asm__("cpuid"
 149                 : "=a" (*eax),
 150                   "=b" (*ebx),
 151                   "=c" (*ecx),
 152                   "=d" (*edx)
 153                 : "0" (*eax), "2" (*ecx));
 154 }
 155
 156 static inline void load_cr3(pgd_t *pgdir)
 157 {
 158         write_cr3(__pa(pgdir));
 159 }
 160
 161 #ifdef CONFIG_X86_32
 162 /* This is the TSS defined by the hardware. */
 163 struct x86_hw_tss {
 164         unsigned short  back_link, __blh;
 165         unsigned long   sp0;
 166         unsigned short  ss0, __ss0h;
 167         unsigned long   sp1;
 168         unsigned short  ss1, __ss1h;    /* ss1 caches MSR_IA32_SYSENTER_CS */
 169         unsigned long   sp2;
 170         unsigned short  ss2, __ss2h;
 171         unsigned long   __cr3;
 172         unsigned long   ip;
 173         unsigned long   flags;
 174         unsigned long   ax, cx, dx, bx;
 175         unsigned long   sp, bp, si, di;
 176         unsigned short  es, __esh;
 177         unsigned short  cs, __csh;
 178         unsigned short  ss, __ssh;
 179         unsigned short  ds, __dsh;
 180         unsigned short  fs, __fsh;
 181         unsigned short  gs, __gsh;
 182         unsigned short  ldt, __ldth;
 183         unsigned short  trace, io_bitmap_base;
 184 } __attribute__((packed));
 185 #else
 186 struct x86_hw_tss {
 187         u32 reserved1;
 188         u64 sp0;
 189         u64 sp1;
 190         u64 sp2;
 191         u64 reserved2;
 192         u64 ist[7];
 193         u32 reserved3;
 194         u32 reserved4;
 195         u16 reserved5;
 196         u16 io_bitmap_base;
 197 } __attribute__((packed)) ____cacheline_aligned;
 198 #endif
 199
 200 /*
 201  * Size of io_bitmap.
 202  */
 203 #define IO_BITMAP_BITS  65536
 204 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 205 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 206 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
 207 #define INVALID_IO_BITMAP_OFFSET 0x8000
 208 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
 209
 210 struct tss_struct {
 211         struct x86_hw_tss x86_tss;
 212
 213         /*
 214          * The extra 1 is there because the CPU will access an
 215          * additional byte beyond the end of the IO permission
 216          * bitmap. The extra byte must be all 1 bits, and must
 217          * be within the limit.
 218          */
 219         unsigned long   io_bitmap[IO_BITMAP_LONGS + 1];
 220         /*
 221          * Cache the current maximum and the last task that used the bitmap:
 222          */
 223         unsigned long io_bitmap_max;
 224         struct thread_struct *io_bitmap_owner;
 225         /*
 226          * pads the TSS to be cacheline-aligned (size is 0x100)
 227          */
 228         unsigned long __cacheline_filler[35];
 229         /*
 230          * .. and then another 0x100 bytes for emergency kernel stack
 231          */
 232         unsigned long stack[64];
 233 } __attribute__((packed));
 234
 235 DECLARE_PER_CPU(struct tss_struct, init_tss);
 236
 237 /* Save the original ist values for checking stack pointers during debugging */
 238 struct orig_ist {
 239         unsigned long ist[7];
 240 };
 241
 242 #define MXCSR_DEFAULT           0x1f80
 243
 244 struct i387_fsave_struct {
 245         u32     cwd;
 246         u32     swd;
 247         u32     twd;
 248         u32     fip;
 249         u32     fcs;
 250         u32     foo;
 251         u32     fos;
 252         u32     st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 253         u32     status;         /* software status information */
 254 };
 255
 256 struct i387_fxsave_struct {
 257         u16     cwd;
 258         u16     swd;
 259         u16     twd;
 260         u16     fop;
 261         union {
 262                 struct {
 263                         u64     rip;
 264                         u64     rdp;
 265                 };
 266                 struct {
 267                         u32     fip;
 268                         u32     fcs;
 269                         u32     foo;
 270                         u32     fos;
 271                 };
 272         };
 273         u32     mxcsr;
 274         u32     mxcsr_mask;
 275         u32     st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 276         u32     xmm_space[64];  /* 16*16 bytes for each XMM-reg = 256 bytes */
 277         u32     padding[24];
 278 } __attribute__((aligned(16)));
 279
 280 struct i387_soft_struct {
 281         u32     cwd;
 282         u32     swd;
 283         u32     twd;
 284         u32     fip;
 285         u32     fcs;
 286         u32     foo;
 287         u32     fos;
 288         u32     st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 289         u8      ftop, changed, lookahead, no_update, rm, alimit;
 290         struct info     *info;
 291         u32     entry_eip;
 292 };
 293
 294 union i387_union {
 295         struct i387_fsave_struct        fsave;
 296         struct i387_fxsave_struct       fxsave;
 297         struct i387_soft_struct         soft;
 298 };
 299
 300 #ifdef CONFIG_X86_32
 301 /*
 302  * the following now lives in the per cpu area:
 303  * extern       int cpu_llc_id[NR_CPUS];
 304  */
 305 DECLARE_PER_CPU(u8, cpu_llc_id);
 306 #else
 307 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 308 #endif
 309
 310 extern void print_cpu_info(struct cpuinfo_x86 *);
 311 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 312 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 313 extern unsigned short num_cache_leaves;
 314
 315 struct thread_struct {
 316 /* cached TLS descriptors. */
 317         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 318         unsigned long   sp0;
 319         unsigned long   sp;
 320 #ifdef CONFIG_X86_32
 321         unsigned long   sysenter_cs;
 322 #else
 323         unsigned long   usersp; /* Copy from PDA */
 324         unsigned short  es, ds, fsindex, gsindex;
 325 #endif
 326         unsigned long   ip;
 327         unsigned long   fs;
 328         unsigned long   gs;
 329 /* Hardware debugging registers */
 330         unsigned long   debugreg0;
 331         unsigned long   debugreg1;
 332         unsigned long   debugreg2;
 333         unsigned long   debugreg3;
 334         unsigned long   debugreg6;
 335         unsigned long   debugreg7;
 336 /* fault info */
 337         unsigned long   cr2, trap_no, error_code;
 338 /* floating point info */
 339         union i387_union        i387 __attribute__((aligned(16)));;
 340 #ifdef CONFIG_X86_32
 341 /* virtual 86 mode info */
 342         struct vm86_struct __user *vm86_info;
 343         unsigned long           screen_bitmap;
 344         unsigned long           v86flags, v86mask, saved_sp0;
 345         unsigned int            saved_fs, saved_gs;
 346 #endif
 347 /* IO permissions */
 348         unsigned long   *io_bitmap_ptr;
 349         unsigned long   iopl;
 350 /* max allowed port in the bitmap, in bytes: */
 351         unsigned io_bitmap_max;
 352 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
 353         unsigned long   debugctlmsr;
 354 /* Debug Store - if not 0 points to a DS Save Area configuration;
 355  *               goes into MSR_IA32_DS_AREA */
 356         unsigned long   ds_area_msr;
 357 };
 358
 359 static inline unsigned long native_get_debugreg(int regno)
 360 {
 361         unsigned long val = 0;  /* Damn you, gcc! */
 362
 363         switch (regno) {
 364         case 0:
 365                 asm("mov %%db0, %0" :"=r" (val)); break;
 366         case 1:
 367                 asm("mov %%db1, %0" :"=r" (val)); break;
 368         case 2:
 369                 asm("mov %%db2, %0" :"=r" (val)); break;
 370         case 3:
 371                 asm("mov %%db3, %0" :"=r" (val)); break;
 372         case 6:
 373                 asm("mov %%db6, %0" :"=r" (val)); break;
 374         case 7:
 375                 asm("mov %%db7, %0" :"=r" (val)); break;
 376         default:
 377                 BUG();
 378         }
 379         return val;
 380 }
 381
 382 static inline void native_set_debugreg(int regno, unsigned long value)
 383 {
 384         switch (regno) {
 385         case 0:
 386                 asm("mov %0,%%db0"      : /* no output */ :"r" (value));
 387                 break;
 388         case 1:
 389                 asm("mov %0,%%db1"      : /* no output */ :"r" (value));
 390                 break;
 391         case 2:
 392                 asm("mov %0,%%db2"      : /* no output */ :"r" (value));
 393                 break;
 394         case 3:
 395                 asm("mov %0,%%db3"      : /* no output */ :"r" (value));
 396                 break;
 397         case 6:
 398                 asm("mov %0,%%db6"      : /* no output */ :"r" (value));
 399                 break;
 400         case 7:
 401                 asm("mov %0,%%db7"      : /* no output */ :"r" (value));
 402                 break;
 403         default:
 404                 BUG();
 405         }
 406 }
 407
 408 /*
 409  * Set IOPL bits in EFLAGS from given mask
 410  */
 411 static inline void native_set_iopl_mask(unsigned mask)
 412 {
 413 #ifdef CONFIG_X86_32
 414         unsigned int reg;
 415         __asm__ __volatile__ ("pushfl;"
 416                               "popl %0;"
 417                               "andl %1, %0;"
 418                               "orl %2, %0;"
 419                               "pushl %0;"
 420                               "popfl"
 421                                 : "=&r" (reg)
 422                                 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 423 #endif
 424 }
 425
 426 static inline void native_load_sp0(struct tss_struct *tss,
 427                                    struct thread_struct *thread)
 428 {
 429         tss->x86_tss.sp0 = thread->sp0;
 430 #ifdef CONFIG_X86_32
 431         /* Only happens when SEP is enabled, no need to test "SEP"arately */
 432         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 433                 tss->x86_tss.ss1 = thread->sysenter_cs;
 434                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 435         }
 436 #endif
 437 }
 438
 439 static inline void native_swapgs(void)
 440 {
 441 #ifdef CONFIG_X86_64
 442         asm volatile("swapgs" ::: "memory");
 443 #endif
 444 }
 445
 446 #ifdef CONFIG_PARAVIRT
 447 #include <asm/paravirt.h>
 448 #else
 449 #define __cpuid native_cpuid
 450 #define paravirt_enabled() 0
 451
 452 /*
 453  * These special macros can be used to get or set a debugging register
 454  */
 455 #define get_debugreg(var, register)                             \
 456         (var) = native_get_debugreg(register)
 457 #define set_debugreg(value, register)                           \
 458         native_set_debugreg(register, value)
 459
 460 static inline void load_sp0(struct tss_struct *tss,
 461                             struct thread_struct *thread)
 462 {
 463         native_load_sp0(tss, thread);
 464 }
 465
 466 #define set_iopl_mask native_set_iopl_mask
 467 #define SWAPGS  swapgs
 468 #endif /* CONFIG_PARAVIRT */
 469
 470 /*
 471  * Save the cr4 feature set we're using (ie
 472  * Pentium 4MB enable and PPro Global page
 473  * enable), so that any CPU's that boot up
 474  * after us can get the correct flags.
 475  */
 476 extern unsigned long mmu_cr4_features;
 477
 478 static inline void set_in_cr4(unsigned long mask)
 479 {
 480         unsigned cr4;
 481         mmu_cr4_features |= mask;
 482         cr4 = read_cr4();
 483         cr4 |= mask;
 484         write_cr4(cr4);
 485 }
 486
 487 static inline void clear_in_cr4(unsigned long mask)
 488 {
 489         unsigned cr4;
 490         mmu_cr4_features &= ~mask;
 491         cr4 = read_cr4();
 492         cr4 &= ~mask;
 493         write_cr4(cr4);
 494 }
 495
 496 struct microcode_header {
 497         unsigned int hdrver;
 498         unsigned int rev;
 499         unsigned int date;
 500         unsigned int sig;
 501         unsigned int cksum;
 502         unsigned int ldrver;
 503         unsigned int pf;
 504         unsigned int datasize;
 505         unsigned int totalsize;
 506         unsigned int reserved[3];
 507 };
 508
 509 struct microcode {
 510         struct microcode_header hdr;
 511         unsigned int bits[0];
 512 };
 513
 514 typedef struct microcode microcode_t;
 515 typedef struct microcode_header microcode_header_t;
 516
 517 /* microcode format is extended from prescott processors */
 518 struct extended_signature {
 519         unsigned int sig;
 520         unsigned int pf;
 521         unsigned int cksum;
 522 };
 523
 524 struct extended_sigtable {
 525         unsigned int count;
 526         unsigned int cksum;
 527         unsigned int reserved[3];
 528         struct extended_signature sigs[0];
 529 };
 530
 531 typedef struct {
 532         unsigned long seg;
 533 } mm_segment_t;
 534
 535
 536 /*
 537  * create a kernel thread without removing it from tasklists
 538  */
 539 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 540
 541 /* Free all resources held by a thread. */
 542 extern void release_thread(struct task_struct *);
 543
 544 /* Prepare to copy thread state - unlazy all lazy status */
 545 extern void prepare_to_copy(struct task_struct *tsk);
 546
 547 unsigned long get_wchan(struct task_struct *p);
 548
 549 /*
 550  * Generic CPUID function
 551  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 552  * resulting in stale register contents being returned.
 553  */
 554 static inline void cpuid(unsigned int op,
 555                          unsigned int *eax, unsigned int *ebx,
 556                          unsigned int *ecx, unsigned int *edx)
 557 {
 558         *eax = op;
 559         *ecx = 0;
 560         __cpuid(eax, ebx, ecx, edx);
 561 }
 562
 563 /* Some CPUID calls want 'count' to be placed in ecx */
 564 static inline void cpuid_count(unsigned int op, int count,
 565                                unsigned int *eax, unsigned int *ebx,
 566                                unsigned int *ecx, unsigned int *edx)
 567 {
 568         *eax = op;
 569         *ecx = count;
 570         __cpuid(eax, ebx, ecx, edx);
 571 }
 572
 573 /*
 574  * CPUID functions returning a single datum
 575  */
 576 static inline unsigned int cpuid_eax(unsigned int op)
 577 {
 578         unsigned int eax, ebx, ecx, edx;
 579
 580         cpuid(op, &eax, &ebx, &ecx, &edx);
 581         return eax;
 582 }
 583 static inline unsigned int cpuid_ebx(unsigned int op)
 584 {
 585         unsigned int eax, ebx, ecx, edx;
 586
 587         cpuid(op, &eax, &ebx, &ecx, &edx);
 588         return ebx;
 589 }
 590 static inline unsigned int cpuid_ecx(unsigned int op)
 591 {
 592         unsigned int eax, ebx, ecx, edx;
 593
 594         cpuid(op, &eax, &ebx, &ecx, &edx);
 595         return ecx;
 596 }
 597 static inline unsigned int cpuid_edx(unsigned int op)
 598 {
 599         unsigned int eax, ebx, ecx, edx;
 600
 601         cpuid(op, &eax, &ebx, &ecx, &edx);
 602         return edx;
 603 }
 604
 605 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 606 static inline void rep_nop(void)
 607 {
 608         __asm__ __volatile__("rep;nop": : :"memory");
 609 }
 610
 611 /* Stop speculative execution */
 612 static inline void sync_core(void)
 613 {
 614         int tmp;
 615         asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 616                                           : "ebx", "ecx", "edx", "memory");
 617 }
 618
 619 #define cpu_relax()   rep_nop()
 620
 621 static inline void __monitor(const void *eax, unsigned long ecx,
 622                 unsigned long edx)
 623 {
 624         /* "monitor %eax,%ecx,%edx;" */
 625         asm volatile(
 626                 ".byte 0x0f,0x01,0xc8;"
 627                 : :"a" (eax), "c" (ecx), "d"(edx));
 628 }
 629
 630 static inline void __mwait(unsigned long eax, unsigned long ecx)
 631 {
 632         /* "mwait %eax,%ecx;" */
 633         asm volatile(
 634                 ".byte 0x0f,0x01,0xc9;"
 635                 : :"a" (eax), "c" (ecx));
 636 }
 637
 638 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 639 {
 640         /* "mwait %eax,%ecx;" */
 641         asm volatile(
 642                 "sti; .byte 0x0f,0x01,0xc9;"
 643                 : :"a" (eax), "c" (ecx));
 644 }
 645
 646 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 647
 648 extern int force_mwait;
 649
 650 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 651
 652 extern unsigned long boot_option_idle_override;
 653
 654 extern void enable_sep_cpu(void);
 655 extern int sysenter_setup(void);
 656
 657 /* Defined in head.S */
 658 extern struct desc_ptr early_gdt_descr;
 659
 660 extern void cpu_set_gdt(int);
 661 extern void switch_to_new_gdt(void);
 662 extern void cpu_init(void);
 663 extern void init_gdt(int cpu);
 664
 665 /* from system description table in BIOS.  Mostly for MCA use, but
 666  * others may find it useful. */
 667 extern unsigned int machine_id;
 668 extern unsigned int machine_submodel_id;
 669 extern unsigned int BIOS_revision;
 670 extern unsigned int mca_pentium_flag;
 671
 672 /* Boot loader type from the setup header */
 673 extern int bootloader_type;
 674
 675 extern char ignore_fpu_irq;
 676 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 677
 678 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 679 #define ARCH_HAS_PREFETCHW
 680 #define ARCH_HAS_SPINLOCK_PREFETCH
 681
 682 #ifdef CONFIG_X86_32
 683 #define BASE_PREFETCH   ASM_NOP4
 684 #define ARCH_HAS_PREFETCH
 685 #else
 686 #define BASE_PREFETCH   "prefetcht0 (%1)"
 687 #endif
 688
 689 /* Prefetch instructions for Pentium III and AMD Athlon */
 690 /* It's not worth to care about 3dnow! prefetches for the K6
 691    because they are microcoded there and very slow.
 692    However we don't do prefetches for pre XP Athlons currently
 693    That should be fixed. */
 694 static inline void prefetch(const void *x)
 695 {
 696         alternative_input(BASE_PREFETCH,
 697                           "prefetchnta (%1)",
 698                           X86_FEATURE_XMM,
 699                           "r" (x));
 700 }
 701
 702 /* 3dnow! prefetch to get an exclusive cache line. Useful for
 703    spinlocks to avoid one state transition in the cache coherency protocol. */
 704 static inline void prefetchw(const void *x)
 705 {
 706         alternative_input(BASE_PREFETCH,
 707                           "prefetchw (%1)",
 708                           X86_FEATURE_3DNOW,
 709                           "r" (x));
 710 }
 711
 712 #define spin_lock_prefetch(x)   prefetchw(x)
 713 #ifdef CONFIG_X86_32
 714 /*
 715  * User space process size: 3GB (default).
 716  */
 717 #define TASK_SIZE       (PAGE_OFFSET)
 718
 719 #define INIT_THREAD  {                                                  \
 720         .sp0 = sizeof(init_stack) + (long)&init_stack,                  \
 721         .vm86_info = NULL,                                              \
 722         .sysenter_cs = __KERNEL_CS,                                     \
 723         .io_bitmap_ptr = NULL,                                          \
 724         .fs = __KERNEL_PERCPU,                                          \
 725 }
 726
 727 /*
 728  * Note that the .io_bitmap member must be extra-big. This is because
 729  * the CPU will access an additional byte beyond the end of the IO
 730  * permission bitmap. The extra byte must be all 1 bits, and must
 731  * be within the limit.
 732  */
 733 #define INIT_TSS  {                                                     \
 734         .x86_tss = {                                                    \
 735                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 736                 .ss0            = __KERNEL_DS,                          \
 737                 .ss1            = __KERNEL_CS,                          \
 738                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,             \
 739          },                                                             \
 740         .io_bitmap      = { [0 ... IO_BITMAP_LONGS] = ~0 },             \
 741 }
 742
 743 #define start_thread(regs, new_eip, new_esp) do {               \
 744         __asm__("movl %0,%%gs": :"r" (0));                      \
 745         regs->fs = 0;                                           \
 746         set_fs(USER_DS);                                        \
 747         regs->ds = __USER_DS;                                   \
 748         regs->es = __USER_DS;                                   \
 749         regs->ss = __USER_DS;                                   \
 750         regs->cs = __USER_CS;                                   \
 751         regs->ip = new_eip;                                     \
 752         regs->sp = new_esp;                                     \
 753 } while (0)
 754
 755
 756 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 757
 758 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 759 #define KSTK_TOP(info)                                                 \
 760 ({                                                                     \
 761        unsigned long *__ptr = (unsigned long *)(info);                 \
 762        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 763 })
 764
 765 /*
 766  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 767  * This is necessary to guarantee that the entire "struct pt_regs"
 768  * is accessable even if the CPU haven't stored the SS/ESP registers
 769  * on the stack (interrupt gate does not save these registers
 770  * when switching to the same priv ring).
 771  * Therefore beware: accessing the ss/esp fields of the
 772  * "struct pt_regs" is possible, but they may contain the
 773  * completely wrong values.
 774  */
 775 #define task_pt_regs(task)                                             \
 776 ({                                                                     \
 777        struct pt_regs *__regs__;                                       \
 778        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 779        __regs__ - 1;                                                   \
 780 })
 781
 782 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
 783
 784 #else
 785 /*
 786  * User space process size. 47bits minus one guard page.
 787  */
 788 #define TASK_SIZE64     (0x800000000000UL - 4096)
 789
 790 /* This decides where the kernel will search for a free chunk of vm
 791  * space during mmap's.
 792  */
 793 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
 794                            0xc0000000 : 0xFFFFe000)
 795
 796 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
 797                                  IA32_PAGE_OFFSET : TASK_SIZE64)
 798 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
 799                                   IA32_PAGE_OFFSET : TASK_SIZE64)
 800
 801 #define INIT_THREAD  { \
 802         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 803 }
 804
 805 #define INIT_TSS  { \
 806         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 807 }
 808
 809 #define start_thread(regs, new_rip, new_rsp) do {                            \
 810         asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0));  \
 811         load_gs_index(0);                                                    \
 812         (regs)->ip = (new_rip);                                              \
 813         (regs)->sp = (new_rsp);                                              \
 814         write_pda(oldrsp, (new_rsp));                                        \
 815         (regs)->cs = __USER_CS;                                              \
 816         (regs)->ss = __USER_DS;                                              \
 817         (regs)->flags = 0x200;                                               \
 818         set_fs(USER_DS);                                                     \
 819 } while (0)
 820
 821 /*
 822  * Return saved PC of a blocked thread.
 823  * What is this good for? it will be always the scheduler or ret_from_fork.
 824  */
 825 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
 826
 827 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 828 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
 829 #endif /* CONFIG_X86_64 */
 830
 831 /* This decides where the kernel will search for a free chunk of vm
 832  * space during mmap's.
 833  */
 834 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 835
 836 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
 837
 838 #endif