?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
tg3: Add support for 2 new selfboot formats
[linux-2.6/kvm.git] / drivers / net / tg3.c
blobf08e4b8464588f340921d2b23db625f7fa24cfea
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0 0
59 #define BAR_2 2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.107"
72 #define DRV_MODULE_RELDATE "February 12, 2010"
73
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90 #define TG3_TX_TIMEOUT (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105 #define TG3_RSS_INDIR_TBL_SIZE 128
106
107 /* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113 #define TG3_RX_RCB_RING_SIZE(tp) \
114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
116
117 #define TG3_TX_RING_SIZE 512
118 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125 TG3_RX_RCB_RING_SIZE(tp))
126 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
128 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
130 #define TG3_DMA_BYTE_ENAB 64
131
132 #define TG3_RX_STD_DMA_SZ 1536
133 #define TG3_RX_JMB_DMA_SZ 9046
134
135 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139
140 #define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143 #define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
146 /* minimum number of free TX descriptors required to wake up TX process */
147 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
148
149 #define TG3_RAW_IP_ALIGN 2
150
151 /* number of ETHTOOL_GSTATS u64's */
152 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
154 #define TG3_NUM_TEST 6
155
156 #define FIRMWARE_TG3 "tigon/tg3.bin"
157 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
159
160 static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165 MODULE_LICENSE("GPL");
166 MODULE_VERSION(DRV_MODULE_VERSION);
167 MODULE_FIRMWARE(FIRMWARE_TG3);
168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
171 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
172
173 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174 module_param(tg3_debug, int, 0);
175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
177 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
253 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
254 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
255 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
256 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
257 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
258 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
259 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
260 {}
261 };
262
263 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
264
265 static const struct {
266 const char string[ETH_GSTRING_LEN];
267 } ethtool_stats_keys[TG3_NUM_STATS] = {
268 { "rx_octets" },
269 { "rx_fragments" },
270 { "rx_ucast_packets" },
271 { "rx_mcast_packets" },
272 { "rx_bcast_packets" },
273 { "rx_fcs_errors" },
274 { "rx_align_errors" },
275 { "rx_xon_pause_rcvd" },
276 { "rx_xoff_pause_rcvd" },
277 { "rx_mac_ctrl_rcvd" },
278 { "rx_xoff_entered" },
279 { "rx_frame_too_long_errors" },
280 { "rx_jabbers" },
281 { "rx_undersize_packets" },
282 { "rx_in_length_errors" },
283 { "rx_out_length_errors" },
284 { "rx_64_or_less_octet_packets" },
285 { "rx_65_to_127_octet_packets" },
286 { "rx_128_to_255_octet_packets" },
287 { "rx_256_to_511_octet_packets" },
288 { "rx_512_to_1023_octet_packets" },
289 { "rx_1024_to_1522_octet_packets" },
290 { "rx_1523_to_2047_octet_packets" },
291 { "rx_2048_to_4095_octet_packets" },
292 { "rx_4096_to_8191_octet_packets" },
293 { "rx_8192_to_9022_octet_packets" },
294
295 { "tx_octets" },
296 { "tx_collisions" },
297
298 { "tx_xon_sent" },
299 { "tx_xoff_sent" },
300 { "tx_flow_control" },
301 { "tx_mac_errors" },
302 { "tx_single_collisions" },
303 { "tx_mult_collisions" },
304 { "tx_deferred" },
305 { "tx_excessive_collisions" },
306 { "tx_late_collisions" },
307 { "tx_collide_2times" },
308 { "tx_collide_3times" },
309 { "tx_collide_4times" },
310 { "tx_collide_5times" },
311 { "tx_collide_6times" },
312 { "tx_collide_7times" },
313 { "tx_collide_8times" },
314 { "tx_collide_9times" },
315 { "tx_collide_10times" },
316 { "tx_collide_11times" },
317 { "tx_collide_12times" },
318 { "tx_collide_13times" },
319 { "tx_collide_14times" },
320 { "tx_collide_15times" },
321 { "tx_ucast_packets" },
322 { "tx_mcast_packets" },
323 { "tx_bcast_packets" },
324 { "tx_carrier_sense_errors" },
325 { "tx_discards" },
326 { "tx_errors" },
327
328 { "dma_writeq_full" },
329 { "dma_write_prioq_full" },
330 { "rxbds_empty" },
331 { "rx_discards" },
332 { "rx_errors" },
333 { "rx_threshold_hit" },
334
335 { "dma_readq_full" },
336 { "dma_read_prioq_full" },
337 { "tx_comp_queue_full" },
338
339 { "ring_set_send_prod_index" },
340 { "ring_status_update" },
341 { "nic_irqs" },
342 { "nic_avoided_irqs" },
343 { "nic_tx_threshold_hit" }
344 };
345
346 static const struct {
347 const char string[ETH_GSTRING_LEN];
348 } ethtool_test_keys[TG3_NUM_TEST] = {
349 { "nvram test (online) " },
350 { "link test (online) " },
351 { "register test (offline)" },
352 { "memory test (offline)" },
353 { "loopback test (offline)" },
354 { "interrupt test (offline)" },
355 };
356
357 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
358 {
359 writel(val, tp->regs + off);
360 }
361
362 static u32 tg3_read32(struct tg3 *tp, u32 off)
363 {
364 return (readl(tp->regs + off));
365 }
366
367 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
368 {
369 writel(val, tp->aperegs + off);
370 }
371
372 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
373 {
374 return (readl(tp->aperegs + off));
375 }
376
377 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
378 {
379 unsigned long flags;
380
381 spin_lock_irqsave(&tp->indirect_lock, flags);
382 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
383 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
384 spin_unlock_irqrestore(&tp->indirect_lock, flags);
385 }
386
387 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
388 {
389 writel(val, tp->regs + off);
390 readl(tp->regs + off);
391 }
392
393 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
394 {
395 unsigned long flags;
396 u32 val;
397
398 spin_lock_irqsave(&tp->indirect_lock, flags);
399 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
400 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
401 spin_unlock_irqrestore(&tp->indirect_lock, flags);
402 return val;
403 }
404
405 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
406 {
407 unsigned long flags;
408
409 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
410 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
411 TG3_64BIT_REG_LOW, val);
412 return;
413 }
414 if (off == TG3_RX_STD_PROD_IDX_REG) {
415 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
416 TG3_64BIT_REG_LOW, val);
417 return;
418 }
419
420 spin_lock_irqsave(&tp->indirect_lock, flags);
421 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
422 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
423 spin_unlock_irqrestore(&tp->indirect_lock, flags);
424
425 /* In indirect mode when disabling interrupts, we also need
426 * to clear the interrupt bit in the GRC local ctrl register.
427 */
428 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
429 (val == 0x1)) {
430 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
431 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
432 }
433 }
434
435 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
436 {
437 unsigned long flags;
438 u32 val;
439
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
442 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
444 return val;
445 }
446
447 /* usec_wait specifies the wait time in usec when writing to certain registers
448 * where it is unsafe to read back the register without some delay.
449 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
450 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
451 */
452 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
453 {
454 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
455 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
456 /* Non-posted methods */
457 tp->write32(tp, off, val);
458 else {
459 /* Posted method */
460 tg3_write32(tp, off, val);
461 if (usec_wait)
462 udelay(usec_wait);
463 tp->read32(tp, off);
464 }
465 /* Wait again after the read for the posted method to guarantee that
466 * the wait time is met.
467 */
468 if (usec_wait)
469 udelay(usec_wait);
470 }
471
472 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
473 {
474 tp->write32_mbox(tp, off, val);
475 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
476 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
477 tp->read32_mbox(tp, off);
478 }
479
480 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
481 {
482 void __iomem *mbox = tp->regs + off;
483 writel(val, mbox);
484 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
485 writel(val, mbox);
486 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
487 readl(mbox);
488 }
489
490 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
491 {
492 return (readl(tp->regs + off + GRCMBOX_BASE));
493 }
494
495 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
496 {
497 writel(val, tp->regs + off + GRCMBOX_BASE);
498 }
499
500 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
501 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
502 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
503 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
504 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
505
506 #define tw32(reg,val) tp->write32(tp, reg, val)
507 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
508 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
509 #define tr32(reg) tp->read32(tp, reg)
510
511 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
512 {
513 unsigned long flags;
514
515 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
516 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
517 return;
518
519 spin_lock_irqsave(&tp->indirect_lock, flags);
520 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
521 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
523
524 /* Always leave this as zero. */
525 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 } else {
527 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
528 tw32_f(TG3PCI_MEM_WIN_DATA, val);
529
530 /* Always leave this as zero. */
531 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
532 }
533 spin_unlock_irqrestore(&tp->indirect_lock, flags);
534 }
535
536 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
537 {
538 unsigned long flags;
539
540 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
541 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
542 *val = 0;
543 return;
544 }
545
546 spin_lock_irqsave(&tp->indirect_lock, flags);
547 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
548 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
549 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
550
551 /* Always leave this as zero. */
552 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
553 } else {
554 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
555 *val = tr32(TG3PCI_MEM_WIN_DATA);
556
557 /* Always leave this as zero. */
558 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
559 }
560 spin_unlock_irqrestore(&tp->indirect_lock, flags);
561 }
562
563 static void tg3_ape_lock_init(struct tg3 *tp)
564 {
565 int i;
566
567 /* Make sure the driver hasn't any stale locks. */
568 for (i = 0; i < 8; i++)
569 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
570 APE_LOCK_GRANT_DRIVER);
571 }
572
573 static int tg3_ape_lock(struct tg3 *tp, int locknum)
574 {
575 int i, off;
576 int ret = 0;
577 u32 status;
578
579 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
580 return 0;
581
582 switch (locknum) {
583 case TG3_APE_LOCK_GRC:
584 case TG3_APE_LOCK_MEM:
585 break;
586 default:
587 return -EINVAL;
588 }
589
590 off = 4 * locknum;
591
592 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
593
594 /* Wait for up to 1 millisecond to acquire lock. */
595 for (i = 0; i < 100; i++) {
596 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
597 if (status == APE_LOCK_GRANT_DRIVER)
598 break;
599 udelay(10);
600 }
601
602 if (status != APE_LOCK_GRANT_DRIVER) {
603 /* Revoke the lock request. */
604 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
605 APE_LOCK_GRANT_DRIVER);
606
607 ret = -EBUSY;
608 }
609
610 return ret;
611 }
612
613 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
614 {
615 int off;
616
617 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
618 return;
619
620 switch (locknum) {
621 case TG3_APE_LOCK_GRC:
622 case TG3_APE_LOCK_MEM:
623 break;
624 default:
625 return;
626 }
627
628 off = 4 * locknum;
629 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
630 }
631
632 static void tg3_disable_ints(struct tg3 *tp)
633 {
634 int i;
635
636 tw32(TG3PCI_MISC_HOST_CTRL,
637 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
638 for (i = 0; i < tp->irq_max; i++)
639 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
640 }
641
642 static void tg3_enable_ints(struct tg3 *tp)
643 {
644 int i;
645
646 tp->irq_sync = 0;
647 wmb();
648
649 tw32(TG3PCI_MISC_HOST_CTRL,
650 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
651
652 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
653 for (i = 0; i < tp->irq_cnt; i++) {
654 struct tg3_napi *tnapi = &tp->napi[i];
655 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
656 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
657 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
658
659 tp->coal_now |= tnapi->coal_now;
660 }
661
662 /* Force an initial interrupt */
663 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
664 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
665 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
666 else
667 tw32(HOSTCC_MODE, tp->coal_now);
668
669 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
670 }
671
672 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
673 {
674 struct tg3 *tp = tnapi->tp;
675 struct tg3_hw_status *sblk = tnapi->hw_status;
676 unsigned int work_exists = 0;
677
678 /* check for phy events */
679 if (!(tp->tg3_flags &
680 (TG3_FLAG_USE_LINKCHG_REG |
681 TG3_FLAG_POLL_SERDES))) {
682 if (sblk->status & SD_STATUS_LINK_CHG)
683 work_exists = 1;
684 }
685 /* check for RX/TX work to do */
686 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
687 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
688 work_exists = 1;
689
690 return work_exists;
691 }
692
693 /* tg3_int_reenable
694 * similar to tg3_enable_ints, but it accurately determines whether there
695 * is new work pending and can return without flushing the PIO write
696 * which reenables interrupts
697 */
698 static void tg3_int_reenable(struct tg3_napi *tnapi)
699 {
700 struct tg3 *tp = tnapi->tp;
701
702 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
703 mmiowb();
704
705 /* When doing tagged status, this work check is unnecessary.
706 * The last_tag we write above tells the chip which piece of
707 * work we've completed.
708 */
709 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
710 tg3_has_work(tnapi))
711 tw32(HOSTCC_MODE, tp->coalesce_mode |
712 HOSTCC_MODE_ENABLE | tnapi->coal_now);
713 }
714
715 static void tg3_napi_disable(struct tg3 *tp)
716 {
717 int i;
718
719 for (i = tp->irq_cnt - 1; i >= 0; i--)
720 napi_disable(&tp->napi[i].napi);
721 }
722
723 static void tg3_napi_enable(struct tg3 *tp)
724 {
725 int i;
726
727 for (i = 0; i < tp->irq_cnt; i++)
728 napi_enable(&tp->napi[i].napi);
729 }
730
731 static inline void tg3_netif_stop(struct tg3 *tp)
732 {
733 tp->dev->trans_start = jiffies; /* prevent tx timeout */
734 tg3_napi_disable(tp);
735 netif_tx_disable(tp->dev);
736 }
737
738 static inline void tg3_netif_start(struct tg3 *tp)
739 {
740 /* NOTE: unconditional netif_tx_wake_all_queues is only
741 * appropriate so long as all callers are assured to
742 * have free tx slots (such as after tg3_init_hw)
743 */
744 netif_tx_wake_all_queues(tp->dev);
745
746 tg3_napi_enable(tp);
747 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
748 tg3_enable_ints(tp);
749 }
750
751 static void tg3_switch_clocks(struct tg3 *tp)
752 {
753 u32 clock_ctrl;
754 u32 orig_clock_ctrl;
755
756 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
757 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
758 return;
759
760 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
761
762 orig_clock_ctrl = clock_ctrl;
763 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
764 CLOCK_CTRL_CLKRUN_OENABLE |
765 0x1f);
766 tp->pci_clock_ctrl = clock_ctrl;
767
768 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
769 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
770 tw32_wait_f(TG3PCI_CLOCK_CTRL,
771 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
772 }
773 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
774 tw32_wait_f(TG3PCI_CLOCK_CTRL,
775 clock_ctrl |
776 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
777 40);
778 tw32_wait_f(TG3PCI_CLOCK_CTRL,
779 clock_ctrl | (CLOCK_CTRL_ALTCLK),
780 40);
781 }
782 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
783 }
784
785 #define PHY_BUSY_LOOPS 5000
786
787 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
788 {
789 u32 frame_val;
790 unsigned int loops;
791 int ret;
792
793 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
794 tw32_f(MAC_MI_MODE,
795 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
796 udelay(80);
797 }
798
799 *val = 0x0;
800
801 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
802 MI_COM_PHY_ADDR_MASK);
803 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
804 MI_COM_REG_ADDR_MASK);
805 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
806
807 tw32_f(MAC_MI_COM, frame_val);
808
809 loops = PHY_BUSY_LOOPS;
810 while (loops != 0) {
811 udelay(10);
812 frame_val = tr32(MAC_MI_COM);
813
814 if ((frame_val & MI_COM_BUSY) == 0) {
815 udelay(5);
816 frame_val = tr32(MAC_MI_COM);
817 break;
818 }
819 loops -= 1;
820 }
821
822 ret = -EBUSY;
823 if (loops != 0) {
824 *val = frame_val & MI_COM_DATA_MASK;
825 ret = 0;
826 }
827
828 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
829 tw32_f(MAC_MI_MODE, tp->mi_mode);
830 udelay(80);
831 }
832
833 return ret;
834 }
835
836 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
837 {
838 u32 frame_val;
839 unsigned int loops;
840 int ret;
841
842 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
843 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
844 return 0;
845
846 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
847 tw32_f(MAC_MI_MODE,
848 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
849 udelay(80);
850 }
851
852 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
853 MI_COM_PHY_ADDR_MASK);
854 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
855 MI_COM_REG_ADDR_MASK);
856 frame_val |= (val & MI_COM_DATA_MASK);
857 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
858
859 tw32_f(MAC_MI_COM, frame_val);
860
861 loops = PHY_BUSY_LOOPS;
862 while (loops != 0) {
863 udelay(10);
864 frame_val = tr32(MAC_MI_COM);
865 if ((frame_val & MI_COM_BUSY) == 0) {
866 udelay(5);
867 frame_val = tr32(MAC_MI_COM);
868 break;
869 }
870 loops -= 1;
871 }
872
873 ret = -EBUSY;
874 if (loops != 0)
875 ret = 0;
876
877 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
878 tw32_f(MAC_MI_MODE, tp->mi_mode);
879 udelay(80);
880 }
881
882 return ret;
883 }
884
885 static int tg3_bmcr_reset(struct tg3 *tp)
886 {
887 u32 phy_control;
888 int limit, err;
889
890 /* OK, reset it, and poll the BMCR_RESET bit until it
891 * clears or we time out.
892 */
893 phy_control = BMCR_RESET;
894 err = tg3_writephy(tp, MII_BMCR, phy_control);
895 if (err != 0)
896 return -EBUSY;
897
898 limit = 5000;
899 while (limit--) {
900 err = tg3_readphy(tp, MII_BMCR, &phy_control);
901 if (err != 0)
902 return -EBUSY;
903
904 if ((phy_control & BMCR_RESET) == 0) {
905 udelay(40);
906 break;
907 }
908 udelay(10);
909 }
910 if (limit < 0)
911 return -EBUSY;
912
913 return 0;
914 }
915
916 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
917 {
918 struct tg3 *tp = bp->priv;
919 u32 val;
920
921 spin_lock_bh(&tp->lock);
922
923 if (tg3_readphy(tp, reg, &val))
924 val = -EIO;
925
926 spin_unlock_bh(&tp->lock);
927
928 return val;
929 }
930
931 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
932 {
933 struct tg3 *tp = bp->priv;
934 u32 ret = 0;
935
936 spin_lock_bh(&tp->lock);
937
938 if (tg3_writephy(tp, reg, val))
939 ret = -EIO;
940
941 spin_unlock_bh(&tp->lock);
942
943 return ret;
944 }
945
946 static int tg3_mdio_reset(struct mii_bus *bp)
947 {
948 return 0;
949 }
950
951 static void tg3_mdio_config_5785(struct tg3 *tp)
952 {
953 u32 val;
954 struct phy_device *phydev;
955
956 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
957 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
958 case TG3_PHY_ID_BCM50610:
959 case TG3_PHY_ID_BCM50610M:
960 val = MAC_PHYCFG2_50610_LED_MODES;
961 break;
962 case TG3_PHY_ID_BCMAC131:
963 val = MAC_PHYCFG2_AC131_LED_MODES;
964 break;
965 case TG3_PHY_ID_RTL8211C:
966 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
967 break;
968 case TG3_PHY_ID_RTL8201E:
969 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
970 break;
971 default:
972 return;
973 }
974
975 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
976 tw32(MAC_PHYCFG2, val);
977
978 val = tr32(MAC_PHYCFG1);
979 val &= ~(MAC_PHYCFG1_RGMII_INT |
980 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
981 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
982 tw32(MAC_PHYCFG1, val);
983
984 return;
985 }
986
987 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
988 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
989 MAC_PHYCFG2_FMODE_MASK_MASK |
990 MAC_PHYCFG2_GMODE_MASK_MASK |
991 MAC_PHYCFG2_ACT_MASK_MASK |
992 MAC_PHYCFG2_QUAL_MASK_MASK |
993 MAC_PHYCFG2_INBAND_ENABLE;
994
995 tw32(MAC_PHYCFG2, val);
996
997 val = tr32(MAC_PHYCFG1);
998 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
999 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1000 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1001 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1002 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1004 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1005 }
1006 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1007 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1008 tw32(MAC_PHYCFG1, val);
1009
1010 val = tr32(MAC_EXT_RGMII_MODE);
1011 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1012 MAC_RGMII_MODE_RX_QUALITY |
1013 MAC_RGMII_MODE_RX_ACTIVITY |
1014 MAC_RGMII_MODE_RX_ENG_DET |
1015 MAC_RGMII_MODE_TX_ENABLE |
1016 MAC_RGMII_MODE_TX_LOWPWR |
1017 MAC_RGMII_MODE_TX_RESET);
1018 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1019 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1020 val |= MAC_RGMII_MODE_RX_INT_B |
1021 MAC_RGMII_MODE_RX_QUALITY |
1022 MAC_RGMII_MODE_RX_ACTIVITY |
1023 MAC_RGMII_MODE_RX_ENG_DET;
1024 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1025 val |= MAC_RGMII_MODE_TX_ENABLE |
1026 MAC_RGMII_MODE_TX_LOWPWR |
1027 MAC_RGMII_MODE_TX_RESET;
1028 }
1029 tw32(MAC_EXT_RGMII_MODE, val);
1030 }
1031
1032 static void tg3_mdio_start(struct tg3 *tp)
1033 {
1034 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1035 tw32_f(MAC_MI_MODE, tp->mi_mode);
1036 udelay(80);
1037
1038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1039 u32 funcnum, is_serdes;
1040
1041 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1042 if (funcnum)
1043 tp->phy_addr = 2;
1044 else
1045 tp->phy_addr = 1;
1046
1047 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1048 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1049 else
1050 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1051 TG3_CPMU_PHY_STRAP_IS_SERDES;
1052 if (is_serdes)
1053 tp->phy_addr += 7;
1054 } else
1055 tp->phy_addr = TG3_PHY_MII_ADDR;
1056
1057 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1059 tg3_mdio_config_5785(tp);
1060 }
1061
1062 static int tg3_mdio_init(struct tg3 *tp)
1063 {
1064 int i;
1065 u32 reg;
1066 struct phy_device *phydev;
1067
1068 tg3_mdio_start(tp);
1069
1070 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1071 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1072 return 0;
1073
1074 tp->mdio_bus = mdiobus_alloc();
1075 if (tp->mdio_bus == NULL)
1076 return -ENOMEM;
1077
1078 tp->mdio_bus->name = "tg3 mdio bus";
1079 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1080 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1081 tp->mdio_bus->priv = tp;
1082 tp->mdio_bus->parent = &tp->pdev->dev;
1083 tp->mdio_bus->read = &tg3_mdio_read;
1084 tp->mdio_bus->write = &tg3_mdio_write;
1085 tp->mdio_bus->reset = &tg3_mdio_reset;
1086 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1087 tp->mdio_bus->irq = &tp->mdio_irq[0];
1088
1089 for (i = 0; i < PHY_MAX_ADDR; i++)
1090 tp->mdio_bus->irq[i] = PHY_POLL;
1091
1092 /* The bus registration will look for all the PHYs on the mdio bus.
1093 * Unfortunately, it does not ensure the PHY is powered up before
1094 * accessing the PHY ID registers. A chip reset is the
1095 * quickest way to bring the device back to an operational state..
1096 */
1097 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1098 tg3_bmcr_reset(tp);
1099
1100 i = mdiobus_register(tp->mdio_bus);
1101 if (i) {
1102 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1103 tp->dev->name, i);
1104 mdiobus_free(tp->mdio_bus);
1105 return i;
1106 }
1107
1108 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1109
1110 if (!phydev || !phydev->drv) {
1111 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1112 mdiobus_unregister(tp->mdio_bus);
1113 mdiobus_free(tp->mdio_bus);
1114 return -ENODEV;
1115 }
1116
1117 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1118 case TG3_PHY_ID_BCM57780:
1119 phydev->interface = PHY_INTERFACE_MODE_GMII;
1120 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1121 break;
1122 case TG3_PHY_ID_BCM50610:
1123 case TG3_PHY_ID_BCM50610M:
1124 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1125 PHY_BRCM_RX_REFCLK_UNUSED |
1126 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1127 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1128 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1129 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1130 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1131 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1132 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1133 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1134 /* fallthru */
1135 case TG3_PHY_ID_RTL8211C:
1136 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1137 break;
1138 case TG3_PHY_ID_RTL8201E:
1139 case TG3_PHY_ID_BCMAC131:
1140 phydev->interface = PHY_INTERFACE_MODE_MII;
1141 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1142 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1143 break;
1144 }
1145
1146 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1147
1148 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1149 tg3_mdio_config_5785(tp);
1150
1151 return 0;
1152 }
1153
1154 static void tg3_mdio_fini(struct tg3 *tp)
1155 {
1156 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1157 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1158 mdiobus_unregister(tp->mdio_bus);
1159 mdiobus_free(tp->mdio_bus);
1160 }
1161 }
1162
1163 /* tp->lock is held. */
1164 static inline void tg3_generate_fw_event(struct tg3 *tp)
1165 {
1166 u32 val;
1167
1168 val = tr32(GRC_RX_CPU_EVENT);
1169 val |= GRC_RX_CPU_DRIVER_EVENT;
1170 tw32_f(GRC_RX_CPU_EVENT, val);
1171
1172 tp->last_event_jiffies = jiffies;
1173 }
1174
1175 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1176
1177 /* tp->lock is held. */
1178 static void tg3_wait_for_event_ack(struct tg3 *tp)
1179 {
1180 int i;
1181 unsigned int delay_cnt;
1182 long time_remain;
1183
1184 /* If enough time has passed, no wait is necessary. */
1185 time_remain = (long)(tp->last_event_jiffies + 1 +
1186 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1187 (long)jiffies;
1188 if (time_remain < 0)
1189 return;
1190
1191 /* Check if we can shorten the wait time. */
1192 delay_cnt = jiffies_to_usecs(time_remain);
1193 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1194 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1195 delay_cnt = (delay_cnt >> 3) + 1;
1196
1197 for (i = 0; i < delay_cnt; i++) {
1198 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1199 break;
1200 udelay(8);
1201 }
1202 }
1203
1204 /* tp->lock is held. */
1205 static void tg3_ump_link_report(struct tg3 *tp)
1206 {
1207 u32 reg;
1208 u32 val;
1209
1210 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1211 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1212 return;
1213
1214 tg3_wait_for_event_ack(tp);
1215
1216 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1217
1218 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1219
1220 val = 0;
1221 if (!tg3_readphy(tp, MII_BMCR, &reg))
1222 val = reg << 16;
1223 if (!tg3_readphy(tp, MII_BMSR, &reg))
1224 val |= (reg & 0xffff);
1225 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1226
1227 val = 0;
1228 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1229 val = reg << 16;
1230 if (!tg3_readphy(tp, MII_LPA, &reg))
1231 val |= (reg & 0xffff);
1232 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1233
1234 val = 0;
1235 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1236 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1237 val = reg << 16;
1238 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1239 val |= (reg & 0xffff);
1240 }
1241 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1242
1243 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1244 val = reg << 16;
1245 else
1246 val = 0;
1247 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1248
1249 tg3_generate_fw_event(tp);
1250 }
1251
1252 static void tg3_link_report(struct tg3 *tp)
1253 {
1254 if (!netif_carrier_ok(tp->dev)) {
1255 if (netif_msg_link(tp))
1256 printk(KERN_INFO PFX "%s: Link is down.\n",
1257 tp->dev->name);
1258 tg3_ump_link_report(tp);
1259 } else if (netif_msg_link(tp)) {
1260 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1261 tp->dev->name,
1262 (tp->link_config.active_speed == SPEED_1000 ?
1263 1000 :
1264 (tp->link_config.active_speed == SPEED_100 ?
1265 100 : 10)),
1266 (tp->link_config.active_duplex == DUPLEX_FULL ?
1267 "full" : "half"));
1268
1269 printk(KERN_INFO PFX
1270 "%s: Flow control is %s for TX and %s for RX.\n",
1271 tp->dev->name,
1272 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1273 "on" : "off",
1274 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1275 "on" : "off");
1276 tg3_ump_link_report(tp);
1277 }
1278 }
1279
1280 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1281 {
1282 u16 miireg;
1283
1284 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1285 miireg = ADVERTISE_PAUSE_CAP;
1286 else if (flow_ctrl & FLOW_CTRL_TX)
1287 miireg = ADVERTISE_PAUSE_ASYM;
1288 else if (flow_ctrl & FLOW_CTRL_RX)
1289 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1290 else
1291 miireg = 0;
1292
1293 return miireg;
1294 }
1295
1296 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1297 {
1298 u16 miireg;
1299
1300 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1301 miireg = ADVERTISE_1000XPAUSE;
1302 else if (flow_ctrl & FLOW_CTRL_TX)
1303 miireg = ADVERTISE_1000XPSE_ASYM;
1304 else if (flow_ctrl & FLOW_CTRL_RX)
1305 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1306 else
1307 miireg = 0;
1308
1309 return miireg;
1310 }
1311
1312 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1313 {
1314 u8 cap = 0;
1315
1316 if (lcladv & ADVERTISE_1000XPAUSE) {
1317 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1318 if (rmtadv & LPA_1000XPAUSE)
1319 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1320 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1321 cap = FLOW_CTRL_RX;
1322 } else {
1323 if (rmtadv & LPA_1000XPAUSE)
1324 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1325 }
1326 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1327 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1328 cap = FLOW_CTRL_TX;
1329 }
1330
1331 return cap;
1332 }
1333
1334 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1335 {
1336 u8 autoneg;
1337 u8 flowctrl = 0;
1338 u32 old_rx_mode = tp->rx_mode;
1339 u32 old_tx_mode = tp->tx_mode;
1340
1341 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1342 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1343 else
1344 autoneg = tp->link_config.autoneg;
1345
1346 if (autoneg == AUTONEG_ENABLE &&
1347 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1348 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1349 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1350 else
1351 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1352 } else
1353 flowctrl = tp->link_config.flowctrl;
1354
1355 tp->link_config.active_flowctrl = flowctrl;
1356
1357 if (flowctrl & FLOW_CTRL_RX)
1358 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1359 else
1360 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1361
1362 if (old_rx_mode != tp->rx_mode)
1363 tw32_f(MAC_RX_MODE, tp->rx_mode);
1364
1365 if (flowctrl & FLOW_CTRL_TX)
1366 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1367 else
1368 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1369
1370 if (old_tx_mode != tp->tx_mode)
1371 tw32_f(MAC_TX_MODE, tp->tx_mode);
1372 }
1373
1374 static void tg3_adjust_link(struct net_device *dev)
1375 {
1376 u8 oldflowctrl, linkmesg = 0;
1377 u32 mac_mode, lcl_adv, rmt_adv;
1378 struct tg3 *tp = netdev_priv(dev);
1379 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1380
1381 spin_lock_bh(&tp->lock);
1382
1383 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1384 MAC_MODE_HALF_DUPLEX);
1385
1386 oldflowctrl = tp->link_config.active_flowctrl;
1387
1388 if (phydev->link) {
1389 lcl_adv = 0;
1390 rmt_adv = 0;
1391
1392 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1393 mac_mode |= MAC_MODE_PORT_MODE_MII;
1394 else if (phydev->speed == SPEED_1000 ||
1395 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1396 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1397 else
1398 mac_mode |= MAC_MODE_PORT_MODE_MII;
1399
1400 if (phydev->duplex == DUPLEX_HALF)
1401 mac_mode |= MAC_MODE_HALF_DUPLEX;
1402 else {
1403 lcl_adv = tg3_advert_flowctrl_1000T(
1404 tp->link_config.flowctrl);
1405
1406 if (phydev->pause)
1407 rmt_adv = LPA_PAUSE_CAP;
1408 if (phydev->asym_pause)
1409 rmt_adv |= LPA_PAUSE_ASYM;
1410 }
1411
1412 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1413 } else
1414 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1415
1416 if (mac_mode != tp->mac_mode) {
1417 tp->mac_mode = mac_mode;
1418 tw32_f(MAC_MODE, tp->mac_mode);
1419 udelay(40);
1420 }
1421
1422 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1423 if (phydev->speed == SPEED_10)
1424 tw32(MAC_MI_STAT,
1425 MAC_MI_STAT_10MBPS_MODE |
1426 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1427 else
1428 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1429 }
1430
1431 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1432 tw32(MAC_TX_LENGTHS,
1433 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1434 (6 << TX_LENGTHS_IPG_SHIFT) |
1435 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1436 else
1437 tw32(MAC_TX_LENGTHS,
1438 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1439 (6 << TX_LENGTHS_IPG_SHIFT) |
1440 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1441
1442 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1443 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1444 phydev->speed != tp->link_config.active_speed ||
1445 phydev->duplex != tp->link_config.active_duplex ||
1446 oldflowctrl != tp->link_config.active_flowctrl)
1447 linkmesg = 1;
1448
1449 tp->link_config.active_speed = phydev->speed;
1450 tp->link_config.active_duplex = phydev->duplex;
1451
1452 spin_unlock_bh(&tp->lock);
1453
1454 if (linkmesg)
1455 tg3_link_report(tp);
1456 }
1457
1458 static int tg3_phy_init(struct tg3 *tp)
1459 {
1460 struct phy_device *phydev;
1461
1462 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1463 return 0;
1464
1465 /* Bring the PHY back to a known state. */
1466 tg3_bmcr_reset(tp);
1467
1468 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1469
1470 /* Attach the MAC to the PHY. */
1471 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1472 phydev->dev_flags, phydev->interface);
1473 if (IS_ERR(phydev)) {
1474 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1475 return PTR_ERR(phydev);
1476 }
1477
1478 /* Mask with MAC supported features. */
1479 switch (phydev->interface) {
1480 case PHY_INTERFACE_MODE_GMII:
1481 case PHY_INTERFACE_MODE_RGMII:
1482 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1483 phydev->supported &= (PHY_GBIT_FEATURES |
1484 SUPPORTED_Pause |
1485 SUPPORTED_Asym_Pause);
1486 break;
1487 }
1488 /* fallthru */
1489 case PHY_INTERFACE_MODE_MII:
1490 phydev->supported &= (PHY_BASIC_FEATURES |
1491 SUPPORTED_Pause |
1492 SUPPORTED_Asym_Pause);
1493 break;
1494 default:
1495 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1496 return -EINVAL;
1497 }
1498
1499 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1500
1501 phydev->advertising = phydev->supported;
1502
1503 return 0;
1504 }
1505
1506 static void tg3_phy_start(struct tg3 *tp)
1507 {
1508 struct phy_device *phydev;
1509
1510 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511 return;
1512
1513 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1514
1515 if (tp->link_config.phy_is_low_power) {
1516 tp->link_config.phy_is_low_power = 0;
1517 phydev->speed = tp->link_config.orig_speed;
1518 phydev->duplex = tp->link_config.orig_duplex;
1519 phydev->autoneg = tp->link_config.orig_autoneg;
1520 phydev->advertising = tp->link_config.orig_advertising;
1521 }
1522
1523 phy_start(phydev);
1524
1525 phy_start_aneg(phydev);
1526 }
1527
1528 static void tg3_phy_stop(struct tg3 *tp)
1529 {
1530 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1531 return;
1532
1533 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1534 }
1535
1536 static void tg3_phy_fini(struct tg3 *tp)
1537 {
1538 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1539 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1540 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1541 }
1542 }
1543
1544 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1545 {
1546 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1547 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1548 }
1549
1550 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1551 {
1552 u32 phytest;
1553
1554 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1555 u32 phy;
1556
1557 tg3_writephy(tp, MII_TG3_FET_TEST,
1558 phytest | MII_TG3_FET_SHADOW_EN);
1559 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1560 if (enable)
1561 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1562 else
1563 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1564 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1565 }
1566 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1567 }
1568 }
1569
1570 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1571 {
1572 u32 reg;
1573
1574 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1575 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1576 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1577 return;
1578
1579 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1580 tg3_phy_fet_toggle_apd(tp, enable);
1581 return;
1582 }
1583
1584 reg = MII_TG3_MISC_SHDW_WREN |
1585 MII_TG3_MISC_SHDW_SCR5_SEL |
1586 MII_TG3_MISC_SHDW_SCR5_LPED |
1587 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1588 MII_TG3_MISC_SHDW_SCR5_SDTL |
1589 MII_TG3_MISC_SHDW_SCR5_C125OE;
1590 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1591 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1592
1593 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1594
1595
1596 reg = MII_TG3_MISC_SHDW_WREN |
1597 MII_TG3_MISC_SHDW_APD_SEL |
1598 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1599 if (enable)
1600 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1601
1602 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1603 }
1604
1605 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1606 {
1607 u32 phy;
1608
1609 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1610 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1611 return;
1612
1613 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1614 u32 ephy;
1615
1616 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1617 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1618
1619 tg3_writephy(tp, MII_TG3_FET_TEST,
1620 ephy | MII_TG3_FET_SHADOW_EN);
1621 if (!tg3_readphy(tp, reg, &phy)) {
1622 if (enable)
1623 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1624 else
1625 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1626 tg3_writephy(tp, reg, phy);
1627 }
1628 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1629 }
1630 } else {
1631 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1632 MII_TG3_AUXCTL_SHDWSEL_MISC;
1633 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1634 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1635 if (enable)
1636 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1637 else
1638 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1639 phy |= MII_TG3_AUXCTL_MISC_WREN;
1640 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1641 }
1642 }
1643 }
1644
1645 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1646 {
1647 u32 val;
1648
1649 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1650 return;
1651
1652 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1653 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1654 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1655 (val | (1 << 15) | (1 << 4)));
1656 }
1657
1658 static void tg3_phy_apply_otp(struct tg3 *tp)
1659 {
1660 u32 otp, phy;
1661
1662 if (!tp->phy_otp)
1663 return;
1664
1665 otp = tp->phy_otp;
1666
1667 /* Enable SM_DSP clock and tx 6dB coding. */
1668 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1669 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1670 MII_TG3_AUXCTL_ACTL_TX_6DB;
1671 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1672
1673 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1674 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1675 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1676
1677 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1678 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1679 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1680
1681 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1682 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1683 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1684
1685 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1686 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1687
1688 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1689 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1690
1691 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1692 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1693 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1694
1695 /* Turn off SM_DSP clock. */
1696 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1697 MII_TG3_AUXCTL_ACTL_TX_6DB;
1698 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1699 }
1700
1701 static int tg3_wait_macro_done(struct tg3 *tp)
1702 {
1703 int limit = 100;
1704
1705 while (limit--) {
1706 u32 tmp32;
1707
1708 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1709 if ((tmp32 & 0x1000) == 0)
1710 break;
1711 }
1712 }
1713 if (limit < 0)
1714 return -EBUSY;
1715
1716 return 0;
1717 }
1718
1719 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1720 {
1721 static const u32 test_pat[4][6] = {
1722 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1723 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1724 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1725 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1726 };
1727 int chan;
1728
1729 for (chan = 0; chan < 4; chan++) {
1730 int i;
1731
1732 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1733 (chan * 0x2000) | 0x0200);
1734 tg3_writephy(tp, 0x16, 0x0002);
1735
1736 for (i = 0; i < 6; i++)
1737 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1738 test_pat[chan][i]);
1739
1740 tg3_writephy(tp, 0x16, 0x0202);
1741 if (tg3_wait_macro_done(tp)) {
1742 *resetp = 1;
1743 return -EBUSY;
1744 }
1745
1746 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1747 (chan * 0x2000) | 0x0200);
1748 tg3_writephy(tp, 0x16, 0x0082);
1749 if (tg3_wait_macro_done(tp)) {
1750 *resetp = 1;
1751 return -EBUSY;
1752 }
1753
1754 tg3_writephy(tp, 0x16, 0x0802);
1755 if (tg3_wait_macro_done(tp)) {
1756 *resetp = 1;
1757 return -EBUSY;
1758 }
1759
1760 for (i = 0; i < 6; i += 2) {
1761 u32 low, high;
1762
1763 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1764 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1765 tg3_wait_macro_done(tp)) {
1766 *resetp = 1;
1767 return -EBUSY;
1768 }
1769 low &= 0x7fff;
1770 high &= 0x000f;
1771 if (low != test_pat[chan][i] ||
1772 high != test_pat[chan][i+1]) {
1773 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1775 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1776
1777 return -EBUSY;
1778 }
1779 }
1780 }
1781
1782 return 0;
1783 }
1784
1785 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1786 {
1787 int chan;
1788
1789 for (chan = 0; chan < 4; chan++) {
1790 int i;
1791
1792 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1793 (chan * 0x2000) | 0x0200);
1794 tg3_writephy(tp, 0x16, 0x0002);
1795 for (i = 0; i < 6; i++)
1796 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1797 tg3_writephy(tp, 0x16, 0x0202);
1798 if (tg3_wait_macro_done(tp))
1799 return -EBUSY;
1800 }
1801
1802 return 0;
1803 }
1804
1805 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1806 {
1807 u32 reg32, phy9_orig;
1808 int retries, do_phy_reset, err;
1809
1810 retries = 10;
1811 do_phy_reset = 1;
1812 do {
1813 if (do_phy_reset) {
1814 err = tg3_bmcr_reset(tp);
1815 if (err)
1816 return err;
1817 do_phy_reset = 0;
1818 }
1819
1820 /* Disable transmitter and interrupt. */
1821 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1822 continue;
1823
1824 reg32 |= 0x3000;
1825 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1826
1827 /* Set full-duplex, 1000 mbps. */
1828 tg3_writephy(tp, MII_BMCR,
1829 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1830
1831 /* Set to master mode. */
1832 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1833 continue;
1834
1835 tg3_writephy(tp, MII_TG3_CTRL,
1836 (MII_TG3_CTRL_AS_MASTER |
1837 MII_TG3_CTRL_ENABLE_AS_MASTER));
1838
1839 /* Enable SM_DSP_CLOCK and 6dB. */
1840 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1841
1842 /* Block the PHY control access. */
1843 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1844 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1845
1846 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1847 if (!err)
1848 break;
1849 } while (--retries);
1850
1851 err = tg3_phy_reset_chanpat(tp);
1852 if (err)
1853 return err;
1854
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1857
1858 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1859 tg3_writephy(tp, 0x16, 0x0000);
1860
1861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1862 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1863 /* Set Extended packet length bit for jumbo frames */
1864 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1865 }
1866 else {
1867 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1868 }
1869
1870 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1871
1872 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1873 reg32 &= ~0x3000;
1874 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1875 } else if (!err)
1876 err = -EBUSY;
1877
1878 return err;
1879 }
1880
1881 /* This will reset the tigon3 PHY if there is no valid
1882 * link unless the FORCE argument is non-zero.
1883 */
1884 static int tg3_phy_reset(struct tg3 *tp)
1885 {
1886 u32 cpmuctrl;
1887 u32 phy_status;
1888 int err;
1889
1890 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1891 u32 val;
1892
1893 val = tr32(GRC_MISC_CFG);
1894 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1895 udelay(40);
1896 }
1897 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1898 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1899 if (err != 0)
1900 return -EBUSY;
1901
1902 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1903 netif_carrier_off(tp->dev);
1904 tg3_link_report(tp);
1905 }
1906
1907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1909 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1910 err = tg3_phy_reset_5703_4_5(tp);
1911 if (err)
1912 return err;
1913 goto out;
1914 }
1915
1916 cpmuctrl = 0;
1917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1918 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1919 cpmuctrl = tr32(TG3_CPMU_CTRL);
1920 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1921 tw32(TG3_CPMU_CTRL,
1922 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1923 }
1924
1925 err = tg3_bmcr_reset(tp);
1926 if (err)
1927 return err;
1928
1929 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1930 u32 phy;
1931
1932 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1933 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1934
1935 tw32(TG3_CPMU_CTRL, cpmuctrl);
1936 }
1937
1938 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1939 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1940 u32 val;
1941
1942 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1943 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1944 CPMU_LSPD_1000MB_MACCLK_12_5) {
1945 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1946 udelay(40);
1947 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1948 }
1949 }
1950
1951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1952 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1953 return 0;
1954
1955 tg3_phy_apply_otp(tp);
1956
1957 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1958 tg3_phy_toggle_apd(tp, true);
1959 else
1960 tg3_phy_toggle_apd(tp, false);
1961
1962 out:
1963 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1964 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1965 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1966 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1967 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1968 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1970 }
1971 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1972 tg3_writephy(tp, 0x1c, 0x8d68);
1973 tg3_writephy(tp, 0x1c, 0x8d68);
1974 }
1975 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1976 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1977 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1978 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1979 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1980 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1981 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1982 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1984 }
1985 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1986 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1987 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1988 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1989 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1990 tg3_writephy(tp, MII_TG3_TEST1,
1991 MII_TG3_TEST1_TRIM_EN | 0x4);
1992 } else
1993 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1994 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1995 }
1996 /* Set Extended packet length bit (bit 14) on all chips that */
1997 /* support jumbo frames */
1998 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1999 /* Cannot do read-modify-write on 5401 */
2000 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2001 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2002 u32 phy_reg;
2003
2004 /* Set bit 14 with read-modify-write to preserve other bits */
2005 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2006 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2007 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2008 }
2009
2010 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2011 * jumbo frames transmission.
2012 */
2013 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2014 u32 phy_reg;
2015
2016 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2017 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2018 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2019 }
2020
2021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2022 /* adjust output voltage */
2023 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2024 }
2025
2026 tg3_phy_toggle_automdix(tp, 1);
2027 tg3_phy_set_wirespeed(tp);
2028 return 0;
2029 }
2030
2031 static void tg3_frob_aux_power(struct tg3 *tp)
2032 {
2033 struct tg3 *tp_peer = tp;
2034
2035 /* The GPIOs do something completely different on 57765. */
2036 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2038 return;
2039
2040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2043 struct net_device *dev_peer;
2044
2045 dev_peer = pci_get_drvdata(tp->pdev_peer);
2046 /* remove_one() may have been run on the peer. */
2047 if (!dev_peer)
2048 tp_peer = tp;
2049 else
2050 tp_peer = netdev_priv(dev_peer);
2051 }
2052
2053 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2054 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2055 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2056 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2059 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2060 (GRC_LCLCTRL_GPIO_OE0 |
2061 GRC_LCLCTRL_GPIO_OE1 |
2062 GRC_LCLCTRL_GPIO_OE2 |
2063 GRC_LCLCTRL_GPIO_OUTPUT0 |
2064 GRC_LCLCTRL_GPIO_OUTPUT1),
2065 100);
2066 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2067 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2068 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2069 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2070 GRC_LCLCTRL_GPIO_OE1 |
2071 GRC_LCLCTRL_GPIO_OE2 |
2072 GRC_LCLCTRL_GPIO_OUTPUT0 |
2073 GRC_LCLCTRL_GPIO_OUTPUT1 |
2074 tp->grc_local_ctrl;
2075 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2076
2077 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2078 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2079
2080 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2081 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2082 } else {
2083 u32 no_gpio2;
2084 u32 grc_local_ctrl = 0;
2085
2086 if (tp_peer != tp &&
2087 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2088 return;
2089
2090 /* Workaround to prevent overdrawing Amps. */
2091 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2092 ASIC_REV_5714) {
2093 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095 grc_local_ctrl, 100);
2096 }
2097
2098 /* On 5753 and variants, GPIO2 cannot be used. */
2099 no_gpio2 = tp->nic_sram_data_cfg &
2100 NIC_SRAM_DATA_CFG_NO_GPIO2;
2101
2102 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2103 GRC_LCLCTRL_GPIO_OE1 |
2104 GRC_LCLCTRL_GPIO_OE2 |
2105 GRC_LCLCTRL_GPIO_OUTPUT1 |
2106 GRC_LCLCTRL_GPIO_OUTPUT2;
2107 if (no_gpio2) {
2108 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2109 GRC_LCLCTRL_GPIO_OUTPUT2);
2110 }
2111 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112 grc_local_ctrl, 100);
2113
2114 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2115
2116 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2117 grc_local_ctrl, 100);
2118
2119 if (!no_gpio2) {
2120 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2121 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122 grc_local_ctrl, 100);
2123 }
2124 }
2125 } else {
2126 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2127 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2128 if (tp_peer != tp &&
2129 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2130 return;
2131
2132 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2133 (GRC_LCLCTRL_GPIO_OE1 |
2134 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2135
2136 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2137 GRC_LCLCTRL_GPIO_OE1, 100);
2138
2139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2140 (GRC_LCLCTRL_GPIO_OE1 |
2141 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2142 }
2143 }
2144 }
2145
2146 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2147 {
2148 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2149 return 1;
2150 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2151 if (speed != SPEED_10)
2152 return 1;
2153 } else if (speed == SPEED_10)
2154 return 1;
2155
2156 return 0;
2157 }
2158
2159 static int tg3_setup_phy(struct tg3 *, int);
2160
2161 #define RESET_KIND_SHUTDOWN 0
2162 #define RESET_KIND_INIT 1
2163 #define RESET_KIND_SUSPEND 2
2164
2165 static void tg3_write_sig_post_reset(struct tg3 *, int);
2166 static int tg3_halt_cpu(struct tg3 *, u32);
2167
2168 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2169 {
2170 u32 val;
2171
2172 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2174 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2175 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2176
2177 sg_dig_ctrl |=
2178 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2179 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2180 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2181 }
2182 return;
2183 }
2184
2185 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2186 tg3_bmcr_reset(tp);
2187 val = tr32(GRC_MISC_CFG);
2188 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2189 udelay(40);
2190 return;
2191 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2192 u32 phytest;
2193 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2194 u32 phy;
2195
2196 tg3_writephy(tp, MII_ADVERTISE, 0);
2197 tg3_writephy(tp, MII_BMCR,
2198 BMCR_ANENABLE | BMCR_ANRESTART);
2199
2200 tg3_writephy(tp, MII_TG3_FET_TEST,
2201 phytest | MII_TG3_FET_SHADOW_EN);
2202 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2203 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2204 tg3_writephy(tp,
2205 MII_TG3_FET_SHDW_AUXMODE4,
2206 phy);
2207 }
2208 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2209 }
2210 return;
2211 } else if (do_low_power) {
2212 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2213 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2214
2215 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2216 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2217 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2218 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2219 MII_TG3_AUXCTL_PCTL_VREG_11V);
2220 }
2221
2222 /* The PHY should not be powered down on some chips because
2223 * of bugs.
2224 */
2225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2227 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2228 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2229 return;
2230
2231 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2232 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2233 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2234 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2235 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2236 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2237 }
2238
2239 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2240 }
2241
2242 /* tp->lock is held. */
2243 static int tg3_nvram_lock(struct tg3 *tp)
2244 {
2245 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2246 int i;
2247
2248 if (tp->nvram_lock_cnt == 0) {
2249 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2250 for (i = 0; i < 8000; i++) {
2251 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2252 break;
2253 udelay(20);
2254 }
2255 if (i == 8000) {
2256 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2257 return -ENODEV;
2258 }
2259 }
2260 tp->nvram_lock_cnt++;
2261 }
2262 return 0;
2263 }
2264
2265 /* tp->lock is held. */
2266 static void tg3_nvram_unlock(struct tg3 *tp)
2267 {
2268 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2269 if (tp->nvram_lock_cnt > 0)
2270 tp->nvram_lock_cnt--;
2271 if (tp->nvram_lock_cnt == 0)
2272 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2273 }
2274 }
2275
2276 /* tp->lock is held. */
2277 static void tg3_enable_nvram_access(struct tg3 *tp)
2278 {
2279 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2280 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2281 u32 nvaccess = tr32(NVRAM_ACCESS);
2282
2283 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2284 }
2285 }
2286
2287 /* tp->lock is held. */
2288 static void tg3_disable_nvram_access(struct tg3 *tp)
2289 {
2290 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2291 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2292 u32 nvaccess = tr32(NVRAM_ACCESS);
2293
2294 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2295 }
2296 }
2297
2298 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2299 u32 offset, u32 *val)
2300 {
2301 u32 tmp;
2302 int i;
2303
2304 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2305 return -EINVAL;
2306
2307 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2308 EEPROM_ADDR_DEVID_MASK |
2309 EEPROM_ADDR_READ);
2310 tw32(GRC_EEPROM_ADDR,
2311 tmp |
2312 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2313 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2314 EEPROM_ADDR_ADDR_MASK) |
2315 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2316
2317 for (i = 0; i < 1000; i++) {
2318 tmp = tr32(GRC_EEPROM_ADDR);
2319
2320 if (tmp & EEPROM_ADDR_COMPLETE)
2321 break;
2322 msleep(1);
2323 }
2324 if (!(tmp & EEPROM_ADDR_COMPLETE))
2325 return -EBUSY;
2326
2327 tmp = tr32(GRC_EEPROM_DATA);
2328
2329 /*
2330 * The data will always be opposite the native endian
2331 * format. Perform a blind byteswap to compensate.
2332 */
2333 *val = swab32(tmp);
2334
2335 return 0;
2336 }
2337
2338 #define NVRAM_CMD_TIMEOUT 10000
2339
2340 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2341 {
2342 int i;
2343
2344 tw32(NVRAM_CMD, nvram_cmd);
2345 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2346 udelay(10);
2347 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2348 udelay(10);
2349 break;
2350 }
2351 }
2352
2353 if (i == NVRAM_CMD_TIMEOUT)
2354 return -EBUSY;
2355
2356 return 0;
2357 }
2358
2359 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2360 {
2361 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2362 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2363 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2364 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2365 (tp->nvram_jedecnum == JEDEC_ATMEL))
2366
2367 addr = ((addr / tp->nvram_pagesize) <<
2368 ATMEL_AT45DB0X1B_PAGE_POS) +
2369 (addr % tp->nvram_pagesize);
2370
2371 return addr;
2372 }
2373
2374 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2375 {
2376 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2377 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2378 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2379 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2380 (tp->nvram_jedecnum == JEDEC_ATMEL))
2381
2382 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2383 tp->nvram_pagesize) +
2384 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2385
2386 return addr;
2387 }
2388
2389 /* NOTE: Data read in from NVRAM is byteswapped according to
2390 * the byteswapping settings for all other register accesses.
2391 * tg3 devices are BE devices, so on a BE machine, the data
2392 * returned will be exactly as it is seen in NVRAM. On a LE
2393 * machine, the 32-bit value will be byteswapped.
2394 */
2395 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2396 {
2397 int ret;
2398
2399 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2400 return tg3_nvram_read_using_eeprom(tp, offset, val);
2401
2402 offset = tg3_nvram_phys_addr(tp, offset);
2403
2404 if (offset > NVRAM_ADDR_MSK)
2405 return -EINVAL;
2406
2407 ret = tg3_nvram_lock(tp);
2408 if (ret)
2409 return ret;
2410
2411 tg3_enable_nvram_access(tp);
2412
2413 tw32(NVRAM_ADDR, offset);
2414 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2415 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2416
2417 if (ret == 0)
2418 *val = tr32(NVRAM_RDDATA);
2419
2420 tg3_disable_nvram_access(tp);
2421
2422 tg3_nvram_unlock(tp);
2423
2424 return ret;
2425 }
2426
2427 /* Ensures NVRAM data is in bytestream format. */
2428 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2429 {
2430 u32 v;
2431 int res = tg3_nvram_read(tp, offset, &v);
2432 if (!res)
2433 *val = cpu_to_be32(v);
2434 return res;
2435 }
2436
2437 /* tp->lock is held. */
2438 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2439 {
2440 u32 addr_high, addr_low;
2441 int i;
2442
2443 addr_high = ((tp->dev->dev_addr[0] << 8) |
2444 tp->dev->dev_addr[1]);
2445 addr_low = ((tp->dev->dev_addr[2] << 24) |
2446 (tp->dev->dev_addr[3] << 16) |
2447 (tp->dev->dev_addr[4] << 8) |
2448 (tp->dev->dev_addr[5] << 0));
2449 for (i = 0; i < 4; i++) {
2450 if (i == 1 && skip_mac_1)
2451 continue;
2452 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2453 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2454 }
2455
2456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2457 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2458 for (i = 0; i < 12; i++) {
2459 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2460 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2461 }
2462 }
2463
2464 addr_high = (tp->dev->dev_addr[0] +
2465 tp->dev->dev_addr[1] +
2466 tp->dev->dev_addr[2] +
2467 tp->dev->dev_addr[3] +
2468 tp->dev->dev_addr[4] +
2469 tp->dev->dev_addr[5]) &
2470 TX_BACKOFF_SEED_MASK;
2471 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2472 }
2473
2474 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2475 {
2476 u32 misc_host_ctrl;
2477 bool device_should_wake, do_low_power;
2478
2479 /* Make sure register accesses (indirect or otherwise)
2480 * will function correctly.
2481 */
2482 pci_write_config_dword(tp->pdev,
2483 TG3PCI_MISC_HOST_CTRL,
2484 tp->misc_host_ctrl);
2485
2486 switch (state) {
2487 case PCI_D0:
2488 pci_enable_wake(tp->pdev, state, false);
2489 pci_set_power_state(tp->pdev, PCI_D0);
2490
2491 /* Switch out of Vaux if it is a NIC */
2492 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2493 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2494
2495 return 0;
2496
2497 case PCI_D1:
2498 case PCI_D2:
2499 case PCI_D3hot:
2500 break;
2501
2502 default:
2503 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2504 tp->dev->name, state);
2505 return -EINVAL;
2506 }
2507
2508 /* Restore the CLKREQ setting. */
2509 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2510 u16 lnkctl;
2511
2512 pci_read_config_word(tp->pdev,
2513 tp->pcie_cap + PCI_EXP_LNKCTL,
2514 &lnkctl);
2515 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2516 pci_write_config_word(tp->pdev,
2517 tp->pcie_cap + PCI_EXP_LNKCTL,
2518 lnkctl);
2519 }
2520
2521 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2522 tw32(TG3PCI_MISC_HOST_CTRL,
2523 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2524
2525 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2526 device_may_wakeup(&tp->pdev->dev) &&
2527 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2528
2529 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2530 do_low_power = false;
2531 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2532 !tp->link_config.phy_is_low_power) {
2533 struct phy_device *phydev;
2534 u32 phyid, advertising;
2535
2536 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2537
2538 tp->link_config.phy_is_low_power = 1;
2539
2540 tp->link_config.orig_speed = phydev->speed;
2541 tp->link_config.orig_duplex = phydev->duplex;
2542 tp->link_config.orig_autoneg = phydev->autoneg;
2543 tp->link_config.orig_advertising = phydev->advertising;
2544
2545 advertising = ADVERTISED_TP |
2546 ADVERTISED_Pause |
2547 ADVERTISED_Autoneg |
2548 ADVERTISED_10baseT_Half;
2549
2550 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2551 device_should_wake) {
2552 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2553 advertising |=
2554 ADVERTISED_100baseT_Half |
2555 ADVERTISED_100baseT_Full |
2556 ADVERTISED_10baseT_Full;
2557 else
2558 advertising |= ADVERTISED_10baseT_Full;
2559 }
2560
2561 phydev->advertising = advertising;
2562
2563 phy_start_aneg(phydev);
2564
2565 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2566 if (phyid != TG3_PHY_ID_BCMAC131) {
2567 phyid &= TG3_PHY_OUI_MASK;
2568 if (phyid == TG3_PHY_OUI_1 ||
2569 phyid == TG3_PHY_OUI_2 ||
2570 phyid == TG3_PHY_OUI_3)
2571 do_low_power = true;
2572 }
2573 }
2574 } else {
2575 do_low_power = true;
2576
2577 if (tp->link_config.phy_is_low_power == 0) {
2578 tp->link_config.phy_is_low_power = 1;
2579 tp->link_config.orig_speed = tp->link_config.speed;
2580 tp->link_config.orig_duplex = tp->link_config.duplex;
2581 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2582 }
2583
2584 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2585 tp->link_config.speed = SPEED_10;
2586 tp->link_config.duplex = DUPLEX_HALF;
2587 tp->link_config.autoneg = AUTONEG_ENABLE;
2588 tg3_setup_phy(tp, 0);
2589 }
2590 }
2591
2592 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2593 u32 val;
2594
2595 val = tr32(GRC_VCPU_EXT_CTRL);
2596 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2597 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2598 int i;
2599 u32 val;
2600
2601 for (i = 0; i < 200; i++) {
2602 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2603 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2604 break;
2605 msleep(1);
2606 }
2607 }
2608 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2609 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2610 WOL_DRV_STATE_SHUTDOWN |
2611 WOL_DRV_WOL |
2612 WOL_SET_MAGIC_PKT);
2613
2614 if (device_should_wake) {
2615 u32 mac_mode;
2616
2617 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2618 if (do_low_power) {
2619 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2620 udelay(40);
2621 }
2622
2623 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2624 mac_mode = MAC_MODE_PORT_MODE_GMII;
2625 else
2626 mac_mode = MAC_MODE_PORT_MODE_MII;
2627
2628 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2629 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2630 ASIC_REV_5700) {
2631 u32 speed = (tp->tg3_flags &
2632 TG3_FLAG_WOL_SPEED_100MB) ?
2633 SPEED_100 : SPEED_10;
2634 if (tg3_5700_link_polarity(tp, speed))
2635 mac_mode |= MAC_MODE_LINK_POLARITY;
2636 else
2637 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2638 }
2639 } else {
2640 mac_mode = MAC_MODE_PORT_MODE_TBI;
2641 }
2642
2643 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2644 tw32(MAC_LED_CTRL, tp->led_ctrl);
2645
2646 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2647 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2648 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2649 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2650 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2651 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2652
2653 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2654 mac_mode |= tp->mac_mode &
2655 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2656 if (mac_mode & MAC_MODE_APE_TX_EN)
2657 mac_mode |= MAC_MODE_TDE_ENABLE;
2658 }
2659
2660 tw32_f(MAC_MODE, mac_mode);
2661 udelay(100);
2662
2663 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2664 udelay(10);
2665 }
2666
2667 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2668 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2669 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2670 u32 base_val;
2671
2672 base_val = tp->pci_clock_ctrl;
2673 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2674 CLOCK_CTRL_TXCLK_DISABLE);
2675
2676 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2677 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2678 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2679 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2680 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2681 /* do nothing */
2682 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2683 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2684 u32 newbits1, newbits2;
2685
2686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2687 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2688 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2689 CLOCK_CTRL_TXCLK_DISABLE |
2690 CLOCK_CTRL_ALTCLK);
2691 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2692 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2693 newbits1 = CLOCK_CTRL_625_CORE;
2694 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2695 } else {
2696 newbits1 = CLOCK_CTRL_ALTCLK;
2697 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2698 }
2699
2700 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2701 40);
2702
2703 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2704 40);
2705
2706 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2707 u32 newbits3;
2708
2709 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2710 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2711 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2712 CLOCK_CTRL_TXCLK_DISABLE |
2713 CLOCK_CTRL_44MHZ_CORE);
2714 } else {
2715 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2716 }
2717
2718 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2719 tp->pci_clock_ctrl | newbits3, 40);
2720 }
2721 }
2722
2723 if (!(device_should_wake) &&
2724 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2725 tg3_power_down_phy(tp, do_low_power);
2726
2727 tg3_frob_aux_power(tp);
2728
2729 /* Workaround for unstable PLL clock */
2730 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2731 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2732 u32 val = tr32(0x7d00);
2733
2734 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2735 tw32(0x7d00, val);
2736 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2737 int err;
2738
2739 err = tg3_nvram_lock(tp);
2740 tg3_halt_cpu(tp, RX_CPU_BASE);
2741 if (!err)
2742 tg3_nvram_unlock(tp);
2743 }
2744 }
2745
2746 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2747
2748 if (device_should_wake)
2749 pci_enable_wake(tp->pdev, state, true);
2750
2751 /* Finally, set the new power state. */
2752 pci_set_power_state(tp->pdev, state);
2753
2754 return 0;
2755 }
2756
2757 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2758 {
2759 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2760 case MII_TG3_AUX_STAT_10HALF:
2761 *speed = SPEED_10;
2762 *duplex = DUPLEX_HALF;
2763 break;
2764
2765 case MII_TG3_AUX_STAT_10FULL:
2766 *speed = SPEED_10;
2767 *duplex = DUPLEX_FULL;
2768 break;
2769
2770 case MII_TG3_AUX_STAT_100HALF:
2771 *speed = SPEED_100;
2772 *duplex = DUPLEX_HALF;
2773 break;
2774
2775 case MII_TG3_AUX_STAT_100FULL:
2776 *speed = SPEED_100;
2777 *duplex = DUPLEX_FULL;
2778 break;
2779
2780 case MII_TG3_AUX_STAT_1000HALF:
2781 *speed = SPEED_1000;
2782 *duplex = DUPLEX_HALF;
2783 break;
2784
2785 case MII_TG3_AUX_STAT_1000FULL:
2786 *speed = SPEED_1000;
2787 *duplex = DUPLEX_FULL;
2788 break;
2789
2790 default:
2791 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2792 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2793 SPEED_10;
2794 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2795 DUPLEX_HALF;
2796 break;
2797 }
2798 *speed = SPEED_INVALID;
2799 *duplex = DUPLEX_INVALID;
2800 break;
2801 }
2802 }
2803
2804 static void tg3_phy_copper_begin(struct tg3 *tp)
2805 {
2806 u32 new_adv;
2807 int i;
2808
2809 if (tp->link_config.phy_is_low_power) {
2810 /* Entering low power mode. Disable gigabit and
2811 * 100baseT advertisements.
2812 */
2813 tg3_writephy(tp, MII_TG3_CTRL, 0);
2814
2815 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2816 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2817 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2818 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2819
2820 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821 } else if (tp->link_config.speed == SPEED_INVALID) {
2822 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2823 tp->link_config.advertising &=
2824 ~(ADVERTISED_1000baseT_Half |
2825 ADVERTISED_1000baseT_Full);
2826
2827 new_adv = ADVERTISE_CSMA;
2828 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2829 new_adv |= ADVERTISE_10HALF;
2830 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2831 new_adv |= ADVERTISE_10FULL;
2832 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2833 new_adv |= ADVERTISE_100HALF;
2834 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2835 new_adv |= ADVERTISE_100FULL;
2836
2837 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2838
2839 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2840
2841 if (tp->link_config.advertising &
2842 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2843 new_adv = 0;
2844 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2845 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2846 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2847 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2848 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2849 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2850 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2851 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2852 MII_TG3_CTRL_ENABLE_AS_MASTER);
2853 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2854 } else {
2855 tg3_writephy(tp, MII_TG3_CTRL, 0);
2856 }
2857 } else {
2858 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2859 new_adv |= ADVERTISE_CSMA;
2860
2861 /* Asking for a specific link mode. */
2862 if (tp->link_config.speed == SPEED_1000) {
2863 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2864
2865 if (tp->link_config.duplex == DUPLEX_FULL)
2866 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2867 else
2868 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2869 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2870 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2871 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2872 MII_TG3_CTRL_ENABLE_AS_MASTER);
2873 } else {
2874 if (tp->link_config.speed == SPEED_100) {
2875 if (tp->link_config.duplex == DUPLEX_FULL)
2876 new_adv |= ADVERTISE_100FULL;
2877 else
2878 new_adv |= ADVERTISE_100HALF;
2879 } else {
2880 if (tp->link_config.duplex == DUPLEX_FULL)
2881 new_adv |= ADVERTISE_10FULL;
2882 else
2883 new_adv |= ADVERTISE_10HALF;
2884 }
2885 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2886
2887 new_adv = 0;
2888 }
2889
2890 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2891 }
2892
2893 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2894 tp->link_config.speed != SPEED_INVALID) {
2895 u32 bmcr, orig_bmcr;
2896
2897 tp->link_config.active_speed = tp->link_config.speed;
2898 tp->link_config.active_duplex = tp->link_config.duplex;
2899
2900 bmcr = 0;
2901 switch (tp->link_config.speed) {
2902 default:
2903 case SPEED_10:
2904 break;
2905
2906 case SPEED_100:
2907 bmcr |= BMCR_SPEED100;
2908 break;
2909
2910 case SPEED_1000:
2911 bmcr |= TG3_BMCR_SPEED1000;
2912 break;
2913 }
2914
2915 if (tp->link_config.duplex == DUPLEX_FULL)
2916 bmcr |= BMCR_FULLDPLX;
2917
2918 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2919 (bmcr != orig_bmcr)) {
2920 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2921 for (i = 0; i < 1500; i++) {
2922 u32 tmp;
2923
2924 udelay(10);
2925 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2926 tg3_readphy(tp, MII_BMSR, &tmp))
2927 continue;
2928 if (!(tmp & BMSR_LSTATUS)) {
2929 udelay(40);
2930 break;
2931 }
2932 }
2933 tg3_writephy(tp, MII_BMCR, bmcr);
2934 udelay(40);
2935 }
2936 } else {
2937 tg3_writephy(tp, MII_BMCR,
2938 BMCR_ANENABLE | BMCR_ANRESTART);
2939 }
2940 }
2941
2942 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2943 {
2944 int err;
2945
2946 /* Turn off tap power management. */
2947 /* Set Extended packet length bit */
2948 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2949
2950 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2951 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2952
2953 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2954 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2955
2956 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2957 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2958
2959 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2960 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2961
2962 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2963 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2964
2965 udelay(40);
2966
2967 return err;
2968 }
2969
2970 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2971 {
2972 u32 adv_reg, all_mask = 0;
2973
2974 if (mask & ADVERTISED_10baseT_Half)
2975 all_mask |= ADVERTISE_10HALF;
2976 if (mask & ADVERTISED_10baseT_Full)
2977 all_mask |= ADVERTISE_10FULL;
2978 if (mask & ADVERTISED_100baseT_Half)
2979 all_mask |= ADVERTISE_100HALF;
2980 if (mask & ADVERTISED_100baseT_Full)
2981 all_mask |= ADVERTISE_100FULL;
2982
2983 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2984 return 0;
2985
2986 if ((adv_reg & all_mask) != all_mask)
2987 return 0;
2988 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2989 u32 tg3_ctrl;
2990
2991 all_mask = 0;
2992 if (mask & ADVERTISED_1000baseT_Half)
2993 all_mask |= ADVERTISE_1000HALF;
2994 if (mask & ADVERTISED_1000baseT_Full)
2995 all_mask |= ADVERTISE_1000FULL;
2996
2997 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2998 return 0;
2999
3000 if ((tg3_ctrl & all_mask) != all_mask)
3001 return 0;
3002 }
3003 return 1;
3004 }
3005
3006 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3007 {
3008 u32 curadv, reqadv;
3009
3010 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3011 return 1;
3012
3013 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3014 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3015
3016 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3017 if (curadv != reqadv)
3018 return 0;
3019
3020 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3021 tg3_readphy(tp, MII_LPA, rmtadv);
3022 } else {
3023 /* Reprogram the advertisement register, even if it
3024 * does not affect the current link. If the link
3025 * gets renegotiated in the future, we can save an
3026 * additional renegotiation cycle by advertising
3027 * it correctly in the first place.
3028 */
3029 if (curadv != reqadv) {
3030 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3031 ADVERTISE_PAUSE_ASYM);
3032 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3033 }
3034 }
3035
3036 return 1;
3037 }
3038
3039 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3040 {
3041 int current_link_up;
3042 u32 bmsr, dummy;
3043 u32 lcl_adv, rmt_adv;
3044 u16 current_speed;
3045 u8 current_duplex;
3046 int i, err;
3047
3048 tw32(MAC_EVENT, 0);
3049
3050 tw32_f(MAC_STATUS,
3051 (MAC_STATUS_SYNC_CHANGED |
3052 MAC_STATUS_CFG_CHANGED |
3053 MAC_STATUS_MI_COMPLETION |
3054 MAC_STATUS_LNKSTATE_CHANGED));
3055 udelay(40);
3056
3057 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3058 tw32_f(MAC_MI_MODE,
3059 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3060 udelay(80);
3061 }
3062
3063 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3064
3065 /* Some third-party PHYs need to be reset on link going
3066 * down.
3067 */
3068 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3071 netif_carrier_ok(tp->dev)) {
3072 tg3_readphy(tp, MII_BMSR, &bmsr);
3073 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3074 !(bmsr & BMSR_LSTATUS))
3075 force_reset = 1;
3076 }
3077 if (force_reset)
3078 tg3_phy_reset(tp);
3079
3080 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3081 tg3_readphy(tp, MII_BMSR, &bmsr);
3082 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3083 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3084 bmsr = 0;
3085
3086 if (!(bmsr & BMSR_LSTATUS)) {
3087 err = tg3_init_5401phy_dsp(tp);
3088 if (err)
3089 return err;
3090
3091 tg3_readphy(tp, MII_BMSR, &bmsr);
3092 for (i = 0; i < 1000; i++) {
3093 udelay(10);
3094 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3095 (bmsr & BMSR_LSTATUS)) {
3096 udelay(40);
3097 break;
3098 }
3099 }
3100
3101 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3102 !(bmsr & BMSR_LSTATUS) &&
3103 tp->link_config.active_speed == SPEED_1000) {
3104 err = tg3_phy_reset(tp);
3105 if (!err)
3106 err = tg3_init_5401phy_dsp(tp);
3107 if (err)
3108 return err;
3109 }
3110 }
3111 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3112 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3113 /* 5701 {A0,B0} CRC bug workaround */
3114 tg3_writephy(tp, 0x15, 0x0a75);
3115 tg3_writephy(tp, 0x1c, 0x8c68);
3116 tg3_writephy(tp, 0x1c, 0x8d68);
3117 tg3_writephy(tp, 0x1c, 0x8c68);
3118 }
3119
3120 /* Clear pending interrupts... */
3121 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3122 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3123
3124 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3125 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3126 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3127 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3128
3129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3131 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3132 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3133 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3134 else
3135 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3136 }
3137
3138 current_link_up = 0;
3139 current_speed = SPEED_INVALID;
3140 current_duplex = DUPLEX_INVALID;
3141
3142 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3143 u32 val;
3144
3145 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3146 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3147 if (!(val & (1 << 10))) {
3148 val |= (1 << 10);
3149 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3150 goto relink;
3151 }
3152 }
3153
3154 bmsr = 0;
3155 for (i = 0; i < 100; i++) {
3156 tg3_readphy(tp, MII_BMSR, &bmsr);
3157 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3158 (bmsr & BMSR_LSTATUS))
3159 break;
3160 udelay(40);
3161 }
3162
3163 if (bmsr & BMSR_LSTATUS) {
3164 u32 aux_stat, bmcr;
3165
3166 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3167 for (i = 0; i < 2000; i++) {
3168 udelay(10);
3169 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3170 aux_stat)
3171 break;
3172 }
3173
3174 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3175 &current_speed,
3176 &current_duplex);
3177
3178 bmcr = 0;
3179 for (i = 0; i < 200; i++) {
3180 tg3_readphy(tp, MII_BMCR, &bmcr);
3181 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3182 continue;
3183 if (bmcr && bmcr != 0x7fff)
3184 break;
3185 udelay(10);
3186 }
3187
3188 lcl_adv = 0;
3189 rmt_adv = 0;
3190
3191 tp->link_config.active_speed = current_speed;
3192 tp->link_config.active_duplex = current_duplex;
3193
3194 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3195 if ((bmcr & BMCR_ANENABLE) &&
3196 tg3_copper_is_advertising_all(tp,
3197 tp->link_config.advertising)) {
3198 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3199 &rmt_adv))
3200 current_link_up = 1;
3201 }
3202 } else {
3203 if (!(bmcr & BMCR_ANENABLE) &&
3204 tp->link_config.speed == current_speed &&
3205 tp->link_config.duplex == current_duplex &&
3206 tp->link_config.flowctrl ==
3207 tp->link_config.active_flowctrl) {
3208 current_link_up = 1;
3209 }
3210 }
3211
3212 if (current_link_up == 1 &&
3213 tp->link_config.active_duplex == DUPLEX_FULL)
3214 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3215 }
3216
3217 relink:
3218 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3219 u32 tmp;
3220
3221 tg3_phy_copper_begin(tp);
3222
3223 tg3_readphy(tp, MII_BMSR, &tmp);
3224 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3225 (tmp & BMSR_LSTATUS))
3226 current_link_up = 1;
3227 }
3228
3229 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3230 if (current_link_up == 1) {
3231 if (tp->link_config.active_speed == SPEED_100 ||
3232 tp->link_config.active_speed == SPEED_10)
3233 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3234 else
3235 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3236 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3237 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3238 else
3239 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3240
3241 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3242 if (tp->link_config.active_duplex == DUPLEX_HALF)
3243 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3244
3245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3246 if (current_link_up == 1 &&
3247 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3248 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3249 else
3250 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3251 }
3252
3253 /* ??? Without this setting Netgear GA302T PHY does not
3254 * ??? send/receive packets...
3255 */
3256 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3257 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3258 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3259 tw32_f(MAC_MI_MODE, tp->mi_mode);
3260 udelay(80);
3261 }
3262
3263 tw32_f(MAC_MODE, tp->mac_mode);
3264 udelay(40);
3265
3266 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3267 /* Polled via timer. */
3268 tw32_f(MAC_EVENT, 0);
3269 } else {
3270 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3271 }
3272 udelay(40);
3273
3274 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3275 current_link_up == 1 &&
3276 tp->link_config.active_speed == SPEED_1000 &&
3277 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3278 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3279 udelay(120);
3280 tw32_f(MAC_STATUS,
3281 (MAC_STATUS_SYNC_CHANGED |
3282 MAC_STATUS_CFG_CHANGED));
3283 udelay(40);
3284 tg3_write_mem(tp,
3285 NIC_SRAM_FIRMWARE_MBOX,
3286 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3287 }
3288
3289 /* Prevent send BD corruption. */
3290 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3291 u16 oldlnkctl, newlnkctl;
3292
3293 pci_read_config_word(tp->pdev,
3294 tp->pcie_cap + PCI_EXP_LNKCTL,
3295 &oldlnkctl);
3296 if (tp->link_config.active_speed == SPEED_100 ||
3297 tp->link_config.active_speed == SPEED_10)
3298 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3299 else
3300 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3301 if (newlnkctl != oldlnkctl)
3302 pci_write_config_word(tp->pdev,
3303 tp->pcie_cap + PCI_EXP_LNKCTL,
3304 newlnkctl);
3305 }
3306
3307 if (current_link_up != netif_carrier_ok(tp->dev)) {
3308 if (current_link_up)
3309 netif_carrier_on(tp->dev);
3310 else
3311 netif_carrier_off(tp->dev);
3312 tg3_link_report(tp);
3313 }
3314
3315 return 0;
3316 }
3317
3318 struct tg3_fiber_aneginfo {
3319 int state;
3320 #define ANEG_STATE_UNKNOWN 0
3321 #define ANEG_STATE_AN_ENABLE 1
3322 #define ANEG_STATE_RESTART_INIT 2
3323 #define ANEG_STATE_RESTART 3
3324 #define ANEG_STATE_DISABLE_LINK_OK 4
3325 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3326 #define ANEG_STATE_ABILITY_DETECT 6
3327 #define ANEG_STATE_ACK_DETECT_INIT 7
3328 #define ANEG_STATE_ACK_DETECT 8
3329 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3330 #define ANEG_STATE_COMPLETE_ACK 10
3331 #define ANEG_STATE_IDLE_DETECT_INIT 11
3332 #define ANEG_STATE_IDLE_DETECT 12
3333 #define ANEG_STATE_LINK_OK 13
3334 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3335 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3336
3337 u32 flags;
3338 #define MR_AN_ENABLE 0x00000001
3339 #define MR_RESTART_AN 0x00000002
3340 #define MR_AN_COMPLETE 0x00000004
3341 #define MR_PAGE_RX 0x00000008
3342 #define MR_NP_LOADED 0x00000010
3343 #define MR_TOGGLE_TX 0x00000020
3344 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3345 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3346 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3347 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3348 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3349 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3350 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3351 #define MR_TOGGLE_RX 0x00002000
3352 #define MR_NP_RX 0x00004000
3353
3354 #define MR_LINK_OK 0x80000000
3355
3356 unsigned long link_time, cur_time;
3357
3358 u32 ability_match_cfg;
3359 int ability_match_count;
3360
3361 char ability_match, idle_match, ack_match;
3362
3363 u32 txconfig, rxconfig;
3364 #define ANEG_CFG_NP 0x00000080
3365 #define ANEG_CFG_ACK 0x00000040
3366 #define ANEG_CFG_RF2 0x00000020
3367 #define ANEG_CFG_RF1 0x00000010
3368 #define ANEG_CFG_PS2 0x00000001
3369 #define ANEG_CFG_PS1 0x00008000
3370 #define ANEG_CFG_HD 0x00004000
3371 #define ANEG_CFG_FD 0x00002000
3372 #define ANEG_CFG_INVAL 0x00001f06
3373
3374 };
3375 #define ANEG_OK 0
3376 #define ANEG_DONE 1
3377 #define ANEG_TIMER_ENAB 2
3378 #define ANEG_FAILED -1
3379
3380 #define ANEG_STATE_SETTLE_TIME 10000
3381
3382 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3383 struct tg3_fiber_aneginfo *ap)
3384 {
3385 u16 flowctrl;
3386 unsigned long delta;
3387 u32 rx_cfg_reg;
3388 int ret;
3389
3390 if (ap->state == ANEG_STATE_UNKNOWN) {
3391 ap->rxconfig = 0;
3392 ap->link_time = 0;
3393 ap->cur_time = 0;
3394 ap->ability_match_cfg = 0;
3395 ap->ability_match_count = 0;
3396 ap->ability_match = 0;
3397 ap->idle_match = 0;
3398 ap->ack_match = 0;
3399 }
3400 ap->cur_time++;
3401
3402 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3403 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3404
3405 if (rx_cfg_reg != ap->ability_match_cfg) {
3406 ap->ability_match_cfg = rx_cfg_reg;
3407 ap->ability_match = 0;
3408 ap->ability_match_count = 0;
3409 } else {
3410 if (++ap->ability_match_count > 1) {
3411 ap->ability_match = 1;
3412 ap->ability_match_cfg = rx_cfg_reg;
3413 }
3414 }
3415 if (rx_cfg_reg & ANEG_CFG_ACK)
3416 ap->ack_match = 1;
3417 else
3418 ap->ack_match = 0;
3419
3420 ap->idle_match = 0;
3421 } else {
3422 ap->idle_match = 1;
3423 ap->ability_match_cfg = 0;
3424 ap->ability_match_count = 0;
3425 ap->ability_match = 0;
3426 ap->ack_match = 0;
3427
3428 rx_cfg_reg = 0;
3429 }
3430
3431 ap->rxconfig = rx_cfg_reg;
3432 ret = ANEG_OK;
3433
3434 switch(ap->state) {
3435 case ANEG_STATE_UNKNOWN:
3436 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3437 ap->state = ANEG_STATE_AN_ENABLE;
3438
3439 /* fallthru */
3440 case ANEG_STATE_AN_ENABLE:
3441 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3442 if (ap->flags & MR_AN_ENABLE) {
3443 ap->link_time = 0;
3444 ap->cur_time = 0;
3445 ap->ability_match_cfg = 0;
3446 ap->ability_match_count = 0;
3447 ap->ability_match = 0;
3448 ap->idle_match = 0;
3449 ap->ack_match = 0;
3450
3451 ap->state = ANEG_STATE_RESTART_INIT;
3452 } else {
3453 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3454 }
3455 break;
3456
3457 case ANEG_STATE_RESTART_INIT:
3458 ap->link_time = ap->cur_time;
3459 ap->flags &= ~(MR_NP_LOADED);
3460 ap->txconfig = 0;
3461 tw32(MAC_TX_AUTO_NEG, 0);
3462 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3463 tw32_f(MAC_MODE, tp->mac_mode);
3464 udelay(40);
3465
3466 ret = ANEG_TIMER_ENAB;
3467 ap->state = ANEG_STATE_RESTART;
3468
3469 /* fallthru */
3470 case ANEG_STATE_RESTART:
3471 delta = ap->cur_time - ap->link_time;
3472 if (delta > ANEG_STATE_SETTLE_TIME) {
3473 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3474 } else {
3475 ret = ANEG_TIMER_ENAB;
3476 }
3477 break;
3478
3479 case ANEG_STATE_DISABLE_LINK_OK:
3480 ret = ANEG_DONE;
3481 break;
3482
3483 case ANEG_STATE_ABILITY_DETECT_INIT:
3484 ap->flags &= ~(MR_TOGGLE_TX);
3485 ap->txconfig = ANEG_CFG_FD;
3486 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3487 if (flowctrl & ADVERTISE_1000XPAUSE)
3488 ap->txconfig |= ANEG_CFG_PS1;
3489 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3490 ap->txconfig |= ANEG_CFG_PS2;
3491 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3492 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3493 tw32_f(MAC_MODE, tp->mac_mode);
3494 udelay(40);
3495
3496 ap->state = ANEG_STATE_ABILITY_DETECT;
3497 break;
3498
3499 case ANEG_STATE_ABILITY_DETECT:
3500 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3501 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3502 }
3503 break;
3504
3505 case ANEG_STATE_ACK_DETECT_INIT:
3506 ap->txconfig |= ANEG_CFG_ACK;
3507 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3508 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3509 tw32_f(MAC_MODE, tp->mac_mode);
3510 udelay(40);
3511
3512 ap->state = ANEG_STATE_ACK_DETECT;
3513
3514 /* fallthru */
3515 case ANEG_STATE_ACK_DETECT:
3516 if (ap->ack_match != 0) {
3517 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3518 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3519 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3520 } else {
3521 ap->state = ANEG_STATE_AN_ENABLE;
3522 }
3523 } else if (ap->ability_match != 0 &&
3524 ap->rxconfig == 0) {
3525 ap->state = ANEG_STATE_AN_ENABLE;
3526 }
3527 break;
3528
3529 case ANEG_STATE_COMPLETE_ACK_INIT:
3530 if (ap->rxconfig & ANEG_CFG_INVAL) {
3531 ret = ANEG_FAILED;
3532 break;
3533 }
3534 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3535 MR_LP_ADV_HALF_DUPLEX |
3536 MR_LP_ADV_SYM_PAUSE |
3537 MR_LP_ADV_ASYM_PAUSE |
3538 MR_LP_ADV_REMOTE_FAULT1 |
3539 MR_LP_ADV_REMOTE_FAULT2 |
3540 MR_LP_ADV_NEXT_PAGE |
3541 MR_TOGGLE_RX |
3542 MR_NP_RX);
3543 if (ap->rxconfig & ANEG_CFG_FD)
3544 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3545 if (ap->rxconfig & ANEG_CFG_HD)
3546 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3547 if (ap->rxconfig & ANEG_CFG_PS1)
3548 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3549 if (ap->rxconfig & ANEG_CFG_PS2)
3550 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3551 if (ap->rxconfig & ANEG_CFG_RF1)
3552 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3553 if (ap->rxconfig & ANEG_CFG_RF2)
3554 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3555 if (ap->rxconfig & ANEG_CFG_NP)
3556 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3557
3558 ap->link_time = ap->cur_time;
3559
3560 ap->flags ^= (MR_TOGGLE_TX);
3561 if (ap->rxconfig & 0x0008)
3562 ap->flags |= MR_TOGGLE_RX;
3563 if (ap->rxconfig & ANEG_CFG_NP)
3564 ap->flags |= MR_NP_RX;
3565 ap->flags |= MR_PAGE_RX;
3566
3567 ap->state = ANEG_STATE_COMPLETE_ACK;
3568 ret = ANEG_TIMER_ENAB;
3569 break;
3570
3571 case ANEG_STATE_COMPLETE_ACK:
3572 if (ap->ability_match != 0 &&
3573 ap->rxconfig == 0) {
3574 ap->state = ANEG_STATE_AN_ENABLE;
3575 break;
3576 }
3577 delta = ap->cur_time - ap->link_time;
3578 if (delta > ANEG_STATE_SETTLE_TIME) {
3579 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3580 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3581 } else {
3582 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3583 !(ap->flags & MR_NP_RX)) {
3584 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3585 } else {
3586 ret = ANEG_FAILED;
3587 }
3588 }
3589 }
3590 break;
3591
3592 case ANEG_STATE_IDLE_DETECT_INIT:
3593 ap->link_time = ap->cur_time;
3594 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3595 tw32_f(MAC_MODE, tp->mac_mode);
3596 udelay(40);
3597
3598 ap->state = ANEG_STATE_IDLE_DETECT;
3599 ret = ANEG_TIMER_ENAB;
3600 break;
3601
3602 case ANEG_STATE_IDLE_DETECT:
3603 if (ap->ability_match != 0 &&
3604 ap->rxconfig == 0) {
3605 ap->state = ANEG_STATE_AN_ENABLE;
3606 break;
3607 }
3608 delta = ap->cur_time - ap->link_time;
3609 if (delta > ANEG_STATE_SETTLE_TIME) {
3610 /* XXX another gem from the Broadcom driver :( */
3611 ap->state = ANEG_STATE_LINK_OK;
3612 }
3613 break;
3614
3615 case ANEG_STATE_LINK_OK:
3616 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3617 ret = ANEG_DONE;
3618 break;
3619
3620 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3621 /* ??? unimplemented */
3622 break;
3623
3624 case ANEG_STATE_NEXT_PAGE_WAIT:
3625 /* ??? unimplemented */
3626 break;
3627
3628 default:
3629 ret = ANEG_FAILED;
3630 break;
3631 }
3632
3633 return ret;
3634 }
3635
3636 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3637 {
3638 int res = 0;
3639 struct tg3_fiber_aneginfo aninfo;
3640 int status = ANEG_FAILED;
3641 unsigned int tick;
3642 u32 tmp;
3643
3644 tw32_f(MAC_TX_AUTO_NEG, 0);
3645
3646 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3647 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3648 udelay(40);
3649
3650 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3651 udelay(40);
3652
3653 memset(&aninfo, 0, sizeof(aninfo));
3654 aninfo.flags |= MR_AN_ENABLE;
3655 aninfo.state = ANEG_STATE_UNKNOWN;
3656 aninfo.cur_time = 0;
3657 tick = 0;
3658 while (++tick < 195000) {
3659 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3660 if (status == ANEG_DONE || status == ANEG_FAILED)
3661 break;
3662
3663 udelay(1);
3664 }
3665
3666 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3667 tw32_f(MAC_MODE, tp->mac_mode);
3668 udelay(40);
3669
3670 *txflags = aninfo.txconfig;
3671 *rxflags = aninfo.flags;
3672
3673 if (status == ANEG_DONE &&
3674 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3675 MR_LP_ADV_FULL_DUPLEX)))
3676 res = 1;
3677
3678 return res;
3679 }
3680
3681 static void tg3_init_bcm8002(struct tg3 *tp)
3682 {
3683 u32 mac_status = tr32(MAC_STATUS);
3684 int i;
3685
3686 /* Reset when initting first time or we have a link. */
3687 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3688 !(mac_status & MAC_STATUS_PCS_SYNCED))
3689 return;
3690
3691 /* Set PLL lock range. */
3692 tg3_writephy(tp, 0x16, 0x8007);
3693
3694 /* SW reset */
3695 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3696
3697 /* Wait for reset to complete. */
3698 /* XXX schedule_timeout() ... */
3699 for (i = 0; i < 500; i++)
3700 udelay(10);
3701
3702 /* Config mode; select PMA/Ch 1 regs. */
3703 tg3_writephy(tp, 0x10, 0x8411);
3704
3705 /* Enable auto-lock and comdet, select txclk for tx. */
3706 tg3_writephy(tp, 0x11, 0x0a10);
3707
3708 tg3_writephy(tp, 0x18, 0x00a0);
3709 tg3_writephy(tp, 0x16, 0x41ff);
3710
3711 /* Assert and deassert POR. */
3712 tg3_writephy(tp, 0x13, 0x0400);
3713 udelay(40);
3714 tg3_writephy(tp, 0x13, 0x0000);
3715
3716 tg3_writephy(tp, 0x11, 0x0a50);
3717 udelay(40);
3718 tg3_writephy(tp, 0x11, 0x0a10);
3719
3720 /* Wait for signal to stabilize */
3721 /* XXX schedule_timeout() ... */
3722 for (i = 0; i < 15000; i++)
3723 udelay(10);
3724
3725 /* Deselect the channel register so we can read the PHYID
3726 * later.
3727 */
3728 tg3_writephy(tp, 0x10, 0x8011);
3729 }
3730
3731 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3732 {
3733 u16 flowctrl;
3734 u32 sg_dig_ctrl, sg_dig_status;
3735 u32 serdes_cfg, expected_sg_dig_ctrl;
3736 int workaround, port_a;
3737 int current_link_up;
3738
3739 serdes_cfg = 0;
3740 expected_sg_dig_ctrl = 0;
3741 workaround = 0;
3742 port_a = 1;
3743 current_link_up = 0;
3744
3745 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3746 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3747 workaround = 1;
3748 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3749 port_a = 0;
3750
3751 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3752 /* preserve bits 20-23 for voltage regulator */
3753 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3754 }
3755
3756 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3757
3758 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3759 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3760 if (workaround) {
3761 u32 val = serdes_cfg;
3762
3763 if (port_a)
3764 val |= 0xc010000;
3765 else
3766 val |= 0x4010000;
3767 tw32_f(MAC_SERDES_CFG, val);
3768 }
3769
3770 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3771 }
3772 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3773 tg3_setup_flow_control(tp, 0, 0);
3774 current_link_up = 1;
3775 }
3776 goto out;
3777 }
3778
3779 /* Want auto-negotiation. */
3780 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3781
3782 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3783 if (flowctrl & ADVERTISE_1000XPAUSE)
3784 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3785 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3786 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3787
3788 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3789 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3790 tp->serdes_counter &&
3791 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3792 MAC_STATUS_RCVD_CFG)) ==
3793 MAC_STATUS_PCS_SYNCED)) {
3794 tp->serdes_counter--;
3795 current_link_up = 1;
3796 goto out;
3797 }
3798 restart_autoneg:
3799 if (workaround)
3800 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3801 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3802 udelay(5);
3803 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3804
3805 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3806 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3807 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3808 MAC_STATUS_SIGNAL_DET)) {
3809 sg_dig_status = tr32(SG_DIG_STATUS);
3810 mac_status = tr32(MAC_STATUS);
3811
3812 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3813 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3814 u32 local_adv = 0, remote_adv = 0;
3815
3816 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3817 local_adv |= ADVERTISE_1000XPAUSE;
3818 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3819 local_adv |= ADVERTISE_1000XPSE_ASYM;
3820
3821 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3822 remote_adv |= LPA_1000XPAUSE;
3823 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3824 remote_adv |= LPA_1000XPAUSE_ASYM;
3825
3826 tg3_setup_flow_control(tp, local_adv, remote_adv);
3827 current_link_up = 1;
3828 tp->serdes_counter = 0;
3829 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3830 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3831 if (tp->serdes_counter)
3832 tp->serdes_counter--;
3833 else {
3834 if (workaround) {
3835 u32 val = serdes_cfg;
3836
3837 if (port_a)
3838 val |= 0xc010000;
3839 else
3840 val |= 0x4010000;
3841
3842 tw32_f(MAC_SERDES_CFG, val);
3843 }
3844
3845 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3846 udelay(40);
3847
3848 /* Link parallel detection - link is up */
3849 /* only if we have PCS_SYNC and not */
3850 /* receiving config code words */
3851 mac_status = tr32(MAC_STATUS);
3852 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3853 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3854 tg3_setup_flow_control(tp, 0, 0);
3855 current_link_up = 1;
3856 tp->tg3_flags2 |=
3857 TG3_FLG2_PARALLEL_DETECT;
3858 tp->serdes_counter =
3859 SERDES_PARALLEL_DET_TIMEOUT;
3860 } else
3861 goto restart_autoneg;
3862 }
3863 }
3864 } else {
3865 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3866 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3867 }
3868
3869 out:
3870 return current_link_up;
3871 }
3872
3873 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3874 {
3875 int current_link_up = 0;
3876
3877 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3878 goto out;
3879
3880 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3881 u32 txflags, rxflags;
3882 int i;
3883
3884 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3885 u32 local_adv = 0, remote_adv = 0;
3886
3887 if (txflags & ANEG_CFG_PS1)
3888 local_adv |= ADVERTISE_1000XPAUSE;
3889 if (txflags & ANEG_CFG_PS2)
3890 local_adv |= ADVERTISE_1000XPSE_ASYM;
3891
3892 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3893 remote_adv |= LPA_1000XPAUSE;
3894 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3895 remote_adv |= LPA_1000XPAUSE_ASYM;
3896
3897 tg3_setup_flow_control(tp, local_adv, remote_adv);
3898
3899 current_link_up = 1;
3900 }
3901 for (i = 0; i < 30; i++) {
3902 udelay(20);
3903 tw32_f(MAC_STATUS,
3904 (MAC_STATUS_SYNC_CHANGED |
3905 MAC_STATUS_CFG_CHANGED));
3906 udelay(40);
3907 if ((tr32(MAC_STATUS) &
3908 (MAC_STATUS_SYNC_CHANGED |
3909 MAC_STATUS_CFG_CHANGED)) == 0)
3910 break;
3911 }
3912
3913 mac_status = tr32(MAC_STATUS);
3914 if (current_link_up == 0 &&
3915 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3916 !(mac_status & MAC_STATUS_RCVD_CFG))
3917 current_link_up = 1;
3918 } else {
3919 tg3_setup_flow_control(tp, 0, 0);
3920
3921 /* Forcing 1000FD link up. */
3922 current_link_up = 1;
3923
3924 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3925 udelay(40);
3926
3927 tw32_f(MAC_MODE, tp->mac_mode);
3928 udelay(40);
3929 }
3930
3931 out:
3932 return current_link_up;
3933 }
3934
3935 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3936 {
3937 u32 orig_pause_cfg;
3938 u16 orig_active_speed;
3939 u8 orig_active_duplex;
3940 u32 mac_status;
3941 int current_link_up;
3942 int i;
3943
3944 orig_pause_cfg = tp->link_config.active_flowctrl;
3945 orig_active_speed = tp->link_config.active_speed;
3946 orig_active_duplex = tp->link_config.active_duplex;
3947
3948 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3949 netif_carrier_ok(tp->dev) &&
3950 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3951 mac_status = tr32(MAC_STATUS);
3952 mac_status &= (MAC_STATUS_PCS_SYNCED |
3953 MAC_STATUS_SIGNAL_DET |
3954 MAC_STATUS_CFG_CHANGED |
3955 MAC_STATUS_RCVD_CFG);
3956 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3957 MAC_STATUS_SIGNAL_DET)) {
3958 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3959 MAC_STATUS_CFG_CHANGED));
3960 return 0;
3961 }
3962 }
3963
3964 tw32_f(MAC_TX_AUTO_NEG, 0);
3965
3966 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3967 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3968 tw32_f(MAC_MODE, tp->mac_mode);
3969 udelay(40);
3970
3971 if (tp->phy_id == PHY_ID_BCM8002)
3972 tg3_init_bcm8002(tp);
3973
3974 /* Enable link change event even when serdes polling. */
3975 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3976 udelay(40);
3977
3978 current_link_up = 0;
3979 mac_status = tr32(MAC_STATUS);
3980
3981 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3982 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3983 else
3984 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3985
3986 tp->napi[0].hw_status->status =
3987 (SD_STATUS_UPDATED |
3988 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3989
3990 for (i = 0; i < 100; i++) {
3991 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3992 MAC_STATUS_CFG_CHANGED));
3993 udelay(5);
3994 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3995 MAC_STATUS_CFG_CHANGED |
3996 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3997 break;
3998 }
3999
4000 mac_status = tr32(MAC_STATUS);
4001 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4002 current_link_up = 0;
4003 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4004 tp->serdes_counter == 0) {
4005 tw32_f(MAC_MODE, (tp->mac_mode |
4006 MAC_MODE_SEND_CONFIGS));
4007 udelay(1);
4008 tw32_f(MAC_MODE, tp->mac_mode);
4009 }
4010 }
4011
4012 if (current_link_up == 1) {
4013 tp->link_config.active_speed = SPEED_1000;
4014 tp->link_config.active_duplex = DUPLEX_FULL;
4015 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4016 LED_CTRL_LNKLED_OVERRIDE |
4017 LED_CTRL_1000MBPS_ON));
4018 } else {
4019 tp->link_config.active_speed = SPEED_INVALID;
4020 tp->link_config.active_duplex = DUPLEX_INVALID;
4021 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4022 LED_CTRL_LNKLED_OVERRIDE |
4023 LED_CTRL_TRAFFIC_OVERRIDE));
4024 }
4025
4026 if (current_link_up != netif_carrier_ok(tp->dev)) {
4027 if (current_link_up)
4028 netif_carrier_on(tp->dev);
4029 else
4030 netif_carrier_off(tp->dev);
4031 tg3_link_report(tp);
4032 } else {
4033 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4034 if (orig_pause_cfg != now_pause_cfg ||
4035 orig_active_speed != tp->link_config.active_speed ||
4036 orig_active_duplex != tp->link_config.active_duplex)
4037 tg3_link_report(tp);
4038 }
4039
4040 return 0;
4041 }
4042
4043 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4044 {
4045 int current_link_up, err = 0;
4046 u32 bmsr, bmcr;
4047 u16 current_speed;
4048 u8 current_duplex;
4049 u32 local_adv, remote_adv;
4050
4051 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4052 tw32_f(MAC_MODE, tp->mac_mode);
4053 udelay(40);
4054
4055 tw32(MAC_EVENT, 0);
4056
4057 tw32_f(MAC_STATUS,
4058 (MAC_STATUS_SYNC_CHANGED |
4059 MAC_STATUS_CFG_CHANGED |
4060 MAC_STATUS_MI_COMPLETION |
4061 MAC_STATUS_LNKSTATE_CHANGED));
4062 udelay(40);
4063
4064 if (force_reset)
4065 tg3_phy_reset(tp);
4066
4067 current_link_up = 0;
4068 current_speed = SPEED_INVALID;
4069 current_duplex = DUPLEX_INVALID;
4070
4071 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4072 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4074 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4075 bmsr |= BMSR_LSTATUS;
4076 else
4077 bmsr &= ~BMSR_LSTATUS;
4078 }
4079
4080 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4081
4082 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4083 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4084 /* do nothing, just check for link up at the end */
4085 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4086 u32 adv, new_adv;
4087
4088 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4089 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4090 ADVERTISE_1000XPAUSE |
4091 ADVERTISE_1000XPSE_ASYM |
4092 ADVERTISE_SLCT);
4093
4094 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4095
4096 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4097 new_adv |= ADVERTISE_1000XHALF;
4098 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4099 new_adv |= ADVERTISE_1000XFULL;
4100
4101 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4102 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4103 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4104 tg3_writephy(tp, MII_BMCR, bmcr);
4105
4106 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4107 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4108 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4109
4110 return err;
4111 }
4112 } else {
4113 u32 new_bmcr;
4114
4115 bmcr &= ~BMCR_SPEED1000;
4116 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4117
4118 if (tp->link_config.duplex == DUPLEX_FULL)
4119 new_bmcr |= BMCR_FULLDPLX;
4120
4121 if (new_bmcr != bmcr) {
4122 /* BMCR_SPEED1000 is a reserved bit that needs
4123 * to be set on write.
4124 */
4125 new_bmcr |= BMCR_SPEED1000;
4126
4127 /* Force a linkdown */
4128 if (netif_carrier_ok(tp->dev)) {
4129 u32 adv;
4130
4131 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4132 adv &= ~(ADVERTISE_1000XFULL |
4133 ADVERTISE_1000XHALF |
4134 ADVERTISE_SLCT);
4135 tg3_writephy(tp, MII_ADVERTISE, adv);
4136 tg3_writephy(tp, MII_BMCR, bmcr |
4137 BMCR_ANRESTART |
4138 BMCR_ANENABLE);
4139 udelay(10);
4140 netif_carrier_off(tp->dev);
4141 }
4142 tg3_writephy(tp, MII_BMCR, new_bmcr);
4143 bmcr = new_bmcr;
4144 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4145 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4146 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4147 ASIC_REV_5714) {
4148 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4149 bmsr |= BMSR_LSTATUS;
4150 else
4151 bmsr &= ~BMSR_LSTATUS;
4152 }
4153 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4154 }
4155 }
4156
4157 if (bmsr & BMSR_LSTATUS) {
4158 current_speed = SPEED_1000;
4159 current_link_up = 1;
4160 if (bmcr & BMCR_FULLDPLX)
4161 current_duplex = DUPLEX_FULL;
4162 else
4163 current_duplex = DUPLEX_HALF;
4164
4165 local_adv = 0;
4166 remote_adv = 0;
4167
4168 if (bmcr & BMCR_ANENABLE) {
4169 u32 common;
4170
4171 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4172 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4173 common = local_adv & remote_adv;
4174 if (common & (ADVERTISE_1000XHALF |
4175 ADVERTISE_1000XFULL)) {
4176 if (common & ADVERTISE_1000XFULL)
4177 current_duplex = DUPLEX_FULL;
4178 else
4179 current_duplex = DUPLEX_HALF;
4180 }
4181 else
4182 current_link_up = 0;
4183 }
4184 }
4185
4186 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4187 tg3_setup_flow_control(tp, local_adv, remote_adv);
4188
4189 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4190 if (tp->link_config.active_duplex == DUPLEX_HALF)
4191 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4192
4193 tw32_f(MAC_MODE, tp->mac_mode);
4194 udelay(40);
4195
4196 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4197
4198 tp->link_config.active_speed = current_speed;
4199 tp->link_config.active_duplex = current_duplex;
4200
4201 if (current_link_up != netif_carrier_ok(tp->dev)) {
4202 if (current_link_up)
4203 netif_carrier_on(tp->dev);
4204 else {
4205 netif_carrier_off(tp->dev);
4206 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4207 }
4208 tg3_link_report(tp);
4209 }
4210 return err;
4211 }
4212
4213 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4214 {
4215 if (tp->serdes_counter) {
4216 /* Give autoneg time to complete. */
4217 tp->serdes_counter--;
4218 return;
4219 }
4220 if (!netif_carrier_ok(tp->dev) &&
4221 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4222 u32 bmcr;
4223
4224 tg3_readphy(tp, MII_BMCR, &bmcr);
4225 if (bmcr & BMCR_ANENABLE) {
4226 u32 phy1, phy2;
4227
4228 /* Select shadow register 0x1f */
4229 tg3_writephy(tp, 0x1c, 0x7c00);
4230 tg3_readphy(tp, 0x1c, &phy1);
4231
4232 /* Select expansion interrupt status register */
4233 tg3_writephy(tp, 0x17, 0x0f01);
4234 tg3_readphy(tp, 0x15, &phy2);
4235 tg3_readphy(tp, 0x15, &phy2);
4236
4237 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4238 /* We have signal detect and not receiving
4239 * config code words, link is up by parallel
4240 * detection.
4241 */
4242
4243 bmcr &= ~BMCR_ANENABLE;
4244 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4245 tg3_writephy(tp, MII_BMCR, bmcr);
4246 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4247 }
4248 }
4249 }
4250 else if (netif_carrier_ok(tp->dev) &&
4251 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4252 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4253 u32 phy2;
4254
4255 /* Select expansion interrupt status register */
4256 tg3_writephy(tp, 0x17, 0x0f01);
4257 tg3_readphy(tp, 0x15, &phy2);
4258 if (phy2 & 0x20) {
4259 u32 bmcr;
4260
4261 /* Config code words received, turn on autoneg. */
4262 tg3_readphy(tp, MII_BMCR, &bmcr);
4263 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4264
4265 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4266
4267 }
4268 }
4269 }
4270
4271 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4272 {
4273 int err;
4274
4275 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4276 err = tg3_setup_fiber_phy(tp, force_reset);
4277 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4278 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4279 } else {
4280 err = tg3_setup_copper_phy(tp, force_reset);
4281 }
4282
4283 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4284 u32 val, scale;
4285
4286 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4287 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4288 scale = 65;
4289 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4290 scale = 6;
4291 else
4292 scale = 12;
4293
4294 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4295 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4296 tw32(GRC_MISC_CFG, val);
4297 }
4298
4299 if (tp->link_config.active_speed == SPEED_1000 &&
4300 tp->link_config.active_duplex == DUPLEX_HALF)
4301 tw32(MAC_TX_LENGTHS,
4302 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4303 (6 << TX_LENGTHS_IPG_SHIFT) |
4304 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4305 else
4306 tw32(MAC_TX_LENGTHS,
4307 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4308 (6 << TX_LENGTHS_IPG_SHIFT) |
4309 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4310
4311 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4312 if (netif_carrier_ok(tp->dev)) {
4313 tw32(HOSTCC_STAT_COAL_TICKS,
4314 tp->coal.stats_block_coalesce_usecs);
4315 } else {
4316 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4317 }
4318 }
4319
4320 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4321 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4322 if (!netif_carrier_ok(tp->dev))
4323 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4324 tp->pwrmgmt_thresh;
4325 else
4326 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4327 tw32(PCIE_PWR_MGMT_THRESH, val);
4328 }
4329
4330 return err;
4331 }
4332
4333 /* This is called whenever we suspect that the system chipset is re-
4334 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4335 * is bogus tx completions. We try to recover by setting the
4336 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4337 * in the workqueue.
4338 */
4339 static void tg3_tx_recover(struct tg3 *tp)
4340 {
4341 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4342 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4343
4344 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4345 "mapped I/O cycles to the network device, attempting to "
4346 "recover. Please report the problem to the driver maintainer "
4347 "and include system chipset information.\n", tp->dev->name);
4348
4349 spin_lock(&tp->lock);
4350 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4351 spin_unlock(&tp->lock);
4352 }
4353
4354 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4355 {
4356 smp_mb();
4357 return tnapi->tx_pending -
4358 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4359 }
4360
4361 /* Tigon3 never reports partial packet sends. So we do not
4362 * need special logic to handle SKBs that have not had all
4363 * of their frags sent yet, like SunGEM does.
4364 */
4365 static void tg3_tx(struct tg3_napi *tnapi)
4366 {
4367 struct tg3 *tp = tnapi->tp;
4368 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4369 u32 sw_idx = tnapi->tx_cons;
4370 struct netdev_queue *txq;
4371 int index = tnapi - tp->napi;
4372
4373 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4374 index--;
4375
4376 txq = netdev_get_tx_queue(tp->dev, index);
4377
4378 while (sw_idx != hw_idx) {
4379 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4380 struct sk_buff *skb = ri->skb;
4381 int i, tx_bug = 0;
4382
4383 if (unlikely(skb == NULL)) {
4384 tg3_tx_recover(tp);
4385 return;
4386 }
4387
4388 pci_unmap_single(tp->pdev,
4389 pci_unmap_addr(ri, mapping),
4390 skb_headlen(skb),
4391 PCI_DMA_TODEVICE);
4392
4393 ri->skb = NULL;
4394
4395 sw_idx = NEXT_TX(sw_idx);
4396
4397 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4398 ri = &tnapi->tx_buffers[sw_idx];
4399 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4400 tx_bug = 1;
4401
4402 pci_unmap_page(tp->pdev,
4403 pci_unmap_addr(ri, mapping),
4404 skb_shinfo(skb)->frags[i].size,
4405 PCI_DMA_TODEVICE);
4406 sw_idx = NEXT_TX(sw_idx);
4407 }
4408
4409 dev_kfree_skb(skb);
4410
4411 if (unlikely(tx_bug)) {
4412 tg3_tx_recover(tp);
4413 return;
4414 }
4415 }
4416
4417 tnapi->tx_cons = sw_idx;
4418
4419 /* Need to make the tx_cons update visible to tg3_start_xmit()
4420 * before checking for netif_queue_stopped(). Without the
4421 * memory barrier, there is a small possibility that tg3_start_xmit()
4422 * will miss it and cause the queue to be stopped forever.
4423 */
4424 smp_mb();
4425
4426 if (unlikely(netif_tx_queue_stopped(txq) &&
4427 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4428 __netif_tx_lock(txq, smp_processor_id());
4429 if (netif_tx_queue_stopped(txq) &&
4430 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4431 netif_tx_wake_queue(txq);
4432 __netif_tx_unlock(txq);
4433 }
4434 }
4435
4436 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4437 {
4438 if (!ri->skb)
4439 return;
4440
4441 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4442 map_sz, PCI_DMA_FROMDEVICE);
4443 dev_kfree_skb_any(ri->skb);
4444 ri->skb = NULL;
4445 }
4446
4447 /* Returns size of skb allocated or < 0 on error.
4448 *
4449 * We only need to fill in the address because the other members
4450 * of the RX descriptor are invariant, see tg3_init_rings.
4451 *
4452 * Note the purposeful assymetry of cpu vs. chip accesses. For
4453 * posting buffers we only dirty the first cache line of the RX
4454 * descriptor (containing the address). Whereas for the RX status
4455 * buffers the cpu only reads the last cacheline of the RX descriptor
4456 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4457 */
4458 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4459 u32 opaque_key, u32 dest_idx_unmasked)
4460 {
4461 struct tg3_rx_buffer_desc *desc;
4462 struct ring_info *map, *src_map;
4463 struct sk_buff *skb;
4464 dma_addr_t mapping;
4465 int skb_size, dest_idx;
4466
4467 src_map = NULL;
4468 switch (opaque_key) {
4469 case RXD_OPAQUE_RING_STD:
4470 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4471 desc = &tpr->rx_std[dest_idx];
4472 map = &tpr->rx_std_buffers[dest_idx];
4473 skb_size = tp->rx_pkt_map_sz;
4474 break;
4475
4476 case RXD_OPAQUE_RING_JUMBO:
4477 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4478 desc = &tpr->rx_jmb[dest_idx].std;
4479 map = &tpr->rx_jmb_buffers[dest_idx];
4480 skb_size = TG3_RX_JMB_MAP_SZ;
4481 break;
4482
4483 default:
4484 return -EINVAL;
4485 }
4486
4487 /* Do not overwrite any of the map or rp information
4488 * until we are sure we can commit to a new buffer.
4489 *
4490 * Callers depend upon this behavior and assume that
4491 * we leave everything unchanged if we fail.
4492 */
4493 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4494 if (skb == NULL)
4495 return -ENOMEM;
4496
4497 skb_reserve(skb, tp->rx_offset);
4498
4499 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4500 PCI_DMA_FROMDEVICE);
4501 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4502 dev_kfree_skb(skb);
4503 return -EIO;
4504 }
4505
4506 map->skb = skb;
4507 pci_unmap_addr_set(map, mapping, mapping);
4508
4509 desc->addr_hi = ((u64)mapping >> 32);
4510 desc->addr_lo = ((u64)mapping & 0xffffffff);
4511
4512 return skb_size;
4513 }
4514
4515 /* We only need to move over in the address because the other
4516 * members of the RX descriptor are invariant. See notes above
4517 * tg3_alloc_rx_skb for full details.
4518 */
4519 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4520 struct tg3_rx_prodring_set *dpr,
4521 u32 opaque_key, int src_idx,
4522 u32 dest_idx_unmasked)
4523 {
4524 struct tg3 *tp = tnapi->tp;
4525 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4526 struct ring_info *src_map, *dest_map;
4527 int dest_idx;
4528 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4529
4530 switch (opaque_key) {
4531 case RXD_OPAQUE_RING_STD:
4532 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4533 dest_desc = &dpr->rx_std[dest_idx];
4534 dest_map = &dpr->rx_std_buffers[dest_idx];
4535 src_desc = &spr->rx_std[src_idx];
4536 src_map = &spr->rx_std_buffers[src_idx];
4537 break;
4538
4539 case RXD_OPAQUE_RING_JUMBO:
4540 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4541 dest_desc = &dpr->rx_jmb[dest_idx].std;
4542 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4543 src_desc = &spr->rx_jmb[src_idx].std;
4544 src_map = &spr->rx_jmb_buffers[src_idx];
4545 break;
4546
4547 default:
4548 return;
4549 }
4550
4551 dest_map->skb = src_map->skb;
4552 pci_unmap_addr_set(dest_map, mapping,
4553 pci_unmap_addr(src_map, mapping));
4554 dest_desc->addr_hi = src_desc->addr_hi;
4555 dest_desc->addr_lo = src_desc->addr_lo;
4556
4557 /* Ensure that the update to the skb happens after the physical
4558 * addresses have been transferred to the new BD location.
4559 */
4560 smp_wmb();
4561
4562 src_map->skb = NULL;
4563 }
4564
4565 /* The RX ring scheme is composed of multiple rings which post fresh
4566 * buffers to the chip, and one special ring the chip uses to report
4567 * status back to the host.
4568 *
4569 * The special ring reports the status of received packets to the
4570 * host. The chip does not write into the original descriptor the
4571 * RX buffer was obtained from. The chip simply takes the original
4572 * descriptor as provided by the host, updates the status and length
4573 * field, then writes this into the next status ring entry.
4574 *
4575 * Each ring the host uses to post buffers to the chip is described
4576 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4577 * it is first placed into the on-chip ram. When the packet's length
4578 * is known, it walks down the TG3_BDINFO entries to select the ring.
4579 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4580 * which is within the range of the new packet's length is chosen.
4581 *
4582 * The "separate ring for rx status" scheme may sound queer, but it makes
4583 * sense from a cache coherency perspective. If only the host writes
4584 * to the buffer post rings, and only the chip writes to the rx status
4585 * rings, then cache lines never move beyond shared-modified state.
4586 * If both the host and chip were to write into the same ring, cache line
4587 * eviction could occur since both entities want it in an exclusive state.
4588 */
4589 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4590 {
4591 struct tg3 *tp = tnapi->tp;
4592 u32 work_mask, rx_std_posted = 0;
4593 u32 std_prod_idx, jmb_prod_idx;
4594 u32 sw_idx = tnapi->rx_rcb_ptr;
4595 u16 hw_idx;
4596 int received;
4597 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4598
4599 hw_idx = *(tnapi->rx_rcb_prod_idx);
4600 /*
4601 * We need to order the read of hw_idx and the read of
4602 * the opaque cookie.
4603 */
4604 rmb();
4605 work_mask = 0;
4606 received = 0;
4607 std_prod_idx = tpr->rx_std_prod_idx;
4608 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4609 while (sw_idx != hw_idx && budget > 0) {
4610 struct ring_info *ri;
4611 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4612 unsigned int len;
4613 struct sk_buff *skb;
4614 dma_addr_t dma_addr;
4615 u32 opaque_key, desc_idx, *post_ptr;
4616
4617 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4618 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4619 if (opaque_key == RXD_OPAQUE_RING_STD) {
4620 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4621 dma_addr = pci_unmap_addr(ri, mapping);
4622 skb = ri->skb;
4623 post_ptr = &std_prod_idx;
4624 rx_std_posted++;
4625 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4626 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4627 dma_addr = pci_unmap_addr(ri, mapping);
4628 skb = ri->skb;
4629 post_ptr = &jmb_prod_idx;
4630 } else
4631 goto next_pkt_nopost;
4632
4633 work_mask |= opaque_key;
4634
4635 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4636 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4637 drop_it:
4638 tg3_recycle_rx(tnapi, tpr, opaque_key,
4639 desc_idx, *post_ptr);
4640 drop_it_no_recycle:
4641 /* Other statistics kept track of by card. */
4642 tp->net_stats.rx_dropped++;
4643 goto next_pkt;
4644 }
4645
4646 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4647 ETH_FCS_LEN;
4648
4649 if (len > RX_COPY_THRESHOLD &&
4650 tp->rx_offset == NET_IP_ALIGN) {
4651 /* rx_offset will likely not equal NET_IP_ALIGN
4652 * if this is a 5701 card running in PCI-X mode
4653 * [see tg3_get_invariants()]
4654 */
4655 int skb_size;
4656
4657 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4658 *post_ptr);
4659 if (skb_size < 0)
4660 goto drop_it;
4661
4662 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4663 PCI_DMA_FROMDEVICE);
4664
4665 /* Ensure that the update to the skb happens
4666 * after the usage of the old DMA mapping.
4667 */
4668 smp_wmb();
4669
4670 ri->skb = NULL;
4671
4672 skb_put(skb, len);
4673 } else {
4674 struct sk_buff *copy_skb;
4675
4676 tg3_recycle_rx(tnapi, tpr, opaque_key,
4677 desc_idx, *post_ptr);
4678
4679 copy_skb = netdev_alloc_skb(tp->dev,
4680 len + TG3_RAW_IP_ALIGN);
4681 if (copy_skb == NULL)
4682 goto drop_it_no_recycle;
4683
4684 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4685 skb_put(copy_skb, len);
4686 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4687 skb_copy_from_linear_data(skb, copy_skb->data, len);
4688 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4689
4690 /* We'll reuse the original ring buffer. */
4691 skb = copy_skb;
4692 }
4693
4694 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4695 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4696 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4697 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4698 skb->ip_summed = CHECKSUM_UNNECESSARY;
4699 else
4700 skb->ip_summed = CHECKSUM_NONE;
4701
4702 skb->protocol = eth_type_trans(skb, tp->dev);
4703
4704 if (len > (tp->dev->mtu + ETH_HLEN) &&
4705 skb->protocol != htons(ETH_P_8021Q)) {
4706 dev_kfree_skb(skb);
4707 goto next_pkt;
4708 }
4709
4710 #if TG3_VLAN_TAG_USED
4711 if (tp->vlgrp != NULL &&
4712 desc->type_flags & RXD_FLAG_VLAN) {
4713 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4714 desc->err_vlan & RXD_VLAN_MASK, skb);
4715 } else
4716 #endif
4717 napi_gro_receive(&tnapi->napi, skb);
4718
4719 received++;
4720 budget--;
4721
4722 next_pkt:
4723 (*post_ptr)++;
4724
4725 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4726 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4727 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4728 tpr->rx_std_prod_idx);
4729 work_mask &= ~RXD_OPAQUE_RING_STD;
4730 rx_std_posted = 0;
4731 }
4732 next_pkt_nopost:
4733 sw_idx++;
4734 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4735
4736 /* Refresh hw_idx to see if there is new work */
4737 if (sw_idx == hw_idx) {
4738 hw_idx = *(tnapi->rx_rcb_prod_idx);
4739 rmb();
4740 }
4741 }
4742
4743 /* ACK the status ring. */
4744 tnapi->rx_rcb_ptr = sw_idx;
4745 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4746
4747 /* Refill RX ring(s). */
4748 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4749 if (work_mask & RXD_OPAQUE_RING_STD) {
4750 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4751 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4752 tpr->rx_std_prod_idx);
4753 }
4754 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4755 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4756 TG3_RX_JUMBO_RING_SIZE;
4757 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4758 tpr->rx_jmb_prod_idx);
4759 }
4760 mmiowb();
4761 } else if (work_mask) {
4762 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4763 * updated before the producer indices can be updated.
4764 */
4765 smp_wmb();
4766
4767 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4768 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4769
4770 if (tnapi != &tp->napi[1])
4771 napi_schedule(&tp->napi[1].napi);
4772 }
4773
4774 return received;
4775 }
4776
4777 static void tg3_poll_link(struct tg3 *tp)
4778 {
4779 /* handle link change and other phy events */
4780 if (!(tp->tg3_flags &
4781 (TG3_FLAG_USE_LINKCHG_REG |
4782 TG3_FLAG_POLL_SERDES))) {
4783 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4784
4785 if (sblk->status & SD_STATUS_LINK_CHG) {
4786 sblk->status = SD_STATUS_UPDATED |
4787 (sblk->status & ~SD_STATUS_LINK_CHG);
4788 spin_lock(&tp->lock);
4789 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4790 tw32_f(MAC_STATUS,
4791 (MAC_STATUS_SYNC_CHANGED |
4792 MAC_STATUS_CFG_CHANGED |
4793 MAC_STATUS_MI_COMPLETION |
4794 MAC_STATUS_LNKSTATE_CHANGED));
4795 udelay(40);
4796 } else
4797 tg3_setup_phy(tp, 0);
4798 spin_unlock(&tp->lock);
4799 }
4800 }
4801 }
4802
4803 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4804 struct tg3_rx_prodring_set *dpr,
4805 struct tg3_rx_prodring_set *spr)
4806 {
4807 u32 si, di, cpycnt, src_prod_idx;
4808 int i, err = 0;
4809
4810 while (1) {
4811 src_prod_idx = spr->rx_std_prod_idx;
4812
4813 /* Make sure updates to the rx_std_buffers[] entries and the
4814 * standard producer index are seen in the correct order.
4815 */
4816 smp_rmb();
4817
4818 if (spr->rx_std_cons_idx == src_prod_idx)
4819 break;
4820
4821 if (spr->rx_std_cons_idx < src_prod_idx)
4822 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4823 else
4824 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4825
4826 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4827
4828 si = spr->rx_std_cons_idx;
4829 di = dpr->rx_std_prod_idx;
4830
4831 for (i = di; i < di + cpycnt; i++) {
4832 if (dpr->rx_std_buffers[i].skb) {
4833 cpycnt = i - di;
4834 err = -ENOSPC;
4835 break;
4836 }
4837 }
4838
4839 if (!cpycnt)
4840 break;
4841
4842 /* Ensure that updates to the rx_std_buffers ring and the
4843 * shadowed hardware producer ring from tg3_recycle_skb() are
4844 * ordered correctly WRT the skb check above.
4845 */
4846 smp_rmb();
4847
4848 memcpy(&dpr->rx_std_buffers[di],
4849 &spr->rx_std_buffers[si],
4850 cpycnt * sizeof(struct ring_info));
4851
4852 for (i = 0; i < cpycnt; i++, di++, si++) {
4853 struct tg3_rx_buffer_desc *sbd, *dbd;
4854 sbd = &spr->rx_std[si];
4855 dbd = &dpr->rx_std[di];
4856 dbd->addr_hi = sbd->addr_hi;
4857 dbd->addr_lo = sbd->addr_lo;
4858 }
4859
4860 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4861 TG3_RX_RING_SIZE;
4862 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4863 TG3_RX_RING_SIZE;
4864 }
4865
4866 while (1) {
4867 src_prod_idx = spr->rx_jmb_prod_idx;
4868
4869 /* Make sure updates to the rx_jmb_buffers[] entries and
4870 * the jumbo producer index are seen in the correct order.
4871 */
4872 smp_rmb();
4873
4874 if (spr->rx_jmb_cons_idx == src_prod_idx)
4875 break;
4876
4877 if (spr->rx_jmb_cons_idx < src_prod_idx)
4878 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4879 else
4880 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4881
4882 cpycnt = min(cpycnt,
4883 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4884
4885 si = spr->rx_jmb_cons_idx;
4886 di = dpr->rx_jmb_prod_idx;
4887
4888 for (i = di; i < di + cpycnt; i++) {
4889 if (dpr->rx_jmb_buffers[i].skb) {
4890 cpycnt = i - di;
4891 err = -ENOSPC;
4892 break;
4893 }
4894 }
4895
4896 if (!cpycnt)
4897 break;
4898
4899 /* Ensure that updates to the rx_jmb_buffers ring and the
4900 * shadowed hardware producer ring from tg3_recycle_skb() are
4901 * ordered correctly WRT the skb check above.
4902 */
4903 smp_rmb();
4904
4905 memcpy(&dpr->rx_jmb_buffers[di],
4906 &spr->rx_jmb_buffers[si],
4907 cpycnt * sizeof(struct ring_info));
4908
4909 for (i = 0; i < cpycnt; i++, di++, si++) {
4910 struct tg3_rx_buffer_desc *sbd, *dbd;
4911 sbd = &spr->rx_jmb[si].std;
4912 dbd = &dpr->rx_jmb[di].std;
4913 dbd->addr_hi = sbd->addr_hi;
4914 dbd->addr_lo = sbd->addr_lo;
4915 }
4916
4917 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4918 TG3_RX_JUMBO_RING_SIZE;
4919 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4920 TG3_RX_JUMBO_RING_SIZE;
4921 }
4922
4923 return err;
4924 }
4925
4926 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4927 {
4928 struct tg3 *tp = tnapi->tp;
4929
4930 /* run TX completion thread */
4931 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4932 tg3_tx(tnapi);
4933 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4934 return work_done;
4935 }
4936
4937 /* run RX thread, within the bounds set by NAPI.
4938 * All RX "locking" is done by ensuring outside
4939 * code synchronizes with tg3->napi.poll()
4940 */
4941 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4942 work_done += tg3_rx(tnapi, budget - work_done);
4943
4944 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4945 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4946 int i, err = 0;
4947 u32 std_prod_idx = dpr->rx_std_prod_idx;
4948 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4949
4950 for (i = 1; i < tp->irq_cnt; i++)
4951 err |= tg3_rx_prodring_xfer(tp, dpr,
4952 tp->napi[i].prodring);
4953
4954 wmb();
4955
4956 if (std_prod_idx != dpr->rx_std_prod_idx)
4957 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4958 dpr->rx_std_prod_idx);
4959
4960 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4961 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4962 dpr->rx_jmb_prod_idx);
4963
4964 mmiowb();
4965
4966 if (err)
4967 tw32_f(HOSTCC_MODE, tp->coal_now);
4968 }
4969
4970 return work_done;
4971 }
4972
4973 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4974 {
4975 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4976 struct tg3 *tp = tnapi->tp;
4977 int work_done = 0;
4978 struct tg3_hw_status *sblk = tnapi->hw_status;
4979
4980 while (1) {
4981 work_done = tg3_poll_work(tnapi, work_done, budget);
4982
4983 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4984 goto tx_recovery;
4985
4986 if (unlikely(work_done >= budget))
4987 break;
4988
4989 /* tp->last_tag is used in tg3_restart_ints() below
4990 * to tell the hw how much work has been processed,
4991 * so we must read it before checking for more work.
4992 */
4993 tnapi->last_tag = sblk->status_tag;
4994 tnapi->last_irq_tag = tnapi->last_tag;
4995 rmb();
4996
4997 /* check for RX/TX work to do */
4998 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4999 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
5000 napi_complete(napi);
5001 /* Reenable interrupts. */
5002 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5003 mmiowb();
5004 break;
5005 }
5006 }
5007
5008 return work_done;
5009
5010 tx_recovery:
5011 /* work_done is guaranteed to be less than budget. */
5012 napi_complete(napi);
5013 schedule_work(&tp->reset_task);
5014 return work_done;
5015 }
5016
5017 static int tg3_poll(struct napi_struct *napi, int budget)
5018 {
5019 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5020 struct tg3 *tp = tnapi->tp;
5021 int work_done = 0;
5022 struct tg3_hw_status *sblk = tnapi->hw_status;
5023
5024 while (1) {
5025 tg3_poll_link(tp);
5026
5027 work_done = tg3_poll_work(tnapi, work_done, budget);
5028
5029 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5030 goto tx_recovery;
5031
5032 if (unlikely(work_done >= budget))
5033 break;
5034
5035 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5036 /* tp->last_tag is used in tg3_int_reenable() below
5037 * to tell the hw how much work has been processed,
5038 * so we must read it before checking for more work.
5039 */
5040 tnapi->last_tag = sblk->status_tag;
5041 tnapi->last_irq_tag = tnapi->last_tag;
5042 rmb();
5043 } else
5044 sblk->status &= ~SD_STATUS_UPDATED;
5045
5046 if (likely(!tg3_has_work(tnapi))) {
5047 napi_complete(napi);
5048 tg3_int_reenable(tnapi);
5049 break;
5050 }
5051 }
5052
5053 return work_done;
5054
5055 tx_recovery:
5056 /* work_done is guaranteed to be less than budget. */
5057 napi_complete(napi);
5058 schedule_work(&tp->reset_task);
5059 return work_done;
5060 }
5061
5062 static void tg3_irq_quiesce(struct tg3 *tp)
5063 {
5064 int i;
5065
5066 BUG_ON(tp->irq_sync);
5067
5068 tp->irq_sync = 1;
5069 smp_mb();
5070
5071 for (i = 0; i < tp->irq_cnt; i++)
5072 synchronize_irq(tp->napi[i].irq_vec);
5073 }
5074
5075 static inline int tg3_irq_sync(struct tg3 *tp)
5076 {
5077 return tp->irq_sync;
5078 }
5079
5080 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5081 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5082 * with as well. Most of the time, this is not necessary except when
5083 * shutting down the device.
5084 */
5085 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5086 {
5087 spin_lock_bh(&tp->lock);
5088 if (irq_sync)
5089 tg3_irq_quiesce(tp);
5090 }
5091
5092 static inline void tg3_full_unlock(struct tg3 *tp)
5093 {
5094 spin_unlock_bh(&tp->lock);
5095 }
5096
5097 /* One-shot MSI handler - Chip automatically disables interrupt
5098 * after sending MSI so driver doesn't have to do it.
5099 */
5100 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5101 {
5102 struct tg3_napi *tnapi = dev_id;
5103 struct tg3 *tp = tnapi->tp;
5104
5105 prefetch(tnapi->hw_status);
5106 if (tnapi->rx_rcb)
5107 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5108
5109 if (likely(!tg3_irq_sync(tp)))
5110 napi_schedule(&tnapi->napi);
5111
5112 return IRQ_HANDLED;
5113 }
5114
5115 /* MSI ISR - No need to check for interrupt sharing and no need to
5116 * flush status block and interrupt mailbox. PCI ordering rules
5117 * guarantee that MSI will arrive after the status block.
5118 */
5119 static irqreturn_t tg3_msi(int irq, void *dev_id)
5120 {
5121 struct tg3_napi *tnapi = dev_id;
5122 struct tg3 *tp = tnapi->tp;
5123
5124 prefetch(tnapi->hw_status);
5125 if (tnapi->rx_rcb)
5126 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5127 /*
5128 * Writing any value to intr-mbox-0 clears PCI INTA# and
5129 * chip-internal interrupt pending events.
5130 * Writing non-zero to intr-mbox-0 additional tells the
5131 * NIC to stop sending us irqs, engaging "in-intr-handler"
5132 * event coalescing.
5133 */
5134 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5135 if (likely(!tg3_irq_sync(tp)))
5136 napi_schedule(&tnapi->napi);
5137
5138 return IRQ_RETVAL(1);
5139 }
5140
5141 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5142 {
5143 struct tg3_napi *tnapi = dev_id;
5144 struct tg3 *tp = tnapi->tp;
5145 struct tg3_hw_status *sblk = tnapi->hw_status;
5146 unsigned int handled = 1;
5147
5148 /* In INTx mode, it is possible for the interrupt to arrive at
5149 * the CPU before the status block posted prior to the interrupt.
5150 * Reading the PCI State register will confirm whether the
5151 * interrupt is ours and will flush the status block.
5152 */
5153 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5154 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5155 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5156 handled = 0;
5157 goto out;
5158 }
5159 }
5160
5161 /*
5162 * Writing any value to intr-mbox-0 clears PCI INTA# and
5163 * chip-internal interrupt pending events.
5164 * Writing non-zero to intr-mbox-0 additional tells the
5165 * NIC to stop sending us irqs, engaging "in-intr-handler"
5166 * event coalescing.
5167 *
5168 * Flush the mailbox to de-assert the IRQ immediately to prevent
5169 * spurious interrupts. The flush impacts performance but
5170 * excessive spurious interrupts can be worse in some cases.
5171 */
5172 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5173 if (tg3_irq_sync(tp))
5174 goto out;
5175 sblk->status &= ~SD_STATUS_UPDATED;
5176 if (likely(tg3_has_work(tnapi))) {
5177 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5178 napi_schedule(&tnapi->napi);
5179 } else {
5180 /* No work, shared interrupt perhaps? re-enable
5181 * interrupts, and flush that PCI write
5182 */
5183 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5184 0x00000000);
5185 }
5186 out:
5187 return IRQ_RETVAL(handled);
5188 }
5189
5190 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5191 {
5192 struct tg3_napi *tnapi = dev_id;
5193 struct tg3 *tp = tnapi->tp;
5194 struct tg3_hw_status *sblk = tnapi->hw_status;
5195 unsigned int handled = 1;
5196
5197 /* In INTx mode, it is possible for the interrupt to arrive at
5198 * the CPU before the status block posted prior to the interrupt.
5199 * Reading the PCI State register will confirm whether the
5200 * interrupt is ours and will flush the status block.
5201 */
5202 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5203 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5204 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5205 handled = 0;
5206 goto out;
5207 }
5208 }
5209
5210 /*
5211 * writing any value to intr-mbox-0 clears PCI INTA# and
5212 * chip-internal interrupt pending events.
5213 * writing non-zero to intr-mbox-0 additional tells the
5214 * NIC to stop sending us irqs, engaging "in-intr-handler"
5215 * event coalescing.
5216 *
5217 * Flush the mailbox to de-assert the IRQ immediately to prevent
5218 * spurious interrupts. The flush impacts performance but
5219 * excessive spurious interrupts can be worse in some cases.
5220 */
5221 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5222
5223 /*
5224 * In a shared interrupt configuration, sometimes other devices'
5225 * interrupts will scream. We record the current status tag here
5226 * so that the above check can report that the screaming interrupts
5227 * are unhandled. Eventually they will be silenced.
5228 */
5229 tnapi->last_irq_tag = sblk->status_tag;
5230
5231 if (tg3_irq_sync(tp))
5232 goto out;
5233
5234 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5235
5236 napi_schedule(&tnapi->napi);
5237
5238 out:
5239 return IRQ_RETVAL(handled);
5240 }
5241
5242 /* ISR for interrupt test */
5243 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5244 {
5245 struct tg3_napi *tnapi = dev_id;
5246 struct tg3 *tp = tnapi->tp;
5247 struct tg3_hw_status *sblk = tnapi->hw_status;
5248
5249 if ((sblk->status & SD_STATUS_UPDATED) ||
5250 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5251 tg3_disable_ints(tp);
5252 return IRQ_RETVAL(1);
5253 }
5254 return IRQ_RETVAL(0);
5255 }
5256
5257 static int tg3_init_hw(struct tg3 *, int);
5258 static int tg3_halt(struct tg3 *, int, int);
5259
5260 /* Restart hardware after configuration changes, self-test, etc.
5261 * Invoked with tp->lock held.
5262 */
5263 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5264 __releases(tp->lock)
5265 __acquires(tp->lock)
5266 {
5267 int err;
5268
5269 err = tg3_init_hw(tp, reset_phy);
5270 if (err) {
5271 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5272 "aborting.\n", tp->dev->name);
5273 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5274 tg3_full_unlock(tp);
5275 del_timer_sync(&tp->timer);
5276 tp->irq_sync = 0;
5277 tg3_napi_enable(tp);
5278 dev_close(tp->dev);
5279 tg3_full_lock(tp, 0);
5280 }
5281 return err;
5282 }
5283
5284 #ifdef CONFIG_NET_POLL_CONTROLLER
5285 static void tg3_poll_controller(struct net_device *dev)
5286 {
5287 int i;
5288 struct tg3 *tp = netdev_priv(dev);
5289
5290 for (i = 0; i < tp->irq_cnt; i++)
5291 tg3_interrupt(tp->napi[i].irq_vec, dev);
5292 }
5293 #endif
5294
5295 static void tg3_reset_task(struct work_struct *work)
5296 {
5297 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5298 int err;
5299 unsigned int restart_timer;
5300
5301 tg3_full_lock(tp, 0);
5302
5303 if (!netif_running(tp->dev)) {
5304 tg3_full_unlock(tp);
5305 return;
5306 }
5307
5308 tg3_full_unlock(tp);
5309
5310 tg3_phy_stop(tp);
5311
5312 tg3_netif_stop(tp);
5313
5314 tg3_full_lock(tp, 1);
5315
5316 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5317 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5318
5319 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5320 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5321 tp->write32_rx_mbox = tg3_write_flush_reg32;
5322 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5323 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5324 }
5325
5326 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5327 err = tg3_init_hw(tp, 1);
5328 if (err)
5329 goto out;
5330
5331 tg3_netif_start(tp);
5332
5333 if (restart_timer)
5334 mod_timer(&tp->timer, jiffies + 1);
5335
5336 out:
5337 tg3_full_unlock(tp);
5338
5339 if (!err)
5340 tg3_phy_start(tp);
5341 }
5342
5343 static void tg3_dump_short_state(struct tg3 *tp)
5344 {
5345 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5346 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5347 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5348 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5349 }
5350
5351 static void tg3_tx_timeout(struct net_device *dev)
5352 {
5353 struct tg3 *tp = netdev_priv(dev);
5354
5355 if (netif_msg_tx_err(tp)) {
5356 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5357 dev->name);
5358 tg3_dump_short_state(tp);
5359 }
5360
5361 schedule_work(&tp->reset_task);
5362 }
5363
5364 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5365 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5366 {
5367 u32 base = (u32) mapping & 0xffffffff;
5368
5369 return ((base > 0xffffdcc0) &&
5370 (base + len + 8 < base));
5371 }
5372
5373 /* Test for DMA addresses > 40-bit */
5374 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5375 int len)
5376 {
5377 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5378 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5379 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5380 return 0;
5381 #else
5382 return 0;
5383 #endif
5384 }
5385
5386 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5387
5388 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5389 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5390 struct sk_buff *skb, u32 last_plus_one,
5391 u32 *start, u32 base_flags, u32 mss)
5392 {
5393 struct tg3 *tp = tnapi->tp;
5394 struct sk_buff *new_skb;
5395 dma_addr_t new_addr = 0;
5396 u32 entry = *start;
5397 int i, ret = 0;
5398
5399 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5400 new_skb = skb_copy(skb, GFP_ATOMIC);
5401 else {
5402 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5403
5404 new_skb = skb_copy_expand(skb,
5405 skb_headroom(skb) + more_headroom,
5406 skb_tailroom(skb), GFP_ATOMIC);
5407 }
5408
5409 if (!new_skb) {
5410 ret = -1;
5411 } else {
5412 /* New SKB is guaranteed to be linear. */
5413 entry = *start;
5414 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5415 PCI_DMA_TODEVICE);
5416 /* Make sure the mapping succeeded */
5417 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5418 ret = -1;
5419 dev_kfree_skb(new_skb);
5420 new_skb = NULL;
5421
5422 /* Make sure new skb does not cross any 4G boundaries.
5423 * Drop the packet if it does.
5424 */
5425 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5426 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5427 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5428 PCI_DMA_TODEVICE);
5429 ret = -1;
5430 dev_kfree_skb(new_skb);
5431 new_skb = NULL;
5432 } else {
5433 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5434 base_flags, 1 | (mss << 1));
5435 *start = NEXT_TX(entry);
5436 }
5437 }
5438
5439 /* Now clean up the sw ring entries. */
5440 i = 0;
5441 while (entry != last_plus_one) {
5442 int len;
5443
5444 if (i == 0)
5445 len = skb_headlen(skb);
5446 else
5447 len = skb_shinfo(skb)->frags[i-1].size;
5448
5449 pci_unmap_single(tp->pdev,
5450 pci_unmap_addr(&tnapi->tx_buffers[entry],
5451 mapping),
5452 len, PCI_DMA_TODEVICE);
5453 if (i == 0) {
5454 tnapi->tx_buffers[entry].skb = new_skb;
5455 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5456 new_addr);
5457 } else {
5458 tnapi->tx_buffers[entry].skb = NULL;
5459 }
5460 entry = NEXT_TX(entry);
5461 i++;
5462 }
5463
5464 dev_kfree_skb(skb);
5465
5466 return ret;
5467 }
5468
5469 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5470 dma_addr_t mapping, int len, u32 flags,
5471 u32 mss_and_is_end)
5472 {
5473 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5474 int is_end = (mss_and_is_end & 0x1);
5475 u32 mss = (mss_and_is_end >> 1);
5476 u32 vlan_tag = 0;
5477
5478 if (is_end)
5479 flags |= TXD_FLAG_END;
5480 if (flags & TXD_FLAG_VLAN) {
5481 vlan_tag = flags >> 16;
5482 flags &= 0xffff;
5483 }
5484 vlan_tag |= (mss << TXD_MSS_SHIFT);
5485
5486 txd->addr_hi = ((u64) mapping >> 32);
5487 txd->addr_lo = ((u64) mapping & 0xffffffff);
5488 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5489 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5490 }
5491
5492 /* hard_start_xmit for devices that don't have any bugs and
5493 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5494 */
5495 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5496 struct net_device *dev)
5497 {
5498 struct tg3 *tp = netdev_priv(dev);
5499 u32 len, entry, base_flags, mss;
5500 dma_addr_t mapping;
5501 struct tg3_napi *tnapi;
5502 struct netdev_queue *txq;
5503 unsigned int i, last;
5504
5505
5506 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5507 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5508 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5509 tnapi++;
5510
5511 /* We are running in BH disabled context with netif_tx_lock
5512 * and TX reclaim runs via tp->napi.poll inside of a software
5513 * interrupt. Furthermore, IRQ processing runs lockless so we have
5514 * no IRQ context deadlocks to worry about either. Rejoice!
5515 */
5516 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5517 if (!netif_tx_queue_stopped(txq)) {
5518 netif_tx_stop_queue(txq);
5519
5520 /* This is a hard error, log it. */
5521 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5522 "queue awake!\n", dev->name);
5523 }
5524 return NETDEV_TX_BUSY;
5525 }
5526
5527 entry = tnapi->tx_prod;
5528 base_flags = 0;
5529 mss = 0;
5530 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5531 int tcp_opt_len, ip_tcp_len;
5532 u32 hdrlen;
5533
5534 if (skb_header_cloned(skb) &&
5535 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5536 dev_kfree_skb(skb);
5537 goto out_unlock;
5538 }
5539
5540 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5541 hdrlen = skb_headlen(skb) - ETH_HLEN;
5542 else {
5543 struct iphdr *iph = ip_hdr(skb);
5544
5545 tcp_opt_len = tcp_optlen(skb);
5546 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5547
5548 iph->check = 0;
5549 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5550 hdrlen = ip_tcp_len + tcp_opt_len;
5551 }
5552
5553 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5554 mss |= (hdrlen & 0xc) << 12;
5555 if (hdrlen & 0x10)
5556 base_flags |= 0x00000010;
5557 base_flags |= (hdrlen & 0x3e0) << 5;
5558 } else
5559 mss |= hdrlen << 9;
5560
5561 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5562 TXD_FLAG_CPU_POST_DMA);
5563
5564 tcp_hdr(skb)->check = 0;
5565
5566 }
5567 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5568 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5569 #if TG3_VLAN_TAG_USED
5570 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5571 base_flags |= (TXD_FLAG_VLAN |
5572 (vlan_tx_tag_get(skb) << 16));
5573 #endif
5574
5575 len = skb_headlen(skb);
5576
5577 /* Queue skb data, a.k.a. the main skb fragment. */
5578 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5579 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5580 dev_kfree_skb(skb);
5581 goto out_unlock;
5582 }
5583
5584 tnapi->tx_buffers[entry].skb = skb;
5585 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5586
5587 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5588 !mss && skb->len > ETH_DATA_LEN)
5589 base_flags |= TXD_FLAG_JMB_PKT;
5590
5591 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5592 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5593
5594 entry = NEXT_TX(entry);
5595
5596 /* Now loop through additional data fragments, and queue them. */
5597 if (skb_shinfo(skb)->nr_frags > 0) {
5598 last = skb_shinfo(skb)->nr_frags - 1;
5599 for (i = 0; i <= last; i++) {
5600 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5601
5602 len = frag->size;
5603 mapping = pci_map_page(tp->pdev,
5604 frag->page,
5605 frag->page_offset,
5606 len, PCI_DMA_TODEVICE);
5607 if (pci_dma_mapping_error(tp->pdev, mapping))
5608 goto dma_error;
5609
5610 tnapi->tx_buffers[entry].skb = NULL;
5611 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5612 mapping);
5613
5614 tg3_set_txd(tnapi, entry, mapping, len,
5615 base_flags, (i == last) | (mss << 1));
5616
5617 entry = NEXT_TX(entry);
5618 }
5619 }
5620
5621 /* Packets are ready, update Tx producer idx local and on card. */
5622 tw32_tx_mbox(tnapi->prodmbox, entry);
5623
5624 tnapi->tx_prod = entry;
5625 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5626 netif_tx_stop_queue(txq);
5627 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5628 netif_tx_wake_queue(txq);
5629 }
5630
5631 out_unlock:
5632 mmiowb();
5633
5634 return NETDEV_TX_OK;
5635
5636 dma_error:
5637 last = i;
5638 entry = tnapi->tx_prod;
5639 tnapi->tx_buffers[entry].skb = NULL;
5640 pci_unmap_single(tp->pdev,
5641 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5642 skb_headlen(skb),
5643 PCI_DMA_TODEVICE);
5644 for (i = 0; i <= last; i++) {
5645 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5646 entry = NEXT_TX(entry);
5647
5648 pci_unmap_page(tp->pdev,
5649 pci_unmap_addr(&tnapi->tx_buffers[entry],
5650 mapping),
5651 frag->size, PCI_DMA_TODEVICE);
5652 }
5653
5654 dev_kfree_skb(skb);
5655 return NETDEV_TX_OK;
5656 }
5657
5658 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5659 struct net_device *);
5660
5661 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5662 * TSO header is greater than 80 bytes.
5663 */
5664 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5665 {
5666 struct sk_buff *segs, *nskb;
5667 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5668
5669 /* Estimate the number of fragments in the worst case */
5670 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5671 netif_stop_queue(tp->dev);
5672 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5673 return NETDEV_TX_BUSY;
5674
5675 netif_wake_queue(tp->dev);
5676 }
5677
5678 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5679 if (IS_ERR(segs))
5680 goto tg3_tso_bug_end;
5681
5682 do {
5683 nskb = segs;
5684 segs = segs->next;
5685 nskb->next = NULL;
5686 tg3_start_xmit_dma_bug(nskb, tp->dev);
5687 } while (segs);
5688
5689 tg3_tso_bug_end:
5690 dev_kfree_skb(skb);
5691
5692 return NETDEV_TX_OK;
5693 }
5694
5695 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5696 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5697 */
5698 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5699 struct net_device *dev)
5700 {
5701 struct tg3 *tp = netdev_priv(dev);
5702 u32 len, entry, base_flags, mss;
5703 int would_hit_hwbug;
5704 dma_addr_t mapping;
5705 struct tg3_napi *tnapi;
5706 struct netdev_queue *txq;
5707 unsigned int i, last;
5708
5709
5710 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5711 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5712 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5713 tnapi++;
5714
5715 /* We are running in BH disabled context with netif_tx_lock
5716 * and TX reclaim runs via tp->napi.poll inside of a software
5717 * interrupt. Furthermore, IRQ processing runs lockless so we have
5718 * no IRQ context deadlocks to worry about either. Rejoice!
5719 */
5720 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5721 if (!netif_tx_queue_stopped(txq)) {
5722 netif_tx_stop_queue(txq);
5723
5724 /* This is a hard error, log it. */
5725 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5726 "queue awake!\n", dev->name);
5727 }
5728 return NETDEV_TX_BUSY;
5729 }
5730
5731 entry = tnapi->tx_prod;
5732 base_flags = 0;
5733 if (skb->ip_summed == CHECKSUM_PARTIAL)
5734 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5735
5736 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5737 struct iphdr *iph;
5738 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5739
5740 if (skb_header_cloned(skb) &&
5741 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5742 dev_kfree_skb(skb);
5743 goto out_unlock;
5744 }
5745
5746 tcp_opt_len = tcp_optlen(skb);
5747 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5748
5749 hdr_len = ip_tcp_len + tcp_opt_len;
5750 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5751 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5752 return (tg3_tso_bug(tp, skb));
5753
5754 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5755 TXD_FLAG_CPU_POST_DMA);
5756
5757 iph = ip_hdr(skb);
5758 iph->check = 0;
5759 iph->tot_len = htons(mss + hdr_len);
5760 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5761 tcp_hdr(skb)->check = 0;
5762 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5763 } else
5764 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5765 iph->daddr, 0,
5766 IPPROTO_TCP,
5767 0);
5768
5769 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5770 mss |= (hdr_len & 0xc) << 12;
5771 if (hdr_len & 0x10)
5772 base_flags |= 0x00000010;
5773 base_flags |= (hdr_len & 0x3e0) << 5;
5774 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5775 mss |= hdr_len << 9;
5776 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5777 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5778 if (tcp_opt_len || iph->ihl > 5) {
5779 int tsflags;
5780
5781 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5782 mss |= (tsflags << 11);
5783 }
5784 } else {
5785 if (tcp_opt_len || iph->ihl > 5) {
5786 int tsflags;
5787
5788 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5789 base_flags |= tsflags << 12;
5790 }
5791 }
5792 }
5793 #if TG3_VLAN_TAG_USED
5794 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5795 base_flags |= (TXD_FLAG_VLAN |
5796 (vlan_tx_tag_get(skb) << 16));
5797 #endif
5798
5799 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5800 !mss && skb->len > ETH_DATA_LEN)
5801 base_flags |= TXD_FLAG_JMB_PKT;
5802
5803 len = skb_headlen(skb);
5804
5805 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5806 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5807 dev_kfree_skb(skb);
5808 goto out_unlock;
5809 }
5810
5811 tnapi->tx_buffers[entry].skb = skb;
5812 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5813
5814 would_hit_hwbug = 0;
5815
5816 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5817 would_hit_hwbug = 1;
5818
5819 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5820 tg3_4g_overflow_test(mapping, len))
5821 would_hit_hwbug = 1;
5822
5823 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5824 tg3_40bit_overflow_test(tp, mapping, len))
5825 would_hit_hwbug = 1;
5826
5827 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5828 would_hit_hwbug = 1;
5829
5830 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5831 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5832
5833 entry = NEXT_TX(entry);
5834
5835 /* Now loop through additional data fragments, and queue them. */
5836 if (skb_shinfo(skb)->nr_frags > 0) {
5837 last = skb_shinfo(skb)->nr_frags - 1;
5838 for (i = 0; i <= last; i++) {
5839 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5840
5841 len = frag->size;
5842 mapping = pci_map_page(tp->pdev,
5843 frag->page,
5844 frag->page_offset,
5845 len, PCI_DMA_TODEVICE);
5846
5847 tnapi->tx_buffers[entry].skb = NULL;
5848 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5849 mapping);
5850 if (pci_dma_mapping_error(tp->pdev, mapping))
5851 goto dma_error;
5852
5853 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5854 len <= 8)
5855 would_hit_hwbug = 1;
5856
5857 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5858 tg3_4g_overflow_test(mapping, len))
5859 would_hit_hwbug = 1;
5860
5861 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5862 tg3_40bit_overflow_test(tp, mapping, len))
5863 would_hit_hwbug = 1;
5864
5865 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5866 tg3_set_txd(tnapi, entry, mapping, len,
5867 base_flags, (i == last)|(mss << 1));
5868 else
5869 tg3_set_txd(tnapi, entry, mapping, len,
5870 base_flags, (i == last));
5871
5872 entry = NEXT_TX(entry);
5873 }
5874 }
5875
5876 if (would_hit_hwbug) {
5877 u32 last_plus_one = entry;
5878 u32 start;
5879
5880 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5881 start &= (TG3_TX_RING_SIZE - 1);
5882
5883 /* If the workaround fails due to memory/mapping
5884 * failure, silently drop this packet.
5885 */
5886 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5887 &start, base_flags, mss))
5888 goto out_unlock;
5889
5890 entry = start;
5891 }
5892
5893 /* Packets are ready, update Tx producer idx local and on card. */
5894 tw32_tx_mbox(tnapi->prodmbox, entry);
5895
5896 tnapi->tx_prod = entry;
5897 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5898 netif_tx_stop_queue(txq);
5899 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5900 netif_tx_wake_queue(txq);
5901 }
5902
5903 out_unlock:
5904 mmiowb();
5905
5906 return NETDEV_TX_OK;
5907
5908 dma_error:
5909 last = i;
5910 entry = tnapi->tx_prod;
5911 tnapi->tx_buffers[entry].skb = NULL;
5912 pci_unmap_single(tp->pdev,
5913 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5914 skb_headlen(skb),
5915 PCI_DMA_TODEVICE);
5916 for (i = 0; i <= last; i++) {
5917 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5918 entry = NEXT_TX(entry);
5919
5920 pci_unmap_page(tp->pdev,
5921 pci_unmap_addr(&tnapi->tx_buffers[entry],
5922 mapping),
5923 frag->size, PCI_DMA_TODEVICE);
5924 }
5925
5926 dev_kfree_skb(skb);
5927 return NETDEV_TX_OK;
5928 }
5929
5930 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5931 int new_mtu)
5932 {
5933 dev->mtu = new_mtu;
5934
5935 if (new_mtu > ETH_DATA_LEN) {
5936 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5937 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5938 ethtool_op_set_tso(dev, 0);
5939 }
5940 else
5941 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5942 } else {
5943 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5944 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5945 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5946 }
5947 }
5948
5949 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5950 {
5951 struct tg3 *tp = netdev_priv(dev);
5952 int err;
5953
5954 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5955 return -EINVAL;
5956
5957 if (!netif_running(dev)) {
5958 /* We'll just catch it later when the
5959 * device is up'd.
5960 */
5961 tg3_set_mtu(dev, tp, new_mtu);
5962 return 0;
5963 }
5964
5965 tg3_phy_stop(tp);
5966
5967 tg3_netif_stop(tp);
5968
5969 tg3_full_lock(tp, 1);
5970
5971 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5972
5973 tg3_set_mtu(dev, tp, new_mtu);
5974
5975 err = tg3_restart_hw(tp, 0);
5976
5977 if (!err)
5978 tg3_netif_start(tp);
5979
5980 tg3_full_unlock(tp);
5981
5982 if (!err)
5983 tg3_phy_start(tp);
5984
5985 return err;
5986 }
5987
5988 static void tg3_rx_prodring_free(struct tg3 *tp,
5989 struct tg3_rx_prodring_set *tpr)
5990 {
5991 int i;
5992
5993 if (tpr != &tp->prodring[0]) {
5994 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5995 i = (i + 1) % TG3_RX_RING_SIZE)
5996 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5997 tp->rx_pkt_map_sz);
5998
5999 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6000 for (i = tpr->rx_jmb_cons_idx;
6001 i != tpr->rx_jmb_prod_idx;
6002 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6003 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6004 TG3_RX_JMB_MAP_SZ);
6005 }
6006 }
6007
6008 return;
6009 }
6010
6011 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6012 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6013 tp->rx_pkt_map_sz);
6014
6015 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6016 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6017 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6018 TG3_RX_JMB_MAP_SZ);
6019 }
6020 }
6021
6022 /* Initialize tx/rx rings for packet processing.
6023 *
6024 * The chip has been shut down and the driver detached from
6025 * the networking, so no interrupts or new tx packets will
6026 * end up in the driver. tp->{tx,}lock are held and thus
6027 * we may not sleep.
6028 */
6029 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6030 struct tg3_rx_prodring_set *tpr)
6031 {
6032 u32 i, rx_pkt_dma_sz;
6033
6034 tpr->rx_std_cons_idx = 0;
6035 tpr->rx_std_prod_idx = 0;
6036 tpr->rx_jmb_cons_idx = 0;
6037 tpr->rx_jmb_prod_idx = 0;
6038
6039 if (tpr != &tp->prodring[0]) {
6040 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6041 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6042 memset(&tpr->rx_jmb_buffers[0], 0,
6043 TG3_RX_JMB_BUFF_RING_SIZE);
6044 goto done;
6045 }
6046
6047 /* Zero out all descriptors. */
6048 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6049
6050 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6051 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6052 tp->dev->mtu > ETH_DATA_LEN)
6053 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6054 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6055
6056 /* Initialize invariants of the rings, we only set this
6057 * stuff once. This works because the card does not
6058 * write into the rx buffer posting rings.
6059 */
6060 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6061 struct tg3_rx_buffer_desc *rxd;
6062
6063 rxd = &tpr->rx_std[i];
6064 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6065 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6066 rxd->opaque = (RXD_OPAQUE_RING_STD |
6067 (i << RXD_OPAQUE_INDEX_SHIFT));
6068 }
6069
6070 /* Now allocate fresh SKBs for each rx ring. */
6071 for (i = 0; i < tp->rx_pending; i++) {
6072 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6073 printk(KERN_WARNING PFX
6074 "%s: Using a smaller RX standard ring, "
6075 "only %d out of %d buffers were allocated "
6076 "successfully.\n",
6077 tp->dev->name, i, tp->rx_pending);
6078 if (i == 0)
6079 goto initfail;
6080 tp->rx_pending = i;
6081 break;
6082 }
6083 }
6084
6085 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6086 goto done;
6087
6088 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6089
6090 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6091 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6092 struct tg3_rx_buffer_desc *rxd;
6093
6094 rxd = &tpr->rx_jmb[i].std;
6095 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6096 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6097 RXD_FLAG_JUMBO;
6098 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6099 (i << RXD_OPAQUE_INDEX_SHIFT));
6100 }
6101
6102 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6103 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6104 i) < 0) {
6105 printk(KERN_WARNING PFX
6106 "%s: Using a smaller RX jumbo ring, "
6107 "only %d out of %d buffers were "
6108 "allocated successfully.\n",
6109 tp->dev->name, i, tp->rx_jumbo_pending);
6110 if (i == 0)
6111 goto initfail;
6112 tp->rx_jumbo_pending = i;
6113 break;
6114 }
6115 }
6116 }
6117
6118 done:
6119 return 0;
6120
6121 initfail:
6122 tg3_rx_prodring_free(tp, tpr);
6123 return -ENOMEM;
6124 }
6125
6126 static void tg3_rx_prodring_fini(struct tg3 *tp,
6127 struct tg3_rx_prodring_set *tpr)
6128 {
6129 kfree(tpr->rx_std_buffers);
6130 tpr->rx_std_buffers = NULL;
6131 kfree(tpr->rx_jmb_buffers);
6132 tpr->rx_jmb_buffers = NULL;
6133 if (tpr->rx_std) {
6134 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6135 tpr->rx_std, tpr->rx_std_mapping);
6136 tpr->rx_std = NULL;
6137 }
6138 if (tpr->rx_jmb) {
6139 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6140 tpr->rx_jmb, tpr->rx_jmb_mapping);
6141 tpr->rx_jmb = NULL;
6142 }
6143 }
6144
6145 static int tg3_rx_prodring_init(struct tg3 *tp,
6146 struct tg3_rx_prodring_set *tpr)
6147 {
6148 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6149 if (!tpr->rx_std_buffers)
6150 return -ENOMEM;
6151
6152 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6153 &tpr->rx_std_mapping);
6154 if (!tpr->rx_std)
6155 goto err_out;
6156
6157 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6158 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6159 GFP_KERNEL);
6160 if (!tpr->rx_jmb_buffers)
6161 goto err_out;
6162
6163 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6164 TG3_RX_JUMBO_RING_BYTES,
6165 &tpr->rx_jmb_mapping);
6166 if (!tpr->rx_jmb)
6167 goto err_out;
6168 }
6169
6170 return 0;
6171
6172 err_out:
6173 tg3_rx_prodring_fini(tp, tpr);
6174 return -ENOMEM;
6175 }
6176
6177 /* Free up pending packets in all rx/tx rings.
6178 *
6179 * The chip has been shut down and the driver detached from
6180 * the networking, so no interrupts or new tx packets will
6181 * end up in the driver. tp->{tx,}lock is not held and we are not
6182 * in an interrupt context and thus may sleep.
6183 */
6184 static void tg3_free_rings(struct tg3 *tp)
6185 {
6186 int i, j;
6187
6188 for (j = 0; j < tp->irq_cnt; j++) {
6189 struct tg3_napi *tnapi = &tp->napi[j];
6190
6191 if (!tnapi->tx_buffers)
6192 continue;
6193
6194 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6195 struct ring_info *txp;
6196 struct sk_buff *skb;
6197 unsigned int k;
6198
6199 txp = &tnapi->tx_buffers[i];
6200 skb = txp->skb;
6201
6202 if (skb == NULL) {
6203 i++;
6204 continue;
6205 }
6206
6207 pci_unmap_single(tp->pdev,
6208 pci_unmap_addr(txp, mapping),
6209 skb_headlen(skb),
6210 PCI_DMA_TODEVICE);
6211 txp->skb = NULL;
6212
6213 i++;
6214
6215 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6216 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6217 pci_unmap_page(tp->pdev,
6218 pci_unmap_addr(txp, mapping),
6219 skb_shinfo(skb)->frags[k].size,
6220 PCI_DMA_TODEVICE);
6221 i++;
6222 }
6223
6224 dev_kfree_skb_any(skb);
6225 }
6226
6227 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6228 }
6229 }
6230
6231 /* Initialize tx/rx rings for packet processing.
6232 *
6233 * The chip has been shut down and the driver detached from
6234 * the networking, so no interrupts or new tx packets will
6235 * end up in the driver. tp->{tx,}lock are held and thus
6236 * we may not sleep.
6237 */
6238 static int tg3_init_rings(struct tg3 *tp)
6239 {
6240 int i;
6241
6242 /* Free up all the SKBs. */
6243 tg3_free_rings(tp);
6244
6245 for (i = 0; i < tp->irq_cnt; i++) {
6246 struct tg3_napi *tnapi = &tp->napi[i];
6247
6248 tnapi->last_tag = 0;
6249 tnapi->last_irq_tag = 0;
6250 tnapi->hw_status->status = 0;
6251 tnapi->hw_status->status_tag = 0;
6252 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6253
6254 tnapi->tx_prod = 0;
6255 tnapi->tx_cons = 0;
6256 if (tnapi->tx_ring)
6257 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6258
6259 tnapi->rx_rcb_ptr = 0;
6260 if (tnapi->rx_rcb)
6261 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6262
6263 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6264 tg3_free_rings(tp);
6265 return -ENOMEM;
6266 }
6267 }
6268
6269 return 0;
6270 }
6271
6272 /*
6273 * Must not be invoked with interrupt sources disabled and
6274 * the hardware shutdown down.
6275 */
6276 static void tg3_free_consistent(struct tg3 *tp)
6277 {
6278 int i;
6279
6280 for (i = 0; i < tp->irq_cnt; i++) {
6281 struct tg3_napi *tnapi = &tp->napi[i];
6282
6283 if (tnapi->tx_ring) {
6284 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6285 tnapi->tx_ring, tnapi->tx_desc_mapping);
6286 tnapi->tx_ring = NULL;
6287 }
6288
6289 kfree(tnapi->tx_buffers);
6290 tnapi->tx_buffers = NULL;
6291
6292 if (tnapi->rx_rcb) {
6293 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6294 tnapi->rx_rcb,
6295 tnapi->rx_rcb_mapping);
6296 tnapi->rx_rcb = NULL;
6297 }
6298
6299 if (tnapi->hw_status) {
6300 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6301 tnapi->hw_status,
6302 tnapi->status_mapping);
6303 tnapi->hw_status = NULL;
6304 }
6305 }
6306
6307 if (tp->hw_stats) {
6308 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6309 tp->hw_stats, tp->stats_mapping);
6310 tp->hw_stats = NULL;
6311 }
6312
6313 for (i = 0; i < tp->irq_cnt; i++)
6314 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6315 }
6316
6317 /*
6318 * Must not be invoked with interrupt sources disabled and
6319 * the hardware shutdown down. Can sleep.
6320 */
6321 static int tg3_alloc_consistent(struct tg3 *tp)
6322 {
6323 int i;
6324
6325 for (i = 0; i < tp->irq_cnt; i++) {
6326 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6327 goto err_out;
6328 }
6329
6330 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6331 sizeof(struct tg3_hw_stats),
6332 &tp->stats_mapping);
6333 if (!tp->hw_stats)
6334 goto err_out;
6335
6336 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6337
6338 for (i = 0; i < tp->irq_cnt; i++) {
6339 struct tg3_napi *tnapi = &tp->napi[i];
6340 struct tg3_hw_status *sblk;
6341
6342 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6343 TG3_HW_STATUS_SIZE,
6344 &tnapi->status_mapping);
6345 if (!tnapi->hw_status)
6346 goto err_out;
6347
6348 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6349 sblk = tnapi->hw_status;
6350
6351 /* If multivector TSS is enabled, vector 0 does not handle
6352 * tx interrupts. Don't allocate any resources for it.
6353 */
6354 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6355 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6356 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6357 TG3_TX_RING_SIZE,
6358 GFP_KERNEL);
6359 if (!tnapi->tx_buffers)
6360 goto err_out;
6361
6362 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6363 TG3_TX_RING_BYTES,
6364 &tnapi->tx_desc_mapping);
6365 if (!tnapi->tx_ring)
6366 goto err_out;
6367 }
6368
6369 /*
6370 * When RSS is enabled, the status block format changes
6371 * slightly. The "rx_jumbo_consumer", "reserved",
6372 * and "rx_mini_consumer" members get mapped to the
6373 * other three rx return ring producer indexes.
6374 */
6375 switch (i) {
6376 default:
6377 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6378 break;
6379 case 2:
6380 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6381 break;
6382 case 3:
6383 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6384 break;
6385 case 4:
6386 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6387 break;
6388 }
6389
6390 tnapi->prodring = &tp->prodring[i];
6391
6392 /*
6393 * If multivector RSS is enabled, vector 0 does not handle
6394 * rx or tx interrupts. Don't allocate any resources for it.
6395 */
6396 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6397 continue;
6398
6399 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6400 TG3_RX_RCB_RING_BYTES(tp),
6401 &tnapi->rx_rcb_mapping);
6402 if (!tnapi->rx_rcb)
6403 goto err_out;
6404
6405 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6406 }
6407
6408 return 0;
6409
6410 err_out:
6411 tg3_free_consistent(tp);
6412 return -ENOMEM;
6413 }
6414
6415 #define MAX_WAIT_CNT 1000
6416
6417 /* To stop a block, clear the enable bit and poll till it
6418 * clears. tp->lock is held.
6419 */
6420 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6421 {
6422 unsigned int i;
6423 u32 val;
6424
6425 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6426 switch (ofs) {
6427 case RCVLSC_MODE:
6428 case DMAC_MODE:
6429 case MBFREE_MODE:
6430 case BUFMGR_MODE:
6431 case MEMARB_MODE:
6432 /* We can't enable/disable these bits of the
6433 * 5705/5750, just say success.
6434 */
6435 return 0;
6436
6437 default:
6438 break;
6439 }
6440 }
6441
6442 val = tr32(ofs);
6443 val &= ~enable_bit;
6444 tw32_f(ofs, val);
6445
6446 for (i = 0; i < MAX_WAIT_CNT; i++) {
6447 udelay(100);
6448 val = tr32(ofs);
6449 if ((val & enable_bit) == 0)
6450 break;
6451 }
6452
6453 if (i == MAX_WAIT_CNT && !silent) {
6454 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6455 "ofs=%lx enable_bit=%x\n",
6456 ofs, enable_bit);
6457 return -ENODEV;
6458 }
6459
6460 return 0;
6461 }
6462
6463 /* tp->lock is held. */
6464 static int tg3_abort_hw(struct tg3 *tp, int silent)
6465 {
6466 int i, err;
6467
6468 tg3_disable_ints(tp);
6469
6470 tp->rx_mode &= ~RX_MODE_ENABLE;
6471 tw32_f(MAC_RX_MODE, tp->rx_mode);
6472 udelay(10);
6473
6474 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6475 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6476 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6477 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6478 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6479 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6480
6481 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6482 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6483 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6484 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6485 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6486 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6487 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6488
6489 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6490 tw32_f(MAC_MODE, tp->mac_mode);
6491 udelay(40);
6492
6493 tp->tx_mode &= ~TX_MODE_ENABLE;
6494 tw32_f(MAC_TX_MODE, tp->tx_mode);
6495
6496 for (i = 0; i < MAX_WAIT_CNT; i++) {
6497 udelay(100);
6498 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6499 break;
6500 }
6501 if (i >= MAX_WAIT_CNT) {
6502 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6503 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6504 tp->dev->name, tr32(MAC_TX_MODE));
6505 err |= -ENODEV;
6506 }
6507
6508 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6509 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6510 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6511
6512 tw32(FTQ_RESET, 0xffffffff);
6513 tw32(FTQ_RESET, 0x00000000);
6514
6515 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6516 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6517
6518 for (i = 0; i < tp->irq_cnt; i++) {
6519 struct tg3_napi *tnapi = &tp->napi[i];
6520 if (tnapi->hw_status)
6521 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6522 }
6523 if (tp->hw_stats)
6524 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6525
6526 return err;
6527 }
6528
6529 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6530 {
6531 int i;
6532 u32 apedata;
6533
6534 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6535 if (apedata != APE_SEG_SIG_MAGIC)
6536 return;
6537
6538 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6539 if (!(apedata & APE_FW_STATUS_READY))
6540 return;
6541
6542 /* Wait for up to 1 millisecond for APE to service previous event. */
6543 for (i = 0; i < 10; i++) {
6544 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6545 return;
6546
6547 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6548
6549 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6550 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6551 event | APE_EVENT_STATUS_EVENT_PENDING);
6552
6553 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6554
6555 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6556 break;
6557
6558 udelay(100);
6559 }
6560
6561 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6562 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6563 }
6564
6565 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6566 {
6567 u32 event;
6568 u32 apedata;
6569
6570 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6571 return;
6572
6573 switch (kind) {
6574 case RESET_KIND_INIT:
6575 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6576 APE_HOST_SEG_SIG_MAGIC);
6577 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6578 APE_HOST_SEG_LEN_MAGIC);
6579 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6580 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6581 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6582 APE_HOST_DRIVER_ID_MAGIC);
6583 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6584 APE_HOST_BEHAV_NO_PHYLOCK);
6585
6586 event = APE_EVENT_STATUS_STATE_START;
6587 break;
6588 case RESET_KIND_SHUTDOWN:
6589 /* With the interface we are currently using,
6590 * APE does not track driver state. Wiping
6591 * out the HOST SEGMENT SIGNATURE forces
6592 * the APE to assume OS absent status.
6593 */
6594 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6595
6596 event = APE_EVENT_STATUS_STATE_UNLOAD;
6597 break;
6598 case RESET_KIND_SUSPEND:
6599 event = APE_EVENT_STATUS_STATE_SUSPEND;
6600 break;
6601 default:
6602 return;
6603 }
6604
6605 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6606
6607 tg3_ape_send_event(tp, event);
6608 }
6609
6610 /* tp->lock is held. */
6611 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6612 {
6613 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6614 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6615
6616 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6617 switch (kind) {
6618 case RESET_KIND_INIT:
6619 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6620 DRV_STATE_START);
6621 break;
6622
6623 case RESET_KIND_SHUTDOWN:
6624 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6625 DRV_STATE_UNLOAD);
6626 break;
6627
6628 case RESET_KIND_SUSPEND:
6629 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6630 DRV_STATE_SUSPEND);
6631 break;
6632
6633 default:
6634 break;
6635 }
6636 }
6637
6638 if (kind == RESET_KIND_INIT ||
6639 kind == RESET_KIND_SUSPEND)
6640 tg3_ape_driver_state_change(tp, kind);
6641 }
6642
6643 /* tp->lock is held. */
6644 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6645 {
6646 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6647 switch (kind) {
6648 case RESET_KIND_INIT:
6649 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6650 DRV_STATE_START_DONE);
6651 break;
6652
6653 case RESET_KIND_SHUTDOWN:
6654 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6655 DRV_STATE_UNLOAD_DONE);
6656 break;
6657
6658 default:
6659 break;
6660 }
6661 }
6662
6663 if (kind == RESET_KIND_SHUTDOWN)
6664 tg3_ape_driver_state_change(tp, kind);
6665 }
6666
6667 /* tp->lock is held. */
6668 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6669 {
6670 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6671 switch (kind) {
6672 case RESET_KIND_INIT:
6673 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6674 DRV_STATE_START);
6675 break;
6676
6677 case RESET_KIND_SHUTDOWN:
6678 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6679 DRV_STATE_UNLOAD);
6680 break;
6681
6682 case RESET_KIND_SUSPEND:
6683 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6684 DRV_STATE_SUSPEND);
6685 break;
6686
6687 default:
6688 break;
6689 }
6690 }
6691 }
6692
6693 static int tg3_poll_fw(struct tg3 *tp)
6694 {
6695 int i;
6696 u32 val;
6697
6698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6699 /* Wait up to 20ms for init done. */
6700 for (i = 0; i < 200; i++) {
6701 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6702 return 0;
6703 udelay(100);
6704 }
6705 return -ENODEV;
6706 }
6707
6708 /* Wait for firmware initialization to complete. */
6709 for (i = 0; i < 100000; i++) {
6710 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6711 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6712 break;
6713 udelay(10);
6714 }
6715
6716 /* Chip might not be fitted with firmware. Some Sun onboard
6717 * parts are configured like that. So don't signal the timeout
6718 * of the above loop as an error, but do report the lack of
6719 * running firmware once.
6720 */
6721 if (i >= 100000 &&
6722 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6723 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6724
6725 printk(KERN_INFO PFX "%s: No firmware running.\n",
6726 tp->dev->name);
6727 }
6728
6729 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6730 /* The 57765 A0 needs a little more
6731 * time to do some important work.
6732 */
6733 mdelay(10);
6734 }
6735
6736 return 0;
6737 }
6738
6739 /* Save PCI command register before chip reset */
6740 static void tg3_save_pci_state(struct tg3 *tp)
6741 {
6742 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6743 }
6744
6745 /* Restore PCI state after chip reset */
6746 static void tg3_restore_pci_state(struct tg3 *tp)
6747 {
6748 u32 val;
6749
6750 /* Re-enable indirect register accesses. */
6751 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6752 tp->misc_host_ctrl);
6753
6754 /* Set MAX PCI retry to zero. */
6755 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6756 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6757 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6758 val |= PCISTATE_RETRY_SAME_DMA;
6759 /* Allow reads and writes to the APE register and memory space. */
6760 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6761 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6762 PCISTATE_ALLOW_APE_SHMEM_WR;
6763 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6764
6765 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6766
6767 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6768 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6769 pcie_set_readrq(tp->pdev, 4096);
6770 else {
6771 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6772 tp->pci_cacheline_sz);
6773 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6774 tp->pci_lat_timer);
6775 }
6776 }
6777
6778 /* Make sure PCI-X relaxed ordering bit is clear. */
6779 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6780 u16 pcix_cmd;
6781
6782 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6783 &pcix_cmd);
6784 pcix_cmd &= ~PCI_X_CMD_ERO;
6785 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6786 pcix_cmd);
6787 }
6788
6789 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6790
6791 /* Chip reset on 5780 will reset MSI enable bit,
6792 * so need to restore it.
6793 */
6794 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6795 u16 ctrl;
6796
6797 pci_read_config_word(tp->pdev,
6798 tp->msi_cap + PCI_MSI_FLAGS,
6799 &ctrl);
6800 pci_write_config_word(tp->pdev,
6801 tp->msi_cap + PCI_MSI_FLAGS,
6802 ctrl | PCI_MSI_FLAGS_ENABLE);
6803 val = tr32(MSGINT_MODE);
6804 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6805 }
6806 }
6807 }
6808
6809 static void tg3_stop_fw(struct tg3 *);
6810
6811 /* tp->lock is held. */
6812 static int tg3_chip_reset(struct tg3 *tp)
6813 {
6814 u32 val;
6815 void (*write_op)(struct tg3 *, u32, u32);
6816 int i, err;
6817
6818 tg3_nvram_lock(tp);
6819
6820 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6821
6822 /* No matching tg3_nvram_unlock() after this because
6823 * chip reset below will undo the nvram lock.
6824 */
6825 tp->nvram_lock_cnt = 0;
6826
6827 /* GRC_MISC_CFG core clock reset will clear the memory
6828 * enable bit in PCI register 4 and the MSI enable bit
6829 * on some chips, so we save relevant registers here.
6830 */
6831 tg3_save_pci_state(tp);
6832
6833 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6834 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6835 tw32(GRC_FASTBOOT_PC, 0);
6836
6837 /*
6838 * We must avoid the readl() that normally takes place.
6839 * It locks machines, causes machine checks, and other
6840 * fun things. So, temporarily disable the 5701
6841 * hardware workaround, while we do the reset.
6842 */
6843 write_op = tp->write32;
6844 if (write_op == tg3_write_flush_reg32)
6845 tp->write32 = tg3_write32;
6846
6847 /* Prevent the irq handler from reading or writing PCI registers
6848 * during chip reset when the memory enable bit in the PCI command
6849 * register may be cleared. The chip does not generate interrupt
6850 * at this time, but the irq handler may still be called due to irq
6851 * sharing or irqpoll.
6852 */
6853 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6854 for (i = 0; i < tp->irq_cnt; i++) {
6855 struct tg3_napi *tnapi = &tp->napi[i];
6856 if (tnapi->hw_status) {
6857 tnapi->hw_status->status = 0;
6858 tnapi->hw_status->status_tag = 0;
6859 }
6860 tnapi->last_tag = 0;
6861 tnapi->last_irq_tag = 0;
6862 }
6863 smp_mb();
6864
6865 for (i = 0; i < tp->irq_cnt; i++)
6866 synchronize_irq(tp->napi[i].irq_vec);
6867
6868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6869 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6870 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6871 }
6872
6873 /* do the reset */
6874 val = GRC_MISC_CFG_CORECLK_RESET;
6875
6876 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6877 if (tr32(0x7e2c) == 0x60) {
6878 tw32(0x7e2c, 0x20);
6879 }
6880 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6881 tw32(GRC_MISC_CFG, (1 << 29));
6882 val |= (1 << 29);
6883 }
6884 }
6885
6886 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6887 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6888 tw32(GRC_VCPU_EXT_CTRL,
6889 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6890 }
6891
6892 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6893 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6894 tw32(GRC_MISC_CFG, val);
6895
6896 /* restore 5701 hardware bug workaround write method */
6897 tp->write32 = write_op;
6898
6899 /* Unfortunately, we have to delay before the PCI read back.
6900 * Some 575X chips even will not respond to a PCI cfg access
6901 * when the reset command is given to the chip.
6902 *
6903 * How do these hardware designers expect things to work
6904 * properly if the PCI write is posted for a long period
6905 * of time? It is always necessary to have some method by
6906 * which a register read back can occur to push the write
6907 * out which does the reset.
6908 *
6909 * For most tg3 variants the trick below was working.
6910 * Ho hum...
6911 */
6912 udelay(120);
6913
6914 /* Flush PCI posted writes. The normal MMIO registers
6915 * are inaccessible at this time so this is the only
6916 * way to make this reliably (actually, this is no longer
6917 * the case, see above). I tried to use indirect
6918 * register read/write but this upset some 5701 variants.
6919 */
6920 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6921
6922 udelay(120);
6923
6924 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6925 u16 val16;
6926
6927 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6928 int i;
6929 u32 cfg_val;
6930
6931 /* Wait for link training to complete. */
6932 for (i = 0; i < 5000; i++)
6933 udelay(100);
6934
6935 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6936 pci_write_config_dword(tp->pdev, 0xc4,
6937 cfg_val | (1 << 15));
6938 }
6939
6940 /* Clear the "no snoop" and "relaxed ordering" bits. */
6941 pci_read_config_word(tp->pdev,
6942 tp->pcie_cap + PCI_EXP_DEVCTL,
6943 &val16);
6944 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6945 PCI_EXP_DEVCTL_NOSNOOP_EN);
6946 /*
6947 * Older PCIe devices only support the 128 byte
6948 * MPS setting. Enforce the restriction.
6949 */
6950 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6951 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6952 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6953 pci_write_config_word(tp->pdev,
6954 tp->pcie_cap + PCI_EXP_DEVCTL,
6955 val16);
6956
6957 pcie_set_readrq(tp->pdev, 4096);
6958
6959 /* Clear error status */
6960 pci_write_config_word(tp->pdev,
6961 tp->pcie_cap + PCI_EXP_DEVSTA,
6962 PCI_EXP_DEVSTA_CED |
6963 PCI_EXP_DEVSTA_NFED |
6964 PCI_EXP_DEVSTA_FED |
6965 PCI_EXP_DEVSTA_URD);
6966 }
6967
6968 tg3_restore_pci_state(tp);
6969
6970 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6971
6972 val = 0;
6973 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6974 val = tr32(MEMARB_MODE);
6975 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6976
6977 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6978 tg3_stop_fw(tp);
6979 tw32(0x5000, 0x400);
6980 }
6981
6982 tw32(GRC_MODE, tp->grc_mode);
6983
6984 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6985 val = tr32(0xc4);
6986
6987 tw32(0xc4, val | (1 << 15));
6988 }
6989
6990 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6992 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6993 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6994 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6995 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6996 }
6997
6998 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6999 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7000 tw32_f(MAC_MODE, tp->mac_mode);
7001 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7002 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7003 tw32_f(MAC_MODE, tp->mac_mode);
7004 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7005 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7006 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7007 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7008 tw32_f(MAC_MODE, tp->mac_mode);
7009 } else
7010 tw32_f(MAC_MODE, 0);
7011 udelay(40);
7012
7013 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7014
7015 err = tg3_poll_fw(tp);
7016 if (err)
7017 return err;
7018
7019 tg3_mdio_start(tp);
7020
7021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7022 u8 phy_addr;
7023
7024 phy_addr = tp->phy_addr;
7025 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7026
7027 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7028 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7029 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7030 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7031 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7032 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7033 udelay(10);
7034
7035 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7036 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7037 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7038 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7039 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7040 udelay(10);
7041
7042 tp->phy_addr = phy_addr;
7043 }
7044
7045 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7046 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7047 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7048 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7049 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7050 val = tr32(0x7c00);
7051
7052 tw32(0x7c00, val | (1 << 25));
7053 }
7054
7055 /* Reprobe ASF enable state. */
7056 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7057 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7058 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7059 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7060 u32 nic_cfg;
7061
7062 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7063 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7064 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7065 tp->last_event_jiffies = jiffies;
7066 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7067 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7068 }
7069 }
7070
7071 return 0;
7072 }
7073
7074 /* tp->lock is held. */
7075 static void tg3_stop_fw(struct tg3 *tp)
7076 {
7077 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7078 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7079 /* Wait for RX cpu to ACK the previous event. */
7080 tg3_wait_for_event_ack(tp);
7081
7082 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7083
7084 tg3_generate_fw_event(tp);
7085
7086 /* Wait for RX cpu to ACK this event. */
7087 tg3_wait_for_event_ack(tp);
7088 }
7089 }
7090
7091 /* tp->lock is held. */
7092 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7093 {
7094 int err;
7095
7096 tg3_stop_fw(tp);
7097
7098 tg3_write_sig_pre_reset(tp, kind);
7099
7100 tg3_abort_hw(tp, silent);
7101 err = tg3_chip_reset(tp);
7102
7103 __tg3_set_mac_addr(tp, 0);
7104
7105 tg3_write_sig_legacy(tp, kind);
7106 tg3_write_sig_post_reset(tp, kind);
7107
7108 if (err)
7109 return err;
7110
7111 return 0;
7112 }
7113
7114 #define RX_CPU_SCRATCH_BASE 0x30000
7115 #define RX_CPU_SCRATCH_SIZE 0x04000
7116 #define TX_CPU_SCRATCH_BASE 0x34000
7117 #define TX_CPU_SCRATCH_SIZE 0x04000
7118
7119 /* tp->lock is held. */
7120 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7121 {
7122 int i;
7123
7124 BUG_ON(offset == TX_CPU_BASE &&
7125 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7126
7127 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7128 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7129
7130 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7131 return 0;
7132 }
7133 if (offset == RX_CPU_BASE) {
7134 for (i = 0; i < 10000; i++) {
7135 tw32(offset + CPU_STATE, 0xffffffff);
7136 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7137 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7138 break;
7139 }
7140
7141 tw32(offset + CPU_STATE, 0xffffffff);
7142 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7143 udelay(10);
7144 } else {
7145 for (i = 0; i < 10000; i++) {
7146 tw32(offset + CPU_STATE, 0xffffffff);
7147 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7148 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7149 break;
7150 }
7151 }
7152
7153 if (i >= 10000) {
7154 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7155 "and %s CPU\n",
7156 tp->dev->name,
7157 (offset == RX_CPU_BASE ? "RX" : "TX"));
7158 return -ENODEV;
7159 }
7160
7161 /* Clear firmware's nvram arbitration. */
7162 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7163 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7164 return 0;
7165 }
7166
7167 struct fw_info {
7168 unsigned int fw_base;
7169 unsigned int fw_len;
7170 const __be32 *fw_data;
7171 };
7172
7173 /* tp->lock is held. */
7174 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7175 int cpu_scratch_size, struct fw_info *info)
7176 {
7177 int err, lock_err, i;
7178 void (*write_op)(struct tg3 *, u32, u32);
7179
7180 if (cpu_base == TX_CPU_BASE &&
7181 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7182 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7183 "TX cpu firmware on %s which is 5705.\n",
7184 tp->dev->name);
7185 return -EINVAL;
7186 }
7187
7188 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7189 write_op = tg3_write_mem;
7190 else
7191 write_op = tg3_write_indirect_reg32;
7192
7193 /* It is possible that bootcode is still loading at this point.
7194 * Get the nvram lock first before halting the cpu.
7195 */
7196 lock_err = tg3_nvram_lock(tp);
7197 err = tg3_halt_cpu(tp, cpu_base);
7198 if (!lock_err)
7199 tg3_nvram_unlock(tp);
7200 if (err)
7201 goto out;
7202
7203 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7204 write_op(tp, cpu_scratch_base + i, 0);
7205 tw32(cpu_base + CPU_STATE, 0xffffffff);
7206 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7207 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7208 write_op(tp, (cpu_scratch_base +
7209 (info->fw_base & 0xffff) +
7210 (i * sizeof(u32))),
7211 be32_to_cpu(info->fw_data[i]));
7212
7213 err = 0;
7214
7215 out:
7216 return err;
7217 }
7218
7219 /* tp->lock is held. */
7220 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7221 {
7222 struct fw_info info;
7223 const __be32 *fw_data;
7224 int err, i;
7225
7226 fw_data = (void *)tp->fw->data;
7227
7228 /* Firmware blob starts with version numbers, followed by
7229 start address and length. We are setting complete length.
7230 length = end_address_of_bss - start_address_of_text.
7231 Remainder is the blob to be loaded contiguously
7232 from start address. */
7233
7234 info.fw_base = be32_to_cpu(fw_data[1]);
7235 info.fw_len = tp->fw->size - 12;
7236 info.fw_data = &fw_data[3];
7237
7238 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7239 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7240 &info);
7241 if (err)
7242 return err;
7243
7244 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7245 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7246 &info);
7247 if (err)
7248 return err;
7249
7250 /* Now startup only the RX cpu. */
7251 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7252 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7253
7254 for (i = 0; i < 5; i++) {
7255 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7256 break;
7257 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7258 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7259 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7260 udelay(1000);
7261 }
7262 if (i >= 5) {
7263 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7264 "to set RX CPU PC, is %08x should be %08x\n",
7265 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7266 info.fw_base);
7267 return -ENODEV;
7268 }
7269 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7270 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7271
7272 return 0;
7273 }
7274
7275 /* 5705 needs a special version of the TSO firmware. */
7276
7277 /* tp->lock is held. */
7278 static int tg3_load_tso_firmware(struct tg3 *tp)
7279 {
7280 struct fw_info info;
7281 const __be32 *fw_data;
7282 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7283 int err, i;
7284
7285 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7286 return 0;
7287
7288 fw_data = (void *)tp->fw->data;
7289
7290 /* Firmware blob starts with version numbers, followed by
7291 start address and length. We are setting complete length.
7292 length = end_address_of_bss - start_address_of_text.
7293 Remainder is the blob to be loaded contiguously
7294 from start address. */
7295
7296 info.fw_base = be32_to_cpu(fw_data[1]);
7297 cpu_scratch_size = tp->fw_len;
7298 info.fw_len = tp->fw->size - 12;
7299 info.fw_data = &fw_data[3];
7300
7301 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7302 cpu_base = RX_CPU_BASE;
7303 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7304 } else {
7305 cpu_base = TX_CPU_BASE;
7306 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7307 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7308 }
7309
7310 err = tg3_load_firmware_cpu(tp, cpu_base,
7311 cpu_scratch_base, cpu_scratch_size,
7312 &info);
7313 if (err)
7314 return err;
7315
7316 /* Now startup the cpu. */
7317 tw32(cpu_base + CPU_STATE, 0xffffffff);
7318 tw32_f(cpu_base + CPU_PC, info.fw_base);
7319
7320 for (i = 0; i < 5; i++) {
7321 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7322 break;
7323 tw32(cpu_base + CPU_STATE, 0xffffffff);
7324 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7325 tw32_f(cpu_base + CPU_PC, info.fw_base);
7326 udelay(1000);
7327 }
7328 if (i >= 5) {
7329 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7330 "to set CPU PC, is %08x should be %08x\n",
7331 tp->dev->name, tr32(cpu_base + CPU_PC),
7332 info.fw_base);
7333 return -ENODEV;
7334 }
7335 tw32(cpu_base + CPU_STATE, 0xffffffff);
7336 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7337 return 0;
7338 }
7339
7340
7341 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7342 {
7343 struct tg3 *tp = netdev_priv(dev);
7344 struct sockaddr *addr = p;
7345 int err = 0, skip_mac_1 = 0;
7346
7347 if (!is_valid_ether_addr(addr->sa_data))
7348 return -EINVAL;
7349
7350 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7351
7352 if (!netif_running(dev))
7353 return 0;
7354
7355 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7356 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7357
7358 addr0_high = tr32(MAC_ADDR_0_HIGH);
7359 addr0_low = tr32(MAC_ADDR_0_LOW);
7360 addr1_high = tr32(MAC_ADDR_1_HIGH);
7361 addr1_low = tr32(MAC_ADDR_1_LOW);
7362
7363 /* Skip MAC addr 1 if ASF is using it. */
7364 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7365 !(addr1_high == 0 && addr1_low == 0))
7366 skip_mac_1 = 1;
7367 }
7368 spin_lock_bh(&tp->lock);
7369 __tg3_set_mac_addr(tp, skip_mac_1);
7370 spin_unlock_bh(&tp->lock);
7371
7372 return err;
7373 }
7374
7375 /* tp->lock is held. */
7376 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7377 dma_addr_t mapping, u32 maxlen_flags,
7378 u32 nic_addr)
7379 {
7380 tg3_write_mem(tp,
7381 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7382 ((u64) mapping >> 32));
7383 tg3_write_mem(tp,
7384 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7385 ((u64) mapping & 0xffffffff));
7386 tg3_write_mem(tp,
7387 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7388 maxlen_flags);
7389
7390 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7391 tg3_write_mem(tp,
7392 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7393 nic_addr);
7394 }
7395
7396 static void __tg3_set_rx_mode(struct net_device *);
7397 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7398 {
7399 int i;
7400
7401 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7402 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7403 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7404 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7405 } else {
7406 tw32(HOSTCC_TXCOL_TICKS, 0);
7407 tw32(HOSTCC_TXMAX_FRAMES, 0);
7408 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7409 }
7410
7411 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7412 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7413 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7414 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7415 } else {
7416 tw32(HOSTCC_RXCOL_TICKS, 0);
7417 tw32(HOSTCC_RXMAX_FRAMES, 0);
7418 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7419 }
7420
7421 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7422 u32 val = ec->stats_block_coalesce_usecs;
7423
7424 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7425 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7426
7427 if (!netif_carrier_ok(tp->dev))
7428 val = 0;
7429
7430 tw32(HOSTCC_STAT_COAL_TICKS, val);
7431 }
7432
7433 for (i = 0; i < tp->irq_cnt - 1; i++) {
7434 u32 reg;
7435
7436 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7437 tw32(reg, ec->rx_coalesce_usecs);
7438 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7439 tw32(reg, ec->rx_max_coalesced_frames);
7440 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7441 tw32(reg, ec->rx_max_coalesced_frames_irq);
7442
7443 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7444 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7445 tw32(reg, ec->tx_coalesce_usecs);
7446 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7447 tw32(reg, ec->tx_max_coalesced_frames);
7448 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7449 tw32(reg, ec->tx_max_coalesced_frames_irq);
7450 }
7451 }
7452
7453 for (; i < tp->irq_max - 1; i++) {
7454 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7455 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7456 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7457
7458 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7459 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7460 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7461 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7462 }
7463 }
7464 }
7465
7466 /* tp->lock is held. */
7467 static void tg3_rings_reset(struct tg3 *tp)
7468 {
7469 int i;
7470 u32 stblk, txrcb, rxrcb, limit;
7471 struct tg3_napi *tnapi = &tp->napi[0];
7472
7473 /* Disable all transmit rings but the first. */
7474 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7475 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7476 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7477 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7478 else
7479 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7480
7481 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7482 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7483 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7484 BDINFO_FLAGS_DISABLED);
7485
7486
7487 /* Disable all receive return rings but the first. */
7488 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7489 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7490 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7491 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7492 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7493 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7494 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7495 else
7496 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7497
7498 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7499 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7500 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7501 BDINFO_FLAGS_DISABLED);
7502
7503 /* Disable interrupts */
7504 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7505
7506 /* Zero mailbox registers. */
7507 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7508 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7509 tp->napi[i].tx_prod = 0;
7510 tp->napi[i].tx_cons = 0;
7511 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7512 tw32_mailbox(tp->napi[i].prodmbox, 0);
7513 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7514 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7515 }
7516 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7517 tw32_mailbox(tp->napi[0].prodmbox, 0);
7518 } else {
7519 tp->napi[0].tx_prod = 0;
7520 tp->napi[0].tx_cons = 0;
7521 tw32_mailbox(tp->napi[0].prodmbox, 0);
7522 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7523 }
7524
7525 /* Make sure the NIC-based send BD rings are disabled. */
7526 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7527 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7528 for (i = 0; i < 16; i++)
7529 tw32_tx_mbox(mbox + i * 8, 0);
7530 }
7531
7532 txrcb = NIC_SRAM_SEND_RCB;
7533 rxrcb = NIC_SRAM_RCV_RET_RCB;
7534
7535 /* Clear status block in ram. */
7536 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7537
7538 /* Set status block DMA address */
7539 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7540 ((u64) tnapi->status_mapping >> 32));
7541 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7542 ((u64) tnapi->status_mapping & 0xffffffff));
7543
7544 if (tnapi->tx_ring) {
7545 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7546 (TG3_TX_RING_SIZE <<
7547 BDINFO_FLAGS_MAXLEN_SHIFT),
7548 NIC_SRAM_TX_BUFFER_DESC);
7549 txrcb += TG3_BDINFO_SIZE;
7550 }
7551
7552 if (tnapi->rx_rcb) {
7553 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7554 (TG3_RX_RCB_RING_SIZE(tp) <<
7555 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7556 rxrcb += TG3_BDINFO_SIZE;
7557 }
7558
7559 stblk = HOSTCC_STATBLCK_RING1;
7560
7561 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7562 u64 mapping = (u64)tnapi->status_mapping;
7563 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7564 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7565
7566 /* Clear status block in ram. */
7567 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7568
7569 if (tnapi->tx_ring) {
7570 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7571 (TG3_TX_RING_SIZE <<
7572 BDINFO_FLAGS_MAXLEN_SHIFT),
7573 NIC_SRAM_TX_BUFFER_DESC);
7574 txrcb += TG3_BDINFO_SIZE;
7575 }
7576
7577 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7578 (TG3_RX_RCB_RING_SIZE(tp) <<
7579 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7580
7581 stblk += 8;
7582 rxrcb += TG3_BDINFO_SIZE;
7583 }
7584 }
7585
7586 /* tp->lock is held. */
7587 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7588 {
7589 u32 val, rdmac_mode;
7590 int i, err, limit;
7591 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7592
7593 tg3_disable_ints(tp);
7594
7595 tg3_stop_fw(tp);
7596
7597 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7598
7599 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7600 tg3_abort_hw(tp, 1);
7601 }
7602
7603 if (reset_phy)
7604 tg3_phy_reset(tp);
7605
7606 err = tg3_chip_reset(tp);
7607 if (err)
7608 return err;
7609
7610 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7611
7612 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7613 val = tr32(TG3_CPMU_CTRL);
7614 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7615 tw32(TG3_CPMU_CTRL, val);
7616
7617 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7618 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7619 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7620 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7621
7622 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7623 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7624 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7625 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7626
7627 val = tr32(TG3_CPMU_HST_ACC);
7628 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7629 val |= CPMU_HST_ACC_MACCLK_6_25;
7630 tw32(TG3_CPMU_HST_ACC, val);
7631 }
7632
7633 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7634 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7635 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7636 PCIE_PWR_MGMT_L1_THRESH_4MS;
7637 tw32(PCIE_PWR_MGMT_THRESH, val);
7638
7639 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7640 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7641
7642 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7643
7644 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7645 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7646 }
7647
7648 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7649 u32 grc_mode = tr32(GRC_MODE);
7650
7651 /* Access the lower 1K of PL PCIE block registers. */
7652 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7653 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7654
7655 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7656 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7657 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7658
7659 tw32(GRC_MODE, grc_mode);
7660 }
7661
7662 /* This works around an issue with Athlon chipsets on
7663 * B3 tigon3 silicon. This bit has no effect on any
7664 * other revision. But do not set this on PCI Express
7665 * chips and don't even touch the clocks if the CPMU is present.
7666 */
7667 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7668 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7669 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7670 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7671 }
7672
7673 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7674 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7675 val = tr32(TG3PCI_PCISTATE);
7676 val |= PCISTATE_RETRY_SAME_DMA;
7677 tw32(TG3PCI_PCISTATE, val);
7678 }
7679
7680 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7681 /* Allow reads and writes to the
7682 * APE register and memory space.
7683 */
7684 val = tr32(TG3PCI_PCISTATE);
7685 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7686 PCISTATE_ALLOW_APE_SHMEM_WR;
7687 tw32(TG3PCI_PCISTATE, val);
7688 }
7689
7690 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7691 /* Enable some hw fixes. */
7692 val = tr32(TG3PCI_MSI_DATA);
7693 val |= (1 << 26) | (1 << 28) | (1 << 29);
7694 tw32(TG3PCI_MSI_DATA, val);
7695 }
7696
7697 /* Descriptor ring init may make accesses to the
7698 * NIC SRAM area to setup the TX descriptors, so we
7699 * can only do this after the hardware has been
7700 * successfully reset.
7701 */
7702 err = tg3_init_rings(tp);
7703 if (err)
7704 return err;
7705
7706 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7707 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7708 val = tr32(TG3PCI_DMA_RW_CTRL) &
7709 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7710 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7711 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7712 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7713 /* This value is determined during the probe time DMA
7714 * engine test, tg3_test_dma.
7715 */
7716 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7717 }
7718
7719 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7720 GRC_MODE_4X_NIC_SEND_RINGS |
7721 GRC_MODE_NO_TX_PHDR_CSUM |
7722 GRC_MODE_NO_RX_PHDR_CSUM);
7723 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7724
7725 /* Pseudo-header checksum is done by hardware logic and not
7726 * the offload processers, so make the chip do the pseudo-
7727 * header checksums on receive. For transmit it is more
7728 * convenient to do the pseudo-header checksum in software
7729 * as Linux does that on transmit for us in all cases.
7730 */
7731 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7732
7733 tw32(GRC_MODE,
7734 tp->grc_mode |
7735 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7736
7737 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7738 val = tr32(GRC_MISC_CFG);
7739 val &= ~0xff;
7740 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7741 tw32(GRC_MISC_CFG, val);
7742
7743 /* Initialize MBUF/DESC pool. */
7744 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7745 /* Do nothing. */
7746 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7747 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7748 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7749 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7750 else
7751 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7752 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7753 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7754 }
7755 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7756 int fw_len;
7757
7758 fw_len = tp->fw_len;
7759 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7760 tw32(BUFMGR_MB_POOL_ADDR,
7761 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7762 tw32(BUFMGR_MB_POOL_SIZE,
7763 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7764 }
7765
7766 if (tp->dev->mtu <= ETH_DATA_LEN) {
7767 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7768 tp->bufmgr_config.mbuf_read_dma_low_water);
7769 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7770 tp->bufmgr_config.mbuf_mac_rx_low_water);
7771 tw32(BUFMGR_MB_HIGH_WATER,
7772 tp->bufmgr_config.mbuf_high_water);
7773 } else {
7774 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7775 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7776 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7777 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7778 tw32(BUFMGR_MB_HIGH_WATER,
7779 tp->bufmgr_config.mbuf_high_water_jumbo);
7780 }
7781 tw32(BUFMGR_DMA_LOW_WATER,
7782 tp->bufmgr_config.dma_low_water);
7783 tw32(BUFMGR_DMA_HIGH_WATER,
7784 tp->bufmgr_config.dma_high_water);
7785
7786 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7787 for (i = 0; i < 2000; i++) {
7788 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7789 break;
7790 udelay(10);
7791 }
7792 if (i >= 2000) {
7793 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7794 tp->dev->name);
7795 return -ENODEV;
7796 }
7797
7798 /* Setup replenish threshold. */
7799 val = tp->rx_pending / 8;
7800 if (val == 0)
7801 val = 1;
7802 else if (val > tp->rx_std_max_post)
7803 val = tp->rx_std_max_post;
7804 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7805 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7806 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7807
7808 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7809 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7810 }
7811
7812 tw32(RCVBDI_STD_THRESH, val);
7813
7814 /* Initialize TG3_BDINFO's at:
7815 * RCVDBDI_STD_BD: standard eth size rx ring
7816 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7817 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7818 *
7819 * like so:
7820 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7821 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7822 * ring attribute flags
7823 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7824 *
7825 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7826 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7827 *
7828 * The size of each ring is fixed in the firmware, but the location is
7829 * configurable.
7830 */
7831 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7832 ((u64) tpr->rx_std_mapping >> 32));
7833 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7834 ((u64) tpr->rx_std_mapping & 0xffffffff));
7835 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7836 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7837 NIC_SRAM_RX_BUFFER_DESC);
7838
7839 /* Disable the mini ring */
7840 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7841 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7842 BDINFO_FLAGS_DISABLED);
7843
7844 /* Program the jumbo buffer descriptor ring control
7845 * blocks on those devices that have them.
7846 */
7847 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7848 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7849 /* Setup replenish threshold. */
7850 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7851
7852 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7853 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7854 ((u64) tpr->rx_jmb_mapping >> 32));
7855 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7856 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7857 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7858 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7859 BDINFO_FLAGS_USE_EXT_RECV);
7860 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7861 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7862 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7863 } else {
7864 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7865 BDINFO_FLAGS_DISABLED);
7866 }
7867
7868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7869 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7870 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7871 (RX_STD_MAX_SIZE << 2);
7872 else
7873 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7874 } else
7875 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7876
7877 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7878
7879 tpr->rx_std_prod_idx = tp->rx_pending;
7880 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7881
7882 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7883 tp->rx_jumbo_pending : 0;
7884 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7885
7886 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7887 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7888 tw32(STD_REPLENISH_LWM, 32);
7889 tw32(JMB_REPLENISH_LWM, 16);
7890 }
7891
7892 tg3_rings_reset(tp);
7893
7894 /* Initialize MAC address and backoff seed. */
7895 __tg3_set_mac_addr(tp, 0);
7896
7897 /* MTU + ethernet header + FCS + optional VLAN tag */
7898 tw32(MAC_RX_MTU_SIZE,
7899 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7900
7901 /* The slot time is changed by tg3_setup_phy if we
7902 * run at gigabit with half duplex.
7903 */
7904 tw32(MAC_TX_LENGTHS,
7905 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7906 (6 << TX_LENGTHS_IPG_SHIFT) |
7907 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7908
7909 /* Receive rules. */
7910 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7911 tw32(RCVLPC_CONFIG, 0x0181);
7912
7913 /* Calculate RDMAC_MODE setting early, we need it to determine
7914 * the RCVLPC_STATE_ENABLE mask.
7915 */
7916 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7917 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7918 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7919 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7920 RDMAC_MODE_LNGREAD_ENAB);
7921
7922 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7923 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7924
7925 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7926 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7927 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7928 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7929 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7930 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7931
7932 /* If statement applies to 5705 and 5750 PCI devices only */
7933 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7934 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7935 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7936 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7937 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7938 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7939 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7940 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7941 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7942 }
7943 }
7944
7945 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7946 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7947
7948 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7949 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7950
7951 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7952 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7954 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7955
7956 /* Receive/send statistics. */
7957 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7958 val = tr32(RCVLPC_STATS_ENABLE);
7959 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7960 tw32(RCVLPC_STATS_ENABLE, val);
7961 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7962 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7963 val = tr32(RCVLPC_STATS_ENABLE);
7964 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7965 tw32(RCVLPC_STATS_ENABLE, val);
7966 } else {
7967 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7968 }
7969 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7970 tw32(SNDDATAI_STATSENAB, 0xffffff);
7971 tw32(SNDDATAI_STATSCTRL,
7972 (SNDDATAI_SCTRL_ENABLE |
7973 SNDDATAI_SCTRL_FASTUPD));
7974
7975 /* Setup host coalescing engine. */
7976 tw32(HOSTCC_MODE, 0);
7977 for (i = 0; i < 2000; i++) {
7978 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7979 break;
7980 udelay(10);
7981 }
7982
7983 __tg3_set_coalesce(tp, &tp->coal);
7984
7985 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7986 /* Status/statistics block address. See tg3_timer,
7987 * the tg3_periodic_fetch_stats call there, and
7988 * tg3_get_stats to see how this works for 5705/5750 chips.
7989 */
7990 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7991 ((u64) tp->stats_mapping >> 32));
7992 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7993 ((u64) tp->stats_mapping & 0xffffffff));
7994 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7995
7996 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7997
7998 /* Clear statistics and status block memory areas */
7999 for (i = NIC_SRAM_STATS_BLK;
8000 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8001 i += sizeof(u32)) {
8002 tg3_write_mem(tp, i, 0);
8003 udelay(40);
8004 }
8005 }
8006
8007 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8008
8009 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8010 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8011 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8012 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8013
8014 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8015 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8016 /* reset to prevent losing 1st rx packet intermittently */
8017 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8018 udelay(10);
8019 }
8020
8021 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8022 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8023 else
8024 tp->mac_mode = 0;
8025 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8026 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8027 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8028 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8029 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8030 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8031 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8032 udelay(40);
8033
8034 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8035 * If TG3_FLG2_IS_NIC is zero, we should read the
8036 * register to preserve the GPIO settings for LOMs. The GPIOs,
8037 * whether used as inputs or outputs, are set by boot code after
8038 * reset.
8039 */
8040 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8041 u32 gpio_mask;
8042
8043 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8044 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8045 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8046
8047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8048 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8049 GRC_LCLCTRL_GPIO_OUTPUT3;
8050
8051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8052 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8053
8054 tp->grc_local_ctrl &= ~gpio_mask;
8055 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8056
8057 /* GPIO1 must be driven high for eeprom write protect */
8058 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8059 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8060 GRC_LCLCTRL_GPIO_OUTPUT1);
8061 }
8062 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8063 udelay(100);
8064
8065 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8066 val = tr32(MSGINT_MODE);
8067 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8068 tw32(MSGINT_MODE, val);
8069 }
8070
8071 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8072 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8073 udelay(40);
8074 }
8075
8076 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8077 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8078 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8079 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8080 WDMAC_MODE_LNGREAD_ENAB);
8081
8082 /* If statement applies to 5705 and 5750 PCI devices only */
8083 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8084 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8086 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8087 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8088 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8089 /* nothing */
8090 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8091 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8092 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8093 val |= WDMAC_MODE_RX_ACCEL;
8094 }
8095 }
8096
8097 /* Enable host coalescing bug fix */
8098 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8099 val |= WDMAC_MODE_STATUS_TAG_FIX;
8100
8101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8102 val |= WDMAC_MODE_BURST_ALL_DATA;
8103
8104 tw32_f(WDMAC_MODE, val);
8105 udelay(40);
8106
8107 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8108 u16 pcix_cmd;
8109
8110 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8111 &pcix_cmd);
8112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8113 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8114 pcix_cmd |= PCI_X_CMD_READ_2K;
8115 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8116 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8117 pcix_cmd |= PCI_X_CMD_READ_2K;
8118 }
8119 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8120 pcix_cmd);
8121 }
8122
8123 tw32_f(RDMAC_MODE, rdmac_mode);
8124 udelay(40);
8125
8126 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8127 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8128 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8129
8130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8131 tw32(SNDDATAC_MODE,
8132 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8133 else
8134 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8135
8136 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8137 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8138 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8139 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8140 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8141 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8142 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8143 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8144 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8145 tw32(SNDBDI_MODE, val);
8146 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8147
8148 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8149 err = tg3_load_5701_a0_firmware_fix(tp);
8150 if (err)
8151 return err;
8152 }
8153
8154 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8155 err = tg3_load_tso_firmware(tp);
8156 if (err)
8157 return err;
8158 }
8159
8160 tp->tx_mode = TX_MODE_ENABLE;
8161 tw32_f(MAC_TX_MODE, tp->tx_mode);
8162 udelay(100);
8163
8164 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8165 u32 reg = MAC_RSS_INDIR_TBL_0;
8166 u8 *ent = (u8 *)&val;
8167
8168 /* Setup the indirection table */
8169 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8170 int idx = i % sizeof(val);
8171
8172 ent[idx] = i % (tp->irq_cnt - 1);
8173 if (idx == sizeof(val) - 1) {
8174 tw32(reg, val);
8175 reg += 4;
8176 }
8177 }
8178
8179 /* Setup the "secret" hash key. */
8180 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8181 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8182 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8183 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8184 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8185 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8186 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8187 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8188 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8189 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8190 }
8191
8192 tp->rx_mode = RX_MODE_ENABLE;
8193 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8194 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8195
8196 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8197 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8198 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8199 RX_MODE_RSS_IPV6_HASH_EN |
8200 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8201 RX_MODE_RSS_IPV4_HASH_EN |
8202 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8203
8204 tw32_f(MAC_RX_MODE, tp->rx_mode);
8205 udelay(10);
8206
8207 tw32(MAC_LED_CTRL, tp->led_ctrl);
8208
8209 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8210 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8211 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8212 udelay(10);
8213 }
8214 tw32_f(MAC_RX_MODE, tp->rx_mode);
8215 udelay(10);
8216
8217 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8218 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8219 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8220 /* Set drive transmission level to 1.2V */
8221 /* only if the signal pre-emphasis bit is not set */
8222 val = tr32(MAC_SERDES_CFG);
8223 val &= 0xfffff000;
8224 val |= 0x880;
8225 tw32(MAC_SERDES_CFG, val);
8226 }
8227 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8228 tw32(MAC_SERDES_CFG, 0x616000);
8229 }
8230
8231 /* Prevent chip from dropping frames when flow control
8232 * is enabled.
8233 */
8234 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8235 val = 1;
8236 else
8237 val = 2;
8238 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8239
8240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8241 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8242 /* Use hardware link auto-negotiation */
8243 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8244 }
8245
8246 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8247 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8248 u32 tmp;
8249
8250 tmp = tr32(SERDES_RX_CTRL);
8251 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8252 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8253 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8254 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8255 }
8256
8257 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8258 if (tp->link_config.phy_is_low_power) {
8259 tp->link_config.phy_is_low_power = 0;
8260 tp->link_config.speed = tp->link_config.orig_speed;
8261 tp->link_config.duplex = tp->link_config.orig_duplex;
8262 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8263 }
8264
8265 err = tg3_setup_phy(tp, 0);
8266 if (err)
8267 return err;
8268
8269 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8270 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8271 u32 tmp;
8272
8273 /* Clear CRC stats. */
8274 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8275 tg3_writephy(tp, MII_TG3_TEST1,
8276 tmp | MII_TG3_TEST1_CRC_EN);
8277 tg3_readphy(tp, 0x14, &tmp);
8278 }
8279 }
8280 }
8281
8282 __tg3_set_rx_mode(tp->dev);
8283
8284 /* Initialize receive rules. */
8285 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8286 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8287 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8288 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8289
8290 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8291 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8292 limit = 8;
8293 else
8294 limit = 16;
8295 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8296 limit -= 4;
8297 switch (limit) {
8298 case 16:
8299 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8300 case 15:
8301 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8302 case 14:
8303 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8304 case 13:
8305 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8306 case 12:
8307 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8308 case 11:
8309 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8310 case 10:
8311 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8312 case 9:
8313 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8314 case 8:
8315 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8316 case 7:
8317 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8318 case 6:
8319 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8320 case 5:
8321 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8322 case 4:
8323 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8324 case 3:
8325 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8326 case 2:
8327 case 1:
8328
8329 default:
8330 break;
8331 }
8332
8333 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8334 /* Write our heartbeat update interval to APE. */
8335 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8336 APE_HOST_HEARTBEAT_INT_DISABLE);
8337
8338 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8339
8340 return 0;
8341 }
8342
8343 /* Called at device open time to get the chip ready for
8344 * packet processing. Invoked with tp->lock held.
8345 */
8346 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8347 {
8348 tg3_switch_clocks(tp);
8349
8350 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8351
8352 return tg3_reset_hw(tp, reset_phy);
8353 }
8354
8355 #define TG3_STAT_ADD32(PSTAT, REG) \
8356 do { u32 __val = tr32(REG); \
8357 (PSTAT)->low += __val; \
8358 if ((PSTAT)->low < __val) \
8359 (PSTAT)->high += 1; \
8360 } while (0)
8361
8362 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8363 {
8364 struct tg3_hw_stats *sp = tp->hw_stats;
8365
8366 if (!netif_carrier_ok(tp->dev))
8367 return;
8368
8369 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8370 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8371 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8372 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8373 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8374 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8375 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8376 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8377 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8378 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8379 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8380 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8381 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8382
8383 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8384 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8385 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8386 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8387 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8388 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8389 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8390 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8391 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8392 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8393 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8394 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8395 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8396 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8397
8398 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8399 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8400 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8401 }
8402
8403 static void tg3_timer(unsigned long __opaque)
8404 {
8405 struct tg3 *tp = (struct tg3 *) __opaque;
8406
8407 if (tp->irq_sync)
8408 goto restart_timer;
8409
8410 spin_lock(&tp->lock);
8411
8412 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8413 /* All of this garbage is because when using non-tagged
8414 * IRQ status the mailbox/status_block protocol the chip
8415 * uses with the cpu is race prone.
8416 */
8417 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8418 tw32(GRC_LOCAL_CTRL,
8419 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8420 } else {
8421 tw32(HOSTCC_MODE, tp->coalesce_mode |
8422 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8423 }
8424
8425 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8426 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8427 spin_unlock(&tp->lock);
8428 schedule_work(&tp->reset_task);
8429 return;
8430 }
8431 }
8432
8433 /* This part only runs once per second. */
8434 if (!--tp->timer_counter) {
8435 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8436 tg3_periodic_fetch_stats(tp);
8437
8438 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8439 u32 mac_stat;
8440 int phy_event;
8441
8442 mac_stat = tr32(MAC_STATUS);
8443
8444 phy_event = 0;
8445 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8446 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8447 phy_event = 1;
8448 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8449 phy_event = 1;
8450
8451 if (phy_event)
8452 tg3_setup_phy(tp, 0);
8453 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8454 u32 mac_stat = tr32(MAC_STATUS);
8455 int need_setup = 0;
8456
8457 if (netif_carrier_ok(tp->dev) &&
8458 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8459 need_setup = 1;
8460 }
8461 if (! netif_carrier_ok(tp->dev) &&
8462 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8463 MAC_STATUS_SIGNAL_DET))) {
8464 need_setup = 1;
8465 }
8466 if (need_setup) {
8467 if (!tp->serdes_counter) {
8468 tw32_f(MAC_MODE,
8469 (tp->mac_mode &
8470 ~MAC_MODE_PORT_MODE_MASK));
8471 udelay(40);
8472 tw32_f(MAC_MODE, tp->mac_mode);
8473 udelay(40);
8474 }
8475 tg3_setup_phy(tp, 0);
8476 }
8477 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8478 tg3_serdes_parallel_detect(tp);
8479
8480 tp->timer_counter = tp->timer_multiplier;
8481 }
8482
8483 /* Heartbeat is only sent once every 2 seconds.
8484 *
8485 * The heartbeat is to tell the ASF firmware that the host
8486 * driver is still alive. In the event that the OS crashes,
8487 * ASF needs to reset the hardware to free up the FIFO space
8488 * that may be filled with rx packets destined for the host.
8489 * If the FIFO is full, ASF will no longer function properly.
8490 *
8491 * Unintended resets have been reported on real time kernels
8492 * where the timer doesn't run on time. Netpoll will also have
8493 * same problem.
8494 *
8495 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8496 * to check the ring condition when the heartbeat is expiring
8497 * before doing the reset. This will prevent most unintended
8498 * resets.
8499 */
8500 if (!--tp->asf_counter) {
8501 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8502 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8503 tg3_wait_for_event_ack(tp);
8504
8505 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8506 FWCMD_NICDRV_ALIVE3);
8507 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8508 /* 5 seconds timeout */
8509 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8510
8511 tg3_generate_fw_event(tp);
8512 }
8513 tp->asf_counter = tp->asf_multiplier;
8514 }
8515
8516 spin_unlock(&tp->lock);
8517
8518 restart_timer:
8519 tp->timer.expires = jiffies + tp->timer_offset;
8520 add_timer(&tp->timer);
8521 }
8522
8523 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8524 {
8525 irq_handler_t fn;
8526 unsigned long flags;
8527 char *name;
8528 struct tg3_napi *tnapi = &tp->napi[irq_num];
8529
8530 if (tp->irq_cnt == 1)
8531 name = tp->dev->name;
8532 else {
8533 name = &tnapi->irq_lbl[0];
8534 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8535 name[IFNAMSIZ-1] = 0;
8536 }
8537
8538 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8539 fn = tg3_msi;
8540 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8541 fn = tg3_msi_1shot;
8542 flags = IRQF_SAMPLE_RANDOM;
8543 } else {
8544 fn = tg3_interrupt;
8545 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8546 fn = tg3_interrupt_tagged;
8547 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8548 }
8549
8550 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8551 }
8552
8553 static int tg3_test_interrupt(struct tg3 *tp)
8554 {
8555 struct tg3_napi *tnapi = &tp->napi[0];
8556 struct net_device *dev = tp->dev;
8557 int err, i, intr_ok = 0;
8558 u32 val;
8559
8560 if (!netif_running(dev))
8561 return -ENODEV;
8562
8563 tg3_disable_ints(tp);
8564
8565 free_irq(tnapi->irq_vec, tnapi);
8566
8567 /*
8568 * Turn off MSI one shot mode. Otherwise this test has no
8569 * observable way to know whether the interrupt was delivered.
8570 */
8571 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8573 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8574 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8575 tw32(MSGINT_MODE, val);
8576 }
8577
8578 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8579 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8580 if (err)
8581 return err;
8582
8583 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8584 tg3_enable_ints(tp);
8585
8586 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8587 tnapi->coal_now);
8588
8589 for (i = 0; i < 5; i++) {
8590 u32 int_mbox, misc_host_ctrl;
8591
8592 int_mbox = tr32_mailbox(tnapi->int_mbox);
8593 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8594
8595 if ((int_mbox != 0) ||
8596 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8597 intr_ok = 1;
8598 break;
8599 }
8600
8601 msleep(10);
8602 }
8603
8604 tg3_disable_ints(tp);
8605
8606 free_irq(tnapi->irq_vec, tnapi);
8607
8608 err = tg3_request_irq(tp, 0);
8609
8610 if (err)
8611 return err;
8612
8613 if (intr_ok) {
8614 /* Reenable MSI one shot mode. */
8615 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8616 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8617 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8618 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8619 tw32(MSGINT_MODE, val);
8620 }
8621 return 0;
8622 }
8623
8624 return -EIO;
8625 }
8626
8627 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8628 * successfully restored
8629 */
8630 static int tg3_test_msi(struct tg3 *tp)
8631 {
8632 int err;
8633 u16 pci_cmd;
8634
8635 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8636 return 0;
8637
8638 /* Turn off SERR reporting in case MSI terminates with Master
8639 * Abort.
8640 */
8641 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8642 pci_write_config_word(tp->pdev, PCI_COMMAND,
8643 pci_cmd & ~PCI_COMMAND_SERR);
8644
8645 err = tg3_test_interrupt(tp);
8646
8647 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8648
8649 if (!err)
8650 return 0;
8651
8652 /* other failures */
8653 if (err != -EIO)
8654 return err;
8655
8656 /* MSI test failed, go back to INTx mode */
8657 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8658 "switching to INTx mode. Please report this failure to "
8659 "the PCI maintainer and include system chipset information.\n",
8660 tp->dev->name);
8661
8662 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8663
8664 pci_disable_msi(tp->pdev);
8665
8666 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8667
8668 err = tg3_request_irq(tp, 0);
8669 if (err)
8670 return err;
8671
8672 /* Need to reset the chip because the MSI cycle may have terminated
8673 * with Master Abort.
8674 */
8675 tg3_full_lock(tp, 1);
8676
8677 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8678 err = tg3_init_hw(tp, 1);
8679
8680 tg3_full_unlock(tp);
8681
8682 if (err)
8683 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8684
8685 return err;
8686 }
8687
8688 static int tg3_request_firmware(struct tg3 *tp)
8689 {
8690 const __be32 *fw_data;
8691
8692 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8693 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8694 tp->dev->name, tp->fw_needed);
8695 return -ENOENT;
8696 }
8697
8698 fw_data = (void *)tp->fw->data;
8699
8700 /* Firmware blob starts with version numbers, followed by
8701 * start address and _full_ length including BSS sections
8702 * (which must be longer than the actual data, of course
8703 */
8704
8705 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8706 if (tp->fw_len < (tp->fw->size - 12)) {
8707 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8708 tp->dev->name, tp->fw_len, tp->fw_needed);
8709 release_firmware(tp->fw);
8710 tp->fw = NULL;
8711 return -EINVAL;
8712 }
8713
8714 /* We no longer need firmware; we have it. */
8715 tp->fw_needed = NULL;
8716 return 0;
8717 }
8718
8719 static bool tg3_enable_msix(struct tg3 *tp)
8720 {
8721 int i, rc, cpus = num_online_cpus();
8722 struct msix_entry msix_ent[tp->irq_max];
8723
8724 if (cpus == 1)
8725 /* Just fallback to the simpler MSI mode. */
8726 return false;
8727
8728 /*
8729 * We want as many rx rings enabled as there are cpus.
8730 * The first MSIX vector only deals with link interrupts, etc,
8731 * so we add one to the number of vectors we are requesting.
8732 */
8733 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8734
8735 for (i = 0; i < tp->irq_max; i++) {
8736 msix_ent[i].entry = i;
8737 msix_ent[i].vector = 0;
8738 }
8739
8740 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8741 if (rc != 0) {
8742 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8743 return false;
8744 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8745 return false;
8746 printk(KERN_NOTICE
8747 "%s: Requested %d MSI-X vectors, received %d\n",
8748 tp->dev->name, tp->irq_cnt, rc);
8749 tp->irq_cnt = rc;
8750 }
8751
8752 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8753
8754 for (i = 0; i < tp->irq_max; i++)
8755 tp->napi[i].irq_vec = msix_ent[i].vector;
8756
8757 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8758 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8759 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8760 } else
8761 tp->dev->real_num_tx_queues = 1;
8762
8763 return true;
8764 }
8765
8766 static void tg3_ints_init(struct tg3 *tp)
8767 {
8768 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8769 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8770 /* All MSI supporting chips should support tagged
8771 * status. Assert that this is the case.
8772 */
8773 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8774 "Not using MSI.\n", tp->dev->name);
8775 goto defcfg;
8776 }
8777
8778 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8779 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8780 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8781 pci_enable_msi(tp->pdev) == 0)
8782 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8783
8784 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8785 u32 msi_mode = tr32(MSGINT_MODE);
8786 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8787 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8788 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8789 }
8790 defcfg:
8791 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8792 tp->irq_cnt = 1;
8793 tp->napi[0].irq_vec = tp->pdev->irq;
8794 tp->dev->real_num_tx_queues = 1;
8795 }
8796 }
8797
8798 static void tg3_ints_fini(struct tg3 *tp)
8799 {
8800 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8801 pci_disable_msix(tp->pdev);
8802 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8803 pci_disable_msi(tp->pdev);
8804 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8805 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8806 }
8807
8808 static int tg3_open(struct net_device *dev)
8809 {
8810 struct tg3 *tp = netdev_priv(dev);
8811 int i, err;
8812
8813 if (tp->fw_needed) {
8814 err = tg3_request_firmware(tp);
8815 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8816 if (err)
8817 return err;
8818 } else if (err) {
8819 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8820 tp->dev->name);
8821 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8822 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8823 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8824 tp->dev->name);
8825 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8826 }
8827 }
8828
8829 netif_carrier_off(tp->dev);
8830
8831 err = tg3_set_power_state(tp, PCI_D0);
8832 if (err)
8833 return err;
8834
8835 tg3_full_lock(tp, 0);
8836
8837 tg3_disable_ints(tp);
8838 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8839
8840 tg3_full_unlock(tp);
8841
8842 /*
8843 * Setup interrupts first so we know how
8844 * many NAPI resources to allocate
8845 */
8846 tg3_ints_init(tp);
8847
8848 /* The placement of this call is tied
8849 * to the setup and use of Host TX descriptors.
8850 */
8851 err = tg3_alloc_consistent(tp);
8852 if (err)
8853 goto err_out1;
8854
8855 tg3_napi_enable(tp);
8856
8857 for (i = 0; i < tp->irq_cnt; i++) {
8858 struct tg3_napi *tnapi = &tp->napi[i];
8859 err = tg3_request_irq(tp, i);
8860 if (err) {
8861 for (i--; i >= 0; i--)
8862 free_irq(tnapi->irq_vec, tnapi);
8863 break;
8864 }
8865 }
8866
8867 if (err)
8868 goto err_out2;
8869
8870 tg3_full_lock(tp, 0);
8871
8872 err = tg3_init_hw(tp, 1);
8873 if (err) {
8874 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8875 tg3_free_rings(tp);
8876 } else {
8877 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8878 tp->timer_offset = HZ;
8879 else
8880 tp->timer_offset = HZ / 10;
8881
8882 BUG_ON(tp->timer_offset > HZ);
8883 tp->timer_counter = tp->timer_multiplier =
8884 (HZ / tp->timer_offset);
8885 tp->asf_counter = tp->asf_multiplier =
8886 ((HZ / tp->timer_offset) * 2);
8887
8888 init_timer(&tp->timer);
8889 tp->timer.expires = jiffies + tp->timer_offset;
8890 tp->timer.data = (unsigned long) tp;
8891 tp->timer.function = tg3_timer;
8892 }
8893
8894 tg3_full_unlock(tp);
8895
8896 if (err)
8897 goto err_out3;
8898
8899 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8900 err = tg3_test_msi(tp);
8901
8902 if (err) {
8903 tg3_full_lock(tp, 0);
8904 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8905 tg3_free_rings(tp);
8906 tg3_full_unlock(tp);
8907
8908 goto err_out2;
8909 }
8910
8911 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8912 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8913 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8914 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8915 u32 val = tr32(PCIE_TRANSACTION_CFG);
8916
8917 tw32(PCIE_TRANSACTION_CFG,
8918 val | PCIE_TRANS_CFG_1SHOT_MSI);
8919 }
8920 }
8921
8922 tg3_phy_start(tp);
8923
8924 tg3_full_lock(tp, 0);
8925
8926 add_timer(&tp->timer);
8927 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8928 tg3_enable_ints(tp);
8929
8930 tg3_full_unlock(tp);
8931
8932 netif_tx_start_all_queues(dev);
8933
8934 return 0;
8935
8936 err_out3:
8937 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8938 struct tg3_napi *tnapi = &tp->napi[i];
8939 free_irq(tnapi->irq_vec, tnapi);
8940 }
8941
8942 err_out2:
8943 tg3_napi_disable(tp);
8944 tg3_free_consistent(tp);
8945
8946 err_out1:
8947 tg3_ints_fini(tp);
8948 return err;
8949 }
8950
8951 #if 0
8952 /*static*/ void tg3_dump_state(struct tg3 *tp)
8953 {
8954 u32 val32, val32_2, val32_3, val32_4, val32_5;
8955 u16 val16;
8956 int i;
8957 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8958
8959 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8960 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8961 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8962 val16, val32);
8963
8964 /* MAC block */
8965 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8966 tr32(MAC_MODE), tr32(MAC_STATUS));
8967 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8968 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8969 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8970 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8971 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8972 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8973
8974 /* Send data initiator control block */
8975 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8976 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8977 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8978 tr32(SNDDATAI_STATSCTRL));
8979
8980 /* Send data completion control block */
8981 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8982
8983 /* Send BD ring selector block */
8984 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8985 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8986
8987 /* Send BD initiator control block */
8988 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8989 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8990
8991 /* Send BD completion control block */
8992 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8993
8994 /* Receive list placement control block */
8995 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8996 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8997 printk(" RCVLPC_STATSCTRL[%08x]\n",
8998 tr32(RCVLPC_STATSCTRL));
8999
9000 /* Receive data and receive BD initiator control block */
9001 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
9002 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
9003
9004 /* Receive data completion control block */
9005 printk("DEBUG: RCVDCC_MODE[%08x]\n",
9006 tr32(RCVDCC_MODE));
9007
9008 /* Receive BD initiator control block */
9009 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
9010 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
9011
9012 /* Receive BD completion control block */
9013 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
9014 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
9015
9016 /* Receive list selector control block */
9017 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
9018 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
9019
9020 /* Mbuf cluster free block */
9021 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
9022 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
9023
9024 /* Host coalescing control block */
9025 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
9026 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
9027 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
9028 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9029 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9030 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
9031 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9032 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9033 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9034 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9035 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9036 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9037
9038 /* Memory arbiter control block */
9039 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9040 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9041
9042 /* Buffer manager control block */
9043 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9044 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9045 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9046 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9047 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9048 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9049 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9050 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9051
9052 /* Read DMA control block */
9053 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9054 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9055
9056 /* Write DMA control block */
9057 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9058 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9059
9060 /* DMA completion block */
9061 printk("DEBUG: DMAC_MODE[%08x]\n",
9062 tr32(DMAC_MODE));
9063
9064 /* GRC block */
9065 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9066 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9067 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9068 tr32(GRC_LOCAL_CTRL));
9069
9070 /* TG3_BDINFOs */
9071 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9072 tr32(RCVDBDI_JUMBO_BD + 0x0),
9073 tr32(RCVDBDI_JUMBO_BD + 0x4),
9074 tr32(RCVDBDI_JUMBO_BD + 0x8),
9075 tr32(RCVDBDI_JUMBO_BD + 0xc));
9076 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9077 tr32(RCVDBDI_STD_BD + 0x0),
9078 tr32(RCVDBDI_STD_BD + 0x4),
9079 tr32(RCVDBDI_STD_BD + 0x8),
9080 tr32(RCVDBDI_STD_BD + 0xc));
9081 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9082 tr32(RCVDBDI_MINI_BD + 0x0),
9083 tr32(RCVDBDI_MINI_BD + 0x4),
9084 tr32(RCVDBDI_MINI_BD + 0x8),
9085 tr32(RCVDBDI_MINI_BD + 0xc));
9086
9087 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9088 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9089 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9090 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9091 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9092 val32, val32_2, val32_3, val32_4);
9093
9094 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9095 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9096 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9097 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9098 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9099 val32, val32_2, val32_3, val32_4);
9100
9101 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9102 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9103 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9104 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9105 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9106 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9107 val32, val32_2, val32_3, val32_4, val32_5);
9108
9109 /* SW status block */
9110 printk(KERN_DEBUG
9111 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9112 sblk->status,
9113 sblk->status_tag,
9114 sblk->rx_jumbo_consumer,
9115 sblk->rx_consumer,
9116 sblk->rx_mini_consumer,
9117 sblk->idx[0].rx_producer,
9118 sblk->idx[0].tx_consumer);
9119
9120 /* SW statistics block */
9121 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9122 ((u32 *)tp->hw_stats)[0],
9123 ((u32 *)tp->hw_stats)[1],
9124 ((u32 *)tp->hw_stats)[2],
9125 ((u32 *)tp->hw_stats)[3]);
9126
9127 /* Mailboxes */
9128 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9129 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9130 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9131 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9132 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9133
9134 /* NIC side send descriptors. */
9135 for (i = 0; i < 6; i++) {
9136 unsigned long txd;
9137
9138 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9139 + (i * sizeof(struct tg3_tx_buffer_desc));
9140 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9141 i,
9142 readl(txd + 0x0), readl(txd + 0x4),
9143 readl(txd + 0x8), readl(txd + 0xc));
9144 }
9145
9146 /* NIC side RX descriptors. */
9147 for (i = 0; i < 6; i++) {
9148 unsigned long rxd;
9149
9150 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9151 + (i * sizeof(struct tg3_rx_buffer_desc));
9152 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9153 i,
9154 readl(rxd + 0x0), readl(rxd + 0x4),
9155 readl(rxd + 0x8), readl(rxd + 0xc));
9156 rxd += (4 * sizeof(u32));
9157 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9158 i,
9159 readl(rxd + 0x0), readl(rxd + 0x4),
9160 readl(rxd + 0x8), readl(rxd + 0xc));
9161 }
9162
9163 for (i = 0; i < 6; i++) {
9164 unsigned long rxd;
9165
9166 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9167 + (i * sizeof(struct tg3_rx_buffer_desc));
9168 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9169 i,
9170 readl(rxd + 0x0), readl(rxd + 0x4),
9171 readl(rxd + 0x8), readl(rxd + 0xc));
9172 rxd += (4 * sizeof(u32));
9173 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9174 i,
9175 readl(rxd + 0x0), readl(rxd + 0x4),
9176 readl(rxd + 0x8), readl(rxd + 0xc));
9177 }
9178 }
9179 #endif
9180
9181 static struct net_device_stats *tg3_get_stats(struct net_device *);
9182 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9183
9184 static int tg3_close(struct net_device *dev)
9185 {
9186 int i;
9187 struct tg3 *tp = netdev_priv(dev);
9188
9189 tg3_napi_disable(tp);
9190 cancel_work_sync(&tp->reset_task);
9191
9192 netif_tx_stop_all_queues(dev);
9193
9194 del_timer_sync(&tp->timer);
9195
9196 tg3_phy_stop(tp);
9197
9198 tg3_full_lock(tp, 1);
9199 #if 0
9200 tg3_dump_state(tp);
9201 #endif
9202
9203 tg3_disable_ints(tp);
9204
9205 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9206 tg3_free_rings(tp);
9207 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9208
9209 tg3_full_unlock(tp);
9210
9211 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9212 struct tg3_napi *tnapi = &tp->napi[i];
9213 free_irq(tnapi->irq_vec, tnapi);
9214 }
9215
9216 tg3_ints_fini(tp);
9217
9218 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9219 sizeof(tp->net_stats_prev));
9220 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9221 sizeof(tp->estats_prev));
9222
9223 tg3_free_consistent(tp);
9224
9225 tg3_set_power_state(tp, PCI_D3hot);
9226
9227 netif_carrier_off(tp->dev);
9228
9229 return 0;
9230 }
9231
9232 static inline unsigned long get_stat64(tg3_stat64_t *val)
9233 {
9234 unsigned long ret;
9235
9236 #if (BITS_PER_LONG == 32)
9237 ret = val->low;
9238 #else
9239 ret = ((u64)val->high << 32) | ((u64)val->low);
9240 #endif
9241 return ret;
9242 }
9243
9244 static inline u64 get_estat64(tg3_stat64_t *val)
9245 {
9246 return ((u64)val->high << 32) | ((u64)val->low);
9247 }
9248
9249 static unsigned long calc_crc_errors(struct tg3 *tp)
9250 {
9251 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9252
9253 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9254 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9255 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9256 u32 val;
9257
9258 spin_lock_bh(&tp->lock);
9259 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9260 tg3_writephy(tp, MII_TG3_TEST1,
9261 val | MII_TG3_TEST1_CRC_EN);
9262 tg3_readphy(tp, 0x14, &val);
9263 } else
9264 val = 0;
9265 spin_unlock_bh(&tp->lock);
9266
9267 tp->phy_crc_errors += val;
9268
9269 return tp->phy_crc_errors;
9270 }
9271
9272 return get_stat64(&hw_stats->rx_fcs_errors);
9273 }
9274
9275 #define ESTAT_ADD(member) \
9276 estats->member = old_estats->member + \
9277 get_estat64(&hw_stats->member)
9278
9279 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9280 {
9281 struct tg3_ethtool_stats *estats = &tp->estats;
9282 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9283 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9284
9285 if (!hw_stats)
9286 return old_estats;
9287
9288 ESTAT_ADD(rx_octets);
9289 ESTAT_ADD(rx_fragments);
9290 ESTAT_ADD(rx_ucast_packets);
9291 ESTAT_ADD(rx_mcast_packets);
9292 ESTAT_ADD(rx_bcast_packets);
9293 ESTAT_ADD(rx_fcs_errors);
9294 ESTAT_ADD(rx_align_errors);
9295 ESTAT_ADD(rx_xon_pause_rcvd);
9296 ESTAT_ADD(rx_xoff_pause_rcvd);
9297 ESTAT_ADD(rx_mac_ctrl_rcvd);
9298 ESTAT_ADD(rx_xoff_entered);
9299 ESTAT_ADD(rx_frame_too_long_errors);
9300 ESTAT_ADD(rx_jabbers);
9301 ESTAT_ADD(rx_undersize_packets);
9302 ESTAT_ADD(rx_in_length_errors);
9303 ESTAT_ADD(rx_out_length_errors);
9304 ESTAT_ADD(rx_64_or_less_octet_packets);
9305 ESTAT_ADD(rx_65_to_127_octet_packets);
9306 ESTAT_ADD(rx_128_to_255_octet_packets);
9307 ESTAT_ADD(rx_256_to_511_octet_packets);
9308 ESTAT_ADD(rx_512_to_1023_octet_packets);
9309 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9310 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9311 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9312 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9313 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9314
9315 ESTAT_ADD(tx_octets);
9316 ESTAT_ADD(tx_collisions);
9317 ESTAT_ADD(tx_xon_sent);
9318 ESTAT_ADD(tx_xoff_sent);
9319 ESTAT_ADD(tx_flow_control);
9320 ESTAT_ADD(tx_mac_errors);
9321 ESTAT_ADD(tx_single_collisions);
9322 ESTAT_ADD(tx_mult_collisions);
9323 ESTAT_ADD(tx_deferred);
9324 ESTAT_ADD(tx_excessive_collisions);
9325 ESTAT_ADD(tx_late_collisions);
9326 ESTAT_ADD(tx_collide_2times);
9327 ESTAT_ADD(tx_collide_3times);
9328 ESTAT_ADD(tx_collide_4times);
9329 ESTAT_ADD(tx_collide_5times);
9330 ESTAT_ADD(tx_collide_6times);
9331 ESTAT_ADD(tx_collide_7times);
9332 ESTAT_ADD(tx_collide_8times);
9333 ESTAT_ADD(tx_collide_9times);
9334 ESTAT_ADD(tx_collide_10times);
9335 ESTAT_ADD(tx_collide_11times);
9336 ESTAT_ADD(tx_collide_12times);
9337 ESTAT_ADD(tx_collide_13times);
9338 ESTAT_ADD(tx_collide_14times);
9339 ESTAT_ADD(tx_collide_15times);
9340 ESTAT_ADD(tx_ucast_packets);
9341 ESTAT_ADD(tx_mcast_packets);
9342 ESTAT_ADD(tx_bcast_packets);
9343 ESTAT_ADD(tx_carrier_sense_errors);
9344 ESTAT_ADD(tx_discards);
9345 ESTAT_ADD(tx_errors);
9346
9347 ESTAT_ADD(dma_writeq_full);
9348 ESTAT_ADD(dma_write_prioq_full);
9349 ESTAT_ADD(rxbds_empty);
9350 ESTAT_ADD(rx_discards);
9351 ESTAT_ADD(rx_errors);
9352 ESTAT_ADD(rx_threshold_hit);
9353
9354 ESTAT_ADD(dma_readq_full);
9355 ESTAT_ADD(dma_read_prioq_full);
9356 ESTAT_ADD(tx_comp_queue_full);
9357
9358 ESTAT_ADD(ring_set_send_prod_index);
9359 ESTAT_ADD(ring_status_update);
9360 ESTAT_ADD(nic_irqs);
9361 ESTAT_ADD(nic_avoided_irqs);
9362 ESTAT_ADD(nic_tx_threshold_hit);
9363
9364 return estats;
9365 }
9366
9367 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9368 {
9369 struct tg3 *tp = netdev_priv(dev);
9370 struct net_device_stats *stats = &tp->net_stats;
9371 struct net_device_stats *old_stats = &tp->net_stats_prev;
9372 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9373
9374 if (!hw_stats)
9375 return old_stats;
9376
9377 stats->rx_packets = old_stats->rx_packets +
9378 get_stat64(&hw_stats->rx_ucast_packets) +
9379 get_stat64(&hw_stats->rx_mcast_packets) +
9380 get_stat64(&hw_stats->rx_bcast_packets);
9381
9382 stats->tx_packets = old_stats->tx_packets +
9383 get_stat64(&hw_stats->tx_ucast_packets) +
9384 get_stat64(&hw_stats->tx_mcast_packets) +
9385 get_stat64(&hw_stats->tx_bcast_packets);
9386
9387 stats->rx_bytes = old_stats->rx_bytes +
9388 get_stat64(&hw_stats->rx_octets);
9389 stats->tx_bytes = old_stats->tx_bytes +
9390 get_stat64(&hw_stats->tx_octets);
9391
9392 stats->rx_errors = old_stats->rx_errors +
9393 get_stat64(&hw_stats->rx_errors);
9394 stats->tx_errors = old_stats->tx_errors +
9395 get_stat64(&hw_stats->tx_errors) +
9396 get_stat64(&hw_stats->tx_mac_errors) +
9397 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9398 get_stat64(&hw_stats->tx_discards);
9399
9400 stats->multicast = old_stats->multicast +
9401 get_stat64(&hw_stats->rx_mcast_packets);
9402 stats->collisions = old_stats->collisions +
9403 get_stat64(&hw_stats->tx_collisions);
9404
9405 stats->rx_length_errors = old_stats->rx_length_errors +
9406 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9407 get_stat64(&hw_stats->rx_undersize_packets);
9408
9409 stats->rx_over_errors = old_stats->rx_over_errors +
9410 get_stat64(&hw_stats->rxbds_empty);
9411 stats->rx_frame_errors = old_stats->rx_frame_errors +
9412 get_stat64(&hw_stats->rx_align_errors);
9413 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9414 get_stat64(&hw_stats->tx_discards);
9415 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9416 get_stat64(&hw_stats->tx_carrier_sense_errors);
9417
9418 stats->rx_crc_errors = old_stats->rx_crc_errors +
9419 calc_crc_errors(tp);
9420
9421 stats->rx_missed_errors = old_stats->rx_missed_errors +
9422 get_stat64(&hw_stats->rx_discards);
9423
9424 return stats;
9425 }
9426
9427 static inline u32 calc_crc(unsigned char *buf, int len)
9428 {
9429 u32 reg;
9430 u32 tmp;
9431 int j, k;
9432
9433 reg = 0xffffffff;
9434
9435 for (j = 0; j < len; j++) {
9436 reg ^= buf[j];
9437
9438 for (k = 0; k < 8; k++) {
9439 tmp = reg & 0x01;
9440
9441 reg >>= 1;
9442
9443 if (tmp) {
9444 reg ^= 0xedb88320;
9445 }
9446 }
9447 }
9448
9449 return ~reg;
9450 }
9451
9452 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9453 {
9454 /* accept or reject all multicast frames */
9455 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9456 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9457 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9458 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9459 }
9460
9461 static void __tg3_set_rx_mode(struct net_device *dev)
9462 {
9463 struct tg3 *tp = netdev_priv(dev);
9464 u32 rx_mode;
9465
9466 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9467 RX_MODE_KEEP_VLAN_TAG);
9468
9469 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9470 * flag clear.
9471 */
9472 #if TG3_VLAN_TAG_USED
9473 if (!tp->vlgrp &&
9474 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9475 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9476 #else
9477 /* By definition, VLAN is disabled always in this
9478 * case.
9479 */
9480 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9481 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9482 #endif
9483
9484 if (dev->flags & IFF_PROMISC) {
9485 /* Promiscuous mode. */
9486 rx_mode |= RX_MODE_PROMISC;
9487 } else if (dev->flags & IFF_ALLMULTI) {
9488 /* Accept all multicast. */
9489 tg3_set_multi (tp, 1);
9490 } else if (netdev_mc_empty(dev)) {
9491 /* Reject all multicast. */
9492 tg3_set_multi (tp, 0);
9493 } else {
9494 /* Accept one or more multicast(s). */
9495 struct dev_mc_list *mclist;
9496 unsigned int i;
9497 u32 mc_filter[4] = { 0, };
9498 u32 regidx;
9499 u32 bit;
9500 u32 crc;
9501
9502 for (i = 0, mclist = dev->mc_list; mclist && i < netdev_mc_count(dev);
9503 i++, mclist = mclist->next) {
9504
9505 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9506 bit = ~crc & 0x7f;
9507 regidx = (bit & 0x60) >> 5;
9508 bit &= 0x1f;
9509 mc_filter[regidx] |= (1 << bit);
9510 }
9511
9512 tw32(MAC_HASH_REG_0, mc_filter[0]);
9513 tw32(MAC_HASH_REG_1, mc_filter[1]);
9514 tw32(MAC_HASH_REG_2, mc_filter[2]);
9515 tw32(MAC_HASH_REG_3, mc_filter[3]);
9516 }
9517
9518 if (rx_mode != tp->rx_mode) {
9519 tp->rx_mode = rx_mode;
9520 tw32_f(MAC_RX_MODE, rx_mode);
9521 udelay(10);
9522 }
9523 }
9524
9525 static void tg3_set_rx_mode(struct net_device *dev)
9526 {
9527 struct tg3 *tp = netdev_priv(dev);
9528
9529 if (!netif_running(dev))
9530 return;
9531
9532 tg3_full_lock(tp, 0);
9533 __tg3_set_rx_mode(dev);
9534 tg3_full_unlock(tp);
9535 }
9536
9537 #define TG3_REGDUMP_LEN (32 * 1024)
9538
9539 static int tg3_get_regs_len(struct net_device *dev)
9540 {
9541 return TG3_REGDUMP_LEN;
9542 }
9543
9544 static void tg3_get_regs(struct net_device *dev,
9545 struct ethtool_regs *regs, void *_p)
9546 {
9547 u32 *p = _p;
9548 struct tg3 *tp = netdev_priv(dev);
9549 u8 *orig_p = _p;
9550 int i;
9551
9552 regs->version = 0;
9553
9554 memset(p, 0, TG3_REGDUMP_LEN);
9555
9556 if (tp->link_config.phy_is_low_power)
9557 return;
9558
9559 tg3_full_lock(tp, 0);
9560
9561 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9562 #define GET_REG32_LOOP(base,len) \
9563 do { p = (u32 *)(orig_p + (base)); \
9564 for (i = 0; i < len; i += 4) \
9565 __GET_REG32((base) + i); \
9566 } while (0)
9567 #define GET_REG32_1(reg) \
9568 do { p = (u32 *)(orig_p + (reg)); \
9569 __GET_REG32((reg)); \
9570 } while (0)
9571
9572 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9573 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9574 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9575 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9576 GET_REG32_1(SNDDATAC_MODE);
9577 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9578 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9579 GET_REG32_1(SNDBDC_MODE);
9580 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9581 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9582 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9583 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9584 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9585 GET_REG32_1(RCVDCC_MODE);
9586 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9587 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9588 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9589 GET_REG32_1(MBFREE_MODE);
9590 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9591 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9592 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9593 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9594 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9595 GET_REG32_1(RX_CPU_MODE);
9596 GET_REG32_1(RX_CPU_STATE);
9597 GET_REG32_1(RX_CPU_PGMCTR);
9598 GET_REG32_1(RX_CPU_HWBKPT);
9599 GET_REG32_1(TX_CPU_MODE);
9600 GET_REG32_1(TX_CPU_STATE);
9601 GET_REG32_1(TX_CPU_PGMCTR);
9602 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9603 GET_REG32_LOOP(FTQ_RESET, 0x120);
9604 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9605 GET_REG32_1(DMAC_MODE);
9606 GET_REG32_LOOP(GRC_MODE, 0x4c);
9607 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9608 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9609
9610 #undef __GET_REG32
9611 #undef GET_REG32_LOOP
9612 #undef GET_REG32_1
9613
9614 tg3_full_unlock(tp);
9615 }
9616
9617 static int tg3_get_eeprom_len(struct net_device *dev)
9618 {
9619 struct tg3 *tp = netdev_priv(dev);
9620
9621 return tp->nvram_size;
9622 }
9623
9624 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9625 {
9626 struct tg3 *tp = netdev_priv(dev);
9627 int ret;
9628 u8 *pd;
9629 u32 i, offset, len, b_offset, b_count;
9630 __be32 val;
9631
9632 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9633 return -EINVAL;
9634
9635 if (tp->link_config.phy_is_low_power)
9636 return -EAGAIN;
9637
9638 offset = eeprom->offset;
9639 len = eeprom->len;
9640 eeprom->len = 0;
9641
9642 eeprom->magic = TG3_EEPROM_MAGIC;
9643
9644 if (offset & 3) {
9645 /* adjustments to start on required 4 byte boundary */
9646 b_offset = offset & 3;
9647 b_count = 4 - b_offset;
9648 if (b_count > len) {
9649 /* i.e. offset=1 len=2 */
9650 b_count = len;
9651 }
9652 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9653 if (ret)
9654 return ret;
9655 memcpy(data, ((char*)&val) + b_offset, b_count);
9656 len -= b_count;
9657 offset += b_count;
9658 eeprom->len += b_count;
9659 }
9660
9661 /* read bytes upto the last 4 byte boundary */
9662 pd = &data[eeprom->len];
9663 for (i = 0; i < (len - (len & 3)); i += 4) {
9664 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9665 if (ret) {
9666 eeprom->len += i;
9667 return ret;
9668 }
9669 memcpy(pd + i, &val, 4);
9670 }
9671 eeprom->len += i;
9672
9673 if (len & 3) {
9674 /* read last bytes not ending on 4 byte boundary */
9675 pd = &data[eeprom->len];
9676 b_count = len & 3;
9677 b_offset = offset + len - b_count;
9678 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9679 if (ret)
9680 return ret;
9681 memcpy(pd, &val, b_count);
9682 eeprom->len += b_count;
9683 }
9684 return 0;
9685 }
9686
9687 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9688
9689 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9690 {
9691 struct tg3 *tp = netdev_priv(dev);
9692 int ret;
9693 u32 offset, len, b_offset, odd_len;
9694 u8 *buf;
9695 __be32 start, end;
9696
9697 if (tp->link_config.phy_is_low_power)
9698 return -EAGAIN;
9699
9700 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9701 eeprom->magic != TG3_EEPROM_MAGIC)
9702 return -EINVAL;
9703
9704 offset = eeprom->offset;
9705 len = eeprom->len;
9706
9707 if ((b_offset = (offset & 3))) {
9708 /* adjustments to start on required 4 byte boundary */
9709 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9710 if (ret)
9711 return ret;
9712 len += b_offset;
9713 offset &= ~3;
9714 if (len < 4)
9715 len = 4;
9716 }
9717
9718 odd_len = 0;
9719 if (len & 3) {
9720 /* adjustments to end on required 4 byte boundary */
9721 odd_len = 1;
9722 len = (len + 3) & ~3;
9723 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9724 if (ret)
9725 return ret;
9726 }
9727
9728 buf = data;
9729 if (b_offset || odd_len) {
9730 buf = kmalloc(len, GFP_KERNEL);
9731 if (!buf)
9732 return -ENOMEM;
9733 if (b_offset)
9734 memcpy(buf, &start, 4);
9735 if (odd_len)
9736 memcpy(buf+len-4, &end, 4);
9737 memcpy(buf + b_offset, data, eeprom->len);
9738 }
9739
9740 ret = tg3_nvram_write_block(tp, offset, len, buf);
9741
9742 if (buf != data)
9743 kfree(buf);
9744
9745 return ret;
9746 }
9747
9748 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9749 {
9750 struct tg3 *tp = netdev_priv(dev);
9751
9752 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9753 struct phy_device *phydev;
9754 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9755 return -EAGAIN;
9756 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9757 return phy_ethtool_gset(phydev, cmd);
9758 }
9759
9760 cmd->supported = (SUPPORTED_Autoneg);
9761
9762 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9763 cmd->supported |= (SUPPORTED_1000baseT_Half |
9764 SUPPORTED_1000baseT_Full);
9765
9766 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9767 cmd->supported |= (SUPPORTED_100baseT_Half |
9768 SUPPORTED_100baseT_Full |
9769 SUPPORTED_10baseT_Half |
9770 SUPPORTED_10baseT_Full |
9771 SUPPORTED_TP);
9772 cmd->port = PORT_TP;
9773 } else {
9774 cmd->supported |= SUPPORTED_FIBRE;
9775 cmd->port = PORT_FIBRE;
9776 }
9777
9778 cmd->advertising = tp->link_config.advertising;
9779 if (netif_running(dev)) {
9780 cmd->speed = tp->link_config.active_speed;
9781 cmd->duplex = tp->link_config.active_duplex;
9782 }
9783 cmd->phy_address = tp->phy_addr;
9784 cmd->transceiver = XCVR_INTERNAL;
9785 cmd->autoneg = tp->link_config.autoneg;
9786 cmd->maxtxpkt = 0;
9787 cmd->maxrxpkt = 0;
9788 return 0;
9789 }
9790
9791 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9792 {
9793 struct tg3 *tp = netdev_priv(dev);
9794
9795 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9796 struct phy_device *phydev;
9797 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9798 return -EAGAIN;
9799 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9800 return phy_ethtool_sset(phydev, cmd);
9801 }
9802
9803 if (cmd->autoneg != AUTONEG_ENABLE &&
9804 cmd->autoneg != AUTONEG_DISABLE)
9805 return -EINVAL;
9806
9807 if (cmd->autoneg == AUTONEG_DISABLE &&
9808 cmd->duplex != DUPLEX_FULL &&
9809 cmd->duplex != DUPLEX_HALF)
9810 return -EINVAL;
9811
9812 if (cmd->autoneg == AUTONEG_ENABLE) {
9813 u32 mask = ADVERTISED_Autoneg |
9814 ADVERTISED_Pause |
9815 ADVERTISED_Asym_Pause;
9816
9817 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9818 mask |= ADVERTISED_1000baseT_Half |
9819 ADVERTISED_1000baseT_Full;
9820
9821 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9822 mask |= ADVERTISED_100baseT_Half |
9823 ADVERTISED_100baseT_Full |
9824 ADVERTISED_10baseT_Half |
9825 ADVERTISED_10baseT_Full |
9826 ADVERTISED_TP;
9827 else
9828 mask |= ADVERTISED_FIBRE;
9829
9830 if (cmd->advertising & ~mask)
9831 return -EINVAL;
9832
9833 mask &= (ADVERTISED_1000baseT_Half |
9834 ADVERTISED_1000baseT_Full |
9835 ADVERTISED_100baseT_Half |
9836 ADVERTISED_100baseT_Full |
9837 ADVERTISED_10baseT_Half |
9838 ADVERTISED_10baseT_Full);
9839
9840 cmd->advertising &= mask;
9841 } else {
9842 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9843 if (cmd->speed != SPEED_1000)
9844 return -EINVAL;
9845
9846 if (cmd->duplex != DUPLEX_FULL)
9847 return -EINVAL;
9848 } else {
9849 if (cmd->speed != SPEED_100 &&
9850 cmd->speed != SPEED_10)
9851 return -EINVAL;
9852 }
9853 }
9854
9855 tg3_full_lock(tp, 0);
9856
9857 tp->link_config.autoneg = cmd->autoneg;
9858 if (cmd->autoneg == AUTONEG_ENABLE) {
9859 tp->link_config.advertising = (cmd->advertising |
9860 ADVERTISED_Autoneg);
9861 tp->link_config.speed = SPEED_INVALID;
9862 tp->link_config.duplex = DUPLEX_INVALID;
9863 } else {
9864 tp->link_config.advertising = 0;
9865 tp->link_config.speed = cmd->speed;
9866 tp->link_config.duplex = cmd->duplex;
9867 }
9868
9869 tp->link_config.orig_speed = tp->link_config.speed;
9870 tp->link_config.orig_duplex = tp->link_config.duplex;
9871 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9872
9873 if (netif_running(dev))
9874 tg3_setup_phy(tp, 1);
9875
9876 tg3_full_unlock(tp);
9877
9878 return 0;
9879 }
9880
9881 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9882 {
9883 struct tg3 *tp = netdev_priv(dev);
9884
9885 strcpy(info->driver, DRV_MODULE_NAME);
9886 strcpy(info->version, DRV_MODULE_VERSION);
9887 strcpy(info->fw_version, tp->fw_ver);
9888 strcpy(info->bus_info, pci_name(tp->pdev));
9889 }
9890
9891 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9892 {
9893 struct tg3 *tp = netdev_priv(dev);
9894
9895 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9896 device_can_wakeup(&tp->pdev->dev))
9897 wol->supported = WAKE_MAGIC;
9898 else
9899 wol->supported = 0;
9900 wol->wolopts = 0;
9901 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9902 device_can_wakeup(&tp->pdev->dev))
9903 wol->wolopts = WAKE_MAGIC;
9904 memset(&wol->sopass, 0, sizeof(wol->sopass));
9905 }
9906
9907 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9908 {
9909 struct tg3 *tp = netdev_priv(dev);
9910 struct device *dp = &tp->pdev->dev;
9911
9912 if (wol->wolopts & ~WAKE_MAGIC)
9913 return -EINVAL;
9914 if ((wol->wolopts & WAKE_MAGIC) &&
9915 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9916 return -EINVAL;
9917
9918 spin_lock_bh(&tp->lock);
9919 if (wol->wolopts & WAKE_MAGIC) {
9920 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9921 device_set_wakeup_enable(dp, true);
9922 } else {
9923 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9924 device_set_wakeup_enable(dp, false);
9925 }
9926 spin_unlock_bh(&tp->lock);
9927
9928 return 0;
9929 }
9930
9931 static u32 tg3_get_msglevel(struct net_device *dev)
9932 {
9933 struct tg3 *tp = netdev_priv(dev);
9934 return tp->msg_enable;
9935 }
9936
9937 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9938 {
9939 struct tg3 *tp = netdev_priv(dev);
9940 tp->msg_enable = value;
9941 }
9942
9943 static int tg3_set_tso(struct net_device *dev, u32 value)
9944 {
9945 struct tg3 *tp = netdev_priv(dev);
9946
9947 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9948 if (value)
9949 return -EINVAL;
9950 return 0;
9951 }
9952 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9953 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9954 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9955 if (value) {
9956 dev->features |= NETIF_F_TSO6;
9957 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9959 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9960 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9961 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9962 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9963 dev->features |= NETIF_F_TSO_ECN;
9964 } else
9965 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9966 }
9967 return ethtool_op_set_tso(dev, value);
9968 }
9969
9970 static int tg3_nway_reset(struct net_device *dev)
9971 {
9972 struct tg3 *tp = netdev_priv(dev);
9973 int r;
9974
9975 if (!netif_running(dev))
9976 return -EAGAIN;
9977
9978 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9979 return -EINVAL;
9980
9981 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9982 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9983 return -EAGAIN;
9984 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9985 } else {
9986 u32 bmcr;
9987
9988 spin_lock_bh(&tp->lock);
9989 r = -EINVAL;
9990 tg3_readphy(tp, MII_BMCR, &bmcr);
9991 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9992 ((bmcr & BMCR_ANENABLE) ||
9993 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9994 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9995 BMCR_ANENABLE);
9996 r = 0;
9997 }
9998 spin_unlock_bh(&tp->lock);
9999 }
10000
10001 return r;
10002 }
10003
10004 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10005 {
10006 struct tg3 *tp = netdev_priv(dev);
10007
10008 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
10009 ering->rx_mini_max_pending = 0;
10010 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10011 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
10012 else
10013 ering->rx_jumbo_max_pending = 0;
10014
10015 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10016
10017 ering->rx_pending = tp->rx_pending;
10018 ering->rx_mini_pending = 0;
10019 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10020 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10021 else
10022 ering->rx_jumbo_pending = 0;
10023
10024 ering->tx_pending = tp->napi[0].tx_pending;
10025 }
10026
10027 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10028 {
10029 struct tg3 *tp = netdev_priv(dev);
10030 int i, irq_sync = 0, err = 0;
10031
10032 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
10033 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
10034 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10035 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10036 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10037 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10038 return -EINVAL;
10039
10040 if (netif_running(dev)) {
10041 tg3_phy_stop(tp);
10042 tg3_netif_stop(tp);
10043 irq_sync = 1;
10044 }
10045
10046 tg3_full_lock(tp, irq_sync);
10047
10048 tp->rx_pending = ering->rx_pending;
10049
10050 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10051 tp->rx_pending > 63)
10052 tp->rx_pending = 63;
10053 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10054
10055 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
10056 tp->napi[i].tx_pending = ering->tx_pending;
10057
10058 if (netif_running(dev)) {
10059 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10060 err = tg3_restart_hw(tp, 1);
10061 if (!err)
10062 tg3_netif_start(tp);
10063 }
10064
10065 tg3_full_unlock(tp);
10066
10067 if (irq_sync && !err)
10068 tg3_phy_start(tp);
10069
10070 return err;
10071 }
10072
10073 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10074 {
10075 struct tg3 *tp = netdev_priv(dev);
10076
10077 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10078
10079 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10080 epause->rx_pause = 1;
10081 else
10082 epause->rx_pause = 0;
10083
10084 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10085 epause->tx_pause = 1;
10086 else
10087 epause->tx_pause = 0;
10088 }
10089
10090 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10091 {
10092 struct tg3 *tp = netdev_priv(dev);
10093 int err = 0;
10094
10095 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10096 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10097 return -EAGAIN;
10098
10099 if (epause->autoneg) {
10100 u32 newadv;
10101 struct phy_device *phydev;
10102
10103 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10104
10105 if (epause->rx_pause) {
10106 if (epause->tx_pause)
10107 newadv = ADVERTISED_Pause;
10108 else
10109 newadv = ADVERTISED_Pause |
10110 ADVERTISED_Asym_Pause;
10111 } else if (epause->tx_pause) {
10112 newadv = ADVERTISED_Asym_Pause;
10113 } else
10114 newadv = 0;
10115
10116 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10117 u32 oldadv = phydev->advertising &
10118 (ADVERTISED_Pause |
10119 ADVERTISED_Asym_Pause);
10120 if (oldadv != newadv) {
10121 phydev->advertising &=
10122 ~(ADVERTISED_Pause |
10123 ADVERTISED_Asym_Pause);
10124 phydev->advertising |= newadv;
10125 err = phy_start_aneg(phydev);
10126 }
10127 } else {
10128 tp->link_config.advertising &=
10129 ~(ADVERTISED_Pause |
10130 ADVERTISED_Asym_Pause);
10131 tp->link_config.advertising |= newadv;
10132 }
10133 } else {
10134 if (epause->rx_pause)
10135 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10136 else
10137 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10138
10139 if (epause->tx_pause)
10140 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10141 else
10142 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10143
10144 if (netif_running(dev))
10145 tg3_setup_flow_control(tp, 0, 0);
10146 }
10147 } else {
10148 int irq_sync = 0;
10149
10150 if (netif_running(dev)) {
10151 tg3_netif_stop(tp);
10152 irq_sync = 1;
10153 }
10154
10155 tg3_full_lock(tp, irq_sync);
10156
10157 if (epause->autoneg)
10158 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10159 else
10160 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10161 if (epause->rx_pause)
10162 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10163 else
10164 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10165 if (epause->tx_pause)
10166 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10167 else
10168 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10169
10170 if (netif_running(dev)) {
10171 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10172 err = tg3_restart_hw(tp, 1);
10173 if (!err)
10174 tg3_netif_start(tp);
10175 }
10176
10177 tg3_full_unlock(tp);
10178 }
10179
10180 return err;
10181 }
10182
10183 static u32 tg3_get_rx_csum(struct net_device *dev)
10184 {
10185 struct tg3 *tp = netdev_priv(dev);
10186 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10187 }
10188
10189 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10190 {
10191 struct tg3 *tp = netdev_priv(dev);
10192
10193 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10194 if (data != 0)
10195 return -EINVAL;
10196 return 0;
10197 }
10198
10199 spin_lock_bh(&tp->lock);
10200 if (data)
10201 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10202 else
10203 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10204 spin_unlock_bh(&tp->lock);
10205
10206 return 0;
10207 }
10208
10209 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10210 {
10211 struct tg3 *tp = netdev_priv(dev);
10212
10213 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10214 if (data != 0)
10215 return -EINVAL;
10216 return 0;
10217 }
10218
10219 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10220 ethtool_op_set_tx_ipv6_csum(dev, data);
10221 else
10222 ethtool_op_set_tx_csum(dev, data);
10223
10224 return 0;
10225 }
10226
10227 static int tg3_get_sset_count (struct net_device *dev, int sset)
10228 {
10229 switch (sset) {
10230 case ETH_SS_TEST:
10231 return TG3_NUM_TEST;
10232 case ETH_SS_STATS:
10233 return TG3_NUM_STATS;
10234 default:
10235 return -EOPNOTSUPP;
10236 }
10237 }
10238
10239 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10240 {
10241 switch (stringset) {
10242 case ETH_SS_STATS:
10243 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10244 break;
10245 case ETH_SS_TEST:
10246 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10247 break;
10248 default:
10249 WARN_ON(1); /* we need a WARN() */
10250 break;
10251 }
10252 }
10253
10254 static int tg3_phys_id(struct net_device *dev, u32 data)
10255 {
10256 struct tg3 *tp = netdev_priv(dev);
10257 int i;
10258
10259 if (!netif_running(tp->dev))
10260 return -EAGAIN;
10261
10262 if (data == 0)
10263 data = UINT_MAX / 2;
10264
10265 for (i = 0; i < (data * 2); i++) {
10266 if ((i % 2) == 0)
10267 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10268 LED_CTRL_1000MBPS_ON |
10269 LED_CTRL_100MBPS_ON |
10270 LED_CTRL_10MBPS_ON |
10271 LED_CTRL_TRAFFIC_OVERRIDE |
10272 LED_CTRL_TRAFFIC_BLINK |
10273 LED_CTRL_TRAFFIC_LED);
10274
10275 else
10276 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10277 LED_CTRL_TRAFFIC_OVERRIDE);
10278
10279 if (msleep_interruptible(500))
10280 break;
10281 }
10282 tw32(MAC_LED_CTRL, tp->led_ctrl);
10283 return 0;
10284 }
10285
10286 static void tg3_get_ethtool_stats (struct net_device *dev,
10287 struct ethtool_stats *estats, u64 *tmp_stats)
10288 {
10289 struct tg3 *tp = netdev_priv(dev);
10290 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10291 }
10292
10293 #define NVRAM_TEST_SIZE 0x100
10294 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10295 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10296 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10297 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10298 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10299
10300 static int tg3_test_nvram(struct tg3 *tp)
10301 {
10302 u32 csum, magic;
10303 __be32 *buf;
10304 int i, j, k, err = 0, size;
10305
10306 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10307 return 0;
10308
10309 if (tg3_nvram_read(tp, 0, &magic) != 0)
10310 return -EIO;
10311
10312 if (magic == TG3_EEPROM_MAGIC)
10313 size = NVRAM_TEST_SIZE;
10314 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10315 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10316 TG3_EEPROM_SB_FORMAT_1) {
10317 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10318 case TG3_EEPROM_SB_REVISION_0:
10319 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10320 break;
10321 case TG3_EEPROM_SB_REVISION_2:
10322 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10323 break;
10324 case TG3_EEPROM_SB_REVISION_3:
10325 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10326 break;
10327 default:
10328 return 0;
10329 }
10330 } else
10331 return 0;
10332 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10333 size = NVRAM_SELFBOOT_HW_SIZE;
10334 else
10335 return -EIO;
10336
10337 buf = kmalloc(size, GFP_KERNEL);
10338 if (buf == NULL)
10339 return -ENOMEM;
10340
10341 err = -EIO;
10342 for (i = 0, j = 0; i < size; i += 4, j++) {
10343 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10344 if (err)
10345 break;
10346 }
10347 if (i < size)
10348 goto out;
10349
10350 /* Selfboot format */
10351 magic = be32_to_cpu(buf[0]);
10352 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10353 TG3_EEPROM_MAGIC_FW) {
10354 u8 *buf8 = (u8 *) buf, csum8 = 0;
10355
10356 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10357 TG3_EEPROM_SB_REVISION_2) {
10358 /* For rev 2, the csum doesn't include the MBA. */
10359 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10360 csum8 += buf8[i];
10361 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10362 csum8 += buf8[i];
10363 } else {
10364 for (i = 0; i < size; i++)
10365 csum8 += buf8[i];
10366 }
10367
10368 if (csum8 == 0) {
10369 err = 0;
10370 goto out;
10371 }
10372
10373 err = -EIO;
10374 goto out;
10375 }
10376
10377 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10378 TG3_EEPROM_MAGIC_HW) {
10379 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10380 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10381 u8 *buf8 = (u8 *) buf;
10382
10383 /* Separate the parity bits and the data bytes. */
10384 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10385 if ((i == 0) || (i == 8)) {
10386 int l;
10387 u8 msk;
10388
10389 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10390 parity[k++] = buf8[i] & msk;
10391 i++;
10392 }
10393 else if (i == 16) {
10394 int l;
10395 u8 msk;
10396
10397 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10398 parity[k++] = buf8[i] & msk;
10399 i++;
10400
10401 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10402 parity[k++] = buf8[i] & msk;
10403 i++;
10404 }
10405 data[j++] = buf8[i];
10406 }
10407
10408 err = -EIO;
10409 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10410 u8 hw8 = hweight8(data[i]);
10411
10412 if ((hw8 & 0x1) && parity[i])
10413 goto out;
10414 else if (!(hw8 & 0x1) && !parity[i])
10415 goto out;
10416 }
10417 err = 0;
10418 goto out;
10419 }
10420
10421 /* Bootstrap checksum at offset 0x10 */
10422 csum = calc_crc((unsigned char *) buf, 0x10);
10423 if (csum != be32_to_cpu(buf[0x10/4]))
10424 goto out;
10425
10426 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10427 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10428 if (csum != be32_to_cpu(buf[0xfc/4]))
10429 goto out;
10430
10431 err = 0;
10432
10433 out:
10434 kfree(buf);
10435 return err;
10436 }
10437
10438 #define TG3_SERDES_TIMEOUT_SEC 2
10439 #define TG3_COPPER_TIMEOUT_SEC 6
10440
10441 static int tg3_test_link(struct tg3 *tp)
10442 {
10443 int i, max;
10444
10445 if (!netif_running(tp->dev))
10446 return -ENODEV;
10447
10448 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10449 max = TG3_SERDES_TIMEOUT_SEC;
10450 else
10451 max = TG3_COPPER_TIMEOUT_SEC;
10452
10453 for (i = 0; i < max; i++) {
10454 if (netif_carrier_ok(tp->dev))
10455 return 0;
10456
10457 if (msleep_interruptible(1000))
10458 break;
10459 }
10460
10461 return -EIO;
10462 }
10463
10464 /* Only test the commonly used registers */
10465 static int tg3_test_registers(struct tg3 *tp)
10466 {
10467 int i, is_5705, is_5750;
10468 u32 offset, read_mask, write_mask, val, save_val, read_val;
10469 static struct {
10470 u16 offset;
10471 u16 flags;
10472 #define TG3_FL_5705 0x1
10473 #define TG3_FL_NOT_5705 0x2
10474 #define TG3_FL_NOT_5788 0x4
10475 #define TG3_FL_NOT_5750 0x8
10476 u32 read_mask;
10477 u32 write_mask;
10478 } reg_tbl[] = {
10479 /* MAC Control Registers */
10480 { MAC_MODE, TG3_FL_NOT_5705,
10481 0x00000000, 0x00ef6f8c },
10482 { MAC_MODE, TG3_FL_5705,
10483 0x00000000, 0x01ef6b8c },
10484 { MAC_STATUS, TG3_FL_NOT_5705,
10485 0x03800107, 0x00000000 },
10486 { MAC_STATUS, TG3_FL_5705,
10487 0x03800100, 0x00000000 },
10488 { MAC_ADDR_0_HIGH, 0x0000,
10489 0x00000000, 0x0000ffff },
10490 { MAC_ADDR_0_LOW, 0x0000,
10491 0x00000000, 0xffffffff },
10492 { MAC_RX_MTU_SIZE, 0x0000,
10493 0x00000000, 0x0000ffff },
10494 { MAC_TX_MODE, 0x0000,
10495 0x00000000, 0x00000070 },
10496 { MAC_TX_LENGTHS, 0x0000,
10497 0x00000000, 0x00003fff },
10498 { MAC_RX_MODE, TG3_FL_NOT_5705,
10499 0x00000000, 0x000007fc },
10500 { MAC_RX_MODE, TG3_FL_5705,
10501 0x00000000, 0x000007dc },
10502 { MAC_HASH_REG_0, 0x0000,
10503 0x00000000, 0xffffffff },
10504 { MAC_HASH_REG_1, 0x0000,
10505 0x00000000, 0xffffffff },
10506 { MAC_HASH_REG_2, 0x0000,
10507 0x00000000, 0xffffffff },
10508 { MAC_HASH_REG_3, 0x0000,
10509 0x00000000, 0xffffffff },
10510
10511 /* Receive Data and Receive BD Initiator Control Registers. */
10512 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10513 0x00000000, 0xffffffff },
10514 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10515 0x00000000, 0xffffffff },
10516 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10517 0x00000000, 0x00000003 },
10518 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10519 0x00000000, 0xffffffff },
10520 { RCVDBDI_STD_BD+0, 0x0000,
10521 0x00000000, 0xffffffff },
10522 { RCVDBDI_STD_BD+4, 0x0000,
10523 0x00000000, 0xffffffff },
10524 { RCVDBDI_STD_BD+8, 0x0000,
10525 0x00000000, 0xffff0002 },
10526 { RCVDBDI_STD_BD+0xc, 0x0000,
10527 0x00000000, 0xffffffff },
10528
10529 /* Receive BD Initiator Control Registers. */
10530 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10531 0x00000000, 0xffffffff },
10532 { RCVBDI_STD_THRESH, TG3_FL_5705,
10533 0x00000000, 0x000003ff },
10534 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10535 0x00000000, 0xffffffff },
10536
10537 /* Host Coalescing Control Registers. */
10538 { HOSTCC_MODE, TG3_FL_NOT_5705,
10539 0x00000000, 0x00000004 },
10540 { HOSTCC_MODE, TG3_FL_5705,
10541 0x00000000, 0x000000f6 },
10542 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10543 0x00000000, 0xffffffff },
10544 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10545 0x00000000, 0x000003ff },
10546 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10547 0x00000000, 0xffffffff },
10548 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10549 0x00000000, 0x000003ff },
10550 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10551 0x00000000, 0xffffffff },
10552 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10553 0x00000000, 0x000000ff },
10554 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10555 0x00000000, 0xffffffff },
10556 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10557 0x00000000, 0x000000ff },
10558 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10559 0x00000000, 0xffffffff },
10560 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10561 0x00000000, 0xffffffff },
10562 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10563 0x00000000, 0xffffffff },
10564 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10565 0x00000000, 0x000000ff },
10566 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10567 0x00000000, 0xffffffff },
10568 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10569 0x00000000, 0x000000ff },
10570 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10571 0x00000000, 0xffffffff },
10572 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10573 0x00000000, 0xffffffff },
10574 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10575 0x00000000, 0xffffffff },
10576 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10577 0x00000000, 0xffffffff },
10578 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10579 0x00000000, 0xffffffff },
10580 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10581 0xffffffff, 0x00000000 },
10582 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10583 0xffffffff, 0x00000000 },
10584
10585 /* Buffer Manager Control Registers. */
10586 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10587 0x00000000, 0x007fff80 },
10588 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10589 0x00000000, 0x007fffff },
10590 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10591 0x00000000, 0x0000003f },
10592 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10593 0x00000000, 0x000001ff },
10594 { BUFMGR_MB_HIGH_WATER, 0x0000,
10595 0x00000000, 0x000001ff },
10596 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10597 0xffffffff, 0x00000000 },
10598 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10599 0xffffffff, 0x00000000 },
10600
10601 /* Mailbox Registers */
10602 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10603 0x00000000, 0x000001ff },
10604 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10605 0x00000000, 0x000001ff },
10606 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10607 0x00000000, 0x000007ff },
10608 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10609 0x00000000, 0x000001ff },
10610
10611 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10612 };
10613
10614 is_5705 = is_5750 = 0;
10615 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10616 is_5705 = 1;
10617 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10618 is_5750 = 1;
10619 }
10620
10621 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10622 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10623 continue;
10624
10625 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10626 continue;
10627
10628 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10629 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10630 continue;
10631
10632 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10633 continue;
10634
10635 offset = (u32) reg_tbl[i].offset;
10636 read_mask = reg_tbl[i].read_mask;
10637 write_mask = reg_tbl[i].write_mask;
10638
10639 /* Save the original register content */
10640 save_val = tr32(offset);
10641
10642 /* Determine the read-only value. */
10643 read_val = save_val & read_mask;
10644
10645 /* Write zero to the register, then make sure the read-only bits
10646 * are not changed and the read/write bits are all zeros.
10647 */
10648 tw32(offset, 0);
10649
10650 val = tr32(offset);
10651
10652 /* Test the read-only and read/write bits. */
10653 if (((val & read_mask) != read_val) || (val & write_mask))
10654 goto out;
10655
10656 /* Write ones to all the bits defined by RdMask and WrMask, then
10657 * make sure the read-only bits are not changed and the
10658 * read/write bits are all ones.
10659 */
10660 tw32(offset, read_mask | write_mask);
10661
10662 val = tr32(offset);
10663
10664 /* Test the read-only bits. */
10665 if ((val & read_mask) != read_val)
10666 goto out;
10667
10668 /* Test the read/write bits. */
10669 if ((val & write_mask) != write_mask)
10670 goto out;
10671
10672 tw32(offset, save_val);
10673 }
10674
10675 return 0;
10676
10677 out:
10678 if (netif_msg_hw(tp))
10679 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10680 offset);
10681 tw32(offset, save_val);
10682 return -EIO;
10683 }
10684
10685 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10686 {
10687 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10688 int i;
10689 u32 j;
10690
10691 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10692 for (j = 0; j < len; j += 4) {
10693 u32 val;
10694
10695 tg3_write_mem(tp, offset + j, test_pattern[i]);
10696 tg3_read_mem(tp, offset + j, &val);
10697 if (val != test_pattern[i])
10698 return -EIO;
10699 }
10700 }
10701 return 0;
10702 }
10703
10704 static int tg3_test_memory(struct tg3 *tp)
10705 {
10706 static struct mem_entry {
10707 u32 offset;
10708 u32 len;
10709 } mem_tbl_570x[] = {
10710 { 0x00000000, 0x00b50},
10711 { 0x00002000, 0x1c000},
10712 { 0xffffffff, 0x00000}
10713 }, mem_tbl_5705[] = {
10714 { 0x00000100, 0x0000c},
10715 { 0x00000200, 0x00008},
10716 { 0x00004000, 0x00800},
10717 { 0x00006000, 0x01000},
10718 { 0x00008000, 0x02000},
10719 { 0x00010000, 0x0e000},
10720 { 0xffffffff, 0x00000}
10721 }, mem_tbl_5755[] = {
10722 { 0x00000200, 0x00008},
10723 { 0x00004000, 0x00800},
10724 { 0x00006000, 0x00800},
10725 { 0x00008000, 0x02000},
10726 { 0x00010000, 0x0c000},
10727 { 0xffffffff, 0x00000}
10728 }, mem_tbl_5906[] = {
10729 { 0x00000200, 0x00008},
10730 { 0x00004000, 0x00400},
10731 { 0x00006000, 0x00400},
10732 { 0x00008000, 0x01000},
10733 { 0x00010000, 0x01000},
10734 { 0xffffffff, 0x00000}
10735 }, mem_tbl_5717[] = {
10736 { 0x00000200, 0x00008},
10737 { 0x00010000, 0x0a000},
10738 { 0x00020000, 0x13c00},
10739 { 0xffffffff, 0x00000}
10740 }, mem_tbl_57765[] = {
10741 { 0x00000200, 0x00008},
10742 { 0x00004000, 0x00800},
10743 { 0x00006000, 0x09800},
10744 { 0x00010000, 0x0a000},
10745 { 0xffffffff, 0x00000}
10746 };
10747 struct mem_entry *mem_tbl;
10748 int err = 0;
10749 int i;
10750
10751 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10752 mem_tbl = mem_tbl_5717;
10753 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10754 mem_tbl = mem_tbl_57765;
10755 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10756 mem_tbl = mem_tbl_5755;
10757 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10758 mem_tbl = mem_tbl_5906;
10759 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10760 mem_tbl = mem_tbl_5705;
10761 else
10762 mem_tbl = mem_tbl_570x;
10763
10764 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10765 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10766 mem_tbl[i].len)) != 0)
10767 break;
10768 }
10769
10770 return err;
10771 }
10772
10773 #define TG3_MAC_LOOPBACK 0
10774 #define TG3_PHY_LOOPBACK 1
10775
10776 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10777 {
10778 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10779 u32 desc_idx, coal_now;
10780 struct sk_buff *skb, *rx_skb;
10781 u8 *tx_data;
10782 dma_addr_t map;
10783 int num_pkts, tx_len, rx_len, i, err;
10784 struct tg3_rx_buffer_desc *desc;
10785 struct tg3_napi *tnapi, *rnapi;
10786 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10787
10788 tnapi = &tp->napi[0];
10789 rnapi = &tp->napi[0];
10790 if (tp->irq_cnt > 1) {
10791 rnapi = &tp->napi[1];
10792 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10793 tnapi = &tp->napi[1];
10794 }
10795 coal_now = tnapi->coal_now | rnapi->coal_now;
10796
10797 if (loopback_mode == TG3_MAC_LOOPBACK) {
10798 /* HW errata - mac loopback fails in some cases on 5780.
10799 * Normal traffic and PHY loopback are not affected by
10800 * errata.
10801 */
10802 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10803 return 0;
10804
10805 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10806 MAC_MODE_PORT_INT_LPBACK;
10807 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10808 mac_mode |= MAC_MODE_LINK_POLARITY;
10809 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10810 mac_mode |= MAC_MODE_PORT_MODE_MII;
10811 else
10812 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10813 tw32(MAC_MODE, mac_mode);
10814 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10815 u32 val;
10816
10817 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10818 tg3_phy_fet_toggle_apd(tp, false);
10819 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10820 } else
10821 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10822
10823 tg3_phy_toggle_automdix(tp, 0);
10824
10825 tg3_writephy(tp, MII_BMCR, val);
10826 udelay(40);
10827
10828 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10829 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10830 tg3_writephy(tp, MII_TG3_FET_PTEST,
10831 MII_TG3_FET_PTEST_FRC_TX_LINK |
10832 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10833 /* The write needs to be flushed for the AC131 */
10834 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10835 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10836 mac_mode |= MAC_MODE_PORT_MODE_MII;
10837 } else
10838 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10839
10840 /* reset to prevent losing 1st rx packet intermittently */
10841 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10842 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10843 udelay(10);
10844 tw32_f(MAC_RX_MODE, tp->rx_mode);
10845 }
10846 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10847 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10848 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10849 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10850 mac_mode |= MAC_MODE_LINK_POLARITY;
10851 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10852 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10853 }
10854 tw32(MAC_MODE, mac_mode);
10855 }
10856 else
10857 return -EINVAL;
10858
10859 err = -EIO;
10860
10861 tx_len = 1514;
10862 skb = netdev_alloc_skb(tp->dev, tx_len);
10863 if (!skb)
10864 return -ENOMEM;
10865
10866 tx_data = skb_put(skb, tx_len);
10867 memcpy(tx_data, tp->dev->dev_addr, 6);
10868 memset(tx_data + 6, 0x0, 8);
10869
10870 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10871
10872 for (i = 14; i < tx_len; i++)
10873 tx_data[i] = (u8) (i & 0xff);
10874
10875 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10876 if (pci_dma_mapping_error(tp->pdev, map)) {
10877 dev_kfree_skb(skb);
10878 return -EIO;
10879 }
10880
10881 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10882 rnapi->coal_now);
10883
10884 udelay(10);
10885
10886 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10887
10888 num_pkts = 0;
10889
10890 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10891
10892 tnapi->tx_prod++;
10893 num_pkts++;
10894
10895 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10896 tr32_mailbox(tnapi->prodmbox);
10897
10898 udelay(10);
10899
10900 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10901 for (i = 0; i < 35; i++) {
10902 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10903 coal_now);
10904
10905 udelay(10);
10906
10907 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10908 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10909 if ((tx_idx == tnapi->tx_prod) &&
10910 (rx_idx == (rx_start_idx + num_pkts)))
10911 break;
10912 }
10913
10914 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10915 dev_kfree_skb(skb);
10916
10917 if (tx_idx != tnapi->tx_prod)
10918 goto out;
10919
10920 if (rx_idx != rx_start_idx + num_pkts)
10921 goto out;
10922
10923 desc = &rnapi->rx_rcb[rx_start_idx];
10924 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10925 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10926 if (opaque_key != RXD_OPAQUE_RING_STD)
10927 goto out;
10928
10929 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10930 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10931 goto out;
10932
10933 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10934 if (rx_len != tx_len)
10935 goto out;
10936
10937 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10938
10939 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10940 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10941
10942 for (i = 14; i < tx_len; i++) {
10943 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10944 goto out;
10945 }
10946 err = 0;
10947
10948 /* tg3_free_rings will unmap and free the rx_skb */
10949 out:
10950 return err;
10951 }
10952
10953 #define TG3_MAC_LOOPBACK_FAILED 1
10954 #define TG3_PHY_LOOPBACK_FAILED 2
10955 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10956 TG3_PHY_LOOPBACK_FAILED)
10957
10958 static int tg3_test_loopback(struct tg3 *tp)
10959 {
10960 int err = 0;
10961 u32 cpmuctrl = 0;
10962
10963 if (!netif_running(tp->dev))
10964 return TG3_LOOPBACK_FAILED;
10965
10966 err = tg3_reset_hw(tp, 1);
10967 if (err)
10968 return TG3_LOOPBACK_FAILED;
10969
10970 /* Turn off gphy autopowerdown. */
10971 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10972 tg3_phy_toggle_apd(tp, false);
10973
10974 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10975 int i;
10976 u32 status;
10977
10978 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10979
10980 /* Wait for up to 40 microseconds to acquire lock. */
10981 for (i = 0; i < 4; i++) {
10982 status = tr32(TG3_CPMU_MUTEX_GNT);
10983 if (status == CPMU_MUTEX_GNT_DRIVER)
10984 break;
10985 udelay(10);
10986 }
10987
10988 if (status != CPMU_MUTEX_GNT_DRIVER)
10989 return TG3_LOOPBACK_FAILED;
10990
10991 /* Turn off link-based power management. */
10992 cpmuctrl = tr32(TG3_CPMU_CTRL);
10993 tw32(TG3_CPMU_CTRL,
10994 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10995 CPMU_CTRL_LINK_AWARE_MODE));
10996 }
10997
10998 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10999 err |= TG3_MAC_LOOPBACK_FAILED;
11000
11001 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11002 tw32(TG3_CPMU_CTRL, cpmuctrl);
11003
11004 /* Release the mutex */
11005 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11006 }
11007
11008 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
11009 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11010 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11011 err |= TG3_PHY_LOOPBACK_FAILED;
11012 }
11013
11014 /* Re-enable gphy autopowerdown. */
11015 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
11016 tg3_phy_toggle_apd(tp, true);
11017
11018 return err;
11019 }
11020
11021 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11022 u64 *data)
11023 {
11024 struct tg3 *tp = netdev_priv(dev);
11025
11026 if (tp->link_config.phy_is_low_power)
11027 tg3_set_power_state(tp, PCI_D0);
11028
11029 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11030
11031 if (tg3_test_nvram(tp) != 0) {
11032 etest->flags |= ETH_TEST_FL_FAILED;
11033 data[0] = 1;
11034 }
11035 if (tg3_test_link(tp) != 0) {
11036 etest->flags |= ETH_TEST_FL_FAILED;
11037 data[1] = 1;
11038 }
11039 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11040 int err, err2 = 0, irq_sync = 0;
11041
11042 if (netif_running(dev)) {
11043 tg3_phy_stop(tp);
11044 tg3_netif_stop(tp);
11045 irq_sync = 1;
11046 }
11047
11048 tg3_full_lock(tp, irq_sync);
11049
11050 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11051 err = tg3_nvram_lock(tp);
11052 tg3_halt_cpu(tp, RX_CPU_BASE);
11053 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11054 tg3_halt_cpu(tp, TX_CPU_BASE);
11055 if (!err)
11056 tg3_nvram_unlock(tp);
11057
11058 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
11059 tg3_phy_reset(tp);
11060
11061 if (tg3_test_registers(tp) != 0) {
11062 etest->flags |= ETH_TEST_FL_FAILED;
11063 data[2] = 1;
11064 }
11065 if (tg3_test_memory(tp) != 0) {
11066 etest->flags |= ETH_TEST_FL_FAILED;
11067 data[3] = 1;
11068 }
11069 if ((data[4] = tg3_test_loopback(tp)) != 0)
11070 etest->flags |= ETH_TEST_FL_FAILED;
11071
11072 tg3_full_unlock(tp);
11073
11074 if (tg3_test_interrupt(tp) != 0) {
11075 etest->flags |= ETH_TEST_FL_FAILED;
11076 data[5] = 1;
11077 }
11078
11079 tg3_full_lock(tp, 0);
11080
11081 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11082 if (netif_running(dev)) {
11083 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11084 err2 = tg3_restart_hw(tp, 1);
11085 if (!err2)
11086 tg3_netif_start(tp);
11087 }
11088
11089 tg3_full_unlock(tp);
11090
11091 if (irq_sync && !err2)
11092 tg3_phy_start(tp);
11093 }
11094 if (tp->link_config.phy_is_low_power)
11095 tg3_set_power_state(tp, PCI_D3hot);
11096
11097 }
11098
11099 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11100 {
11101 struct mii_ioctl_data *data = if_mii(ifr);
11102 struct tg3 *tp = netdev_priv(dev);
11103 int err;
11104
11105 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11106 struct phy_device *phydev;
11107 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11108 return -EAGAIN;
11109 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11110 return phy_mii_ioctl(phydev, data, cmd);
11111 }
11112
11113 switch(cmd) {
11114 case SIOCGMIIPHY:
11115 data->phy_id = tp->phy_addr;
11116
11117 /* fallthru */
11118 case SIOCGMIIREG: {
11119 u32 mii_regval;
11120
11121 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11122 break; /* We have no PHY */
11123
11124 if (tp->link_config.phy_is_low_power)
11125 return -EAGAIN;
11126
11127 spin_lock_bh(&tp->lock);
11128 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11129 spin_unlock_bh(&tp->lock);
11130
11131 data->val_out = mii_regval;
11132
11133 return err;
11134 }
11135
11136 case SIOCSMIIREG:
11137 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11138 break; /* We have no PHY */
11139
11140 if (tp->link_config.phy_is_low_power)
11141 return -EAGAIN;
11142
11143 spin_lock_bh(&tp->lock);
11144 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11145 spin_unlock_bh(&tp->lock);
11146
11147 return err;
11148
11149 default:
11150 /* do nothing */
11151 break;
11152 }
11153 return -EOPNOTSUPP;
11154 }
11155
11156 #if TG3_VLAN_TAG_USED
11157 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11158 {
11159 struct tg3 *tp = netdev_priv(dev);
11160
11161 if (!netif_running(dev)) {
11162 tp->vlgrp = grp;
11163 return;
11164 }
11165
11166 tg3_netif_stop(tp);
11167
11168 tg3_full_lock(tp, 0);
11169
11170 tp->vlgrp = grp;
11171
11172 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11173 __tg3_set_rx_mode(dev);
11174
11175 tg3_netif_start(tp);
11176
11177 tg3_full_unlock(tp);
11178 }
11179 #endif
11180
11181 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11182 {
11183 struct tg3 *tp = netdev_priv(dev);
11184
11185 memcpy(ec, &tp->coal, sizeof(*ec));
11186 return 0;
11187 }
11188
11189 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11190 {
11191 struct tg3 *tp = netdev_priv(dev);
11192 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11193 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11194
11195 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11196 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11197 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11198 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11199 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11200 }
11201
11202 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11203 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11204 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11205 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11206 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11207 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11208 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11209 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11210 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11211 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11212 return -EINVAL;
11213
11214 /* No rx interrupts will be generated if both are zero */
11215 if ((ec->rx_coalesce_usecs == 0) &&
11216 (ec->rx_max_coalesced_frames == 0))
11217 return -EINVAL;
11218
11219 /* No tx interrupts will be generated if both are zero */
11220 if ((ec->tx_coalesce_usecs == 0) &&
11221 (ec->tx_max_coalesced_frames == 0))
11222 return -EINVAL;
11223
11224 /* Only copy relevant parameters, ignore all others. */
11225 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11226 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11227 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11228 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11229 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11230 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11231 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11232 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11233 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11234
11235 if (netif_running(dev)) {
11236 tg3_full_lock(tp, 0);
11237 __tg3_set_coalesce(tp, &tp->coal);
11238 tg3_full_unlock(tp);
11239 }
11240 return 0;
11241 }
11242
11243 static const struct ethtool_ops tg3_ethtool_ops = {
11244 .get_settings = tg3_get_settings,
11245 .set_settings = tg3_set_settings,
11246 .get_drvinfo = tg3_get_drvinfo,
11247 .get_regs_len = tg3_get_regs_len,
11248 .get_regs = tg3_get_regs,
11249 .get_wol = tg3_get_wol,
11250 .set_wol = tg3_set_wol,
11251 .get_msglevel = tg3_get_msglevel,
11252 .set_msglevel = tg3_set_msglevel,
11253 .nway_reset = tg3_nway_reset,
11254 .get_link = ethtool_op_get_link,
11255 .get_eeprom_len = tg3_get_eeprom_len,
11256 .get_eeprom = tg3_get_eeprom,
11257 .set_eeprom = tg3_set_eeprom,
11258 .get_ringparam = tg3_get_ringparam,
11259 .set_ringparam = tg3_set_ringparam,
11260 .get_pauseparam = tg3_get_pauseparam,
11261 .set_pauseparam = tg3_set_pauseparam,
11262 .get_rx_csum = tg3_get_rx_csum,
11263 .set_rx_csum = tg3_set_rx_csum,
11264 .set_tx_csum = tg3_set_tx_csum,
11265 .set_sg = ethtool_op_set_sg,
11266 .set_tso = tg3_set_tso,
11267 .self_test = tg3_self_test,
11268 .get_strings = tg3_get_strings,
11269 .phys_id = tg3_phys_id,
11270 .get_ethtool_stats = tg3_get_ethtool_stats,
11271 .get_coalesce = tg3_get_coalesce,
11272 .set_coalesce = tg3_set_coalesce,
11273 .get_sset_count = tg3_get_sset_count,
11274 };
11275
11276 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11277 {
11278 u32 cursize, val, magic;
11279
11280 tp->nvram_size = EEPROM_CHIP_SIZE;
11281
11282 if (tg3_nvram_read(tp, 0, &magic) != 0)
11283 return;
11284
11285 if ((magic != TG3_EEPROM_MAGIC) &&
11286 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11287 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11288 return;
11289
11290 /*
11291 * Size the chip by reading offsets at increasing powers of two.
11292 * When we encounter our validation signature, we know the addressing
11293 * has wrapped around, and thus have our chip size.
11294 */
11295 cursize = 0x10;
11296
11297 while (cursize < tp->nvram_size) {
11298 if (tg3_nvram_read(tp, cursize, &val) != 0)
11299 return;
11300
11301 if (val == magic)
11302 break;
11303
11304 cursize <<= 1;
11305 }
11306
11307 tp->nvram_size = cursize;
11308 }
11309
11310 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11311 {
11312 u32 val;
11313
11314 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11315 tg3_nvram_read(tp, 0, &val) != 0)
11316 return;
11317
11318 /* Selfboot format */
11319 if (val != TG3_EEPROM_MAGIC) {
11320 tg3_get_eeprom_size(tp);
11321 return;
11322 }
11323
11324 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11325 if (val != 0) {
11326 /* This is confusing. We want to operate on the
11327 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11328 * call will read from NVRAM and byteswap the data
11329 * according to the byteswapping settings for all
11330 * other register accesses. This ensures the data we
11331 * want will always reside in the lower 16-bits.
11332 * However, the data in NVRAM is in LE format, which
11333 * means the data from the NVRAM read will always be
11334 * opposite the endianness of the CPU. The 16-bit
11335 * byteswap then brings the data to CPU endianness.
11336 */
11337 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11338 return;
11339 }
11340 }
11341 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11342 }
11343
11344 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11345 {
11346 u32 nvcfg1;
11347
11348 nvcfg1 = tr32(NVRAM_CFG1);
11349 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11350 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11351 } else {
11352 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11353 tw32(NVRAM_CFG1, nvcfg1);
11354 }
11355
11356 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11357 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11358 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11359 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11360 tp->nvram_jedecnum = JEDEC_ATMEL;
11361 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11362 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11363 break;
11364 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11365 tp->nvram_jedecnum = JEDEC_ATMEL;
11366 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11367 break;
11368 case FLASH_VENDOR_ATMEL_EEPROM:
11369 tp->nvram_jedecnum = JEDEC_ATMEL;
11370 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11371 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11372 break;
11373 case FLASH_VENDOR_ST:
11374 tp->nvram_jedecnum = JEDEC_ST;
11375 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11376 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11377 break;
11378 case FLASH_VENDOR_SAIFUN:
11379 tp->nvram_jedecnum = JEDEC_SAIFUN;
11380 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11381 break;
11382 case FLASH_VENDOR_SST_SMALL:
11383 case FLASH_VENDOR_SST_LARGE:
11384 tp->nvram_jedecnum = JEDEC_SST;
11385 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11386 break;
11387 }
11388 } else {
11389 tp->nvram_jedecnum = JEDEC_ATMEL;
11390 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11391 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11392 }
11393 }
11394
11395 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11396 {
11397 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11398 case FLASH_5752PAGE_SIZE_256:
11399 tp->nvram_pagesize = 256;
11400 break;
11401 case FLASH_5752PAGE_SIZE_512:
11402 tp->nvram_pagesize = 512;
11403 break;
11404 case FLASH_5752PAGE_SIZE_1K:
11405 tp->nvram_pagesize = 1024;
11406 break;
11407 case FLASH_5752PAGE_SIZE_2K:
11408 tp->nvram_pagesize = 2048;
11409 break;
11410 case FLASH_5752PAGE_SIZE_4K:
11411 tp->nvram_pagesize = 4096;
11412 break;
11413 case FLASH_5752PAGE_SIZE_264:
11414 tp->nvram_pagesize = 264;
11415 break;
11416 case FLASH_5752PAGE_SIZE_528:
11417 tp->nvram_pagesize = 528;
11418 break;
11419 }
11420 }
11421
11422 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11423 {
11424 u32 nvcfg1;
11425
11426 nvcfg1 = tr32(NVRAM_CFG1);
11427
11428 /* NVRAM protection for TPM */
11429 if (nvcfg1 & (1 << 27))
11430 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11431
11432 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11433 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11434 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11435 tp->nvram_jedecnum = JEDEC_ATMEL;
11436 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11437 break;
11438 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11439 tp->nvram_jedecnum = JEDEC_ATMEL;
11440 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11441 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11442 break;
11443 case FLASH_5752VENDOR_ST_M45PE10:
11444 case FLASH_5752VENDOR_ST_M45PE20:
11445 case FLASH_5752VENDOR_ST_M45PE40:
11446 tp->nvram_jedecnum = JEDEC_ST;
11447 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11448 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11449 break;
11450 }
11451
11452 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11453 tg3_nvram_get_pagesize(tp, nvcfg1);
11454 } else {
11455 /* For eeprom, set pagesize to maximum eeprom size */
11456 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11457
11458 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11459 tw32(NVRAM_CFG1, nvcfg1);
11460 }
11461 }
11462
11463 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11464 {
11465 u32 nvcfg1, protect = 0;
11466
11467 nvcfg1 = tr32(NVRAM_CFG1);
11468
11469 /* NVRAM protection for TPM */
11470 if (nvcfg1 & (1 << 27)) {
11471 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11472 protect = 1;
11473 }
11474
11475 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11476 switch (nvcfg1) {
11477 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11478 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11479 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11480 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11481 tp->nvram_jedecnum = JEDEC_ATMEL;
11482 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11483 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11484 tp->nvram_pagesize = 264;
11485 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11486 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11487 tp->nvram_size = (protect ? 0x3e200 :
11488 TG3_NVRAM_SIZE_512KB);
11489 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11490 tp->nvram_size = (protect ? 0x1f200 :
11491 TG3_NVRAM_SIZE_256KB);
11492 else
11493 tp->nvram_size = (protect ? 0x1f200 :
11494 TG3_NVRAM_SIZE_128KB);
11495 break;
11496 case FLASH_5752VENDOR_ST_M45PE10:
11497 case FLASH_5752VENDOR_ST_M45PE20:
11498 case FLASH_5752VENDOR_ST_M45PE40:
11499 tp->nvram_jedecnum = JEDEC_ST;
11500 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11501 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11502 tp->nvram_pagesize = 256;
11503 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11504 tp->nvram_size = (protect ?
11505 TG3_NVRAM_SIZE_64KB :
11506 TG3_NVRAM_SIZE_128KB);
11507 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11508 tp->nvram_size = (protect ?
11509 TG3_NVRAM_SIZE_64KB :
11510 TG3_NVRAM_SIZE_256KB);
11511 else
11512 tp->nvram_size = (protect ?
11513 TG3_NVRAM_SIZE_128KB :
11514 TG3_NVRAM_SIZE_512KB);
11515 break;
11516 }
11517 }
11518
11519 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11520 {
11521 u32 nvcfg1;
11522
11523 nvcfg1 = tr32(NVRAM_CFG1);
11524
11525 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11526 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11527 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11528 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11529 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11530 tp->nvram_jedecnum = JEDEC_ATMEL;
11531 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11532 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11533
11534 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11535 tw32(NVRAM_CFG1, nvcfg1);
11536 break;
11537 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11538 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11539 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11540 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11541 tp->nvram_jedecnum = JEDEC_ATMEL;
11542 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11543 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11544 tp->nvram_pagesize = 264;
11545 break;
11546 case FLASH_5752VENDOR_ST_M45PE10:
11547 case FLASH_5752VENDOR_ST_M45PE20:
11548 case FLASH_5752VENDOR_ST_M45PE40:
11549 tp->nvram_jedecnum = JEDEC_ST;
11550 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11551 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11552 tp->nvram_pagesize = 256;
11553 break;
11554 }
11555 }
11556
11557 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11558 {
11559 u32 nvcfg1, protect = 0;
11560
11561 nvcfg1 = tr32(NVRAM_CFG1);
11562
11563 /* NVRAM protection for TPM */
11564 if (nvcfg1 & (1 << 27)) {
11565 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11566 protect = 1;
11567 }
11568
11569 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11570 switch (nvcfg1) {
11571 case FLASH_5761VENDOR_ATMEL_ADB021D:
11572 case FLASH_5761VENDOR_ATMEL_ADB041D:
11573 case FLASH_5761VENDOR_ATMEL_ADB081D:
11574 case FLASH_5761VENDOR_ATMEL_ADB161D:
11575 case FLASH_5761VENDOR_ATMEL_MDB021D:
11576 case FLASH_5761VENDOR_ATMEL_MDB041D:
11577 case FLASH_5761VENDOR_ATMEL_MDB081D:
11578 case FLASH_5761VENDOR_ATMEL_MDB161D:
11579 tp->nvram_jedecnum = JEDEC_ATMEL;
11580 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11581 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11582 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11583 tp->nvram_pagesize = 256;
11584 break;
11585 case FLASH_5761VENDOR_ST_A_M45PE20:
11586 case FLASH_5761VENDOR_ST_A_M45PE40:
11587 case FLASH_5761VENDOR_ST_A_M45PE80:
11588 case FLASH_5761VENDOR_ST_A_M45PE16:
11589 case FLASH_5761VENDOR_ST_M_M45PE20:
11590 case FLASH_5761VENDOR_ST_M_M45PE40:
11591 case FLASH_5761VENDOR_ST_M_M45PE80:
11592 case FLASH_5761VENDOR_ST_M_M45PE16:
11593 tp->nvram_jedecnum = JEDEC_ST;
11594 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11595 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11596 tp->nvram_pagesize = 256;
11597 break;
11598 }
11599
11600 if (protect) {
11601 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11602 } else {
11603 switch (nvcfg1) {
11604 case FLASH_5761VENDOR_ATMEL_ADB161D:
11605 case FLASH_5761VENDOR_ATMEL_MDB161D:
11606 case FLASH_5761VENDOR_ST_A_M45PE16:
11607 case FLASH_5761VENDOR_ST_M_M45PE16:
11608 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11609 break;
11610 case FLASH_5761VENDOR_ATMEL_ADB081D:
11611 case FLASH_5761VENDOR_ATMEL_MDB081D:
11612 case FLASH_5761VENDOR_ST_A_M45PE80:
11613 case FLASH_5761VENDOR_ST_M_M45PE80:
11614 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11615 break;
11616 case FLASH_5761VENDOR_ATMEL_ADB041D:
11617 case FLASH_5761VENDOR_ATMEL_MDB041D:
11618 case FLASH_5761VENDOR_ST_A_M45PE40:
11619 case FLASH_5761VENDOR_ST_M_M45PE40:
11620 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11621 break;
11622 case FLASH_5761VENDOR_ATMEL_ADB021D:
11623 case FLASH_5761VENDOR_ATMEL_MDB021D:
11624 case FLASH_5761VENDOR_ST_A_M45PE20:
11625 case FLASH_5761VENDOR_ST_M_M45PE20:
11626 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11627 break;
11628 }
11629 }
11630 }
11631
11632 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11633 {
11634 tp->nvram_jedecnum = JEDEC_ATMEL;
11635 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11636 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11637 }
11638
11639 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11640 {
11641 u32 nvcfg1;
11642
11643 nvcfg1 = tr32(NVRAM_CFG1);
11644
11645 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11646 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11647 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11648 tp->nvram_jedecnum = JEDEC_ATMEL;
11649 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11650 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11651
11652 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11653 tw32(NVRAM_CFG1, nvcfg1);
11654 return;
11655 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11656 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11657 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11658 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11659 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11660 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11661 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11662 tp->nvram_jedecnum = JEDEC_ATMEL;
11663 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11664 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11665
11666 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11667 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11668 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11669 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11670 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11671 break;
11672 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11673 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11674 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11675 break;
11676 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11677 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11678 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11679 break;
11680 }
11681 break;
11682 case FLASH_5752VENDOR_ST_M45PE10:
11683 case FLASH_5752VENDOR_ST_M45PE20:
11684 case FLASH_5752VENDOR_ST_M45PE40:
11685 tp->nvram_jedecnum = JEDEC_ST;
11686 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11687 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11688
11689 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11690 case FLASH_5752VENDOR_ST_M45PE10:
11691 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11692 break;
11693 case FLASH_5752VENDOR_ST_M45PE20:
11694 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11695 break;
11696 case FLASH_5752VENDOR_ST_M45PE40:
11697 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11698 break;
11699 }
11700 break;
11701 default:
11702 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11703 return;
11704 }
11705
11706 tg3_nvram_get_pagesize(tp, nvcfg1);
11707 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11708 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11709 }
11710
11711
11712 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11713 {
11714 u32 nvcfg1;
11715
11716 nvcfg1 = tr32(NVRAM_CFG1);
11717
11718 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11719 case FLASH_5717VENDOR_ATMEL_EEPROM:
11720 case FLASH_5717VENDOR_MICRO_EEPROM:
11721 tp->nvram_jedecnum = JEDEC_ATMEL;
11722 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11723 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11724
11725 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11726 tw32(NVRAM_CFG1, nvcfg1);
11727 return;
11728 case FLASH_5717VENDOR_ATMEL_MDB011D:
11729 case FLASH_5717VENDOR_ATMEL_ADB011B:
11730 case FLASH_5717VENDOR_ATMEL_ADB011D:
11731 case FLASH_5717VENDOR_ATMEL_MDB021D:
11732 case FLASH_5717VENDOR_ATMEL_ADB021B:
11733 case FLASH_5717VENDOR_ATMEL_ADB021D:
11734 case FLASH_5717VENDOR_ATMEL_45USPT:
11735 tp->nvram_jedecnum = JEDEC_ATMEL;
11736 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11737 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11738
11739 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11740 case FLASH_5717VENDOR_ATMEL_MDB021D:
11741 case FLASH_5717VENDOR_ATMEL_ADB021B:
11742 case FLASH_5717VENDOR_ATMEL_ADB021D:
11743 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11744 break;
11745 default:
11746 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11747 break;
11748 }
11749 break;
11750 case FLASH_5717VENDOR_ST_M_M25PE10:
11751 case FLASH_5717VENDOR_ST_A_M25PE10:
11752 case FLASH_5717VENDOR_ST_M_M45PE10:
11753 case FLASH_5717VENDOR_ST_A_M45PE10:
11754 case FLASH_5717VENDOR_ST_M_M25PE20:
11755 case FLASH_5717VENDOR_ST_A_M25PE20:
11756 case FLASH_5717VENDOR_ST_M_M45PE20:
11757 case FLASH_5717VENDOR_ST_A_M45PE20:
11758 case FLASH_5717VENDOR_ST_25USPT:
11759 case FLASH_5717VENDOR_ST_45USPT:
11760 tp->nvram_jedecnum = JEDEC_ST;
11761 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11762 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11763
11764 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11765 case FLASH_5717VENDOR_ST_M_M25PE20:
11766 case FLASH_5717VENDOR_ST_A_M25PE20:
11767 case FLASH_5717VENDOR_ST_M_M45PE20:
11768 case FLASH_5717VENDOR_ST_A_M45PE20:
11769 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11770 break;
11771 default:
11772 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11773 break;
11774 }
11775 break;
11776 default:
11777 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11778 return;
11779 }
11780
11781 tg3_nvram_get_pagesize(tp, nvcfg1);
11782 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11783 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11784 }
11785
11786 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11787 static void __devinit tg3_nvram_init(struct tg3 *tp)
11788 {
11789 tw32_f(GRC_EEPROM_ADDR,
11790 (EEPROM_ADDR_FSM_RESET |
11791 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11792 EEPROM_ADDR_CLKPERD_SHIFT)));
11793
11794 msleep(1);
11795
11796 /* Enable seeprom accesses. */
11797 tw32_f(GRC_LOCAL_CTRL,
11798 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11799 udelay(100);
11800
11801 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11802 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11803 tp->tg3_flags |= TG3_FLAG_NVRAM;
11804
11805 if (tg3_nvram_lock(tp)) {
11806 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11807 "tg3_nvram_init failed.\n", tp->dev->name);
11808 return;
11809 }
11810 tg3_enable_nvram_access(tp);
11811
11812 tp->nvram_size = 0;
11813
11814 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11815 tg3_get_5752_nvram_info(tp);
11816 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11817 tg3_get_5755_nvram_info(tp);
11818 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11819 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11820 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11821 tg3_get_5787_nvram_info(tp);
11822 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11823 tg3_get_5761_nvram_info(tp);
11824 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11825 tg3_get_5906_nvram_info(tp);
11826 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11827 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11828 tg3_get_57780_nvram_info(tp);
11829 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11830 tg3_get_5717_nvram_info(tp);
11831 else
11832 tg3_get_nvram_info(tp);
11833
11834 if (tp->nvram_size == 0)
11835 tg3_get_nvram_size(tp);
11836
11837 tg3_disable_nvram_access(tp);
11838 tg3_nvram_unlock(tp);
11839
11840 } else {
11841 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11842
11843 tg3_get_eeprom_size(tp);
11844 }
11845 }
11846
11847 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11848 u32 offset, u32 len, u8 *buf)
11849 {
11850 int i, j, rc = 0;
11851 u32 val;
11852
11853 for (i = 0; i < len; i += 4) {
11854 u32 addr;
11855 __be32 data;
11856
11857 addr = offset + i;
11858
11859 memcpy(&data, buf + i, 4);
11860
11861 /*
11862 * The SEEPROM interface expects the data to always be opposite
11863 * the native endian format. We accomplish this by reversing
11864 * all the operations that would have been performed on the
11865 * data from a call to tg3_nvram_read_be32().
11866 */
11867 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11868
11869 val = tr32(GRC_EEPROM_ADDR);
11870 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11871
11872 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11873 EEPROM_ADDR_READ);
11874 tw32(GRC_EEPROM_ADDR, val |
11875 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11876 (addr & EEPROM_ADDR_ADDR_MASK) |
11877 EEPROM_ADDR_START |
11878 EEPROM_ADDR_WRITE);
11879
11880 for (j = 0; j < 1000; j++) {
11881 val = tr32(GRC_EEPROM_ADDR);
11882
11883 if (val & EEPROM_ADDR_COMPLETE)
11884 break;
11885 msleep(1);
11886 }
11887 if (!(val & EEPROM_ADDR_COMPLETE)) {
11888 rc = -EBUSY;
11889 break;
11890 }
11891 }
11892
11893 return rc;
11894 }
11895
11896 /* offset and length are dword aligned */
11897 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11898 u8 *buf)
11899 {
11900 int ret = 0;
11901 u32 pagesize = tp->nvram_pagesize;
11902 u32 pagemask = pagesize - 1;
11903 u32 nvram_cmd;
11904 u8 *tmp;
11905
11906 tmp = kmalloc(pagesize, GFP_KERNEL);
11907 if (tmp == NULL)
11908 return -ENOMEM;
11909
11910 while (len) {
11911 int j;
11912 u32 phy_addr, page_off, size;
11913
11914 phy_addr = offset & ~pagemask;
11915
11916 for (j = 0; j < pagesize; j += 4) {
11917 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11918 (__be32 *) (tmp + j));
11919 if (ret)
11920 break;
11921 }
11922 if (ret)
11923 break;
11924
11925 page_off = offset & pagemask;
11926 size = pagesize;
11927 if (len < size)
11928 size = len;
11929
11930 len -= size;
11931
11932 memcpy(tmp + page_off, buf, size);
11933
11934 offset = offset + (pagesize - page_off);
11935
11936 tg3_enable_nvram_access(tp);
11937
11938 /*
11939 * Before we can erase the flash page, we need
11940 * to issue a special "write enable" command.
11941 */
11942 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11943
11944 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11945 break;
11946
11947 /* Erase the target page */
11948 tw32(NVRAM_ADDR, phy_addr);
11949
11950 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11951 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11952
11953 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11954 break;
11955
11956 /* Issue another write enable to start the write. */
11957 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11958
11959 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11960 break;
11961
11962 for (j = 0; j < pagesize; j += 4) {
11963 __be32 data;
11964
11965 data = *((__be32 *) (tmp + j));
11966
11967 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11968
11969 tw32(NVRAM_ADDR, phy_addr + j);
11970
11971 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11972 NVRAM_CMD_WR;
11973
11974 if (j == 0)
11975 nvram_cmd |= NVRAM_CMD_FIRST;
11976 else if (j == (pagesize - 4))
11977 nvram_cmd |= NVRAM_CMD_LAST;
11978
11979 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11980 break;
11981 }
11982 if (ret)
11983 break;
11984 }
11985
11986 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11987 tg3_nvram_exec_cmd(tp, nvram_cmd);
11988
11989 kfree(tmp);
11990
11991 return ret;
11992 }
11993
11994 /* offset and length are dword aligned */
11995 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11996 u8 *buf)
11997 {
11998 int i, ret = 0;
11999
12000 for (i = 0; i < len; i += 4, offset += 4) {
12001 u32 page_off, phy_addr, nvram_cmd;
12002 __be32 data;
12003
12004 memcpy(&data, buf + i, 4);
12005 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12006
12007 page_off = offset % tp->nvram_pagesize;
12008
12009 phy_addr = tg3_nvram_phys_addr(tp, offset);
12010
12011 tw32(NVRAM_ADDR, phy_addr);
12012
12013 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12014
12015 if ((page_off == 0) || (i == 0))
12016 nvram_cmd |= NVRAM_CMD_FIRST;
12017 if (page_off == (tp->nvram_pagesize - 4))
12018 nvram_cmd |= NVRAM_CMD_LAST;
12019
12020 if (i == (len - 4))
12021 nvram_cmd |= NVRAM_CMD_LAST;
12022
12023 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12024 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12025 (tp->nvram_jedecnum == JEDEC_ST) &&
12026 (nvram_cmd & NVRAM_CMD_FIRST)) {
12027
12028 if ((ret = tg3_nvram_exec_cmd(tp,
12029 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12030 NVRAM_CMD_DONE)))
12031
12032 break;
12033 }
12034 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12035 /* We always do complete word writes to eeprom. */
12036 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12037 }
12038
12039 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12040 break;
12041 }
12042 return ret;
12043 }
12044
12045 /* offset and length are dword aligned */
12046 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12047 {
12048 int ret;
12049
12050 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12051 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12052 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12053 udelay(40);
12054 }
12055
12056 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12057 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12058 }
12059 else {
12060 u32 grc_mode;
12061
12062 ret = tg3_nvram_lock(tp);
12063 if (ret)
12064 return ret;
12065
12066 tg3_enable_nvram_access(tp);
12067 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12068 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12069 tw32(NVRAM_WRITE1, 0x406);
12070
12071 grc_mode = tr32(GRC_MODE);
12072 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12073
12074 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12075 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12076
12077 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12078 buf);
12079 }
12080 else {
12081 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12082 buf);
12083 }
12084
12085 grc_mode = tr32(GRC_MODE);
12086 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12087
12088 tg3_disable_nvram_access(tp);
12089 tg3_nvram_unlock(tp);
12090 }
12091
12092 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12093 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12094 udelay(40);
12095 }
12096
12097 return ret;
12098 }
12099
12100 struct subsys_tbl_ent {
12101 u16 subsys_vendor, subsys_devid;
12102 u32 phy_id;
12103 };
12104
12105 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12106 /* Broadcom boards. */
12107 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12108 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12109 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12110 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
12111 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12112 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12113 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
12114 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12115 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12116 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12117 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12118
12119 /* 3com boards. */
12120 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12121 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12122 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
12123 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12124 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12125
12126 /* DELL boards. */
12127 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12128 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12129 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12130 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12131
12132 /* Compaq boards. */
12133 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12134 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12135 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
12136 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12137 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12138
12139 /* IBM boards. */
12140 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12141 };
12142
12143 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12144 {
12145 int i;
12146
12147 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12148 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12149 tp->pdev->subsystem_vendor) &&
12150 (subsys_id_to_phy_id[i].subsys_devid ==
12151 tp->pdev->subsystem_device))
12152 return &subsys_id_to_phy_id[i];
12153 }
12154 return NULL;
12155 }
12156
12157 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12158 {
12159 u32 val;
12160 u16 pmcsr;
12161
12162 /* On some early chips the SRAM cannot be accessed in D3hot state,
12163 * so need make sure we're in D0.
12164 */
12165 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12166 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12167 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12168 msleep(1);
12169
12170 /* Make sure register accesses (indirect or otherwise)
12171 * will function correctly.
12172 */
12173 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12174 tp->misc_host_ctrl);
12175
12176 /* The memory arbiter has to be enabled in order for SRAM accesses
12177 * to succeed. Normally on powerup the tg3 chip firmware will make
12178 * sure it is enabled, but other entities such as system netboot
12179 * code might disable it.
12180 */
12181 val = tr32(MEMARB_MODE);
12182 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12183
12184 tp->phy_id = PHY_ID_INVALID;
12185 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12186
12187 /* Assume an onboard device and WOL capable by default. */
12188 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12189
12190 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12191 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12192 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12193 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12194 }
12195 val = tr32(VCPU_CFGSHDW);
12196 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12197 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12198 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12199 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12200 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12201 goto done;
12202 }
12203
12204 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12205 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12206 u32 nic_cfg, led_cfg;
12207 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12208 int eeprom_phy_serdes = 0;
12209
12210 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12211 tp->nic_sram_data_cfg = nic_cfg;
12212
12213 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12214 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12215 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12216 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12217 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12218 (ver > 0) && (ver < 0x100))
12219 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12220
12221 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12222 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12223
12224 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12225 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12226 eeprom_phy_serdes = 1;
12227
12228 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12229 if (nic_phy_id != 0) {
12230 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12231 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12232
12233 eeprom_phy_id = (id1 >> 16) << 10;
12234 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12235 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12236 } else
12237 eeprom_phy_id = 0;
12238
12239 tp->phy_id = eeprom_phy_id;
12240 if (eeprom_phy_serdes) {
12241 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12242 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12243 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12244 else
12245 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12246 }
12247
12248 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12249 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12250 SHASTA_EXT_LED_MODE_MASK);
12251 else
12252 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12253
12254 switch (led_cfg) {
12255 default:
12256 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12257 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12258 break;
12259
12260 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12261 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12262 break;
12263
12264 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12265 tp->led_ctrl = LED_CTRL_MODE_MAC;
12266
12267 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12268 * read on some older 5700/5701 bootcode.
12269 */
12270 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12271 ASIC_REV_5700 ||
12272 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12273 ASIC_REV_5701)
12274 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12275
12276 break;
12277
12278 case SHASTA_EXT_LED_SHARED:
12279 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12280 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12281 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12282 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12283 LED_CTRL_MODE_PHY_2);
12284 break;
12285
12286 case SHASTA_EXT_LED_MAC:
12287 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12288 break;
12289
12290 case SHASTA_EXT_LED_COMBO:
12291 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12292 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12293 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12294 LED_CTRL_MODE_PHY_2);
12295 break;
12296
12297 }
12298
12299 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12300 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12301 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12302 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12303
12304 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12305 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12306
12307 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12308 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12309 if ((tp->pdev->subsystem_vendor ==
12310 PCI_VENDOR_ID_ARIMA) &&
12311 (tp->pdev->subsystem_device == 0x205a ||
12312 tp->pdev->subsystem_device == 0x2063))
12313 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12314 } else {
12315 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12316 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12317 }
12318
12319 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12320 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12321 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12322 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12323 }
12324
12325 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12326 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12327 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12328
12329 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12330 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12331 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12332
12333 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12334 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12335 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12336
12337 if (cfg2 & (1 << 17))
12338 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12339
12340 /* serdes signal pre-emphasis in register 0x590 set by */
12341 /* bootcode if bit 18 is set */
12342 if (cfg2 & (1 << 18))
12343 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12344
12345 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12346 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12347 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12348 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12349
12350 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12351 u32 cfg3;
12352
12353 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12354 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12355 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12356 }
12357
12358 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12359 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12360 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12361 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12362 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12363 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12364 }
12365 done:
12366 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12367 device_set_wakeup_enable(&tp->pdev->dev,
12368 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12369 }
12370
12371 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12372 {
12373 int i;
12374 u32 val;
12375
12376 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12377 tw32(OTP_CTRL, cmd);
12378
12379 /* Wait for up to 1 ms for command to execute. */
12380 for (i = 0; i < 100; i++) {
12381 val = tr32(OTP_STATUS);
12382 if (val & OTP_STATUS_CMD_DONE)
12383 break;
12384 udelay(10);
12385 }
12386
12387 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12388 }
12389
12390 /* Read the gphy configuration from the OTP region of the chip. The gphy
12391 * configuration is a 32-bit value that straddles the alignment boundary.
12392 * We do two 32-bit reads and then shift and merge the results.
12393 */
12394 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12395 {
12396 u32 bhalf_otp, thalf_otp;
12397
12398 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12399
12400 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12401 return 0;
12402
12403 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12404
12405 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12406 return 0;
12407
12408 thalf_otp = tr32(OTP_READ_DATA);
12409
12410 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12411
12412 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12413 return 0;
12414
12415 bhalf_otp = tr32(OTP_READ_DATA);
12416
12417 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12418 }
12419
12420 static int __devinit tg3_phy_probe(struct tg3 *tp)
12421 {
12422 u32 hw_phy_id_1, hw_phy_id_2;
12423 u32 hw_phy_id, hw_phy_id_masked;
12424 int err;
12425
12426 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12427 return tg3_phy_init(tp);
12428
12429 /* Reading the PHY ID register can conflict with ASF
12430 * firmware access to the PHY hardware.
12431 */
12432 err = 0;
12433 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12434 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12435 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12436 } else {
12437 /* Now read the physical PHY_ID from the chip and verify
12438 * that it is sane. If it doesn't look good, we fall back
12439 * to either the hard-coded table based PHY_ID and failing
12440 * that the value found in the eeprom area.
12441 */
12442 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12443 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12444
12445 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12446 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12447 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12448
12449 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12450 }
12451
12452 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12453 tp->phy_id = hw_phy_id;
12454 if (hw_phy_id_masked == PHY_ID_BCM8002)
12455 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12456 else
12457 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12458 } else {
12459 if (tp->phy_id != PHY_ID_INVALID) {
12460 /* Do nothing, phy ID already set up in
12461 * tg3_get_eeprom_hw_cfg().
12462 */
12463 } else {
12464 struct subsys_tbl_ent *p;
12465
12466 /* No eeprom signature? Try the hardcoded
12467 * subsys device table.
12468 */
12469 p = lookup_by_subsys(tp);
12470 if (!p)
12471 return -ENODEV;
12472
12473 tp->phy_id = p->phy_id;
12474 if (!tp->phy_id ||
12475 tp->phy_id == PHY_ID_BCM8002)
12476 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12477 }
12478 }
12479
12480 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12481 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12482 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12483 u32 bmsr, adv_reg, tg3_ctrl, mask;
12484
12485 tg3_readphy(tp, MII_BMSR, &bmsr);
12486 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12487 (bmsr & BMSR_LSTATUS))
12488 goto skip_phy_reset;
12489
12490 err = tg3_phy_reset(tp);
12491 if (err)
12492 return err;
12493
12494 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12495 ADVERTISE_100HALF | ADVERTISE_100FULL |
12496 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12497 tg3_ctrl = 0;
12498 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12499 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12500 MII_TG3_CTRL_ADV_1000_FULL);
12501 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12502 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12503 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12504 MII_TG3_CTRL_ENABLE_AS_MASTER);
12505 }
12506
12507 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12508 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12509 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12510 if (!tg3_copper_is_advertising_all(tp, mask)) {
12511 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12512
12513 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12514 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12515
12516 tg3_writephy(tp, MII_BMCR,
12517 BMCR_ANENABLE | BMCR_ANRESTART);
12518 }
12519 tg3_phy_set_wirespeed(tp);
12520
12521 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12522 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12523 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12524 }
12525
12526 skip_phy_reset:
12527 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12528 err = tg3_init_5401phy_dsp(tp);
12529 if (err)
12530 return err;
12531 }
12532
12533 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12534 err = tg3_init_5401phy_dsp(tp);
12535 }
12536
12537 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12538 tp->link_config.advertising =
12539 (ADVERTISED_1000baseT_Half |
12540 ADVERTISED_1000baseT_Full |
12541 ADVERTISED_Autoneg |
12542 ADVERTISED_FIBRE);
12543 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12544 tp->link_config.advertising &=
12545 ~(ADVERTISED_1000baseT_Half |
12546 ADVERTISED_1000baseT_Full);
12547
12548 return err;
12549 }
12550
12551 static void __devinit tg3_read_partno(struct tg3 *tp)
12552 {
12553 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
12554 unsigned int i;
12555 u32 magic;
12556
12557 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12558 tg3_nvram_read(tp, 0x0, &magic))
12559 goto out_not_found;
12560
12561 if (magic == TG3_EEPROM_MAGIC) {
12562 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12563 u32 tmp;
12564
12565 /* The data is in little-endian format in NVRAM.
12566 * Use the big-endian read routines to preserve
12567 * the byte order as it exists in NVRAM.
12568 */
12569 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12570 goto out_not_found;
12571
12572 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12573 }
12574 } else {
12575 ssize_t cnt;
12576 unsigned int pos = 0, i = 0;
12577
12578 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12579 cnt = pci_read_vpd(tp->pdev, pos,
12580 TG3_NVM_VPD_LEN - pos,
12581 &vpd_data[pos]);
12582 if (cnt == -ETIMEDOUT || -EINTR)
12583 cnt = 0;
12584 else if (cnt < 0)
12585 goto out_not_found;
12586 }
12587 if (pos != TG3_NVM_VPD_LEN)
12588 goto out_not_found;
12589 }
12590
12591 /* Now parse and find the part number. */
12592 for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
12593 unsigned char val = vpd_data[i];
12594 unsigned int block_end;
12595
12596 if (val == 0x82 || val == 0x91) {
12597 i = (i + 3 +
12598 (vpd_data[i + 1] +
12599 (vpd_data[i + 2] << 8)));
12600 continue;
12601 }
12602
12603 if (val != 0x90)
12604 goto out_not_found;
12605
12606 block_end = (i + 3 +
12607 (vpd_data[i + 1] +
12608 (vpd_data[i + 2] << 8)));
12609 i += 3;
12610
12611 if (block_end > TG3_NVM_VPD_LEN)
12612 goto out_not_found;
12613
12614 while (i < (block_end - 2)) {
12615 if (vpd_data[i + 0] == 'P' &&
12616 vpd_data[i + 1] == 'N') {
12617 int partno_len = vpd_data[i + 2];
12618
12619 i += 3;
12620 if (partno_len > TG3_BPN_SIZE ||
12621 (partno_len + i) > TG3_NVM_VPD_LEN)
12622 goto out_not_found;
12623
12624 memcpy(tp->board_part_number,
12625 &vpd_data[i], partno_len);
12626
12627 /* Success. */
12628 return;
12629 }
12630 i += 3 + vpd_data[i + 2];
12631 }
12632
12633 /* Part number not found. */
12634 goto out_not_found;
12635 }
12636
12637 out_not_found:
12638 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12639 strcpy(tp->board_part_number, "BCM95906");
12640 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12641 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12642 strcpy(tp->board_part_number, "BCM57780");
12643 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12644 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12645 strcpy(tp->board_part_number, "BCM57760");
12646 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12647 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12648 strcpy(tp->board_part_number, "BCM57790");
12649 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12650 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12651 strcpy(tp->board_part_number, "BCM57788");
12652 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12653 strcpy(tp->board_part_number, "BCM57765");
12654 else
12655 strcpy(tp->board_part_number, "none");
12656 }
12657
12658 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12659 {
12660 u32 val;
12661
12662 if (tg3_nvram_read(tp, offset, &val) ||
12663 (val & 0xfc000000) != 0x0c000000 ||
12664 tg3_nvram_read(tp, offset + 4, &val) ||
12665 val != 0)
12666 return 0;
12667
12668 return 1;
12669 }
12670
12671 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12672 {
12673 u32 val, offset, start, ver_offset;
12674 int i;
12675 bool newver = false;
12676
12677 if (tg3_nvram_read(tp, 0xc, &offset) ||
12678 tg3_nvram_read(tp, 0x4, &start))
12679 return;
12680
12681 offset = tg3_nvram_logical_addr(tp, offset);
12682
12683 if (tg3_nvram_read(tp, offset, &val))
12684 return;
12685
12686 if ((val & 0xfc000000) == 0x0c000000) {
12687 if (tg3_nvram_read(tp, offset + 4, &val))
12688 return;
12689
12690 if (val == 0)
12691 newver = true;
12692 }
12693
12694 if (newver) {
12695 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12696 return;
12697
12698 offset = offset + ver_offset - start;
12699 for (i = 0; i < 16; i += 4) {
12700 __be32 v;
12701 if (tg3_nvram_read_be32(tp, offset + i, &v))
12702 return;
12703
12704 memcpy(tp->fw_ver + i, &v, sizeof(v));
12705 }
12706 } else {
12707 u32 major, minor;
12708
12709 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12710 return;
12711
12712 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12713 TG3_NVM_BCVER_MAJSFT;
12714 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12715 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12716 }
12717 }
12718
12719 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12720 {
12721 u32 val, major, minor;
12722
12723 /* Use native endian representation */
12724 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12725 return;
12726
12727 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12728 TG3_NVM_HWSB_CFG1_MAJSFT;
12729 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12730 TG3_NVM_HWSB_CFG1_MINSFT;
12731
12732 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12733 }
12734
12735 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12736 {
12737 u32 offset, major, minor, build;
12738
12739 tp->fw_ver[0] = 's';
12740 tp->fw_ver[1] = 'b';
12741 tp->fw_ver[2] = '\0';
12742
12743 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12744 return;
12745
12746 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12747 case TG3_EEPROM_SB_REVISION_0:
12748 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12749 break;
12750 case TG3_EEPROM_SB_REVISION_2:
12751 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12752 break;
12753 case TG3_EEPROM_SB_REVISION_3:
12754 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12755 break;
12756 case TG3_EEPROM_SB_REVISION_4:
12757 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12758 break;
12759 case TG3_EEPROM_SB_REVISION_5:
12760 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12761 break;
12762 default:
12763 return;
12764 }
12765
12766 if (tg3_nvram_read(tp, offset, &val))
12767 return;
12768
12769 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12770 TG3_EEPROM_SB_EDH_BLD_SHFT;
12771 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12772 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12773 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12774
12775 if (minor > 99 || build > 26)
12776 return;
12777
12778 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12779
12780 if (build > 0) {
12781 tp->fw_ver[8] = 'a' + build - 1;
12782 tp->fw_ver[9] = '\0';
12783 }
12784 }
12785
12786 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12787 {
12788 u32 val, offset, start;
12789 int i, vlen;
12790
12791 for (offset = TG3_NVM_DIR_START;
12792 offset < TG3_NVM_DIR_END;
12793 offset += TG3_NVM_DIRENT_SIZE) {
12794 if (tg3_nvram_read(tp, offset, &val))
12795 return;
12796
12797 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12798 break;
12799 }
12800
12801 if (offset == TG3_NVM_DIR_END)
12802 return;
12803
12804 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12805 start = 0x08000000;
12806 else if (tg3_nvram_read(tp, offset - 4, &start))
12807 return;
12808
12809 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12810 !tg3_fw_img_is_valid(tp, offset) ||
12811 tg3_nvram_read(tp, offset + 8, &val))
12812 return;
12813
12814 offset += val - start;
12815
12816 vlen = strlen(tp->fw_ver);
12817
12818 tp->fw_ver[vlen++] = ',';
12819 tp->fw_ver[vlen++] = ' ';
12820
12821 for (i = 0; i < 4; i++) {
12822 __be32 v;
12823 if (tg3_nvram_read_be32(tp, offset, &v))
12824 return;
12825
12826 offset += sizeof(v);
12827
12828 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12829 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12830 break;
12831 }
12832
12833 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12834 vlen += sizeof(v);
12835 }
12836 }
12837
12838 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12839 {
12840 int vlen;
12841 u32 apedata;
12842
12843 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12844 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12845 return;
12846
12847 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12848 if (apedata != APE_SEG_SIG_MAGIC)
12849 return;
12850
12851 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12852 if (!(apedata & APE_FW_STATUS_READY))
12853 return;
12854
12855 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12856
12857 vlen = strlen(tp->fw_ver);
12858
12859 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12860 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12861 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12862 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12863 (apedata & APE_FW_VERSION_BLDMSK));
12864 }
12865
12866 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12867 {
12868 u32 val;
12869
12870 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12871 tp->fw_ver[0] = 's';
12872 tp->fw_ver[1] = 'b';
12873 tp->fw_ver[2] = '\0';
12874
12875 return;
12876 }
12877
12878 if (tg3_nvram_read(tp, 0, &val))
12879 return;
12880
12881 if (val == TG3_EEPROM_MAGIC)
12882 tg3_read_bc_ver(tp);
12883 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12884 tg3_read_sb_ver(tp, val);
12885 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12886 tg3_read_hwsb_ver(tp);
12887 else
12888 return;
12889
12890 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12891 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12892 return;
12893
12894 tg3_read_mgmtfw_ver(tp);
12895
12896 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12897 }
12898
12899 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12900
12901 static int __devinit tg3_get_invariants(struct tg3 *tp)
12902 {
12903 static struct pci_device_id write_reorder_chipsets[] = {
12904 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12905 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12906 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12907 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12908 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12909 PCI_DEVICE_ID_VIA_8385_0) },
12910 { },
12911 };
12912 u32 misc_ctrl_reg;
12913 u32 pci_state_reg, grc_misc_cfg;
12914 u32 val;
12915 u16 pci_cmd;
12916 int err;
12917
12918 /* Force memory write invalidate off. If we leave it on,
12919 * then on 5700_BX chips we have to enable a workaround.
12920 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12921 * to match the cacheline size. The Broadcom driver have this
12922 * workaround but turns MWI off all the times so never uses
12923 * it. This seems to suggest that the workaround is insufficient.
12924 */
12925 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12926 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12927 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12928
12929 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12930 * has the register indirect write enable bit set before
12931 * we try to access any of the MMIO registers. It is also
12932 * critical that the PCI-X hw workaround situation is decided
12933 * before that as well.
12934 */
12935 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12936 &misc_ctrl_reg);
12937
12938 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12939 MISC_HOST_CTRL_CHIPREV_SHIFT);
12940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12941 u32 prod_id_asic_rev;
12942
12943 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12944 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12945 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12946 pci_read_config_dword(tp->pdev,
12947 TG3PCI_GEN2_PRODID_ASICREV,
12948 &prod_id_asic_rev);
12949 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12950 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12951 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12952 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12953 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12954 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12955 pci_read_config_dword(tp->pdev,
12956 TG3PCI_GEN15_PRODID_ASICREV,
12957 &prod_id_asic_rev);
12958 else
12959 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12960 &prod_id_asic_rev);
12961
12962 tp->pci_chip_rev_id = prod_id_asic_rev;
12963 }
12964
12965 /* Wrong chip ID in 5752 A0. This code can be removed later
12966 * as A0 is not in production.
12967 */
12968 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12969 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12970
12971 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12972 * we need to disable memory and use config. cycles
12973 * only to access all registers. The 5702/03 chips
12974 * can mistakenly decode the special cycles from the
12975 * ICH chipsets as memory write cycles, causing corruption
12976 * of register and memory space. Only certain ICH bridges
12977 * will drive special cycles with non-zero data during the
12978 * address phase which can fall within the 5703's address
12979 * range. This is not an ICH bug as the PCI spec allows
12980 * non-zero address during special cycles. However, only
12981 * these ICH bridges are known to drive non-zero addresses
12982 * during special cycles.
12983 *
12984 * Since special cycles do not cross PCI bridges, we only
12985 * enable this workaround if the 5703 is on the secondary
12986 * bus of these ICH bridges.
12987 */
12988 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12989 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12990 static struct tg3_dev_id {
12991 u32 vendor;
12992 u32 device;
12993 u32 rev;
12994 } ich_chipsets[] = {
12995 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12996 PCI_ANY_ID },
12997 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12998 PCI_ANY_ID },
12999 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13000 0xa },
13001 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13002 PCI_ANY_ID },
13003 { },
13004 };
13005 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13006 struct pci_dev *bridge = NULL;
13007
13008 while (pci_id->vendor != 0) {
13009 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13010 bridge);
13011 if (!bridge) {
13012 pci_id++;
13013 continue;
13014 }
13015 if (pci_id->rev != PCI_ANY_ID) {
13016 if (bridge->revision > pci_id->rev)
13017 continue;
13018 }
13019 if (bridge->subordinate &&
13020 (bridge->subordinate->number ==
13021 tp->pdev->bus->number)) {
13022
13023 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13024 pci_dev_put(bridge);
13025 break;
13026 }
13027 }
13028 }
13029
13030 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13031 static struct tg3_dev_id {
13032 u32 vendor;
13033 u32 device;
13034 } bridge_chipsets[] = {
13035 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13036 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13037 { },
13038 };
13039 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13040 struct pci_dev *bridge = NULL;
13041
13042 while (pci_id->vendor != 0) {
13043 bridge = pci_get_device(pci_id->vendor,
13044 pci_id->device,
13045 bridge);
13046 if (!bridge) {
13047 pci_id++;
13048 continue;
13049 }
13050 if (bridge->subordinate &&
13051 (bridge->subordinate->number <=
13052 tp->pdev->bus->number) &&
13053 (bridge->subordinate->subordinate >=
13054 tp->pdev->bus->number)) {
13055 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13056 pci_dev_put(bridge);
13057 break;
13058 }
13059 }
13060 }
13061
13062 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13063 * DMA addresses > 40-bit. This bridge may have other additional
13064 * 57xx devices behind it in some 4-port NIC designs for example.
13065 * Any tg3 device found behind the bridge will also need the 40-bit
13066 * DMA workaround.
13067 */
13068 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13070 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13071 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13072 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13073 }
13074 else {
13075 struct pci_dev *bridge = NULL;
13076
13077 do {
13078 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13079 PCI_DEVICE_ID_SERVERWORKS_EPB,
13080 bridge);
13081 if (bridge && bridge->subordinate &&
13082 (bridge->subordinate->number <=
13083 tp->pdev->bus->number) &&
13084 (bridge->subordinate->subordinate >=
13085 tp->pdev->bus->number)) {
13086 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13087 pci_dev_put(bridge);
13088 break;
13089 }
13090 } while (bridge);
13091 }
13092
13093 /* Initialize misc host control in PCI block. */
13094 tp->misc_host_ctrl |= (misc_ctrl_reg &
13095 MISC_HOST_CTRL_CHIPREV);
13096 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13097 tp->misc_host_ctrl);
13098
13099 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13102 tp->pdev_peer = tg3_find_peer(tp);
13103
13104 /* Intentionally exclude ASIC_REV_5906 */
13105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13108 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13109 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13113 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13114
13115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13116 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13117 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13118 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13119 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13120 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13121
13122 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13123 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13124 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13125
13126 /* 5700 B0 chips do not support checksumming correctly due
13127 * to hardware bugs.
13128 */
13129 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13130 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13131 else {
13132 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13133 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13134 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13135 tp->dev->features |= NETIF_F_IPV6_CSUM;
13136 }
13137
13138 /* Determine TSO capabilities */
13139 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13140 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13141 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13142 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13143 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13144 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13145 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13146 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13147 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13148 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13149 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13150 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13151 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13152 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13153 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13155 tp->fw_needed = FIRMWARE_TG3TSO5;
13156 else
13157 tp->fw_needed = FIRMWARE_TG3TSO;
13158 }
13159
13160 tp->irq_max = 1;
13161
13162 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13163 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13164 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13165 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13166 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13167 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13168 tp->pdev_peer == tp->pdev))
13169 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13170
13171 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13172 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13173 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13174 }
13175
13176 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13177 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13178 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13179 tp->irq_max = TG3_IRQ_MAX_VECS;
13180 }
13181 }
13182
13183 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13184 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13185 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13186 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13187 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13188 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13189 }
13190
13191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13193 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13194
13195 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13196 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13197 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13198 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13199
13200 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13201 &pci_state_reg);
13202
13203 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13204 if (tp->pcie_cap != 0) {
13205 u16 lnkctl;
13206
13207 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13208
13209 pcie_set_readrq(tp->pdev, 4096);
13210
13211 pci_read_config_word(tp->pdev,
13212 tp->pcie_cap + PCI_EXP_LNKCTL,
13213 &lnkctl);
13214 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13216 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13218 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13219 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13220 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13221 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13222 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13223 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13224 }
13225 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13226 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13227 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13228 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13229 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13230 if (!tp->pcix_cap) {
13231 printk(KERN_ERR PFX "Cannot find PCI-X "
13232 "capability, aborting.\n");
13233 return -EIO;
13234 }
13235
13236 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13237 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13238 }
13239
13240 /* If we have an AMD 762 or VIA K8T800 chipset, write
13241 * reordering to the mailbox registers done by the host
13242 * controller can cause major troubles. We read back from
13243 * every mailbox register write to force the writes to be
13244 * posted to the chip in order.
13245 */
13246 if (pci_dev_present(write_reorder_chipsets) &&
13247 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13248 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13249
13250 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13251 &tp->pci_cacheline_sz);
13252 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13253 &tp->pci_lat_timer);
13254 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13255 tp->pci_lat_timer < 64) {
13256 tp->pci_lat_timer = 64;
13257 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13258 tp->pci_lat_timer);
13259 }
13260
13261 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13262 /* 5700 BX chips need to have their TX producer index
13263 * mailboxes written twice to workaround a bug.
13264 */
13265 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13266
13267 /* If we are in PCI-X mode, enable register write workaround.
13268 *
13269 * The workaround is to use indirect register accesses
13270 * for all chip writes not to mailbox registers.
13271 */
13272 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13273 u32 pm_reg;
13274
13275 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13276
13277 /* The chip can have it's power management PCI config
13278 * space registers clobbered due to this bug.
13279 * So explicitly force the chip into D0 here.
13280 */
13281 pci_read_config_dword(tp->pdev,
13282 tp->pm_cap + PCI_PM_CTRL,
13283 &pm_reg);
13284 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13285 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13286 pci_write_config_dword(tp->pdev,
13287 tp->pm_cap + PCI_PM_CTRL,
13288 pm_reg);
13289
13290 /* Also, force SERR#/PERR# in PCI command. */
13291 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13292 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13293 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13294 }
13295 }
13296
13297 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13298 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13299 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13300 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13301
13302 /* Chip-specific fixup from Broadcom driver */
13303 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13304 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13305 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13306 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13307 }
13308
13309 /* Default fast path register access methods */
13310 tp->read32 = tg3_read32;
13311 tp->write32 = tg3_write32;
13312 tp->read32_mbox = tg3_read32;
13313 tp->write32_mbox = tg3_write32;
13314 tp->write32_tx_mbox = tg3_write32;
13315 tp->write32_rx_mbox = tg3_write32;
13316
13317 /* Various workaround register access methods */
13318 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13319 tp->write32 = tg3_write_indirect_reg32;
13320 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13321 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13322 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13323 /*
13324 * Back to back register writes can cause problems on these
13325 * chips, the workaround is to read back all reg writes
13326 * except those to mailbox regs.
13327 *
13328 * See tg3_write_indirect_reg32().
13329 */
13330 tp->write32 = tg3_write_flush_reg32;
13331 }
13332
13333 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13334 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13335 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13336 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13337 tp->write32_rx_mbox = tg3_write_flush_reg32;
13338 }
13339
13340 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13341 tp->read32 = tg3_read_indirect_reg32;
13342 tp->write32 = tg3_write_indirect_reg32;
13343 tp->read32_mbox = tg3_read_indirect_mbox;
13344 tp->write32_mbox = tg3_write_indirect_mbox;
13345 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13346 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13347
13348 iounmap(tp->regs);
13349 tp->regs = NULL;
13350
13351 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13352 pci_cmd &= ~PCI_COMMAND_MEMORY;
13353 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13354 }
13355 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13356 tp->read32_mbox = tg3_read32_mbox_5906;
13357 tp->write32_mbox = tg3_write32_mbox_5906;
13358 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13359 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13360 }
13361
13362 if (tp->write32 == tg3_write_indirect_reg32 ||
13363 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13364 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13365 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13366 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13367
13368 /* Get eeprom hw config before calling tg3_set_power_state().
13369 * In particular, the TG3_FLG2_IS_NIC flag must be
13370 * determined before calling tg3_set_power_state() so that
13371 * we know whether or not to switch out of Vaux power.
13372 * When the flag is set, it means that GPIO1 is used for eeprom
13373 * write protect and also implies that it is a LOM where GPIOs
13374 * are not used to switch power.
13375 */
13376 tg3_get_eeprom_hw_cfg(tp);
13377
13378 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13379 /* Allow reads and writes to the
13380 * APE register and memory space.
13381 */
13382 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13383 PCISTATE_ALLOW_APE_SHMEM_WR;
13384 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13385 pci_state_reg);
13386 }
13387
13388 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13389 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13390 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13391 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13392 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13393 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13394 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13395
13396 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13397 * GPIO1 driven high will bring 5700's external PHY out of reset.
13398 * It is also used as eeprom write protect on LOMs.
13399 */
13400 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13401 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13402 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13403 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13404 GRC_LCLCTRL_GPIO_OUTPUT1);
13405 /* Unused GPIO3 must be driven as output on 5752 because there
13406 * are no pull-up resistors on unused GPIO pins.
13407 */
13408 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13409 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13410
13411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13412 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13413 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13414 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13415
13416 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13417 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13418 /* Turn off the debug UART. */
13419 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13420 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13421 /* Keep VMain power. */
13422 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13423 GRC_LCLCTRL_GPIO_OUTPUT0;
13424 }
13425
13426 /* Force the chip into D0. */
13427 err = tg3_set_power_state(tp, PCI_D0);
13428 if (err) {
13429 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13430 pci_name(tp->pdev));
13431 return err;
13432 }
13433
13434 /* Derive initial jumbo mode from MTU assigned in
13435 * ether_setup() via the alloc_etherdev() call
13436 */
13437 if (tp->dev->mtu > ETH_DATA_LEN &&
13438 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13439 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13440
13441 /* Determine WakeOnLan speed to use. */
13442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13443 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13444 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13445 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13446 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13447 } else {
13448 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13449 }
13450
13451 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13452 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13453
13454 /* A few boards don't want Ethernet@WireSpeed phy feature */
13455 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13456 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13457 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13458 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13459 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13460 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13461 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13462
13463 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13464 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13465 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13466 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13467 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13468
13469 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13470 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13471 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13472 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13473 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13474 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13475 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13476 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13478 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13479 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13480 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13481 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13482 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13483 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13484 } else
13485 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13486 }
13487
13488 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13489 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13490 tp->phy_otp = tg3_read_otp_phycfg(tp);
13491 if (tp->phy_otp == 0)
13492 tp->phy_otp = TG3_OTP_DEFAULT;
13493 }
13494
13495 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13496 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13497 else
13498 tp->mi_mode = MAC_MI_MODE_BASE;
13499
13500 tp->coalesce_mode = 0;
13501 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13502 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13503 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13504
13505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13507 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13508
13509 err = tg3_mdio_init(tp);
13510 if (err)
13511 return err;
13512
13513 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13514 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13515 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13516 return -ENOTSUPP;
13517
13518 /* Initialize data/descriptor byte/word swapping. */
13519 val = tr32(GRC_MODE);
13520 val &= GRC_MODE_HOST_STACKUP;
13521 tw32(GRC_MODE, val | tp->grc_mode);
13522
13523 tg3_switch_clocks(tp);
13524
13525 /* Clear this out for sanity. */
13526 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13527
13528 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13529 &pci_state_reg);
13530 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13531 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13532 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13533
13534 if (chiprevid == CHIPREV_ID_5701_A0 ||
13535 chiprevid == CHIPREV_ID_5701_B0 ||
13536 chiprevid == CHIPREV_ID_5701_B2 ||
13537 chiprevid == CHIPREV_ID_5701_B5) {
13538 void __iomem *sram_base;
13539
13540 /* Write some dummy words into the SRAM status block
13541 * area, see if it reads back correctly. If the return
13542 * value is bad, force enable the PCIX workaround.
13543 */
13544 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13545
13546 writel(0x00000000, sram_base);
13547 writel(0x00000000, sram_base + 4);
13548 writel(0xffffffff, sram_base + 4);
13549 if (readl(sram_base) != 0x00000000)
13550 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13551 }
13552 }
13553
13554 udelay(50);
13555 tg3_nvram_init(tp);
13556
13557 grc_misc_cfg = tr32(GRC_MISC_CFG);
13558 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13559
13560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13561 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13562 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13563 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13564
13565 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13566 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13567 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13568 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13569 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13570 HOSTCC_MODE_CLRTICK_TXBD);
13571
13572 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13573 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13574 tp->misc_host_ctrl);
13575 }
13576
13577 /* Preserve the APE MAC_MODE bits */
13578 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13579 tp->mac_mode = tr32(MAC_MODE) |
13580 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13581 else
13582 tp->mac_mode = TG3_DEF_MAC_MODE;
13583
13584 /* these are limited to 10/100 only */
13585 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13586 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13587 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13588 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13589 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13590 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13591 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13592 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13593 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13594 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13595 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13596 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13597 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13598 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13599 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13600 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13601
13602 err = tg3_phy_probe(tp);
13603 if (err) {
13604 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13605 pci_name(tp->pdev), err);
13606 /* ... but do not return immediately ... */
13607 tg3_mdio_fini(tp);
13608 }
13609
13610 tg3_read_partno(tp);
13611 tg3_read_fw_ver(tp);
13612
13613 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13614 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13615 } else {
13616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13617 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13618 else
13619 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13620 }
13621
13622 /* 5700 {AX,BX} chips have a broken status block link
13623 * change bit implementation, so we must use the
13624 * status register in those cases.
13625 */
13626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13627 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13628 else
13629 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13630
13631 /* The led_ctrl is set during tg3_phy_probe, here we might
13632 * have to force the link status polling mechanism based
13633 * upon subsystem IDs.
13634 */
13635 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13636 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13637 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13638 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13639 TG3_FLAG_USE_LINKCHG_REG);
13640 }
13641
13642 /* For all SERDES we poll the MAC status register. */
13643 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13644 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13645 else
13646 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13647
13648 tp->rx_offset = NET_IP_ALIGN;
13649 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13650 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13651 tp->rx_offset = 0;
13652
13653 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13654
13655 /* Increment the rx prod index on the rx std ring by at most
13656 * 8 for these chips to workaround hw errata.
13657 */
13658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13659 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13660 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13661 tp->rx_std_max_post = 8;
13662
13663 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13664 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13665 PCIE_PWR_MGMT_L1_THRESH_MSK;
13666
13667 return err;
13668 }
13669
13670 #ifdef CONFIG_SPARC
13671 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13672 {
13673 struct net_device *dev = tp->dev;
13674 struct pci_dev *pdev = tp->pdev;
13675 struct device_node *dp = pci_device_to_OF_node(pdev);
13676 const unsigned char *addr;
13677 int len;
13678
13679 addr = of_get_property(dp, "local-mac-address", &len);
13680 if (addr && len == 6) {
13681 memcpy(dev->dev_addr, addr, 6);
13682 memcpy(dev->perm_addr, dev->dev_addr, 6);
13683 return 0;
13684 }
13685 return -ENODEV;
13686 }
13687
13688 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13689 {
13690 struct net_device *dev = tp->dev;
13691
13692 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13693 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13694 return 0;
13695 }
13696 #endif
13697
13698 static int __devinit tg3_get_device_address(struct tg3 *tp)
13699 {
13700 struct net_device *dev = tp->dev;
13701 u32 hi, lo, mac_offset;
13702 int addr_ok = 0;
13703
13704 #ifdef CONFIG_SPARC
13705 if (!tg3_get_macaddr_sparc(tp))
13706 return 0;
13707 #endif
13708
13709 mac_offset = 0x7c;
13710 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13711 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13712 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13713 mac_offset = 0xcc;
13714 if (tg3_nvram_lock(tp))
13715 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13716 else
13717 tg3_nvram_unlock(tp);
13718 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13719 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13720 mac_offset = 0xcc;
13721 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13722 mac_offset = 0x10;
13723
13724 /* First try to get it from MAC address mailbox. */
13725 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13726 if ((hi >> 16) == 0x484b) {
13727 dev->dev_addr[0] = (hi >> 8) & 0xff;
13728 dev->dev_addr[1] = (hi >> 0) & 0xff;
13729
13730 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13731 dev->dev_addr[2] = (lo >> 24) & 0xff;
13732 dev->dev_addr[3] = (lo >> 16) & 0xff;
13733 dev->dev_addr[4] = (lo >> 8) & 0xff;
13734 dev->dev_addr[5] = (lo >> 0) & 0xff;
13735
13736 /* Some old bootcode may report a 0 MAC address in SRAM */
13737 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13738 }
13739 if (!addr_ok) {
13740 /* Next, try NVRAM. */
13741 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13742 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13743 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13744 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13745 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13746 }
13747 /* Finally just fetch it out of the MAC control regs. */
13748 else {
13749 hi = tr32(MAC_ADDR_0_HIGH);
13750 lo = tr32(MAC_ADDR_0_LOW);
13751
13752 dev->dev_addr[5] = lo & 0xff;
13753 dev->dev_addr[4] = (lo >> 8) & 0xff;
13754 dev->dev_addr[3] = (lo >> 16) & 0xff;
13755 dev->dev_addr[2] = (lo >> 24) & 0xff;
13756 dev->dev_addr[1] = hi & 0xff;
13757 dev->dev_addr[0] = (hi >> 8) & 0xff;
13758 }
13759 }
13760
13761 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13762 #ifdef CONFIG_SPARC
13763 if (!tg3_get_default_macaddr_sparc(tp))
13764 return 0;
13765 #endif
13766 return -EINVAL;
13767 }
13768 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13769 return 0;
13770 }
13771
13772 #define BOUNDARY_SINGLE_CACHELINE 1
13773 #define BOUNDARY_MULTI_CACHELINE 2
13774
13775 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13776 {
13777 int cacheline_size;
13778 u8 byte;
13779 int goal;
13780
13781 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13782 if (byte == 0)
13783 cacheline_size = 1024;
13784 else
13785 cacheline_size = (int) byte * 4;
13786
13787 /* On 5703 and later chips, the boundary bits have no
13788 * effect.
13789 */
13790 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13791 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13792 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13793 goto out;
13794
13795 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13796 goal = BOUNDARY_MULTI_CACHELINE;
13797 #else
13798 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13799 goal = BOUNDARY_SINGLE_CACHELINE;
13800 #else
13801 goal = 0;
13802 #endif
13803 #endif
13804
13805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13806 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13807 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13808 goto out;
13809 }
13810
13811 if (!goal)
13812 goto out;
13813
13814 /* PCI controllers on most RISC systems tend to disconnect
13815 * when a device tries to burst across a cache-line boundary.
13816 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13817 *
13818 * Unfortunately, for PCI-E there are only limited
13819 * write-side controls for this, and thus for reads
13820 * we will still get the disconnects. We'll also waste
13821 * these PCI cycles for both read and write for chips
13822 * other than 5700 and 5701 which do not implement the
13823 * boundary bits.
13824 */
13825 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13826 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13827 switch (cacheline_size) {
13828 case 16:
13829 case 32:
13830 case 64:
13831 case 128:
13832 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13833 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13834 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13835 } else {
13836 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13837 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13838 }
13839 break;
13840
13841 case 256:
13842 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13843 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13844 break;
13845
13846 default:
13847 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13848 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13849 break;
13850 }
13851 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13852 switch (cacheline_size) {
13853 case 16:
13854 case 32:
13855 case 64:
13856 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13857 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13858 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13859 break;
13860 }
13861 /* fallthrough */
13862 case 128:
13863 default:
13864 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13865 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13866 break;
13867 }
13868 } else {
13869 switch (cacheline_size) {
13870 case 16:
13871 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13872 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13873 DMA_RWCTRL_WRITE_BNDRY_16);
13874 break;
13875 }
13876 /* fallthrough */
13877 case 32:
13878 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13879 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13880 DMA_RWCTRL_WRITE_BNDRY_32);
13881 break;
13882 }
13883 /* fallthrough */
13884 case 64:
13885 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13886 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13887 DMA_RWCTRL_WRITE_BNDRY_64);
13888 break;
13889 }
13890 /* fallthrough */
13891 case 128:
13892 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13893 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13894 DMA_RWCTRL_WRITE_BNDRY_128);
13895 break;
13896 }
13897 /* fallthrough */
13898 case 256:
13899 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13900 DMA_RWCTRL_WRITE_BNDRY_256);
13901 break;
13902 case 512:
13903 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13904 DMA_RWCTRL_WRITE_BNDRY_512);
13905 break;
13906 case 1024:
13907 default:
13908 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13909 DMA_RWCTRL_WRITE_BNDRY_1024);
13910 break;
13911 }
13912 }
13913
13914 out:
13915 return val;
13916 }
13917
13918 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13919 {
13920 struct tg3_internal_buffer_desc test_desc;
13921 u32 sram_dma_descs;
13922 int i, ret;
13923
13924 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13925
13926 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13927 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13928 tw32(RDMAC_STATUS, 0);
13929 tw32(WDMAC_STATUS, 0);
13930
13931 tw32(BUFMGR_MODE, 0);
13932 tw32(FTQ_RESET, 0);
13933
13934 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13935 test_desc.addr_lo = buf_dma & 0xffffffff;
13936 test_desc.nic_mbuf = 0x00002100;
13937 test_desc.len = size;
13938
13939 /*
13940 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13941 * the *second* time the tg3 driver was getting loaded after an
13942 * initial scan.
13943 *
13944 * Broadcom tells me:
13945 * ...the DMA engine is connected to the GRC block and a DMA
13946 * reset may affect the GRC block in some unpredictable way...
13947 * The behavior of resets to individual blocks has not been tested.
13948 *
13949 * Broadcom noted the GRC reset will also reset all sub-components.
13950 */
13951 if (to_device) {
13952 test_desc.cqid_sqid = (13 << 8) | 2;
13953
13954 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13955 udelay(40);
13956 } else {
13957 test_desc.cqid_sqid = (16 << 8) | 7;
13958
13959 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13960 udelay(40);
13961 }
13962 test_desc.flags = 0x00000005;
13963
13964 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13965 u32 val;
13966
13967 val = *(((u32 *)&test_desc) + i);
13968 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13969 sram_dma_descs + (i * sizeof(u32)));
13970 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13971 }
13972 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13973
13974 if (to_device) {
13975 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13976 } else {
13977 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13978 }
13979
13980 ret = -ENODEV;
13981 for (i = 0; i < 40; i++) {
13982 u32 val;
13983
13984 if (to_device)
13985 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13986 else
13987 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13988 if ((val & 0xffff) == sram_dma_descs) {
13989 ret = 0;
13990 break;
13991 }
13992
13993 udelay(100);
13994 }
13995
13996 return ret;
13997 }
13998
13999 #define TEST_BUFFER_SIZE 0x2000
14000
14001 static int __devinit tg3_test_dma(struct tg3 *tp)
14002 {
14003 dma_addr_t buf_dma;
14004 u32 *buf, saved_dma_rwctrl;
14005 int ret = 0;
14006
14007 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14008 if (!buf) {
14009 ret = -ENOMEM;
14010 goto out_nofree;
14011 }
14012
14013 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14014 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14015
14016 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14017
14018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
14020 goto out;
14021
14022 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14023 /* DMA read watermark not used on PCIE */
14024 tp->dma_rwctrl |= 0x00180000;
14025 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14026 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14028 tp->dma_rwctrl |= 0x003f0000;
14029 else
14030 tp->dma_rwctrl |= 0x003f000f;
14031 } else {
14032 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14033 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14034 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14035 u32 read_water = 0x7;
14036
14037 /* If the 5704 is behind the EPB bridge, we can
14038 * do the less restrictive ONE_DMA workaround for
14039 * better performance.
14040 */
14041 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14043 tp->dma_rwctrl |= 0x8000;
14044 else if (ccval == 0x6 || ccval == 0x7)
14045 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14046
14047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14048 read_water = 4;
14049 /* Set bit 23 to enable PCIX hw bug fix */
14050 tp->dma_rwctrl |=
14051 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14052 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14053 (1 << 23);
14054 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14055 /* 5780 always in PCIX mode */
14056 tp->dma_rwctrl |= 0x00144000;
14057 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14058 /* 5714 always in PCIX mode */
14059 tp->dma_rwctrl |= 0x00148000;
14060 } else {
14061 tp->dma_rwctrl |= 0x001b000f;
14062 }
14063 }
14064
14065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14067 tp->dma_rwctrl &= 0xfffffff0;
14068
14069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14071 /* Remove this if it causes problems for some boards. */
14072 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14073
14074 /* On 5700/5701 chips, we need to set this bit.
14075 * Otherwise the chip will issue cacheline transactions
14076 * to streamable DMA memory with not all the byte
14077 * enables turned on. This is an error on several
14078 * RISC PCI controllers, in particular sparc64.
14079 *
14080 * On 5703/5704 chips, this bit has been reassigned
14081 * a different meaning. In particular, it is used
14082 * on those chips to enable a PCI-X workaround.
14083 */
14084 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14085 }
14086
14087 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14088
14089 #if 0
14090 /* Unneeded, already done by tg3_get_invariants. */
14091 tg3_switch_clocks(tp);
14092 #endif
14093
14094 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14095 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14096 goto out;
14097
14098 /* It is best to perform DMA test with maximum write burst size
14099 * to expose the 5700/5701 write DMA bug.
14100 */
14101 saved_dma_rwctrl = tp->dma_rwctrl;
14102 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14103 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14104
14105 while (1) {
14106 u32 *p = buf, i;
14107
14108 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14109 p[i] = i;
14110
14111 /* Send the buffer to the chip. */
14112 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14113 if (ret) {
14114 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14115 break;
14116 }
14117
14118 #if 0
14119 /* validate data reached card RAM correctly. */
14120 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14121 u32 val;
14122 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14123 if (le32_to_cpu(val) != p[i]) {
14124 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
14125 /* ret = -ENODEV here? */
14126 }
14127 p[i] = 0;
14128 }
14129 #endif
14130 /* Now read it back. */
14131 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14132 if (ret) {
14133 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14134
14135 break;
14136 }
14137
14138 /* Verify it. */
14139 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14140 if (p[i] == i)
14141 continue;
14142
14143 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14144 DMA_RWCTRL_WRITE_BNDRY_16) {
14145 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14146 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14147 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14148 break;
14149 } else {
14150 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14151 ret = -ENODEV;
14152 goto out;
14153 }
14154 }
14155
14156 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14157 /* Success. */
14158 ret = 0;
14159 break;
14160 }
14161 }
14162 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14163 DMA_RWCTRL_WRITE_BNDRY_16) {
14164 static struct pci_device_id dma_wait_state_chipsets[] = {
14165 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14166 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14167 { },
14168 };
14169
14170 /* DMA test passed without adjusting DMA boundary,
14171 * now look for chipsets that are known to expose the
14172 * DMA bug without failing the test.
14173 */
14174 if (pci_dev_present(dma_wait_state_chipsets)) {
14175 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14176 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14177 }
14178 else
14179 /* Safe to use the calculated DMA boundary. */
14180 tp->dma_rwctrl = saved_dma_rwctrl;
14181
14182 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14183 }
14184
14185 out:
14186 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14187 out_nofree:
14188 return ret;
14189 }
14190
14191 static void __devinit tg3_init_link_config(struct tg3 *tp)
14192 {
14193 tp->link_config.advertising =
14194 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14195 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14196 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14197 ADVERTISED_Autoneg | ADVERTISED_MII);
14198 tp->link_config.speed = SPEED_INVALID;
14199 tp->link_config.duplex = DUPLEX_INVALID;
14200 tp->link_config.autoneg = AUTONEG_ENABLE;
14201 tp->link_config.active_speed = SPEED_INVALID;
14202 tp->link_config.active_duplex = DUPLEX_INVALID;
14203 tp->link_config.phy_is_low_power = 0;
14204 tp->link_config.orig_speed = SPEED_INVALID;
14205 tp->link_config.orig_duplex = DUPLEX_INVALID;
14206 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14207 }
14208
14209 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14210 {
14211 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14212 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14213 tp->bufmgr_config.mbuf_read_dma_low_water =
14214 DEFAULT_MB_RDMA_LOW_WATER_5705;
14215 tp->bufmgr_config.mbuf_mac_rx_low_water =
14216 DEFAULT_MB_MACRX_LOW_WATER_57765;
14217 tp->bufmgr_config.mbuf_high_water =
14218 DEFAULT_MB_HIGH_WATER_57765;
14219
14220 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14221 DEFAULT_MB_RDMA_LOW_WATER_5705;
14222 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14223 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14224 tp->bufmgr_config.mbuf_high_water_jumbo =
14225 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14226 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14227 tp->bufmgr_config.mbuf_read_dma_low_water =
14228 DEFAULT_MB_RDMA_LOW_WATER_5705;
14229 tp->bufmgr_config.mbuf_mac_rx_low_water =
14230 DEFAULT_MB_MACRX_LOW_WATER_5705;
14231 tp->bufmgr_config.mbuf_high_water =
14232 DEFAULT_MB_HIGH_WATER_5705;
14233 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14234 tp->bufmgr_config.mbuf_mac_rx_low_water =
14235 DEFAULT_MB_MACRX_LOW_WATER_5906;
14236 tp->bufmgr_config.mbuf_high_water =
14237 DEFAULT_MB_HIGH_WATER_5906;
14238 }
14239
14240 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14241 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14242 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14243 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14244 tp->bufmgr_config.mbuf_high_water_jumbo =
14245 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14246 } else {
14247 tp->bufmgr_config.mbuf_read_dma_low_water =
14248 DEFAULT_MB_RDMA_LOW_WATER;
14249 tp->bufmgr_config.mbuf_mac_rx_low_water =
14250 DEFAULT_MB_MACRX_LOW_WATER;
14251 tp->bufmgr_config.mbuf_high_water =
14252 DEFAULT_MB_HIGH_WATER;
14253
14254 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14255 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14256 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14257 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14258 tp->bufmgr_config.mbuf_high_water_jumbo =
14259 DEFAULT_MB_HIGH_WATER_JUMBO;
14260 }
14261
14262 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14263 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14264 }
14265
14266 static char * __devinit tg3_phy_string(struct tg3 *tp)
14267 {
14268 switch (tp->phy_id & PHY_ID_MASK) {
14269 case PHY_ID_BCM5400: return "5400";
14270 case PHY_ID_BCM5401: return "5401";
14271 case PHY_ID_BCM5411: return "5411";
14272 case PHY_ID_BCM5701: return "5701";
14273 case PHY_ID_BCM5703: return "5703";
14274 case PHY_ID_BCM5704: return "5704";
14275 case PHY_ID_BCM5705: return "5705";
14276 case PHY_ID_BCM5750: return "5750";
14277 case PHY_ID_BCM5752: return "5752";
14278 case PHY_ID_BCM5714: return "5714";
14279 case PHY_ID_BCM5780: return "5780";
14280 case PHY_ID_BCM5755: return "5755";
14281 case PHY_ID_BCM5787: return "5787";
14282 case PHY_ID_BCM5784: return "5784";
14283 case PHY_ID_BCM5756: return "5722/5756";
14284 case PHY_ID_BCM5906: return "5906";
14285 case PHY_ID_BCM5761: return "5761";
14286 case PHY_ID_BCM5718C: return "5718C";
14287 case PHY_ID_BCM5718S: return "5718S";
14288 case PHY_ID_BCM57765: return "57765";
14289 case PHY_ID_BCM8002: return "8002/serdes";
14290 case 0: return "serdes";
14291 default: return "unknown";
14292 }
14293 }
14294
14295 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14296 {
14297 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14298 strcpy(str, "PCI Express");
14299 return str;
14300 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14301 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14302
14303 strcpy(str, "PCIX:");
14304
14305 if ((clock_ctrl == 7) ||
14306 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14307 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14308 strcat(str, "133MHz");
14309 else if (clock_ctrl == 0)
14310 strcat(str, "33MHz");
14311 else if (clock_ctrl == 2)
14312 strcat(str, "50MHz");
14313 else if (clock_ctrl == 4)
14314 strcat(str, "66MHz");
14315 else if (clock_ctrl == 6)
14316 strcat(str, "100MHz");
14317 } else {
14318 strcpy(str, "PCI:");
14319 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14320 strcat(str, "66MHz");
14321 else
14322 strcat(str, "33MHz");
14323 }
14324 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14325 strcat(str, ":32-bit");
14326 else
14327 strcat(str, ":64-bit");
14328 return str;
14329 }
14330
14331 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14332 {
14333 struct pci_dev *peer;
14334 unsigned int func, devnr = tp->pdev->devfn & ~7;
14335
14336 for (func = 0; func < 8; func++) {
14337 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14338 if (peer && peer != tp->pdev)
14339 break;
14340 pci_dev_put(peer);
14341 }
14342 /* 5704 can be configured in single-port mode, set peer to
14343 * tp->pdev in that case.
14344 */
14345 if (!peer) {
14346 peer = tp->pdev;
14347 return peer;
14348 }
14349
14350 /*
14351 * We don't need to keep the refcount elevated; there's no way
14352 * to remove one half of this device without removing the other
14353 */
14354 pci_dev_put(peer);
14355
14356 return peer;
14357 }
14358
14359 static void __devinit tg3_init_coal(struct tg3 *tp)
14360 {
14361 struct ethtool_coalesce *ec = &tp->coal;
14362
14363 memset(ec, 0, sizeof(*ec));
14364 ec->cmd = ETHTOOL_GCOALESCE;
14365 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14366 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14367 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14368 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14369 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14370 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14371 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14372 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14373 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14374
14375 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14376 HOSTCC_MODE_CLRTICK_TXBD)) {
14377 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14378 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14379 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14380 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14381 }
14382
14383 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14384 ec->rx_coalesce_usecs_irq = 0;
14385 ec->tx_coalesce_usecs_irq = 0;
14386 ec->stats_block_coalesce_usecs = 0;
14387 }
14388 }
14389
14390 static const struct net_device_ops tg3_netdev_ops = {
14391 .ndo_open = tg3_open,
14392 .ndo_stop = tg3_close,
14393 .ndo_start_xmit = tg3_start_xmit,
14394 .ndo_get_stats = tg3_get_stats,
14395 .ndo_validate_addr = eth_validate_addr,
14396 .ndo_set_multicast_list = tg3_set_rx_mode,
14397 .ndo_set_mac_address = tg3_set_mac_addr,
14398 .ndo_do_ioctl = tg3_ioctl,
14399 .ndo_tx_timeout = tg3_tx_timeout,
14400 .ndo_change_mtu = tg3_change_mtu,
14401 #if TG3_VLAN_TAG_USED
14402 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14403 #endif
14404 #ifdef CONFIG_NET_POLL_CONTROLLER
14405 .ndo_poll_controller = tg3_poll_controller,
14406 #endif
14407 };
14408
14409 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14410 .ndo_open = tg3_open,
14411 .ndo_stop = tg3_close,
14412 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14413 .ndo_get_stats = tg3_get_stats,
14414 .ndo_validate_addr = eth_validate_addr,
14415 .ndo_set_multicast_list = tg3_set_rx_mode,
14416 .ndo_set_mac_address = tg3_set_mac_addr,
14417 .ndo_do_ioctl = tg3_ioctl,
14418 .ndo_tx_timeout = tg3_tx_timeout,
14419 .ndo_change_mtu = tg3_change_mtu,
14420 #if TG3_VLAN_TAG_USED
14421 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14422 #endif
14423 #ifdef CONFIG_NET_POLL_CONTROLLER
14424 .ndo_poll_controller = tg3_poll_controller,
14425 #endif
14426 };
14427
14428 static int __devinit tg3_init_one(struct pci_dev *pdev,
14429 const struct pci_device_id *ent)
14430 {
14431 static int tg3_version_printed = 0;
14432 struct net_device *dev;
14433 struct tg3 *tp;
14434 int i, err, pm_cap;
14435 u32 sndmbx, rcvmbx, intmbx;
14436 char str[40];
14437 u64 dma_mask, persist_dma_mask;
14438
14439 if (tg3_version_printed++ == 0)
14440 printk(KERN_INFO "%s", version);
14441
14442 err = pci_enable_device(pdev);
14443 if (err) {
14444 printk(KERN_ERR PFX "Cannot enable PCI device, "
14445 "aborting.\n");
14446 return err;
14447 }
14448
14449 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14450 if (err) {
14451 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14452 "aborting.\n");
14453 goto err_out_disable_pdev;
14454 }
14455
14456 pci_set_master(pdev);
14457
14458 /* Find power-management capability. */
14459 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14460 if (pm_cap == 0) {
14461 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14462 "aborting.\n");
14463 err = -EIO;
14464 goto err_out_free_res;
14465 }
14466
14467 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14468 if (!dev) {
14469 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14470 err = -ENOMEM;
14471 goto err_out_free_res;
14472 }
14473
14474 SET_NETDEV_DEV(dev, &pdev->dev);
14475
14476 #if TG3_VLAN_TAG_USED
14477 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14478 #endif
14479
14480 tp = netdev_priv(dev);
14481 tp->pdev = pdev;
14482 tp->dev = dev;
14483 tp->pm_cap = pm_cap;
14484 tp->rx_mode = TG3_DEF_RX_MODE;
14485 tp->tx_mode = TG3_DEF_TX_MODE;
14486
14487 if (tg3_debug > 0)
14488 tp->msg_enable = tg3_debug;
14489 else
14490 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14491
14492 /* The word/byte swap controls here control register access byte
14493 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14494 * setting below.
14495 */
14496 tp->misc_host_ctrl =
14497 MISC_HOST_CTRL_MASK_PCI_INT |
14498 MISC_HOST_CTRL_WORD_SWAP |
14499 MISC_HOST_CTRL_INDIR_ACCESS |
14500 MISC_HOST_CTRL_PCISTATE_RW;
14501
14502 /* The NONFRM (non-frame) byte/word swap controls take effect
14503 * on descriptor entries, anything which isn't packet data.
14504 *
14505 * The StrongARM chips on the board (one for tx, one for rx)
14506 * are running in big-endian mode.
14507 */
14508 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14509 GRC_MODE_WSWAP_NONFRM_DATA);
14510 #ifdef __BIG_ENDIAN
14511 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14512 #endif
14513 spin_lock_init(&tp->lock);
14514 spin_lock_init(&tp->indirect_lock);
14515 INIT_WORK(&tp->reset_task, tg3_reset_task);
14516
14517 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14518 if (!tp->regs) {
14519 printk(KERN_ERR PFX "Cannot map device registers, "
14520 "aborting.\n");
14521 err = -ENOMEM;
14522 goto err_out_free_dev;
14523 }
14524
14525 tg3_init_link_config(tp);
14526
14527 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14528 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14529
14530 dev->ethtool_ops = &tg3_ethtool_ops;
14531 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14532 dev->irq = pdev->irq;
14533
14534 err = tg3_get_invariants(tp);
14535 if (err) {
14536 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14537 "aborting.\n");
14538 goto err_out_iounmap;
14539 }
14540
14541 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14542 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14543 dev->netdev_ops = &tg3_netdev_ops;
14544 else
14545 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14546
14547
14548 /* The EPB bridge inside 5714, 5715, and 5780 and any
14549 * device behind the EPB cannot support DMA addresses > 40-bit.
14550 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14551 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14552 * do DMA address check in tg3_start_xmit().
14553 */
14554 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14555 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14556 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14557 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14558 #ifdef CONFIG_HIGHMEM
14559 dma_mask = DMA_BIT_MASK(64);
14560 #endif
14561 } else
14562 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14563
14564 /* Configure DMA attributes. */
14565 if (dma_mask > DMA_BIT_MASK(32)) {
14566 err = pci_set_dma_mask(pdev, dma_mask);
14567 if (!err) {
14568 dev->features |= NETIF_F_HIGHDMA;
14569 err = pci_set_consistent_dma_mask(pdev,
14570 persist_dma_mask);
14571 if (err < 0) {
14572 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14573 "DMA for consistent allocations\n");
14574 goto err_out_iounmap;
14575 }
14576 }
14577 }
14578 if (err || dma_mask == DMA_BIT_MASK(32)) {
14579 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14580 if (err) {
14581 printk(KERN_ERR PFX "No usable DMA configuration, "
14582 "aborting.\n");
14583 goto err_out_iounmap;
14584 }
14585 }
14586
14587 tg3_init_bufmgr_config(tp);
14588
14589 /* Selectively allow TSO based on operating conditions */
14590 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14591 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14592 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14593 else {
14594 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14595 tp->fw_needed = NULL;
14596 }
14597
14598 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14599 tp->fw_needed = FIRMWARE_TG3;
14600
14601 /* TSO is on by default on chips that support hardware TSO.
14602 * Firmware TSO on older chips gives lower performance, so it
14603 * is off by default, but can be enabled using ethtool.
14604 */
14605 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14606 (dev->features & NETIF_F_IP_CSUM))
14607 dev->features |= NETIF_F_TSO;
14608
14609 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14610 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14611 if (dev->features & NETIF_F_IPV6_CSUM)
14612 dev->features |= NETIF_F_TSO6;
14613 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14614 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14615 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14616 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14617 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14618 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14619 dev->features |= NETIF_F_TSO_ECN;
14620 }
14621
14622 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14623 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14624 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14625 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14626 tp->rx_pending = 63;
14627 }
14628
14629 err = tg3_get_device_address(tp);
14630 if (err) {
14631 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14632 "aborting.\n");
14633 goto err_out_iounmap;
14634 }
14635
14636 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14637 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14638 if (!tp->aperegs) {
14639 printk(KERN_ERR PFX "Cannot map APE registers, "
14640 "aborting.\n");
14641 err = -ENOMEM;
14642 goto err_out_iounmap;
14643 }
14644
14645 tg3_ape_lock_init(tp);
14646
14647 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14648 tg3_read_dash_ver(tp);
14649 }
14650
14651 /*
14652 * Reset chip in case UNDI or EFI driver did not shutdown
14653 * DMA self test will enable WDMAC and we'll see (spurious)
14654 * pending DMA on the PCI bus at that point.
14655 */
14656 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14657 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14658 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14659 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14660 }
14661
14662 err = tg3_test_dma(tp);
14663 if (err) {
14664 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14665 goto err_out_apeunmap;
14666 }
14667
14668 /* flow control autonegotiation is default behavior */
14669 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14670 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14671
14672 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14673 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14674 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14675 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14676 struct tg3_napi *tnapi = &tp->napi[i];
14677
14678 tnapi->tp = tp;
14679 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14680
14681 tnapi->int_mbox = intmbx;
14682 if (i < 4)
14683 intmbx += 0x8;
14684 else
14685 intmbx += 0x4;
14686
14687 tnapi->consmbox = rcvmbx;
14688 tnapi->prodmbox = sndmbx;
14689
14690 if (i) {
14691 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14692 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14693 } else {
14694 tnapi->coal_now = HOSTCC_MODE_NOW;
14695 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14696 }
14697
14698 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14699 break;
14700
14701 /*
14702 * If we support MSIX, we'll be using RSS. If we're using
14703 * RSS, the first vector only handles link interrupts and the
14704 * remaining vectors handle rx and tx interrupts. Reuse the
14705 * mailbox values for the next iteration. The values we setup
14706 * above are still useful for the single vectored mode.
14707 */
14708 if (!i)
14709 continue;
14710
14711 rcvmbx += 0x8;
14712
14713 if (sndmbx & 0x4)
14714 sndmbx -= 0x4;
14715 else
14716 sndmbx += 0xc;
14717 }
14718
14719 tg3_init_coal(tp);
14720
14721 pci_set_drvdata(pdev, dev);
14722
14723 err = register_netdev(dev);
14724 if (err) {
14725 printk(KERN_ERR PFX "Cannot register net device, "
14726 "aborting.\n");
14727 goto err_out_apeunmap;
14728 }
14729
14730 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14731 dev->name,
14732 tp->board_part_number,
14733 tp->pci_chip_rev_id,
14734 tg3_bus_string(tp, str),
14735 dev->dev_addr);
14736
14737 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14738 struct phy_device *phydev;
14739 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14740 printk(KERN_INFO
14741 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14742 tp->dev->name, phydev->drv->name,
14743 dev_name(&phydev->dev));
14744 } else
14745 printk(KERN_INFO
14746 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14747 tp->dev->name, tg3_phy_string(tp),
14748 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14749 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14750 "10/100/1000Base-T")),
14751 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14752
14753 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14754 dev->name,
14755 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14756 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14757 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14758 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14759 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14760 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14761 dev->name, tp->dma_rwctrl,
14762 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14763 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14764
14765 return 0;
14766
14767 err_out_apeunmap:
14768 if (tp->aperegs) {
14769 iounmap(tp->aperegs);
14770 tp->aperegs = NULL;
14771 }
14772
14773 err_out_iounmap:
14774 if (tp->regs) {
14775 iounmap(tp->regs);
14776 tp->regs = NULL;
14777 }
14778
14779 err_out_free_dev:
14780 free_netdev(dev);
14781
14782 err_out_free_res:
14783 pci_release_regions(pdev);
14784
14785 err_out_disable_pdev:
14786 pci_disable_device(pdev);
14787 pci_set_drvdata(pdev, NULL);
14788 return err;
14789 }
14790
14791 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14792 {
14793 struct net_device *dev = pci_get_drvdata(pdev);
14794
14795 if (dev) {
14796 struct tg3 *tp = netdev_priv(dev);
14797
14798 if (tp->fw)
14799 release_firmware(tp->fw);
14800
14801 flush_scheduled_work();
14802
14803 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14804 tg3_phy_fini(tp);
14805 tg3_mdio_fini(tp);
14806 }
14807
14808 unregister_netdev(dev);
14809 if (tp->aperegs) {
14810 iounmap(tp->aperegs);
14811 tp->aperegs = NULL;
14812 }
14813 if (tp->regs) {
14814 iounmap(tp->regs);
14815 tp->regs = NULL;
14816 }
14817 free_netdev(dev);
14818 pci_release_regions(pdev);
14819 pci_disable_device(pdev);
14820 pci_set_drvdata(pdev, NULL);
14821 }
14822 }
14823
14824 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14825 {
14826 struct net_device *dev = pci_get_drvdata(pdev);
14827 struct tg3 *tp = netdev_priv(dev);
14828 pci_power_t target_state;
14829 int err;
14830
14831 /* PCI register 4 needs to be saved whether netif_running() or not.
14832 * MSI address and data need to be saved if using MSI and
14833 * netif_running().
14834 */
14835 pci_save_state(pdev);
14836
14837 if (!netif_running(dev))
14838 return 0;
14839
14840 flush_scheduled_work();
14841 tg3_phy_stop(tp);
14842 tg3_netif_stop(tp);
14843
14844 del_timer_sync(&tp->timer);
14845
14846 tg3_full_lock(tp, 1);
14847 tg3_disable_ints(tp);
14848 tg3_full_unlock(tp);
14849
14850 netif_device_detach(dev);
14851
14852 tg3_full_lock(tp, 0);
14853 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14854 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14855 tg3_full_unlock(tp);
14856
14857 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14858
14859 err = tg3_set_power_state(tp, target_state);
14860 if (err) {
14861 int err2;
14862
14863 tg3_full_lock(tp, 0);
14864
14865 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14866 err2 = tg3_restart_hw(tp, 1);
14867 if (err2)
14868 goto out;
14869
14870 tp->timer.expires = jiffies + tp->timer_offset;
14871 add_timer(&tp->timer);
14872
14873 netif_device_attach(dev);
14874 tg3_netif_start(tp);
14875
14876 out:
14877 tg3_full_unlock(tp);
14878
14879 if (!err2)
14880 tg3_phy_start(tp);
14881 }
14882
14883 return err;
14884 }
14885
14886 static int tg3_resume(struct pci_dev *pdev)
14887 {
14888 struct net_device *dev = pci_get_drvdata(pdev);
14889 struct tg3 *tp = netdev_priv(dev);
14890 int err;
14891
14892 pci_restore_state(tp->pdev);
14893
14894 if (!netif_running(dev))
14895 return 0;
14896
14897 err = tg3_set_power_state(tp, PCI_D0);
14898 if (err)
14899 return err;
14900
14901 netif_device_attach(dev);
14902
14903 tg3_full_lock(tp, 0);
14904
14905 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14906 err = tg3_restart_hw(tp, 1);
14907 if (err)
14908 goto out;
14909
14910 tp->timer.expires = jiffies + tp->timer_offset;
14911 add_timer(&tp->timer);
14912
14913 tg3_netif_start(tp);
14914
14915 out:
14916 tg3_full_unlock(tp);
14917
14918 if (!err)
14919 tg3_phy_start(tp);
14920
14921 return err;
14922 }
14923
14924 static struct pci_driver tg3_driver = {
14925 .name = DRV_MODULE_NAME,
14926 .id_table = tg3_pci_tbl,
14927 .probe = tg3_init_one,
14928 .remove = __devexit_p(tg3_remove_one),
14929 .suspend = tg3_suspend,
14930 .resume = tg3_resume
14931 };
14932
14933 static int __init tg3_init(void)
14934 {
14935 return pci_register_driver(&tg3_driver);
14936 }
14937
14938 static void __exit tg3_cleanup(void)
14939 {
14940 pci_unregister_driver(&tg3_driver);
14941 }
14942
14943 module_init(tg3_init);
14944 module_exit(tg3_cleanup);
kernel-based virtual machine