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iwlwifi: move _agn statistics related structure
[linux-2.6/kvm.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
blobf62a345d71dc4cbc4fc53910494f12542b49fc7b
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/delay.h>
36 #include <linux/sched.h>
37 #include <linux/skbuff.h>
38 #include <linux/netdevice.h>
39 #include <linux/wireless.h>
40 #include <linux/firmware.h>
41 #include <linux/etherdevice.h>
42 #include <linux/if_arp.h>
43
44 #include <net/mac80211.h>
45
46 #include <asm/div64.h>
47
48 #define DRV_NAME "iwlagn"
49
50 #include "iwl-eeprom.h"
51 #include "iwl-dev.h"
52 #include "iwl-core.h"
53 #include "iwl-io.h"
54 #include "iwl-helpers.h"
55 #include "iwl-sta.h"
56 #include "iwl-calib.h"
57 #include "iwl-agn.h"
58
59
60 /******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
66 /*
67 * module name, copyright, version, etc.
68 */
69 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
70
71 #ifdef CONFIG_IWLWIFI_DEBUG
72 #define VD "d"
73 #else
74 #define VD
75 #endif
76
77 #define DRV_VERSION IWLWIFI_VERSION VD
78
79
80 MODULE_DESCRIPTION(DRV_DESCRIPTION);
81 MODULE_VERSION(DRV_VERSION);
82 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
83 MODULE_LICENSE("GPL");
84 MODULE_ALIAS("iwl4965");
85
86 /**
87 * iwl_commit_rxon - commit staging_rxon to hardware
88 *
89 * The RXON command in staging_rxon is committed to the hardware and
90 * the active_rxon structure is updated with the new data. This
91 * function correctly transitions out of the RXON_ASSOC_MSK state if
92 * a HW tune is required based on the RXON structure changes.
93 */
94 int iwl_commit_rxon(struct iwl_priv *priv)
95 {
96 /* cast away the const for active_rxon in this function */
97 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
98 int ret;
99 bool new_assoc =
100 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
101
102 if (!iwl_is_alive(priv))
103 return -EBUSY;
104
105 /* always get timestamp with Rx frame */
106 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
107
108 ret = iwl_check_rxon_cmd(priv);
109 if (ret) {
110 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
111 return -EINVAL;
112 }
113
114 /*
115 * receive commit_rxon request
116 * abort any previous channel switch if still in process
117 */
118 if (priv->switch_rxon.switch_in_progress &&
119 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
120 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
121 le16_to_cpu(priv->switch_rxon.channel));
122 priv->switch_rxon.switch_in_progress = false;
123 }
124
125 /* If we don't need to send a full RXON, we can use
126 * iwl_rxon_assoc_cmd which is used to reconfigure filter
127 * and other flags for the current radio configuration. */
128 if (!iwl_full_rxon_required(priv)) {
129 ret = iwl_send_rxon_assoc(priv);
130 if (ret) {
131 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
132 return ret;
133 }
134
135 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
136 iwl_print_rx_config_cmd(priv);
137 return 0;
138 }
139
140 /* If we are currently associated and the new config requires
141 * an RXON_ASSOC and the new config wants the associated mask enabled,
142 * we must clear the associated from the active configuration
143 * before we apply the new config */
144 if (iwl_is_associated(priv) && new_assoc) {
145 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
146 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
147
148 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
149 sizeof(struct iwl_rxon_cmd),
150 &priv->active_rxon);
151
152 /* If the mask clearing failed then we set
153 * active_rxon back to what it was previously */
154 if (ret) {
155 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
156 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
157 return ret;
158 }
159 iwl_clear_ucode_stations(priv);
160 iwl_restore_stations(priv);
161 ret = iwl_restore_default_wep_keys(priv);
162 if (ret) {
163 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
164 return ret;
165 }
166 }
167
168 IWL_DEBUG_INFO(priv, "Sending RXON\n"
169 "* with%s RXON_FILTER_ASSOC_MSK\n"
170 "* channel = %d\n"
171 "* bssid = %pM\n",
172 (new_assoc ? "" : "out"),
173 le16_to_cpu(priv->staging_rxon.channel),
174 priv->staging_rxon.bssid_addr);
175
176 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
177
178 /* Apply the new configuration
179 * RXON unassoc clears the station table in uCode so restoration of
180 * stations is needed after it (the RXON command) completes
181 */
182 if (!new_assoc) {
183 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
184 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
185 if (ret) {
186 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
187 return ret;
188 }
189 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
190 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
191 iwl_clear_ucode_stations(priv);
192 iwl_restore_stations(priv);
193 ret = iwl_restore_default_wep_keys(priv);
194 if (ret) {
195 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
196 return ret;
197 }
198 }
199
200 priv->start_calib = 0;
201 if (new_assoc) {
202 /*
203 * allow CTS-to-self if possible for new association.
204 * this is relevant only for 5000 series and up,
205 * but will not damage 4965
206 */
207 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
208
209 /* Apply the new configuration
210 * RXON assoc doesn't clear the station table in uCode,
211 */
212 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
213 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
214 if (ret) {
215 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
216 return ret;
217 }
218 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
219 }
220 iwl_print_rx_config_cmd(priv);
221
222 iwl_init_sensitivity(priv);
223
224 /* If we issue a new RXON command which required a tune then we must
225 * send a new TXPOWER command or we won't be able to Tx any frames */
226 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
227 if (ret) {
228 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
229 return ret;
230 }
231
232 return 0;
233 }
234
235 void iwl_update_chain_flags(struct iwl_priv *priv)
236 {
237
238 if (priv->cfg->ops->hcmd->set_rxon_chain)
239 priv->cfg->ops->hcmd->set_rxon_chain(priv);
240 iwlcore_commit_rxon(priv);
241 }
242
243 static void iwl_clear_free_frames(struct iwl_priv *priv)
244 {
245 struct list_head *element;
246
247 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
248 priv->frames_count);
249
250 while (!list_empty(&priv->free_frames)) {
251 element = priv->free_frames.next;
252 list_del(element);
253 kfree(list_entry(element, struct iwl_frame, list));
254 priv->frames_count--;
255 }
256
257 if (priv->frames_count) {
258 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
259 priv->frames_count);
260 priv->frames_count = 0;
261 }
262 }
263
264 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
265 {
266 struct iwl_frame *frame;
267 struct list_head *element;
268 if (list_empty(&priv->free_frames)) {
269 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
270 if (!frame) {
271 IWL_ERR(priv, "Could not allocate frame!\n");
272 return NULL;
273 }
274
275 priv->frames_count++;
276 return frame;
277 }
278
279 element = priv->free_frames.next;
280 list_del(element);
281 return list_entry(element, struct iwl_frame, list);
282 }
283
284 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
285 {
286 memset(frame, 0, sizeof(*frame));
287 list_add(&frame->list, &priv->free_frames);
288 }
289
290 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
291 struct ieee80211_hdr *hdr,
292 int left)
293 {
294 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
295 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
296 (priv->iw_mode != NL80211_IFTYPE_AP)))
297 return 0;
298
299 if (priv->ibss_beacon->len > left)
300 return 0;
301
302 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
303
304 return priv->ibss_beacon->len;
305 }
306
307 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
308 static void iwl_set_beacon_tim(struct iwl_priv *priv,
309 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
310 u8 *beacon, u32 frame_size)
311 {
312 u16 tim_idx;
313 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
314
315 /*
316 * The index is relative to frame start but we start looking at the
317 * variable-length part of the beacon.
318 */
319 tim_idx = mgmt->u.beacon.variable - beacon;
320
321 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
322 while ((tim_idx < (frame_size - 2)) &&
323 (beacon[tim_idx] != WLAN_EID_TIM))
324 tim_idx += beacon[tim_idx+1] + 2;
325
326 /* If TIM field was found, set variables */
327 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
328 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
329 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
330 } else
331 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
332 }
333
334 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
335 struct iwl_frame *frame)
336 {
337 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
338 u32 frame_size;
339 u32 rate_flags;
340 u32 rate;
341 /*
342 * We have to set up the TX command, the TX Beacon command, and the
343 * beacon contents.
344 */
345
346 /* Initialize memory */
347 tx_beacon_cmd = &frame->u.beacon;
348 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
349
350 /* Set up TX beacon contents */
351 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
352 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
353 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
354 return 0;
355
356 /* Set up TX command fields */
357 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
358 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
359 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
360 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
361 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
362
363 /* Set up TX beacon command fields */
364 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
365 frame_size);
366
367 /* Set up packet rate and flags */
368 rate = iwl_rate_get_lowest_plcp(priv);
369 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
370 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
371 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
372 rate_flags |= RATE_MCS_CCK_MSK;
373 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
374 rate_flags);
375
376 return sizeof(*tx_beacon_cmd) + frame_size;
377 }
378 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
379 {
380 struct iwl_frame *frame;
381 unsigned int frame_size;
382 int rc;
383
384 frame = iwl_get_free_frame(priv);
385 if (!frame) {
386 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
387 "command.\n");
388 return -ENOMEM;
389 }
390
391 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
392 if (!frame_size) {
393 IWL_ERR(priv, "Error configuring the beacon command\n");
394 iwl_free_frame(priv, frame);
395 return -EINVAL;
396 }
397
398 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
399 &frame->u.cmd[0]);
400
401 iwl_free_frame(priv, frame);
402
403 return rc;
404 }
405
406 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
407 {
408 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
409
410 dma_addr_t addr = get_unaligned_le32(&tb->lo);
411 if (sizeof(dma_addr_t) > sizeof(u32))
412 addr |=
413 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
414
415 return addr;
416 }
417
418 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
419 {
420 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
421
422 return le16_to_cpu(tb->hi_n_len) >> 4;
423 }
424
425 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
426 dma_addr_t addr, u16 len)
427 {
428 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
429 u16 hi_n_len = len << 4;
430
431 put_unaligned_le32(addr, &tb->lo);
432 if (sizeof(dma_addr_t) > sizeof(u32))
433 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
434
435 tb->hi_n_len = cpu_to_le16(hi_n_len);
436
437 tfd->num_tbs = idx + 1;
438 }
439
440 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
441 {
442 return tfd->num_tbs & 0x1f;
443 }
444
445 /**
446 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
447 * @priv - driver private data
448 * @txq - tx queue
449 *
450 * Does NOT advance any TFD circular buffer read/write indexes
451 * Does NOT free the TFD itself (which is within circular buffer)
452 */
453 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
454 {
455 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
456 struct iwl_tfd *tfd;
457 struct pci_dev *dev = priv->pci_dev;
458 int index = txq->q.read_ptr;
459 int i;
460 int num_tbs;
461
462 tfd = &tfd_tmp[index];
463
464 /* Sanity check on number of chunks */
465 num_tbs = iwl_tfd_get_num_tbs(tfd);
466
467 if (num_tbs >= IWL_NUM_OF_TBS) {
468 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
469 /* @todo issue fatal error, it is quite serious situation */
470 return;
471 }
472
473 /* Unmap tx_cmd */
474 if (num_tbs)
475 pci_unmap_single(dev,
476 pci_unmap_addr(&txq->meta[index], mapping),
477 pci_unmap_len(&txq->meta[index], len),
478 PCI_DMA_BIDIRECTIONAL);
479
480 /* Unmap chunks, if any. */
481 for (i = 1; i < num_tbs; i++) {
482 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
483 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
484
485 if (txq->txb) {
486 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
487 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
488 }
489 }
490 }
491
492 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
493 struct iwl_tx_queue *txq,
494 dma_addr_t addr, u16 len,
495 u8 reset, u8 pad)
496 {
497 struct iwl_queue *q;
498 struct iwl_tfd *tfd, *tfd_tmp;
499 u32 num_tbs;
500
501 q = &txq->q;
502 tfd_tmp = (struct iwl_tfd *)txq->tfds;
503 tfd = &tfd_tmp[q->write_ptr];
504
505 if (reset)
506 memset(tfd, 0, sizeof(*tfd));
507
508 num_tbs = iwl_tfd_get_num_tbs(tfd);
509
510 /* Each TFD can point to a maximum 20 Tx buffers */
511 if (num_tbs >= IWL_NUM_OF_TBS) {
512 IWL_ERR(priv, "Error can not send more than %d chunks\n",
513 IWL_NUM_OF_TBS);
514 return -EINVAL;
515 }
516
517 BUG_ON(addr & ~DMA_BIT_MASK(36));
518 if (unlikely(addr & ~IWL_TX_DMA_MASK))
519 IWL_ERR(priv, "Unaligned address = %llx\n",
520 (unsigned long long)addr);
521
522 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
523
524 return 0;
525 }
526
527 /*
528 * Tell nic where to find circular buffer of Tx Frame Descriptors for
529 * given Tx queue, and enable the DMA channel used for that queue.
530 *
531 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
532 * channels supported in hardware.
533 */
534 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
535 struct iwl_tx_queue *txq)
536 {
537 int txq_id = txq->q.id;
538
539 /* Circular buffer (TFD queue in DRAM) physical base address */
540 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
541 txq->q.dma_addr >> 8);
542
543 return 0;
544 }
545
546 /******************************************************************************
547 *
548 * Generic RX handler implementations
549 *
550 ******************************************************************************/
551 static void iwl_rx_reply_alive(struct iwl_priv *priv,
552 struct iwl_rx_mem_buffer *rxb)
553 {
554 struct iwl_rx_packet *pkt = rxb_addr(rxb);
555 struct iwl_alive_resp *palive;
556 struct delayed_work *pwork;
557
558 palive = &pkt->u.alive_frame;
559
560 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
561 "0x%01X 0x%01X\n",
562 palive->is_valid, palive->ver_type,
563 palive->ver_subtype);
564
565 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
566 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
567 memcpy(&priv->card_alive_init,
568 &pkt->u.alive_frame,
569 sizeof(struct iwl_init_alive_resp));
570 pwork = &priv->init_alive_start;
571 } else {
572 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
573 memcpy(&priv->card_alive, &pkt->u.alive_frame,
574 sizeof(struct iwl_alive_resp));
575 pwork = &priv->alive_start;
576 }
577
578 /* We delay the ALIVE response by 5ms to
579 * give the HW RF Kill time to activate... */
580 if (palive->is_valid == UCODE_VALID_OK)
581 queue_delayed_work(priv->workqueue, pwork,
582 msecs_to_jiffies(5));
583 else
584 IWL_WARN(priv, "uCode did not respond OK.\n");
585 }
586
587 static void iwl_bg_beacon_update(struct work_struct *work)
588 {
589 struct iwl_priv *priv =
590 container_of(work, struct iwl_priv, beacon_update);
591 struct sk_buff *beacon;
592
593 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
594 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
595
596 if (!beacon) {
597 IWL_ERR(priv, "update beacon failed\n");
598 return;
599 }
600
601 mutex_lock(&priv->mutex);
602 /* new beacon skb is allocated every time; dispose previous.*/
603 if (priv->ibss_beacon)
604 dev_kfree_skb(priv->ibss_beacon);
605
606 priv->ibss_beacon = beacon;
607 mutex_unlock(&priv->mutex);
608
609 iwl_send_beacon_cmd(priv);
610 }
611
612 /**
613 * iwl_bg_statistics_periodic - Timer callback to queue statistics
614 *
615 * This callback is provided in order to send a statistics request.
616 *
617 * This timer function is continually reset to execute within
618 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
619 * was received. We need to ensure we receive the statistics in order
620 * to update the temperature used for calibrating the TXPOWER.
621 */
622 static void iwl_bg_statistics_periodic(unsigned long data)
623 {
624 struct iwl_priv *priv = (struct iwl_priv *)data;
625
626 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
627 return;
628
629 /* dont send host command if rf-kill is on */
630 if (!iwl_is_ready_rf(priv))
631 return;
632
633 iwl_send_statistics_request(priv, CMD_ASYNC, false);
634 }
635
636
637 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
638 u32 start_idx, u32 num_events,
639 u32 mode)
640 {
641 u32 i;
642 u32 ptr; /* SRAM byte address of log data */
643 u32 ev, time, data; /* event log data */
644 unsigned long reg_flags;
645
646 if (mode == 0)
647 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
648 else
649 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
650
651 /* Make sure device is powered up for SRAM reads */
652 spin_lock_irqsave(&priv->reg_lock, reg_flags);
653 if (iwl_grab_nic_access(priv)) {
654 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
655 return;
656 }
657
658 /* Set starting address; reads will auto-increment */
659 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
660 rmb();
661
662 /*
663 * "time" is actually "data" for mode 0 (no timestamp).
664 * place event id # at far right for easier visual parsing.
665 */
666 for (i = 0; i < num_events; i++) {
667 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
668 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
669 if (mode == 0) {
670 trace_iwlwifi_dev_ucode_cont_event(priv,
671 0, time, ev);
672 } else {
673 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
674 trace_iwlwifi_dev_ucode_cont_event(priv,
675 time, data, ev);
676 }
677 }
678 /* Allow device to power down */
679 iwl_release_nic_access(priv);
680 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
681 }
682
683 static void iwl_continuous_event_trace(struct iwl_priv *priv)
684 {
685 u32 capacity; /* event log capacity in # entries */
686 u32 base; /* SRAM byte address of event log header */
687 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
688 u32 num_wraps; /* # times uCode wrapped to top of log */
689 u32 next_entry; /* index of next entry to be written by uCode */
690
691 if (priv->ucode_type == UCODE_INIT)
692 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
693 else
694 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
695 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
696 capacity = iwl_read_targ_mem(priv, base);
697 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
698 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
699 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
700 } else
701 return;
702
703 if (num_wraps == priv->event_log.num_wraps) {
704 iwl_print_cont_event_trace(priv,
705 base, priv->event_log.next_entry,
706 next_entry - priv->event_log.next_entry,
707 mode);
708 priv->event_log.non_wraps_count++;
709 } else {
710 if ((num_wraps - priv->event_log.num_wraps) > 1)
711 priv->event_log.wraps_more_count++;
712 else
713 priv->event_log.wraps_once_count++;
714 trace_iwlwifi_dev_ucode_wrap_event(priv,
715 num_wraps - priv->event_log.num_wraps,
716 next_entry, priv->event_log.next_entry);
717 if (next_entry < priv->event_log.next_entry) {
718 iwl_print_cont_event_trace(priv, base,
719 priv->event_log.next_entry,
720 capacity - priv->event_log.next_entry,
721 mode);
722
723 iwl_print_cont_event_trace(priv, base, 0,
724 next_entry, mode);
725 } else {
726 iwl_print_cont_event_trace(priv, base,
727 next_entry, capacity - next_entry,
728 mode);
729
730 iwl_print_cont_event_trace(priv, base, 0,
731 next_entry, mode);
732 }
733 }
734 priv->event_log.num_wraps = num_wraps;
735 priv->event_log.next_entry = next_entry;
736 }
737
738 /**
739 * iwl_bg_ucode_trace - Timer callback to log ucode event
740 *
741 * The timer is continually set to execute every
742 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
743 * this function is to perform continuous uCode event logging operation
744 * if enabled
745 */
746 static void iwl_bg_ucode_trace(unsigned long data)
747 {
748 struct iwl_priv *priv = (struct iwl_priv *)data;
749
750 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
751 return;
752
753 if (priv->event_log.ucode_trace) {
754 iwl_continuous_event_trace(priv);
755 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
756 mod_timer(&priv->ucode_trace,
757 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
758 }
759 }
760
761 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
762 struct iwl_rx_mem_buffer *rxb)
763 {
764 #ifdef CONFIG_IWLWIFI_DEBUG
765 struct iwl_rx_packet *pkt = rxb_addr(rxb);
766 struct iwl4965_beacon_notif *beacon =
767 (struct iwl4965_beacon_notif *)pkt->u.raw;
768 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
769
770 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
771 "tsf %d %d rate %d\n",
772 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
773 beacon->beacon_notify_hdr.failure_frame,
774 le32_to_cpu(beacon->ibss_mgr_status),
775 le32_to_cpu(beacon->high_tsf),
776 le32_to_cpu(beacon->low_tsf), rate);
777 #endif
778
779 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
780 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
781 queue_work(priv->workqueue, &priv->beacon_update);
782 }
783
784 /* Handle notification from uCode that card's power state is changing
785 * due to software, hardware, or critical temperature RFKILL */
786 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
787 struct iwl_rx_mem_buffer *rxb)
788 {
789 struct iwl_rx_packet *pkt = rxb_addr(rxb);
790 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
791 unsigned long status = priv->status;
792
793 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
794 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
795 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
796 (flags & CT_CARD_DISABLED) ?
797 "Reached" : "Not reached");
798
799 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
800 CT_CARD_DISABLED)) {
801
802 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
803 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
804
805 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
806 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
807
808 if (!(flags & RXON_CARD_DISABLED)) {
809 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
810 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
811 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
812 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
813 }
814 if (flags & CT_CARD_DISABLED)
815 iwl_tt_enter_ct_kill(priv);
816 }
817 if (!(flags & CT_CARD_DISABLED))
818 iwl_tt_exit_ct_kill(priv);
819
820 if (flags & HW_CARD_DISABLED)
821 set_bit(STATUS_RF_KILL_HW, &priv->status);
822 else
823 clear_bit(STATUS_RF_KILL_HW, &priv->status);
824
825
826 if (!(flags & RXON_CARD_DISABLED))
827 iwl_scan_cancel(priv);
828
829 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
830 test_bit(STATUS_RF_KILL_HW, &priv->status)))
831 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
832 test_bit(STATUS_RF_KILL_HW, &priv->status));
833 else
834 wake_up_interruptible(&priv->wait_command_queue);
835 }
836
837 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
838 {
839 if (src == IWL_PWR_SRC_VAUX) {
840 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
841 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
842 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
843 ~APMG_PS_CTRL_MSK_PWR_SRC);
844 } else {
845 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
846 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
847 ~APMG_PS_CTRL_MSK_PWR_SRC);
848 }
849
850 return 0;
851 }
852
853 /**
854 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
855 *
856 * Setup the RX handlers for each of the reply types sent from the uCode
857 * to the host.
858 *
859 * This function chains into the hardware specific files for them to setup
860 * any hardware specific handlers as well.
861 */
862 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
863 {
864 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
865 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
866 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
867 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
868 iwl_rx_spectrum_measure_notif;
869 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
870 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
871 iwl_rx_pm_debug_statistics_notif;
872 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
873
874 /*
875 * The same handler is used for both the REPLY to a discrete
876 * statistics request from the host as well as for the periodic
877 * statistics notifications (after received beacons) from the uCode.
878 */
879 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
880 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
881
882 iwl_setup_rx_scan_handlers(priv);
883
884 /* status change handler */
885 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
886
887 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
888 iwl_rx_missed_beacon_notif;
889 /* Rx handlers */
890 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
891 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
892 /* block ack */
893 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
894 /* Set up hardware specific Rx handlers */
895 priv->cfg->ops->lib->rx_handler_setup(priv);
896 }
897
898 /**
899 * iwl_rx_handle - Main entry function for receiving responses from uCode
900 *
901 * Uses the priv->rx_handlers callback function array to invoke
902 * the appropriate handlers, including command responses,
903 * frame-received notifications, and other notifications.
904 */
905 void iwl_rx_handle(struct iwl_priv *priv)
906 {
907 struct iwl_rx_mem_buffer *rxb;
908 struct iwl_rx_packet *pkt;
909 struct iwl_rx_queue *rxq = &priv->rxq;
910 u32 r, i;
911 int reclaim;
912 unsigned long flags;
913 u8 fill_rx = 0;
914 u32 count = 8;
915 int total_empty;
916
917 /* uCode's read index (stored in shared DRAM) indicates the last Rx
918 * buffer that the driver may process (last buffer filled by ucode). */
919 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
920 i = rxq->read;
921
922 /* Rx interrupt, but nothing sent from uCode */
923 if (i == r)
924 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
925
926 /* calculate total frames need to be restock after handling RX */
927 total_empty = r - rxq->write_actual;
928 if (total_empty < 0)
929 total_empty += RX_QUEUE_SIZE;
930
931 if (total_empty > (RX_QUEUE_SIZE / 2))
932 fill_rx = 1;
933
934 while (i != r) {
935 rxb = rxq->queue[i];
936
937 /* If an RXB doesn't have a Rx queue slot associated with it,
938 * then a bug has been introduced in the queue refilling
939 * routines -- catch it here */
940 BUG_ON(rxb == NULL);
941
942 rxq->queue[i] = NULL;
943
944 pci_unmap_page(priv->pci_dev, rxb->page_dma,
945 PAGE_SIZE << priv->hw_params.rx_page_order,
946 PCI_DMA_FROMDEVICE);
947 pkt = rxb_addr(rxb);
948
949 trace_iwlwifi_dev_rx(priv, pkt,
950 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
951
952 /* Reclaim a command buffer only if this packet is a response
953 * to a (driver-originated) command.
954 * If the packet (e.g. Rx frame) originated from uCode,
955 * there is no command buffer to reclaim.
956 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
957 * but apparently a few don't get set; catch them here. */
958 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
959 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
960 (pkt->hdr.cmd != REPLY_RX) &&
961 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
962 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
963 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
964 (pkt->hdr.cmd != REPLY_TX);
965
966 /* Based on type of command response or notification,
967 * handle those that need handling via function in
968 * rx_handlers table. See iwl_setup_rx_handlers() */
969 if (priv->rx_handlers[pkt->hdr.cmd]) {
970 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
971 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
972 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
973 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
974 } else {
975 /* No handling needed */
976 IWL_DEBUG_RX(priv,
977 "r %d i %d No handler needed for %s, 0x%02x\n",
978 r, i, get_cmd_string(pkt->hdr.cmd),
979 pkt->hdr.cmd);
980 }
981
982 /*
983 * XXX: After here, we should always check rxb->page
984 * against NULL before touching it or its virtual
985 * memory (pkt). Because some rx_handler might have
986 * already taken or freed the pages.
987 */
988
989 if (reclaim) {
990 /* Invoke any callbacks, transfer the buffer to caller,
991 * and fire off the (possibly) blocking iwl_send_cmd()
992 * as we reclaim the driver command queue */
993 if (rxb->page)
994 iwl_tx_cmd_complete(priv, rxb);
995 else
996 IWL_WARN(priv, "Claim null rxb?\n");
997 }
998
999 /* Reuse the page if possible. For notification packets and
1000 * SKBs that fail to Rx correctly, add them back into the
1001 * rx_free list for reuse later. */
1002 spin_lock_irqsave(&rxq->lock, flags);
1003 if (rxb->page != NULL) {
1004 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1005 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1006 PCI_DMA_FROMDEVICE);
1007 list_add_tail(&rxb->list, &rxq->rx_free);
1008 rxq->free_count++;
1009 } else
1010 list_add_tail(&rxb->list, &rxq->rx_used);
1011
1012 spin_unlock_irqrestore(&rxq->lock, flags);
1013
1014 i = (i + 1) & RX_QUEUE_MASK;
1015 /* If there are a lot of unused frames,
1016 * restock the Rx queue so ucode wont assert. */
1017 if (fill_rx) {
1018 count++;
1019 if (count >= 8) {
1020 rxq->read = i;
1021 iwlagn_rx_replenish_now(priv);
1022 count = 0;
1023 }
1024 }
1025 }
1026
1027 /* Backtrack one entry */
1028 rxq->read = i;
1029 if (fill_rx)
1030 iwlagn_rx_replenish_now(priv);
1031 else
1032 iwlagn_rx_queue_restock(priv);
1033 }
1034
1035 /* call this function to flush any scheduled tasklet */
1036 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1037 {
1038 /* wait to make sure we flush pending tasklet*/
1039 synchronize_irq(priv->pci_dev->irq);
1040 tasklet_kill(&priv->irq_tasklet);
1041 }
1042
1043 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1044 {
1045 u32 inta, handled = 0;
1046 u32 inta_fh;
1047 unsigned long flags;
1048 u32 i;
1049 #ifdef CONFIG_IWLWIFI_DEBUG
1050 u32 inta_mask;
1051 #endif
1052
1053 spin_lock_irqsave(&priv->lock, flags);
1054
1055 /* Ack/clear/reset pending uCode interrupts.
1056 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1057 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
1058 inta = iwl_read32(priv, CSR_INT);
1059 iwl_write32(priv, CSR_INT, inta);
1060
1061 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1062 * Any new interrupts that happen after this, either while we're
1063 * in this tasklet, or later, will show up in next ISR/tasklet. */
1064 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1065 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1066
1067 #ifdef CONFIG_IWLWIFI_DEBUG
1068 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1069 /* just for debug */
1070 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1071 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1072 inta, inta_mask, inta_fh);
1073 }
1074 #endif
1075
1076 spin_unlock_irqrestore(&priv->lock, flags);
1077
1078 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1079 * atomic, make sure that inta covers all the interrupts that
1080 * we've discovered, even if FH interrupt came in just after
1081 * reading CSR_INT. */
1082 if (inta_fh & CSR49_FH_INT_RX_MASK)
1083 inta |= CSR_INT_BIT_FH_RX;
1084 if (inta_fh & CSR49_FH_INT_TX_MASK)
1085 inta |= CSR_INT_BIT_FH_TX;
1086
1087 /* Now service all interrupt bits discovered above. */
1088 if (inta & CSR_INT_BIT_HW_ERR) {
1089 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1090
1091 /* Tell the device to stop sending interrupts */
1092 iwl_disable_interrupts(priv);
1093
1094 priv->isr_stats.hw++;
1095 iwl_irq_handle_error(priv);
1096
1097 handled |= CSR_INT_BIT_HW_ERR;
1098
1099 return;
1100 }
1101
1102 #ifdef CONFIG_IWLWIFI_DEBUG
1103 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1104 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1105 if (inta & CSR_INT_BIT_SCD) {
1106 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1107 "the frame/frames.\n");
1108 priv->isr_stats.sch++;
1109 }
1110
1111 /* Alive notification via Rx interrupt will do the real work */
1112 if (inta & CSR_INT_BIT_ALIVE) {
1113 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1114 priv->isr_stats.alive++;
1115 }
1116 }
1117 #endif
1118 /* Safely ignore these bits for debug checks below */
1119 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1120
1121 /* HW RF KILL switch toggled */
1122 if (inta & CSR_INT_BIT_RF_KILL) {
1123 int hw_rf_kill = 0;
1124 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1125 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1126 hw_rf_kill = 1;
1127
1128 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1129 hw_rf_kill ? "disable radio" : "enable radio");
1130
1131 priv->isr_stats.rfkill++;
1132
1133 /* driver only loads ucode once setting the interface up.
1134 * the driver allows loading the ucode even if the radio
1135 * is killed. Hence update the killswitch state here. The
1136 * rfkill handler will care about restarting if needed.
1137 */
1138 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1139 if (hw_rf_kill)
1140 set_bit(STATUS_RF_KILL_HW, &priv->status);
1141 else
1142 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1143 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1144 }
1145
1146 handled |= CSR_INT_BIT_RF_KILL;
1147 }
1148
1149 /* Chip got too hot and stopped itself */
1150 if (inta & CSR_INT_BIT_CT_KILL) {
1151 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1152 priv->isr_stats.ctkill++;
1153 handled |= CSR_INT_BIT_CT_KILL;
1154 }
1155
1156 /* Error detected by uCode */
1157 if (inta & CSR_INT_BIT_SW_ERR) {
1158 IWL_ERR(priv, "Microcode SW error detected. "
1159 " Restarting 0x%X.\n", inta);
1160 priv->isr_stats.sw++;
1161 priv->isr_stats.sw_err = inta;
1162 iwl_irq_handle_error(priv);
1163 handled |= CSR_INT_BIT_SW_ERR;
1164 }
1165
1166 /*
1167 * uCode wakes up after power-down sleep.
1168 * Tell device about any new tx or host commands enqueued,
1169 * and about any Rx buffers made available while asleep.
1170 */
1171 if (inta & CSR_INT_BIT_WAKEUP) {
1172 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1173 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1174 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1175 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1176 priv->isr_stats.wakeup++;
1177 handled |= CSR_INT_BIT_WAKEUP;
1178 }
1179
1180 /* All uCode command responses, including Tx command responses,
1181 * Rx "responses" (frame-received notification), and other
1182 * notifications from uCode come through here*/
1183 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1184 iwl_rx_handle(priv);
1185 priv->isr_stats.rx++;
1186 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1187 }
1188
1189 /* This "Tx" DMA channel is used only for loading uCode */
1190 if (inta & CSR_INT_BIT_FH_TX) {
1191 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1192 priv->isr_stats.tx++;
1193 handled |= CSR_INT_BIT_FH_TX;
1194 /* Wake up uCode load routine, now that load is complete */
1195 priv->ucode_write_complete = 1;
1196 wake_up_interruptible(&priv->wait_command_queue);
1197 }
1198
1199 if (inta & ~handled) {
1200 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1201 priv->isr_stats.unhandled++;
1202 }
1203
1204 if (inta & ~(priv->inta_mask)) {
1205 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1206 inta & ~priv->inta_mask);
1207 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1208 }
1209
1210 /* Re-enable all interrupts */
1211 /* only Re-enable if diabled by irq */
1212 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1213 iwl_enable_interrupts(priv);
1214
1215 #ifdef CONFIG_IWLWIFI_DEBUG
1216 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1217 inta = iwl_read32(priv, CSR_INT);
1218 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1219 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1220 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1221 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1222 }
1223 #endif
1224 }
1225
1226 /* tasklet for iwlagn interrupt */
1227 static void iwl_irq_tasklet(struct iwl_priv *priv)
1228 {
1229 u32 inta = 0;
1230 u32 handled = 0;
1231 unsigned long flags;
1232 u32 i;
1233 #ifdef CONFIG_IWLWIFI_DEBUG
1234 u32 inta_mask;
1235 #endif
1236
1237 spin_lock_irqsave(&priv->lock, flags);
1238
1239 /* Ack/clear/reset pending uCode interrupts.
1240 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1241 */
1242 /* There is a hardware bug in the interrupt mask function that some
1243 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1244 * they are disabled in the CSR_INT_MASK register. Furthermore the
1245 * ICT interrupt handling mechanism has another bug that might cause
1246 * these unmasked interrupts fail to be detected. We workaround the
1247 * hardware bugs here by ACKing all the possible interrupts so that
1248 * interrupt coalescing can still be achieved.
1249 */
1250 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1251
1252 inta = priv->_agn.inta;
1253
1254 #ifdef CONFIG_IWLWIFI_DEBUG
1255 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1256 /* just for debug */
1257 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1258 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1259 inta, inta_mask);
1260 }
1261 #endif
1262
1263 spin_unlock_irqrestore(&priv->lock, flags);
1264
1265 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1266 priv->_agn.inta = 0;
1267
1268 /* Now service all interrupt bits discovered above. */
1269 if (inta & CSR_INT_BIT_HW_ERR) {
1270 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1271
1272 /* Tell the device to stop sending interrupts */
1273 iwl_disable_interrupts(priv);
1274
1275 priv->isr_stats.hw++;
1276 iwl_irq_handle_error(priv);
1277
1278 handled |= CSR_INT_BIT_HW_ERR;
1279
1280 return;
1281 }
1282
1283 #ifdef CONFIG_IWLWIFI_DEBUG
1284 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1285 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1286 if (inta & CSR_INT_BIT_SCD) {
1287 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1288 "the frame/frames.\n");
1289 priv->isr_stats.sch++;
1290 }
1291
1292 /* Alive notification via Rx interrupt will do the real work */
1293 if (inta & CSR_INT_BIT_ALIVE) {
1294 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1295 priv->isr_stats.alive++;
1296 }
1297 }
1298 #endif
1299 /* Safely ignore these bits for debug checks below */
1300 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1301
1302 /* HW RF KILL switch toggled */
1303 if (inta & CSR_INT_BIT_RF_KILL) {
1304 int hw_rf_kill = 0;
1305 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1306 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1307 hw_rf_kill = 1;
1308
1309 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1310 hw_rf_kill ? "disable radio" : "enable radio");
1311
1312 priv->isr_stats.rfkill++;
1313
1314 /* driver only loads ucode once setting the interface up.
1315 * the driver allows loading the ucode even if the radio
1316 * is killed. Hence update the killswitch state here. The
1317 * rfkill handler will care about restarting if needed.
1318 */
1319 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1320 if (hw_rf_kill)
1321 set_bit(STATUS_RF_KILL_HW, &priv->status);
1322 else
1323 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1324 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1325 }
1326
1327 handled |= CSR_INT_BIT_RF_KILL;
1328 }
1329
1330 /* Chip got too hot and stopped itself */
1331 if (inta & CSR_INT_BIT_CT_KILL) {
1332 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1333 priv->isr_stats.ctkill++;
1334 handled |= CSR_INT_BIT_CT_KILL;
1335 }
1336
1337 /* Error detected by uCode */
1338 if (inta & CSR_INT_BIT_SW_ERR) {
1339 IWL_ERR(priv, "Microcode SW error detected. "
1340 " Restarting 0x%X.\n", inta);
1341 priv->isr_stats.sw++;
1342 priv->isr_stats.sw_err = inta;
1343 iwl_irq_handle_error(priv);
1344 handled |= CSR_INT_BIT_SW_ERR;
1345 }
1346
1347 /* uCode wakes up after power-down sleep */
1348 if (inta & CSR_INT_BIT_WAKEUP) {
1349 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1350 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1351 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1352 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1353
1354 priv->isr_stats.wakeup++;
1355
1356 handled |= CSR_INT_BIT_WAKEUP;
1357 }
1358
1359 /* All uCode command responses, including Tx command responses,
1360 * Rx "responses" (frame-received notification), and other
1361 * notifications from uCode come through here*/
1362 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1363 CSR_INT_BIT_RX_PERIODIC)) {
1364 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1365 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1366 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1367 iwl_write32(priv, CSR_FH_INT_STATUS,
1368 CSR49_FH_INT_RX_MASK);
1369 }
1370 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1371 handled |= CSR_INT_BIT_RX_PERIODIC;
1372 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1373 }
1374 /* Sending RX interrupt require many steps to be done in the
1375 * the device:
1376 * 1- write interrupt to current index in ICT table.
1377 * 2- dma RX frame.
1378 * 3- update RX shared data to indicate last write index.
1379 * 4- send interrupt.
1380 * This could lead to RX race, driver could receive RX interrupt
1381 * but the shared data changes does not reflect this;
1382 * periodic interrupt will detect any dangling Rx activity.
1383 */
1384
1385 /* Disable periodic interrupt; we use it as just a one-shot. */
1386 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1387 CSR_INT_PERIODIC_DIS);
1388 iwl_rx_handle(priv);
1389
1390 /*
1391 * Enable periodic interrupt in 8 msec only if we received
1392 * real RX interrupt (instead of just periodic int), to catch
1393 * any dangling Rx interrupt. If it was just the periodic
1394 * interrupt, there was no dangling Rx activity, and no need
1395 * to extend the periodic interrupt; one-shot is enough.
1396 */
1397 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1398 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1399 CSR_INT_PERIODIC_ENA);
1400
1401 priv->isr_stats.rx++;
1402 }
1403
1404 /* This "Tx" DMA channel is used only for loading uCode */
1405 if (inta & CSR_INT_BIT_FH_TX) {
1406 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1407 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1408 priv->isr_stats.tx++;
1409 handled |= CSR_INT_BIT_FH_TX;
1410 /* Wake up uCode load routine, now that load is complete */
1411 priv->ucode_write_complete = 1;
1412 wake_up_interruptible(&priv->wait_command_queue);
1413 }
1414
1415 if (inta & ~handled) {
1416 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1417 priv->isr_stats.unhandled++;
1418 }
1419
1420 if (inta & ~(priv->inta_mask)) {
1421 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1422 inta & ~priv->inta_mask);
1423 }
1424
1425 /* Re-enable all interrupts */
1426 /* only Re-enable if diabled by irq */
1427 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1428 iwl_enable_interrupts(priv);
1429 }
1430
1431 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1432 #define ACK_CNT_RATIO (50)
1433 #define BA_TIMEOUT_CNT (5)
1434 #define BA_TIMEOUT_MAX (16)
1435
1436 /**
1437 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1438 *
1439 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1440 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1441 * operation state.
1442 */
1443 bool iwl_good_ack_health(struct iwl_priv *priv,
1444 struct iwl_rx_packet *pkt)
1445 {
1446 bool rc = true;
1447 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1448 int ba_timeout_delta;
1449
1450 actual_ack_cnt_delta =
1451 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1452 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1453 expected_ack_cnt_delta =
1454 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1455 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1456 ba_timeout_delta =
1457 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1458 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1459 if ((priv->_agn.agg_tids_count > 0) &&
1460 (expected_ack_cnt_delta > 0) &&
1461 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1462 < ACK_CNT_RATIO) &&
1463 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1464 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1465 " expected_ack_cnt = %d\n",
1466 actual_ack_cnt_delta, expected_ack_cnt_delta);
1467
1468 #ifdef CONFIG_IWLWIFI_DEBUG
1469 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1470 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1471 IWL_DEBUG_RADIO(priv,
1472 "ack_or_ba_timeout_collision delta = %d\n",
1473 priv->_agn.delta_statistics.tx.
1474 ack_or_ba_timeout_collision);
1475 #endif
1476 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1477 ba_timeout_delta);
1478 if (!actual_ack_cnt_delta &&
1479 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1480 rc = false;
1481 }
1482 return rc;
1483 }
1484
1485
1486 /******************************************************************************
1487 *
1488 * uCode download functions
1489 *
1490 ******************************************************************************/
1491
1492 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1493 {
1494 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1495 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1496 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1497 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1498 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1499 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1500 }
1501
1502 static void iwl_nic_start(struct iwl_priv *priv)
1503 {
1504 /* Remove all resets to allow NIC to operate */
1505 iwl_write32(priv, CSR_RESET, 0);
1506 }
1507
1508 struct iwlagn_ucode_capabilities {
1509 u32 max_probe_length;
1510 };
1511
1512 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1513 static int iwl_mac_setup_register(struct iwl_priv *priv,
1514 struct iwlagn_ucode_capabilities *capa);
1515
1516 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1517 {
1518 const char *name_pre = priv->cfg->fw_name_pre;
1519
1520 if (first)
1521 priv->fw_index = priv->cfg->ucode_api_max;
1522 else
1523 priv->fw_index--;
1524
1525 if (priv->fw_index < priv->cfg->ucode_api_min) {
1526 IWL_ERR(priv, "no suitable firmware found!\n");
1527 return -ENOENT;
1528 }
1529
1530 sprintf(priv->firmware_name, "%s%d%s",
1531 name_pre, priv->fw_index, ".ucode");
1532
1533 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1534 priv->firmware_name);
1535
1536 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1537 &priv->pci_dev->dev, GFP_KERNEL, priv,
1538 iwl_ucode_callback);
1539 }
1540
1541 struct iwlagn_firmware_pieces {
1542 const void *inst, *data, *init, *init_data, *boot;
1543 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1544
1545 u32 build;
1546 };
1547
1548 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1549 const struct firmware *ucode_raw,
1550 struct iwlagn_firmware_pieces *pieces)
1551 {
1552 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1553 u32 api_ver, hdr_size;
1554 const u8 *src;
1555
1556 priv->ucode_ver = le32_to_cpu(ucode->ver);
1557 api_ver = IWL_UCODE_API(priv->ucode_ver);
1558
1559 switch (api_ver) {
1560 default:
1561 /*
1562 * 4965 doesn't revision the firmware file format
1563 * along with the API version, it always uses v1
1564 * file format.
1565 */
1566 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1567 CSR_HW_REV_TYPE_4965) {
1568 hdr_size = 28;
1569 if (ucode_raw->size < hdr_size) {
1570 IWL_ERR(priv, "File size too small!\n");
1571 return -EINVAL;
1572 }
1573 pieces->build = le32_to_cpu(ucode->u.v2.build);
1574 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1575 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1576 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1577 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1578 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1579 src = ucode->u.v2.data;
1580 break;
1581 }
1582 /* fall through for 4965 */
1583 case 0:
1584 case 1:
1585 case 2:
1586 hdr_size = 24;
1587 if (ucode_raw->size < hdr_size) {
1588 IWL_ERR(priv, "File size too small!\n");
1589 return -EINVAL;
1590 }
1591 pieces->build = 0;
1592 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1593 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1594 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1595 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1596 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1597 src = ucode->u.v1.data;
1598 break;
1599 }
1600
1601 /* Verify size of file vs. image size info in file's header */
1602 if (ucode_raw->size != hdr_size + pieces->inst_size +
1603 pieces->data_size + pieces->init_size +
1604 pieces->init_data_size + pieces->boot_size) {
1605
1606 IWL_ERR(priv,
1607 "uCode file size %d does not match expected size\n",
1608 (int)ucode_raw->size);
1609 return -EINVAL;
1610 }
1611
1612 pieces->inst = src;
1613 src += pieces->inst_size;
1614 pieces->data = src;
1615 src += pieces->data_size;
1616 pieces->init = src;
1617 src += pieces->init_size;
1618 pieces->init_data = src;
1619 src += pieces->init_data_size;
1620 pieces->boot = src;
1621 src += pieces->boot_size;
1622
1623 return 0;
1624 }
1625
1626 static int iwlagn_wanted_ucode_alternative = 1;
1627
1628 static int iwlagn_load_firmware(struct iwl_priv *priv,
1629 const struct firmware *ucode_raw,
1630 struct iwlagn_firmware_pieces *pieces,
1631 struct iwlagn_ucode_capabilities *capa)
1632 {
1633 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1634 struct iwl_ucode_tlv *tlv;
1635 size_t len = ucode_raw->size;
1636 const u8 *data;
1637 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1638 u64 alternatives;
1639
1640 if (len < sizeof(*ucode))
1641 return -EINVAL;
1642
1643 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC))
1644 return -EINVAL;
1645
1646 /*
1647 * Check which alternatives are present, and "downgrade"
1648 * when the chosen alternative is not present, warning
1649 * the user when that happens. Some files may not have
1650 * any alternatives, so don't warn in that case.
1651 */
1652 alternatives = le64_to_cpu(ucode->alternatives);
1653 tmp = wanted_alternative;
1654 if (wanted_alternative > 63)
1655 wanted_alternative = 63;
1656 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1657 wanted_alternative--;
1658 if (wanted_alternative && wanted_alternative != tmp)
1659 IWL_WARN(priv,
1660 "uCode alternative %d not available, choosing %d\n",
1661 tmp, wanted_alternative);
1662
1663 priv->ucode_ver = le32_to_cpu(ucode->ver);
1664 pieces->build = le32_to_cpu(ucode->build);
1665 data = ucode->data;
1666
1667 len -= sizeof(*ucode);
1668
1669 while (len >= sizeof(*tlv)) {
1670 u32 tlv_len;
1671 enum iwl_ucode_tlv_type tlv_type;
1672 u16 tlv_alt;
1673 const u8 *tlv_data;
1674
1675 len -= sizeof(*tlv);
1676 tlv = (void *)data;
1677
1678 tlv_len = le32_to_cpu(tlv->length);
1679 tlv_type = le16_to_cpu(tlv->type);
1680 tlv_alt = le16_to_cpu(tlv->alternative);
1681 tlv_data = tlv->data;
1682
1683 if (len < tlv_len)
1684 return -EINVAL;
1685 len -= ALIGN(tlv_len, 4);
1686 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1687
1688 /*
1689 * Alternative 0 is always valid.
1690 *
1691 * Skip alternative TLVs that are not selected.
1692 */
1693 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1694 continue;
1695
1696 switch (tlv_type) {
1697 case IWL_UCODE_TLV_INST:
1698 pieces->inst = tlv_data;
1699 pieces->inst_size = tlv_len;
1700 break;
1701 case IWL_UCODE_TLV_DATA:
1702 pieces->data = tlv_data;
1703 pieces->data_size = tlv_len;
1704 break;
1705 case IWL_UCODE_TLV_INIT:
1706 pieces->init = tlv_data;
1707 pieces->init_size = tlv_len;
1708 break;
1709 case IWL_UCODE_TLV_INIT_DATA:
1710 pieces->init_data = tlv_data;
1711 pieces->init_data_size = tlv_len;
1712 break;
1713 case IWL_UCODE_TLV_BOOT:
1714 pieces->boot = tlv_data;
1715 pieces->boot_size = tlv_len;
1716 break;
1717 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1718 if (tlv_len != 4)
1719 return -EINVAL;
1720 capa->max_probe_length =
1721 le32_to_cpup((__le32 *)tlv_data);
1722 break;
1723 default:
1724 break;
1725 }
1726 }
1727
1728 if (len)
1729 return -EINVAL;
1730
1731 return 0;
1732 }
1733
1734 /**
1735 * iwl_ucode_callback - callback when firmware was loaded
1736 *
1737 * If loaded successfully, copies the firmware into buffers
1738 * for the card to fetch (via DMA).
1739 */
1740 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1741 {
1742 struct iwl_priv *priv = context;
1743 struct iwl_ucode_header *ucode;
1744 int err;
1745 struct iwlagn_firmware_pieces pieces;
1746 const unsigned int api_max = priv->cfg->ucode_api_max;
1747 const unsigned int api_min = priv->cfg->ucode_api_min;
1748 u32 api_ver;
1749 char buildstr[25];
1750 u32 build;
1751 struct iwlagn_ucode_capabilities ucode_capa = {
1752 .max_probe_length = 200,
1753 };
1754
1755 memset(&pieces, 0, sizeof(pieces));
1756
1757 if (!ucode_raw) {
1758 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
1759 priv->firmware_name);
1760 goto try_again;
1761 }
1762
1763 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1764 priv->firmware_name, ucode_raw->size);
1765
1766 /* Make sure that we got at least the API version number */
1767 if (ucode_raw->size < 4) {
1768 IWL_ERR(priv, "File size way too small!\n");
1769 goto try_again;
1770 }
1771
1772 /* Data from ucode file: header followed by uCode images */
1773 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1774
1775 if (ucode->ver)
1776 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1777 else
1778 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1779 &ucode_capa);
1780
1781 if (err)
1782 goto try_again;
1783
1784 api_ver = IWL_UCODE_API(priv->ucode_ver);
1785 build = pieces.build;
1786
1787 /*
1788 * api_ver should match the api version forming part of the
1789 * firmware filename ... but we don't check for that and only rely
1790 * on the API version read from firmware header from here on forward
1791 */
1792 if (api_ver < api_min || api_ver > api_max) {
1793 IWL_ERR(priv, "Driver unable to support your firmware API. "
1794 "Driver supports v%u, firmware is v%u.\n",
1795 api_max, api_ver);
1796 goto try_again;
1797 }
1798
1799 if (api_ver != api_max)
1800 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
1801 "got v%u. New firmware can be obtained "
1802 "from http://www.intellinuxwireless.org.\n",
1803 api_max, api_ver);
1804
1805 if (build)
1806 sprintf(buildstr, " build %u", build);
1807 else
1808 buildstr[0] = '\0';
1809
1810 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1811 IWL_UCODE_MAJOR(priv->ucode_ver),
1812 IWL_UCODE_MINOR(priv->ucode_ver),
1813 IWL_UCODE_API(priv->ucode_ver),
1814 IWL_UCODE_SERIAL(priv->ucode_ver),
1815 buildstr);
1816
1817 snprintf(priv->hw->wiphy->fw_version,
1818 sizeof(priv->hw->wiphy->fw_version),
1819 "%u.%u.%u.%u%s",
1820 IWL_UCODE_MAJOR(priv->ucode_ver),
1821 IWL_UCODE_MINOR(priv->ucode_ver),
1822 IWL_UCODE_API(priv->ucode_ver),
1823 IWL_UCODE_SERIAL(priv->ucode_ver),
1824 buildstr);
1825
1826 /*
1827 * For any of the failures below (before allocating pci memory)
1828 * we will try to load a version with a smaller API -- maybe the
1829 * user just got a corrupted version of the latest API.
1830 */
1831
1832 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1833 priv->ucode_ver);
1834 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1835 pieces.inst_size);
1836 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1837 pieces.data_size);
1838 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1839 pieces.init_size);
1840 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1841 pieces.init_data_size);
1842 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
1843 pieces.boot_size);
1844
1845 /* Verify that uCode images will fit in card's SRAM */
1846 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1847 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1848 pieces.inst_size);
1849 goto try_again;
1850 }
1851
1852 if (pieces.data_size > priv->hw_params.max_data_size) {
1853 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1854 pieces.data_size);
1855 goto try_again;
1856 }
1857
1858 if (pieces.init_size > priv->hw_params.max_inst_size) {
1859 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1860 pieces.init_size);
1861 goto try_again;
1862 }
1863
1864 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1865 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1866 pieces.init_data_size);
1867 goto try_again;
1868 }
1869
1870 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
1871 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
1872 pieces.boot_size);
1873 goto try_again;
1874 }
1875
1876 /* Allocate ucode buffers for card's bus-master loading ... */
1877
1878 /* Runtime instructions and 2 copies of data:
1879 * 1) unmodified from disk
1880 * 2) backup cache for save/restore during power-downs */
1881 priv->ucode_code.len = pieces.inst_size;
1882 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1883
1884 priv->ucode_data.len = pieces.data_size;
1885 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1886
1887 priv->ucode_data_backup.len = pieces.data_size;
1888 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1889
1890 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1891 !priv->ucode_data_backup.v_addr)
1892 goto err_pci_alloc;
1893
1894 /* Initialization instructions and data */
1895 if (pieces.init_size && pieces.init_data_size) {
1896 priv->ucode_init.len = pieces.init_size;
1897 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1898
1899 priv->ucode_init_data.len = pieces.init_data_size;
1900 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1901
1902 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1903 goto err_pci_alloc;
1904 }
1905
1906 /* Bootstrap (instructions only, no data) */
1907 if (pieces.boot_size) {
1908 priv->ucode_boot.len = pieces.boot_size;
1909 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1910
1911 if (!priv->ucode_boot.v_addr)
1912 goto err_pci_alloc;
1913 }
1914
1915 /* Copy images into buffers for card's bus-master reads ... */
1916
1917 /* Runtime instructions (first block of data in file) */
1918 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1919 pieces.inst_size);
1920 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1921
1922 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1923 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1924
1925 /*
1926 * Runtime data
1927 * NOTE: Copy into backup buffer will be done in iwl_up()
1928 */
1929 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1930 pieces.data_size);
1931 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1932 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
1933
1934 /* Initialization instructions */
1935 if (pieces.init_size) {
1936 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1937 pieces.init_size);
1938 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1939 }
1940
1941 /* Initialization data */
1942 if (pieces.init_data_size) {
1943 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1944 pieces.init_data_size);
1945 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1946 pieces.init_data_size);
1947 }
1948
1949 /* Bootstrap instructions */
1950 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
1951 pieces.boot_size);
1952 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
1953
1954 /**************************************************
1955 * This is still part of probe() in a sense...
1956 *
1957 * 9. Setup and register with mac80211 and debugfs
1958 **************************************************/
1959 err = iwl_mac_setup_register(priv, &ucode_capa);
1960 if (err)
1961 goto out_unbind;
1962
1963 err = iwl_dbgfs_register(priv, DRV_NAME);
1964 if (err)
1965 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1966
1967 /* We have our copies now, allow OS release its copies */
1968 release_firmware(ucode_raw);
1969 complete(&priv->_agn.firmware_loading_complete);
1970 return;
1971
1972 try_again:
1973 /* try next, if any */
1974 if (iwl_request_firmware(priv, false))
1975 goto out_unbind;
1976 release_firmware(ucode_raw);
1977 return;
1978
1979 err_pci_alloc:
1980 IWL_ERR(priv, "failed to allocate pci memory\n");
1981 iwl_dealloc_ucode_pci(priv);
1982 out_unbind:
1983 complete(&priv->_agn.firmware_loading_complete);
1984 device_release_driver(&priv->pci_dev->dev);
1985 release_firmware(ucode_raw);
1986 }
1987
1988 static const char *desc_lookup_text[] = {
1989 "OK",
1990 "FAIL",
1991 "BAD_PARAM",
1992 "BAD_CHECKSUM",
1993 "NMI_INTERRUPT_WDG",
1994 "SYSASSERT",
1995 "FATAL_ERROR",
1996 "BAD_COMMAND",
1997 "HW_ERROR_TUNE_LOCK",
1998 "HW_ERROR_TEMPERATURE",
1999 "ILLEGAL_CHAN_FREQ",
2000 "VCC_NOT_STABLE",
2001 "FH_ERROR",
2002 "NMI_INTERRUPT_HOST",
2003 "NMI_INTERRUPT_ACTION_PT",
2004 "NMI_INTERRUPT_UNKNOWN",
2005 "UCODE_VERSION_MISMATCH",
2006 "HW_ERROR_ABS_LOCK",
2007 "HW_ERROR_CAL_LOCK_FAIL",
2008 "NMI_INTERRUPT_INST_ACTION_PT",
2009 "NMI_INTERRUPT_DATA_ACTION_PT",
2010 "NMI_TRM_HW_ER",
2011 "NMI_INTERRUPT_TRM",
2012 "NMI_INTERRUPT_BREAK_POINT"
2013 "DEBUG_0",
2014 "DEBUG_1",
2015 "DEBUG_2",
2016 "DEBUG_3",
2017 "ADVANCED SYSASSERT"
2018 };
2019
2020 static const char *desc_lookup(int i)
2021 {
2022 int max = ARRAY_SIZE(desc_lookup_text) - 1;
2023
2024 if (i < 0 || i > max)
2025 i = max;
2026
2027 return desc_lookup_text[i];
2028 }
2029
2030 #define ERROR_START_OFFSET (1 * sizeof(u32))
2031 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
2032
2033 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2034 {
2035 u32 data2, line;
2036 u32 desc, time, count, base, data1;
2037 u32 blink1, blink2, ilink1, ilink2;
2038 u32 pc, hcmd;
2039
2040 if (priv->ucode_type == UCODE_INIT)
2041 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2042 else
2043 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2044
2045 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2046 IWL_ERR(priv,
2047 "Not valid error log pointer 0x%08X for %s uCode\n",
2048 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2049 return;
2050 }
2051
2052 count = iwl_read_targ_mem(priv, base);
2053
2054 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2055 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2056 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2057 priv->status, count);
2058 }
2059
2060 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2061 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2062 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2063 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2064 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2065 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2066 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2067 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2068 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2069 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2070 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2071
2072 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2073 blink1, blink2, ilink1, ilink2);
2074
2075 IWL_ERR(priv, "Desc Time "
2076 "data1 data2 line\n");
2077 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
2078 desc_lookup(desc), desc, time, data1, data2, line);
2079 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2080 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2081 pc, blink1, blink2, ilink1, ilink2, hcmd);
2082 }
2083
2084 #define EVENT_START_OFFSET (4 * sizeof(u32))
2085
2086 /**
2087 * iwl_print_event_log - Dump error event log to syslog
2088 *
2089 */
2090 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2091 u32 num_events, u32 mode,
2092 int pos, char **buf, size_t bufsz)
2093 {
2094 u32 i;
2095 u32 base; /* SRAM byte address of event log header */
2096 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2097 u32 ptr; /* SRAM byte address of log data */
2098 u32 ev, time, data; /* event log data */
2099 unsigned long reg_flags;
2100
2101 if (num_events == 0)
2102 return pos;
2103 if (priv->ucode_type == UCODE_INIT)
2104 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2105 else
2106 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2107
2108 if (mode == 0)
2109 event_size = 2 * sizeof(u32);
2110 else
2111 event_size = 3 * sizeof(u32);
2112
2113 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2114
2115 /* Make sure device is powered up for SRAM reads */
2116 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2117 iwl_grab_nic_access(priv);
2118
2119 /* Set starting address; reads will auto-increment */
2120 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2121 rmb();
2122
2123 /* "time" is actually "data" for mode 0 (no timestamp).
2124 * place event id # at far right for easier visual parsing. */
2125 for (i = 0; i < num_events; i++) {
2126 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2127 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2128 if (mode == 0) {
2129 /* data, ev */
2130 if (bufsz) {
2131 pos += scnprintf(*buf + pos, bufsz - pos,
2132 "EVT_LOG:0x%08x:%04u\n",
2133 time, ev);
2134 } else {
2135 trace_iwlwifi_dev_ucode_event(priv, 0,
2136 time, ev);
2137 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2138 time, ev);
2139 }
2140 } else {
2141 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2142 if (bufsz) {
2143 pos += scnprintf(*buf + pos, bufsz - pos,
2144 "EVT_LOGT:%010u:0x%08x:%04u\n",
2145 time, data, ev);
2146 } else {
2147 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2148 time, data, ev);
2149 trace_iwlwifi_dev_ucode_event(priv, time,
2150 data, ev);
2151 }
2152 }
2153 }
2154
2155 /* Allow device to power down */
2156 iwl_release_nic_access(priv);
2157 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2158 return pos;
2159 }
2160
2161 /**
2162 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2163 */
2164 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2165 u32 num_wraps, u32 next_entry,
2166 u32 size, u32 mode,
2167 int pos, char **buf, size_t bufsz)
2168 {
2169 /*
2170 * display the newest DEFAULT_LOG_ENTRIES entries
2171 * i.e the entries just before the next ont that uCode would fill.
2172 */
2173 if (num_wraps) {
2174 if (next_entry < size) {
2175 pos = iwl_print_event_log(priv,
2176 capacity - (size - next_entry),
2177 size - next_entry, mode,
2178 pos, buf, bufsz);
2179 pos = iwl_print_event_log(priv, 0,
2180 next_entry, mode,
2181 pos, buf, bufsz);
2182 } else
2183 pos = iwl_print_event_log(priv, next_entry - size,
2184 size, mode, pos, buf, bufsz);
2185 } else {
2186 if (next_entry < size) {
2187 pos = iwl_print_event_log(priv, 0, next_entry,
2188 mode, pos, buf, bufsz);
2189 } else {
2190 pos = iwl_print_event_log(priv, next_entry - size,
2191 size, mode, pos, buf, bufsz);
2192 }
2193 }
2194 return pos;
2195 }
2196
2197 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2198
2199 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2200 char **buf, bool display)
2201 {
2202 u32 base; /* SRAM byte address of event log header */
2203 u32 capacity; /* event log capacity in # entries */
2204 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2205 u32 num_wraps; /* # times uCode wrapped to top of log */
2206 u32 next_entry; /* index of next entry to be written by uCode */
2207 u32 size; /* # entries that we'll print */
2208 int pos = 0;
2209 size_t bufsz = 0;
2210
2211 if (priv->ucode_type == UCODE_INIT)
2212 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2213 else
2214 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2215
2216 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2217 IWL_ERR(priv,
2218 "Invalid event log pointer 0x%08X for %s uCode\n",
2219 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2220 return -EINVAL;
2221 }
2222
2223 /* event log header */
2224 capacity = iwl_read_targ_mem(priv, base);
2225 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2226 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2227 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2228
2229 if (capacity > priv->cfg->max_event_log_size) {
2230 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2231 capacity, priv->cfg->max_event_log_size);
2232 capacity = priv->cfg->max_event_log_size;
2233 }
2234
2235 if (next_entry > priv->cfg->max_event_log_size) {
2236 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2237 next_entry, priv->cfg->max_event_log_size);
2238 next_entry = priv->cfg->max_event_log_size;
2239 }
2240
2241 size = num_wraps ? capacity : next_entry;
2242
2243 /* bail out if nothing in log */
2244 if (size == 0) {
2245 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2246 return pos;
2247 }
2248
2249 #ifdef CONFIG_IWLWIFI_DEBUG
2250 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2251 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2252 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2253 #else
2254 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2255 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2256 #endif
2257 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2258 size);
2259
2260 #ifdef CONFIG_IWLWIFI_DEBUG
2261 if (display) {
2262 if (full_log)
2263 bufsz = capacity * 48;
2264 else
2265 bufsz = size * 48;
2266 *buf = kmalloc(bufsz, GFP_KERNEL);
2267 if (!*buf)
2268 return -ENOMEM;
2269 }
2270 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2271 /*
2272 * if uCode has wrapped back to top of log,
2273 * start at the oldest entry,
2274 * i.e the next one that uCode would fill.
2275 */
2276 if (num_wraps)
2277 pos = iwl_print_event_log(priv, next_entry,
2278 capacity - next_entry, mode,
2279 pos, buf, bufsz);
2280 /* (then/else) start at top of log */
2281 pos = iwl_print_event_log(priv, 0,
2282 next_entry, mode, pos, buf, bufsz);
2283 } else
2284 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2285 next_entry, size, mode,
2286 pos, buf, bufsz);
2287 #else
2288 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2289 next_entry, size, mode,
2290 pos, buf, bufsz);
2291 #endif
2292 return pos;
2293 }
2294
2295 /**
2296 * iwl_alive_start - called after REPLY_ALIVE notification received
2297 * from protocol/runtime uCode (initialization uCode's
2298 * Alive gets handled by iwl_init_alive_start()).
2299 */
2300 static void iwl_alive_start(struct iwl_priv *priv)
2301 {
2302 int ret = 0;
2303
2304 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2305
2306 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2307 /* We had an error bringing up the hardware, so take it
2308 * all the way back down so we can try again */
2309 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2310 goto restart;
2311 }
2312
2313 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2314 * This is a paranoid check, because we would not have gotten the
2315 * "runtime" alive if code weren't properly loaded. */
2316 if (iwl_verify_ucode(priv)) {
2317 /* Runtime instruction load was bad;
2318 * take it all the way back down so we can try again */
2319 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2320 goto restart;
2321 }
2322
2323 ret = priv->cfg->ops->lib->alive_notify(priv);
2324 if (ret) {
2325 IWL_WARN(priv,
2326 "Could not complete ALIVE transition [ntf]: %d\n", ret);
2327 goto restart;
2328 }
2329
2330 /* After the ALIVE response, we can send host commands to the uCode */
2331 set_bit(STATUS_ALIVE, &priv->status);
2332
2333 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2334 /* Enable timer to monitor the driver queues */
2335 mod_timer(&priv->monitor_recover,
2336 jiffies +
2337 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2338 }
2339
2340 if (iwl_is_rfkill(priv))
2341 return;
2342
2343 ieee80211_wake_queues(priv->hw);
2344
2345 priv->active_rate = IWL_RATES_MASK;
2346
2347 /* Configure Tx antenna selection based on H/W config */
2348 if (priv->cfg->ops->hcmd->set_tx_ant)
2349 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2350
2351 if (iwl_is_associated(priv)) {
2352 struct iwl_rxon_cmd *active_rxon =
2353 (struct iwl_rxon_cmd *)&priv->active_rxon;
2354 /* apply any changes in staging */
2355 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2356 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2357 } else {
2358 /* Initialize our rx_config data */
2359 iwl_connection_init_rx_config(priv, NULL);
2360
2361 if (priv->cfg->ops->hcmd->set_rxon_chain)
2362 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2363
2364 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2365 }
2366
2367 /* Configure Bluetooth device coexistence support */
2368 priv->cfg->ops->hcmd->send_bt_config(priv);
2369
2370 iwl_reset_run_time_calib(priv);
2371
2372 /* Configure the adapter for unassociated operation */
2373 iwlcore_commit_rxon(priv);
2374
2375 /* At this point, the NIC is initialized and operational */
2376 iwl_rf_kill_ct_config(priv);
2377
2378 iwl_leds_init(priv);
2379
2380 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2381 set_bit(STATUS_READY, &priv->status);
2382 wake_up_interruptible(&priv->wait_command_queue);
2383
2384 iwl_power_update_mode(priv, true);
2385 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2386
2387
2388 return;
2389
2390 restart:
2391 queue_work(priv->workqueue, &priv->restart);
2392 }
2393
2394 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2395
2396 static void __iwl_down(struct iwl_priv *priv)
2397 {
2398 unsigned long flags;
2399 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2400
2401 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2402
2403 if (!exit_pending)
2404 set_bit(STATUS_EXIT_PENDING, &priv->status);
2405
2406 iwl_clear_ucode_stations(priv);
2407 iwl_dealloc_bcast_station(priv);
2408 iwl_clear_driver_stations(priv);
2409
2410 /* Unblock any waiting calls */
2411 wake_up_interruptible_all(&priv->wait_command_queue);
2412
2413 /* Wipe out the EXIT_PENDING status bit if we are not actually
2414 * exiting the module */
2415 if (!exit_pending)
2416 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2417
2418 /* stop and reset the on-board processor */
2419 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2420
2421 /* tell the device to stop sending interrupts */
2422 spin_lock_irqsave(&priv->lock, flags);
2423 iwl_disable_interrupts(priv);
2424 spin_unlock_irqrestore(&priv->lock, flags);
2425 iwl_synchronize_irq(priv);
2426
2427 if (priv->mac80211_registered)
2428 ieee80211_stop_queues(priv->hw);
2429
2430 /* If we have not previously called iwl_init() then
2431 * clear all bits but the RF Kill bit and return */
2432 if (!iwl_is_init(priv)) {
2433 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2434 STATUS_RF_KILL_HW |
2435 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2436 STATUS_GEO_CONFIGURED |
2437 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2438 STATUS_EXIT_PENDING;
2439 goto exit;
2440 }
2441
2442 /* ...otherwise clear out all the status bits but the RF Kill
2443 * bit and continue taking the NIC down. */
2444 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2445 STATUS_RF_KILL_HW |
2446 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2447 STATUS_GEO_CONFIGURED |
2448 test_bit(STATUS_FW_ERROR, &priv->status) <<
2449 STATUS_FW_ERROR |
2450 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2451 STATUS_EXIT_PENDING;
2452
2453 /* device going down, Stop using ICT table */
2454 iwl_disable_ict(priv);
2455
2456 iwlagn_txq_ctx_stop(priv);
2457 iwlagn_rxq_stop(priv);
2458
2459 /* Power-down device's busmaster DMA clocks */
2460 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2461 udelay(5);
2462
2463 /* Make sure (redundant) we've released our request to stay awake */
2464 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2465
2466 /* Stop the device, and put it in low power state */
2467 priv->cfg->ops->lib->apm_ops.stop(priv);
2468
2469 exit:
2470 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2471
2472 if (priv->ibss_beacon)
2473 dev_kfree_skb(priv->ibss_beacon);
2474 priv->ibss_beacon = NULL;
2475
2476 /* clear out any free frames */
2477 iwl_clear_free_frames(priv);
2478 }
2479
2480 static void iwl_down(struct iwl_priv *priv)
2481 {
2482 mutex_lock(&priv->mutex);
2483 __iwl_down(priv);
2484 mutex_unlock(&priv->mutex);
2485
2486 iwl_cancel_deferred_work(priv);
2487 }
2488
2489 #define HW_READY_TIMEOUT (50)
2490
2491 static int iwl_set_hw_ready(struct iwl_priv *priv)
2492 {
2493 int ret = 0;
2494
2495 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2496 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2497
2498 /* See if we got it */
2499 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2500 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2501 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2502 HW_READY_TIMEOUT);
2503 if (ret != -ETIMEDOUT)
2504 priv->hw_ready = true;
2505 else
2506 priv->hw_ready = false;
2507
2508 IWL_DEBUG_INFO(priv, "hardware %s\n",
2509 (priv->hw_ready == 1) ? "ready" : "not ready");
2510 return ret;
2511 }
2512
2513 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2514 {
2515 int ret = 0;
2516
2517 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2518
2519 ret = iwl_set_hw_ready(priv);
2520 if (priv->hw_ready)
2521 return ret;
2522
2523 /* If HW is not ready, prepare the conditions to check again */
2524 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2525 CSR_HW_IF_CONFIG_REG_PREPARE);
2526
2527 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2528 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2529 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2530
2531 /* HW should be ready by now, check again. */
2532 if (ret != -ETIMEDOUT)
2533 iwl_set_hw_ready(priv);
2534
2535 return ret;
2536 }
2537
2538 #define MAX_HW_RESTARTS 5
2539
2540 static int __iwl_up(struct iwl_priv *priv)
2541 {
2542 int i;
2543 int ret;
2544
2545 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2546 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2547 return -EIO;
2548 }
2549
2550 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2551 IWL_ERR(priv, "ucode not available for device bringup\n");
2552 return -EIO;
2553 }
2554
2555 ret = iwl_alloc_bcast_station(priv, true);
2556 if (ret)
2557 return ret;
2558
2559 iwl_prepare_card_hw(priv);
2560
2561 if (!priv->hw_ready) {
2562 IWL_WARN(priv, "Exit HW not ready\n");
2563 return -EIO;
2564 }
2565
2566 /* If platform's RF_KILL switch is NOT set to KILL */
2567 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2568 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2569 else
2570 set_bit(STATUS_RF_KILL_HW, &priv->status);
2571
2572 if (iwl_is_rfkill(priv)) {
2573 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2574
2575 iwl_enable_interrupts(priv);
2576 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2577 return 0;
2578 }
2579
2580 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2581
2582 ret = iwlagn_hw_nic_init(priv);
2583 if (ret) {
2584 IWL_ERR(priv, "Unable to init nic\n");
2585 return ret;
2586 }
2587
2588 /* make sure rfkill handshake bits are cleared */
2589 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2590 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2591 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2592
2593 /* clear (again), then enable host interrupts */
2594 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2595 iwl_enable_interrupts(priv);
2596
2597 /* really make sure rfkill handshake bits are cleared */
2598 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2599 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2600
2601 /* Copy original ucode data image from disk into backup cache.
2602 * This will be used to initialize the on-board processor's
2603 * data SRAM for a clean start when the runtime program first loads. */
2604 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2605 priv->ucode_data.len);
2606
2607 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2608
2609 /* load bootstrap state machine,
2610 * load bootstrap program into processor's memory,
2611 * prepare to load the "initialize" uCode */
2612 ret = priv->cfg->ops->lib->load_ucode(priv);
2613
2614 if (ret) {
2615 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2616 ret);
2617 continue;
2618 }
2619
2620 /* start card; "initialize" will load runtime ucode */
2621 iwl_nic_start(priv);
2622
2623 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2624
2625 return 0;
2626 }
2627
2628 set_bit(STATUS_EXIT_PENDING, &priv->status);
2629 __iwl_down(priv);
2630 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2631
2632 /* tried to restart and config the device for as long as our
2633 * patience could withstand */
2634 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2635 return -EIO;
2636 }
2637
2638
2639 /*****************************************************************************
2640 *
2641 * Workqueue callbacks
2642 *
2643 *****************************************************************************/
2644
2645 static void iwl_bg_init_alive_start(struct work_struct *data)
2646 {
2647 struct iwl_priv *priv =
2648 container_of(data, struct iwl_priv, init_alive_start.work);
2649
2650 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2651 return;
2652
2653 mutex_lock(&priv->mutex);
2654 priv->cfg->ops->lib->init_alive_start(priv);
2655 mutex_unlock(&priv->mutex);
2656 }
2657
2658 static void iwl_bg_alive_start(struct work_struct *data)
2659 {
2660 struct iwl_priv *priv =
2661 container_of(data, struct iwl_priv, alive_start.work);
2662
2663 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2664 return;
2665
2666 /* enable dram interrupt */
2667 iwl_reset_ict(priv);
2668
2669 mutex_lock(&priv->mutex);
2670 iwl_alive_start(priv);
2671 mutex_unlock(&priv->mutex);
2672 }
2673
2674 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2675 {
2676 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2677 run_time_calib_work);
2678
2679 mutex_lock(&priv->mutex);
2680
2681 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2682 test_bit(STATUS_SCANNING, &priv->status)) {
2683 mutex_unlock(&priv->mutex);
2684 return;
2685 }
2686
2687 if (priv->start_calib) {
2688 iwl_chain_noise_calibration(priv, &priv->_agn.statistics);
2689
2690 iwl_sensitivity_calibration(priv, &priv->_agn.statistics);
2691 }
2692
2693 mutex_unlock(&priv->mutex);
2694 return;
2695 }
2696
2697 static void iwl_bg_restart(struct work_struct *data)
2698 {
2699 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2700
2701 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2702 return;
2703
2704 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2705 mutex_lock(&priv->mutex);
2706 priv->vif = NULL;
2707 priv->is_open = 0;
2708 mutex_unlock(&priv->mutex);
2709 iwl_down(priv);
2710 ieee80211_restart_hw(priv->hw);
2711 } else {
2712 iwl_down(priv);
2713
2714 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2715 return;
2716
2717 mutex_lock(&priv->mutex);
2718 __iwl_up(priv);
2719 mutex_unlock(&priv->mutex);
2720 }
2721 }
2722
2723 static void iwl_bg_rx_replenish(struct work_struct *data)
2724 {
2725 struct iwl_priv *priv =
2726 container_of(data, struct iwl_priv, rx_replenish);
2727
2728 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2729 return;
2730
2731 mutex_lock(&priv->mutex);
2732 iwlagn_rx_replenish(priv);
2733 mutex_unlock(&priv->mutex);
2734 }
2735
2736 #define IWL_DELAY_NEXT_SCAN (HZ*2)
2737
2738 void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
2739 {
2740 struct ieee80211_conf *conf = NULL;
2741 int ret = 0;
2742
2743 if (!vif || !priv->is_open)
2744 return;
2745
2746 if (vif->type == NL80211_IFTYPE_AP) {
2747 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
2748 return;
2749 }
2750
2751 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2752 return;
2753
2754 iwl_scan_cancel_timeout(priv, 200);
2755
2756 conf = ieee80211_get_hw_conf(priv->hw);
2757
2758 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2759 iwlcore_commit_rxon(priv);
2760
2761 iwl_setup_rxon_timing(priv, vif);
2762 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2763 sizeof(priv->rxon_timing), &priv->rxon_timing);
2764 if (ret)
2765 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2766 "Attempting to continue.\n");
2767
2768 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2769
2770 iwl_set_rxon_ht(priv, &priv->current_ht_config);
2771
2772 if (priv->cfg->ops->hcmd->set_rxon_chain)
2773 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2774
2775 priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
2776
2777 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
2778 vif->bss_conf.aid, vif->bss_conf.beacon_int);
2779
2780 if (vif->bss_conf.assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2781 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2782 else
2783 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2784
2785 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2786 if (vif->bss_conf.assoc_capability &
2787 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2788 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2789 else
2790 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2791
2792 if (vif->type == NL80211_IFTYPE_ADHOC)
2793 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2794 }
2795
2796 iwlcore_commit_rxon(priv);
2797
2798 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
2799 vif->bss_conf.aid, priv->active_rxon.bssid_addr);
2800
2801 switch (vif->type) {
2802 case NL80211_IFTYPE_STATION:
2803 break;
2804 case NL80211_IFTYPE_ADHOC:
2805 iwl_send_beacon_cmd(priv);
2806 break;
2807 default:
2808 IWL_ERR(priv, "%s Should not be called in %d mode\n",
2809 __func__, vif->type);
2810 break;
2811 }
2812
2813 /* the chain noise calibration will enabled PM upon completion
2814 * If chain noise has already been run, then we need to enable
2815 * power management here */
2816 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
2817 iwl_power_update_mode(priv, false);
2818
2819 /* Enable Rx differential gain and sensitivity calibrations */
2820 iwl_chain_noise_reset(priv);
2821 priv->start_calib = 1;
2822
2823 }
2824
2825 /*****************************************************************************
2826 *
2827 * mac80211 entry point functions
2828 *
2829 *****************************************************************************/
2830
2831 #define UCODE_READY_TIMEOUT (4 * HZ)
2832
2833 /*
2834 * Not a mac80211 entry point function, but it fits in with all the
2835 * other mac80211 functions grouped here.
2836 */
2837 static int iwl_mac_setup_register(struct iwl_priv *priv,
2838 struct iwlagn_ucode_capabilities *capa)
2839 {
2840 int ret;
2841 struct ieee80211_hw *hw = priv->hw;
2842 hw->rate_control_algorithm = "iwl-agn-rs";
2843
2844 /* Tell mac80211 our characteristics */
2845 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2846 IEEE80211_HW_AMPDU_AGGREGATION |
2847 IEEE80211_HW_SPECTRUM_MGMT;
2848
2849 if (!priv->cfg->broken_powersave)
2850 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2851 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2852
2853 if (priv->cfg->sku & IWL_SKU_N)
2854 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2855 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2856
2857 hw->sta_data_size = sizeof(struct iwl_station_priv);
2858 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2859
2860 hw->wiphy->interface_modes =
2861 BIT(NL80211_IFTYPE_STATION) |
2862 BIT(NL80211_IFTYPE_ADHOC);
2863
2864 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2865 WIPHY_FLAG_DISABLE_BEACON_HINTS;
2866
2867 /*
2868 * For now, disable PS by default because it affects
2869 * RX performance significantly.
2870 */
2871 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2872
2873 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2874 /* we create the 802.11 header and a zero-length SSID element */
2875 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2876
2877 /* Default value; 4 EDCA QOS priorities */
2878 hw->queues = 4;
2879
2880 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2881
2882 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2883 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2884 &priv->bands[IEEE80211_BAND_2GHZ];
2885 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2886 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2887 &priv->bands[IEEE80211_BAND_5GHZ];
2888
2889 ret = ieee80211_register_hw(priv->hw);
2890 if (ret) {
2891 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2892 return ret;
2893 }
2894 priv->mac80211_registered = 1;
2895
2896 return 0;
2897 }
2898
2899
2900 static int iwl_mac_start(struct ieee80211_hw *hw)
2901 {
2902 struct iwl_priv *priv = hw->priv;
2903 int ret;
2904
2905 IWL_DEBUG_MAC80211(priv, "enter\n");
2906
2907 /* we should be verifying the device is ready to be opened */
2908 mutex_lock(&priv->mutex);
2909 ret = __iwl_up(priv);
2910 mutex_unlock(&priv->mutex);
2911
2912 if (ret)
2913 return ret;
2914
2915 if (iwl_is_rfkill(priv))
2916 goto out;
2917
2918 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2919
2920 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2921 * mac80211 will not be run successfully. */
2922 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2923 test_bit(STATUS_READY, &priv->status),
2924 UCODE_READY_TIMEOUT);
2925 if (!ret) {
2926 if (!test_bit(STATUS_READY, &priv->status)) {
2927 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2928 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2929 return -ETIMEDOUT;
2930 }
2931 }
2932
2933 iwl_led_start(priv);
2934
2935 out:
2936 priv->is_open = 1;
2937 IWL_DEBUG_MAC80211(priv, "leave\n");
2938 return 0;
2939 }
2940
2941 static void iwl_mac_stop(struct ieee80211_hw *hw)
2942 {
2943 struct iwl_priv *priv = hw->priv;
2944
2945 IWL_DEBUG_MAC80211(priv, "enter\n");
2946
2947 if (!priv->is_open)
2948 return;
2949
2950 priv->is_open = 0;
2951
2952 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
2953 /* stop mac, cancel any scan request and clear
2954 * RXON_FILTER_ASSOC_MSK BIT
2955 */
2956 mutex_lock(&priv->mutex);
2957 iwl_scan_cancel_timeout(priv, 100);
2958 mutex_unlock(&priv->mutex);
2959 }
2960
2961 iwl_down(priv);
2962
2963 flush_workqueue(priv->workqueue);
2964
2965 /* enable interrupts again in order to receive rfkill changes */
2966 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2967 iwl_enable_interrupts(priv);
2968
2969 IWL_DEBUG_MAC80211(priv, "leave\n");
2970 }
2971
2972 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2973 {
2974 struct iwl_priv *priv = hw->priv;
2975
2976 IWL_DEBUG_MACDUMP(priv, "enter\n");
2977
2978 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2979 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2980
2981 if (iwlagn_tx_skb(priv, skb))
2982 dev_kfree_skb_any(skb);
2983
2984 IWL_DEBUG_MACDUMP(priv, "leave\n");
2985 return NETDEV_TX_OK;
2986 }
2987
2988 void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
2989 {
2990 int ret = 0;
2991
2992 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2993 return;
2994
2995 /* The following should be done only at AP bring up */
2996 if (!iwl_is_associated(priv)) {
2997
2998 /* RXON - unassoc (to set timing command) */
2999 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3000 iwlcore_commit_rxon(priv);
3001
3002 /* RXON Timing */
3003 iwl_setup_rxon_timing(priv, vif);
3004 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3005 sizeof(priv->rxon_timing), &priv->rxon_timing);
3006 if (ret)
3007 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
3008 "Attempting to continue.\n");
3009
3010 /* AP has all antennas */
3011 priv->chain_noise_data.active_chains =
3012 priv->hw_params.valid_rx_ant;
3013 iwl_set_rxon_ht(priv, &priv->current_ht_config);
3014 if (priv->cfg->ops->hcmd->set_rxon_chain)
3015 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3016
3017 priv->staging_rxon.assoc_id = 0;
3018
3019 if (vif->bss_conf.assoc_capability &
3020 WLAN_CAPABILITY_SHORT_PREAMBLE)
3021 priv->staging_rxon.flags |=
3022 RXON_FLG_SHORT_PREAMBLE_MSK;
3023 else
3024 priv->staging_rxon.flags &=
3025 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3026
3027 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
3028 if (vif->bss_conf.assoc_capability &
3029 WLAN_CAPABILITY_SHORT_SLOT_TIME)
3030 priv->staging_rxon.flags |=
3031 RXON_FLG_SHORT_SLOT_MSK;
3032 else
3033 priv->staging_rxon.flags &=
3034 ~RXON_FLG_SHORT_SLOT_MSK;
3035
3036 if (vif->type == NL80211_IFTYPE_ADHOC)
3037 priv->staging_rxon.flags &=
3038 ~RXON_FLG_SHORT_SLOT_MSK;
3039 }
3040 /* restore RXON assoc */
3041 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
3042 iwlcore_commit_rxon(priv);
3043 }
3044 iwl_send_beacon_cmd(priv);
3045
3046 /* FIXME - we need to add code here to detect a totally new
3047 * configuration, reset the AP, unassoc, rxon timing, assoc,
3048 * clear sta table, add BCAST sta... */
3049 }
3050
3051 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
3052 struct ieee80211_vif *vif,
3053 struct ieee80211_key_conf *keyconf,
3054 struct ieee80211_sta *sta,
3055 u32 iv32, u16 *phase1key)
3056 {
3057
3058 struct iwl_priv *priv = hw->priv;
3059 IWL_DEBUG_MAC80211(priv, "enter\n");
3060
3061 iwl_update_tkip_key(priv, keyconf, sta,
3062 iv32, phase1key);
3063
3064 IWL_DEBUG_MAC80211(priv, "leave\n");
3065 }
3066
3067 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3068 struct ieee80211_vif *vif,
3069 struct ieee80211_sta *sta,
3070 struct ieee80211_key_conf *key)
3071 {
3072 struct iwl_priv *priv = hw->priv;
3073 int ret;
3074 u8 sta_id;
3075 bool is_default_wep_key = false;
3076
3077 IWL_DEBUG_MAC80211(priv, "enter\n");
3078
3079 if (priv->cfg->mod_params->sw_crypto) {
3080 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3081 return -EOPNOTSUPP;
3082 }
3083
3084 sta_id = iwl_sta_id_or_broadcast(priv, sta);
3085 if (sta_id == IWL_INVALID_STATION)
3086 return -EINVAL;
3087
3088 mutex_lock(&priv->mutex);
3089 iwl_scan_cancel_timeout(priv, 100);
3090
3091 /*
3092 * If we are getting WEP group key and we didn't receive any key mapping
3093 * so far, we are in legacy wep mode (group key only), otherwise we are
3094 * in 1X mode.
3095 * In legacy wep mode, we use another host command to the uCode.
3096 */
3097 if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
3098 if (cmd == SET_KEY)
3099 is_default_wep_key = !priv->key_mapping_key;
3100 else
3101 is_default_wep_key =
3102 (key->hw_key_idx == HW_KEY_DEFAULT);
3103 }
3104
3105 switch (cmd) {
3106 case SET_KEY:
3107 if (is_default_wep_key)
3108 ret = iwl_set_default_wep_key(priv, key);
3109 else
3110 ret = iwl_set_dynamic_key(priv, key, sta_id);
3111
3112 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3113 break;
3114 case DISABLE_KEY:
3115 if (is_default_wep_key)
3116 ret = iwl_remove_default_wep_key(priv, key);
3117 else
3118 ret = iwl_remove_dynamic_key(priv, key, sta_id);
3119
3120 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3121 break;
3122 default:
3123 ret = -EINVAL;
3124 }
3125
3126 mutex_unlock(&priv->mutex);
3127 IWL_DEBUG_MAC80211(priv, "leave\n");
3128
3129 return ret;
3130 }
3131
3132 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
3133 struct ieee80211_vif *vif,
3134 enum ieee80211_ampdu_mlme_action action,
3135 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3136 {
3137 struct iwl_priv *priv = hw->priv;
3138 int ret;
3139
3140 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3141 sta->addr, tid);
3142
3143 if (!(priv->cfg->sku & IWL_SKU_N))
3144 return -EACCES;
3145
3146 switch (action) {
3147 case IEEE80211_AMPDU_RX_START:
3148 IWL_DEBUG_HT(priv, "start Rx\n");
3149 return iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3150 case IEEE80211_AMPDU_RX_STOP:
3151 IWL_DEBUG_HT(priv, "stop Rx\n");
3152 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3153 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3154 return 0;
3155 else
3156 return ret;
3157 case IEEE80211_AMPDU_TX_START:
3158 IWL_DEBUG_HT(priv, "start Tx\n");
3159 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3160 if (ret == 0) {
3161 priv->_agn.agg_tids_count++;
3162 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3163 priv->_agn.agg_tids_count);
3164 }
3165 return ret;
3166 case IEEE80211_AMPDU_TX_STOP:
3167 IWL_DEBUG_HT(priv, "stop Tx\n");
3168 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3169 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3170 priv->_agn.agg_tids_count--;
3171 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3172 priv->_agn.agg_tids_count);
3173 }
3174 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3175 return 0;
3176 else
3177 return ret;
3178 case IEEE80211_AMPDU_TX_OPERATIONAL:
3179 /* do nothing */
3180 return -EOPNOTSUPP;
3181 default:
3182 IWL_DEBUG_HT(priv, "unknown\n");
3183 return -EINVAL;
3184 break;
3185 }
3186 return 0;
3187 }
3188
3189 static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3190 struct ieee80211_vif *vif,
3191 enum sta_notify_cmd cmd,
3192 struct ieee80211_sta *sta)
3193 {
3194 struct iwl_priv *priv = hw->priv;
3195 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3196 int sta_id;
3197
3198 switch (cmd) {
3199 case STA_NOTIFY_SLEEP:
3200 WARN_ON(!sta_priv->client);
3201 sta_priv->asleep = true;
3202 if (atomic_read(&sta_priv->pending_frames) > 0)
3203 ieee80211_sta_block_awake(hw, sta, true);
3204 break;
3205 case STA_NOTIFY_AWAKE:
3206 WARN_ON(!sta_priv->client);
3207 if (!sta_priv->asleep)
3208 break;
3209 sta_priv->asleep = false;
3210 sta_id = iwl_sta_id(sta);
3211 if (sta_id != IWL_INVALID_STATION)
3212 iwl_sta_modify_ps_wake(priv, sta_id);
3213 break;
3214 default:
3215 break;
3216 }
3217 }
3218
3219 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3220 struct ieee80211_vif *vif,
3221 struct ieee80211_sta *sta)
3222 {
3223 struct iwl_priv *priv = hw->priv;
3224 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3225 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3226 int ret;
3227 u8 sta_id;
3228
3229 sta_priv->common.sta_id = IWL_INVALID_STATION;
3230
3231 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3232 sta->addr);
3233
3234 atomic_set(&sta_priv->pending_frames, 0);
3235 if (vif->type == NL80211_IFTYPE_AP)
3236 sta_priv->client = true;
3237
3238 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3239 &sta_id);
3240 if (ret) {
3241 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3242 sta->addr, ret);
3243 /* Should we return success if return code is EEXIST ? */
3244 return ret;
3245 }
3246
3247 sta_priv->common.sta_id = sta_id;
3248
3249 /* Initialize rate scaling */
3250 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3251 sta->addr);
3252 iwl_rs_rate_init(priv, sta, sta_id);
3253
3254 return 0;
3255 }
3256
3257 /*****************************************************************************
3258 *
3259 * sysfs attributes
3260 *
3261 *****************************************************************************/
3262
3263 #ifdef CONFIG_IWLWIFI_DEBUG
3264
3265 /*
3266 * The following adds a new attribute to the sysfs representation
3267 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
3268 * used for controlling the debug level.
3269 *
3270 * See the level definitions in iwl for details.
3271 *
3272 * The debug_level being managed using sysfs below is a per device debug
3273 * level that is used instead of the global debug level if it (the per
3274 * device debug level) is set.
3275 */
3276 static ssize_t show_debug_level(struct device *d,
3277 struct device_attribute *attr, char *buf)
3278 {
3279 struct iwl_priv *priv = dev_get_drvdata(d);
3280 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
3281 }
3282 static ssize_t store_debug_level(struct device *d,
3283 struct device_attribute *attr,
3284 const char *buf, size_t count)
3285 {
3286 struct iwl_priv *priv = dev_get_drvdata(d);
3287 unsigned long val;
3288 int ret;
3289
3290 ret = strict_strtoul(buf, 0, &val);
3291 if (ret)
3292 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
3293 else {
3294 priv->debug_level = val;
3295 if (iwl_alloc_traffic_mem(priv))
3296 IWL_ERR(priv,
3297 "Not enough memory to generate traffic log\n");
3298 }
3299 return strnlen(buf, count);
3300 }
3301
3302 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3303 show_debug_level, store_debug_level);
3304
3305
3306 #endif /* CONFIG_IWLWIFI_DEBUG */
3307
3308
3309 static ssize_t show_temperature(struct device *d,
3310 struct device_attribute *attr, char *buf)
3311 {
3312 struct iwl_priv *priv = dev_get_drvdata(d);
3313
3314 if (!iwl_is_alive(priv))
3315 return -EAGAIN;
3316
3317 return sprintf(buf, "%d\n", priv->temperature);
3318 }
3319
3320 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3321
3322 static ssize_t show_tx_power(struct device *d,
3323 struct device_attribute *attr, char *buf)
3324 {
3325 struct iwl_priv *priv = dev_get_drvdata(d);
3326
3327 if (!iwl_is_ready_rf(priv))
3328 return sprintf(buf, "off\n");
3329 else
3330 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
3331 }
3332
3333 static ssize_t store_tx_power(struct device *d,
3334 struct device_attribute *attr,
3335 const char *buf, size_t count)
3336 {
3337 struct iwl_priv *priv = dev_get_drvdata(d);
3338 unsigned long val;
3339 int ret;
3340
3341 ret = strict_strtoul(buf, 10, &val);
3342 if (ret)
3343 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
3344 else {
3345 ret = iwl_set_tx_power(priv, val, false);
3346 if (ret)
3347 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
3348 ret);
3349 else
3350 ret = count;
3351 }
3352 return ret;
3353 }
3354
3355 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3356
3357 static ssize_t show_rts_ht_protection(struct device *d,
3358 struct device_attribute *attr, char *buf)
3359 {
3360 struct iwl_priv *priv = dev_get_drvdata(d);
3361
3362 return sprintf(buf, "%s\n",
3363 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3364 }
3365
3366 static ssize_t store_rts_ht_protection(struct device *d,
3367 struct device_attribute *attr,
3368 const char *buf, size_t count)
3369 {
3370 struct iwl_priv *priv = dev_get_drvdata(d);
3371 unsigned long val;
3372 int ret;
3373
3374 ret = strict_strtoul(buf, 10, &val);
3375 if (ret)
3376 IWL_INFO(priv, "Input is not in decimal form.\n");
3377 else {
3378 if (!iwl_is_associated(priv))
3379 priv->cfg->use_rts_for_ht = val ? true : false;
3380 else
3381 IWL_ERR(priv, "Sta associated with AP - "
3382 "Change protection mechanism is not allowed\n");
3383 ret = count;
3384 }
3385 return ret;
3386 }
3387
3388 static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3389 show_rts_ht_protection, store_rts_ht_protection);
3390
3391
3392 /*****************************************************************************
3393 *
3394 * driver setup and teardown
3395 *
3396 *****************************************************************************/
3397
3398 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3399 {
3400 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3401
3402 init_waitqueue_head(&priv->wait_command_queue);
3403
3404 INIT_WORK(&priv->restart, iwl_bg_restart);
3405 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3406 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3407 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3408 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3409 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3410
3411 iwl_setup_scan_deferred_work(priv);
3412
3413 if (priv->cfg->ops->lib->setup_deferred_work)
3414 priv->cfg->ops->lib->setup_deferred_work(priv);
3415
3416 init_timer(&priv->statistics_periodic);
3417 priv->statistics_periodic.data = (unsigned long)priv;
3418 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3419
3420 init_timer(&priv->ucode_trace);
3421 priv->ucode_trace.data = (unsigned long)priv;
3422 priv->ucode_trace.function = iwl_bg_ucode_trace;
3423
3424 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3425 init_timer(&priv->monitor_recover);
3426 priv->monitor_recover.data = (unsigned long)priv;
3427 priv->monitor_recover.function =
3428 priv->cfg->ops->lib->recover_from_tx_stall;
3429 }
3430
3431 if (!priv->cfg->use_isr_legacy)
3432 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3433 iwl_irq_tasklet, (unsigned long)priv);
3434 else
3435 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3436 iwl_irq_tasklet_legacy, (unsigned long)priv);
3437 }
3438
3439 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3440 {
3441 if (priv->cfg->ops->lib->cancel_deferred_work)
3442 priv->cfg->ops->lib->cancel_deferred_work(priv);
3443
3444 cancel_delayed_work_sync(&priv->init_alive_start);
3445 cancel_delayed_work(&priv->scan_check);
3446 cancel_work_sync(&priv->start_internal_scan);
3447 cancel_delayed_work(&priv->alive_start);
3448 cancel_work_sync(&priv->beacon_update);
3449 del_timer_sync(&priv->statistics_periodic);
3450 del_timer_sync(&priv->ucode_trace);
3451 if (priv->cfg->ops->lib->recover_from_tx_stall)
3452 del_timer_sync(&priv->monitor_recover);
3453 }
3454
3455 static void iwl_init_hw_rates(struct iwl_priv *priv,
3456 struct ieee80211_rate *rates)
3457 {
3458 int i;
3459
3460 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3461 rates[i].bitrate = iwl_rates[i].ieee * 5;
3462 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3463 rates[i].hw_value_short = i;
3464 rates[i].flags = 0;
3465 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3466 /*
3467 * If CCK != 1M then set short preamble rate flag.
3468 */
3469 rates[i].flags |=
3470 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3471 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3472 }
3473 }
3474 }
3475
3476 static int iwl_init_drv(struct iwl_priv *priv)
3477 {
3478 int ret;
3479
3480 priv->ibss_beacon = NULL;
3481
3482 spin_lock_init(&priv->sta_lock);
3483 spin_lock_init(&priv->hcmd_lock);
3484
3485 INIT_LIST_HEAD(&priv->free_frames);
3486
3487 mutex_init(&priv->mutex);
3488 mutex_init(&priv->sync_cmd_mutex);
3489
3490 priv->ieee_channels = NULL;
3491 priv->ieee_rates = NULL;
3492 priv->band = IEEE80211_BAND_2GHZ;
3493
3494 priv->iw_mode = NL80211_IFTYPE_STATION;
3495 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3496 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3497 priv->_agn.agg_tids_count = 0;
3498
3499 /* initialize force reset */
3500 priv->force_reset[IWL_RF_RESET].reset_duration =
3501 IWL_DELAY_NEXT_FORCE_RF_RESET;
3502 priv->force_reset[IWL_FW_RESET].reset_duration =
3503 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3504
3505 /* Choose which receivers/antennas to use */
3506 if (priv->cfg->ops->hcmd->set_rxon_chain)
3507 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3508
3509 iwl_init_scan_params(priv);
3510
3511 /* Set the tx_power_user_lmt to the lowest power level
3512 * this value will get overwritten by channel max power avg
3513 * from eeprom */
3514 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3515
3516 ret = iwl_init_channel_map(priv);
3517 if (ret) {
3518 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3519 goto err;
3520 }
3521
3522 ret = iwlcore_init_geos(priv);
3523 if (ret) {
3524 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3525 goto err_free_channel_map;
3526 }
3527 iwl_init_hw_rates(priv, priv->ieee_rates);
3528
3529 return 0;
3530
3531 err_free_channel_map:
3532 iwl_free_channel_map(priv);
3533 err:
3534 return ret;
3535 }
3536
3537 static void iwl_uninit_drv(struct iwl_priv *priv)
3538 {
3539 iwl_calib_free_results(priv);
3540 iwlcore_free_geos(priv);
3541 iwl_free_channel_map(priv);
3542 kfree(priv->scan_cmd);
3543 }
3544
3545 static struct attribute *iwl_sysfs_entries[] = {
3546 &dev_attr_temperature.attr,
3547 &dev_attr_tx_power.attr,
3548 &dev_attr_rts_ht_protection.attr,
3549 #ifdef CONFIG_IWLWIFI_DEBUG
3550 &dev_attr_debug_level.attr,
3551 #endif
3552 NULL
3553 };
3554
3555 static struct attribute_group iwl_attribute_group = {
3556 .name = NULL, /* put in device directory */
3557 .attrs = iwl_sysfs_entries,
3558 };
3559
3560 static struct ieee80211_ops iwl_hw_ops = {
3561 .tx = iwl_mac_tx,
3562 .start = iwl_mac_start,
3563 .stop = iwl_mac_stop,
3564 .add_interface = iwl_mac_add_interface,
3565 .remove_interface = iwl_mac_remove_interface,
3566 .config = iwl_mac_config,
3567 .configure_filter = iwl_configure_filter,
3568 .set_key = iwl_mac_set_key,
3569 .update_tkip_key = iwl_mac_update_tkip_key,
3570 .conf_tx = iwl_mac_conf_tx,
3571 .reset_tsf = iwl_mac_reset_tsf,
3572 .bss_info_changed = iwl_bss_info_changed,
3573 .ampdu_action = iwl_mac_ampdu_action,
3574 .hw_scan = iwl_mac_hw_scan,
3575 .sta_notify = iwl_mac_sta_notify,
3576 .sta_add = iwlagn_mac_sta_add,
3577 .sta_remove = iwl_mac_sta_remove,
3578 };
3579
3580 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3581 {
3582 int err = 0;
3583 struct iwl_priv *priv;
3584 struct ieee80211_hw *hw;
3585 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3586 unsigned long flags;
3587 u16 pci_cmd;
3588
3589 /************************
3590 * 1. Allocating HW data
3591 ************************/
3592
3593 /* Disabling hardware scan means that mac80211 will perform scans
3594 * "the hard way", rather than using device's scan. */
3595 if (cfg->mod_params->disable_hw_scan) {
3596 if (iwl_debug_level & IWL_DL_INFO)
3597 dev_printk(KERN_DEBUG, &(pdev->dev),
3598 "Disabling hw_scan\n");
3599 iwl_hw_ops.hw_scan = NULL;
3600 }
3601
3602 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
3603 if (!hw) {
3604 err = -ENOMEM;
3605 goto out;
3606 }
3607 priv = hw->priv;
3608 /* At this point both hw and priv are allocated. */
3609
3610 SET_IEEE80211_DEV(hw, &pdev->dev);
3611
3612 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3613 priv->cfg = cfg;
3614 priv->pci_dev = pdev;
3615 priv->inta_mask = CSR_INI_SET_MASK;
3616
3617 #ifdef CONFIG_IWLWIFI_DEBUG
3618 atomic_set(&priv->restrict_refcnt, 0);
3619 #endif
3620 if (iwl_alloc_traffic_mem(priv))
3621 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3622
3623 /**************************
3624 * 2. Initializing PCI bus
3625 **************************/
3626 if (pci_enable_device(pdev)) {
3627 err = -ENODEV;
3628 goto out_ieee80211_free_hw;
3629 }
3630
3631 pci_set_master(pdev);
3632
3633 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3634 if (!err)
3635 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3636 if (err) {
3637 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3638 if (!err)
3639 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3640 /* both attempts failed: */
3641 if (err) {
3642 IWL_WARN(priv, "No suitable DMA available.\n");
3643 goto out_pci_disable_device;
3644 }
3645 }
3646
3647 err = pci_request_regions(pdev, DRV_NAME);
3648 if (err)
3649 goto out_pci_disable_device;
3650
3651 pci_set_drvdata(pdev, priv);
3652
3653
3654 /***********************
3655 * 3. Read REV register
3656 ***********************/
3657 priv->hw_base = pci_iomap(pdev, 0, 0);
3658 if (!priv->hw_base) {
3659 err = -ENODEV;
3660 goto out_pci_release_regions;
3661 }
3662
3663 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3664 (unsigned long long) pci_resource_len(pdev, 0));
3665 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3666
3667 /* these spin locks will be used in apm_ops.init and EEPROM access
3668 * we should init now
3669 */
3670 spin_lock_init(&priv->reg_lock);
3671 spin_lock_init(&priv->lock);
3672
3673 /*
3674 * stop and reset the on-board processor just in case it is in a
3675 * strange state ... like being left stranded by a primary kernel
3676 * and this is now the kdump kernel trying to start up
3677 */
3678 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3679
3680 iwl_hw_detect(priv);
3681 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3682 priv->cfg->name, priv->hw_rev);
3683
3684 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3685 * PCI Tx retries from interfering with C3 CPU state */
3686 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3687
3688 iwl_prepare_card_hw(priv);
3689 if (!priv->hw_ready) {
3690 IWL_WARN(priv, "Failed, HW not ready\n");
3691 goto out_iounmap;
3692 }
3693
3694 /*****************
3695 * 4. Read EEPROM
3696 *****************/
3697 /* Read the EEPROM */
3698 err = iwl_eeprom_init(priv);
3699 if (err) {
3700 IWL_ERR(priv, "Unable to init EEPROM\n");
3701 goto out_iounmap;
3702 }
3703 err = iwl_eeprom_check_version(priv);
3704 if (err)
3705 goto out_free_eeprom;
3706
3707 /* extract MAC Address */
3708 iwl_eeprom_get_mac(priv, priv->mac_addr);
3709 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
3710 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3711
3712 /************************
3713 * 5. Setup HW constants
3714 ************************/
3715 if (iwl_set_hw_params(priv)) {
3716 IWL_ERR(priv, "failed to set hw parameters\n");
3717 goto out_free_eeprom;
3718 }
3719
3720 /*******************
3721 * 6. Setup priv
3722 *******************/
3723
3724 err = iwl_init_drv(priv);
3725 if (err)
3726 goto out_free_eeprom;
3727 /* At this point both hw and priv are initialized. */
3728
3729 /********************
3730 * 7. Setup services
3731 ********************/
3732 spin_lock_irqsave(&priv->lock, flags);
3733 iwl_disable_interrupts(priv);
3734 spin_unlock_irqrestore(&priv->lock, flags);
3735
3736 pci_enable_msi(priv->pci_dev);
3737
3738 iwl_alloc_isr_ict(priv);
3739 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3740 IRQF_SHARED, DRV_NAME, priv);
3741 if (err) {
3742 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3743 goto out_disable_msi;
3744 }
3745 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
3746 if (err) {
3747 IWL_ERR(priv, "failed to create sysfs device attributes\n");
3748 goto out_free_irq;
3749 }
3750
3751 iwl_setup_deferred_work(priv);
3752 iwl_setup_rx_handlers(priv);
3753
3754 /*********************************************
3755 * 8. Enable interrupts and read RFKILL state
3756 *********************************************/
3757
3758 /* enable interrupts if needed: hw bug w/a */
3759 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3760 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3761 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3762 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3763 }
3764
3765 iwl_enable_interrupts(priv);
3766
3767 /* If platform's RF_KILL switch is NOT set to KILL */
3768 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3769 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3770 else
3771 set_bit(STATUS_RF_KILL_HW, &priv->status);
3772
3773 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3774 test_bit(STATUS_RF_KILL_HW, &priv->status));
3775
3776 iwl_power_initialize(priv);
3777 iwl_tt_initialize(priv);
3778
3779 init_completion(&priv->_agn.firmware_loading_complete);
3780
3781 err = iwl_request_firmware(priv, true);
3782 if (err)
3783 goto out_remove_sysfs;
3784
3785 return 0;
3786
3787 out_remove_sysfs:
3788 destroy_workqueue(priv->workqueue);
3789 priv->workqueue = NULL;
3790 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3791 out_free_irq:
3792 free_irq(priv->pci_dev->irq, priv);
3793 iwl_free_isr_ict(priv);
3794 out_disable_msi:
3795 pci_disable_msi(priv->pci_dev);
3796 iwl_uninit_drv(priv);
3797 out_free_eeprom:
3798 iwl_eeprom_free(priv);
3799 out_iounmap:
3800 pci_iounmap(pdev, priv->hw_base);
3801 out_pci_release_regions:
3802 pci_set_drvdata(pdev, NULL);
3803 pci_release_regions(pdev);
3804 out_pci_disable_device:
3805 pci_disable_device(pdev);
3806 out_ieee80211_free_hw:
3807 iwl_free_traffic_mem(priv);
3808 ieee80211_free_hw(priv->hw);
3809 out:
3810 return err;
3811 }
3812
3813 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3814 {
3815 struct iwl_priv *priv = pci_get_drvdata(pdev);
3816 unsigned long flags;
3817
3818 if (!priv)
3819 return;
3820
3821 wait_for_completion(&priv->_agn.firmware_loading_complete);
3822
3823 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3824
3825 iwl_dbgfs_unregister(priv);
3826 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3827
3828 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3829 * to be called and iwl_down since we are removing the device
3830 * we need to set STATUS_EXIT_PENDING bit.
3831 */
3832 set_bit(STATUS_EXIT_PENDING, &priv->status);
3833 if (priv->mac80211_registered) {
3834 ieee80211_unregister_hw(priv->hw);
3835 priv->mac80211_registered = 0;
3836 } else {
3837 iwl_down(priv);
3838 }
3839
3840 /*
3841 * Make sure device is reset to low power before unloading driver.
3842 * This may be redundant with iwl_down(), but there are paths to
3843 * run iwl_down() without calling apm_ops.stop(), and there are
3844 * paths to avoid running iwl_down() at all before leaving driver.
3845 * This (inexpensive) call *makes sure* device is reset.
3846 */
3847 priv->cfg->ops->lib->apm_ops.stop(priv);
3848
3849 iwl_tt_exit(priv);
3850
3851 /* make sure we flush any pending irq or
3852 * tasklet for the driver
3853 */
3854 spin_lock_irqsave(&priv->lock, flags);
3855 iwl_disable_interrupts(priv);
3856 spin_unlock_irqrestore(&priv->lock, flags);
3857
3858 iwl_synchronize_irq(priv);
3859
3860 iwl_dealloc_ucode_pci(priv);
3861
3862 if (priv->rxq.bd)
3863 iwlagn_rx_queue_free(priv, &priv->rxq);
3864 iwlagn_hw_txq_ctx_free(priv);
3865
3866 iwl_eeprom_free(priv);
3867
3868
3869 /*netif_stop_queue(dev); */
3870 flush_workqueue(priv->workqueue);
3871
3872 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3873 * priv->workqueue... so we can't take down the workqueue
3874 * until now... */
3875 destroy_workqueue(priv->workqueue);
3876 priv->workqueue = NULL;
3877 iwl_free_traffic_mem(priv);
3878
3879 free_irq(priv->pci_dev->irq, priv);
3880 pci_disable_msi(priv->pci_dev);
3881 pci_iounmap(pdev, priv->hw_base);
3882 pci_release_regions(pdev);
3883 pci_disable_device(pdev);
3884 pci_set_drvdata(pdev, NULL);
3885
3886 iwl_uninit_drv(priv);
3887
3888 iwl_free_isr_ict(priv);
3889
3890 if (priv->ibss_beacon)
3891 dev_kfree_skb(priv->ibss_beacon);
3892
3893 ieee80211_free_hw(priv->hw);
3894 }
3895
3896
3897 /*****************************************************************************
3898 *
3899 * driver and module entry point
3900 *
3901 *****************************************************************************/
3902
3903 /* Hardware specific file defines the PCI IDs table for that hardware module */
3904 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
3905 #ifdef CONFIG_IWL4965
3906 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3907 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
3908 #endif /* CONFIG_IWL4965 */
3909 #ifdef CONFIG_IWL5000
3910 /* 5100 Series WiFi */
3911 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3912 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3913 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3914 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3915 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3916 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3917 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3918 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3919 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3920 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3921 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3922 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3923 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3924 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3925 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3926 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3927 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3928 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3929 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3930 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3931 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3932 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3933 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3934 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3935
3936 /* 5300 Series WiFi */
3937 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3938 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3939 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3940 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3941 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3942 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3943 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3944 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3945 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3946 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3947 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3948 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3949
3950 /* 5350 Series WiFi/WiMax */
3951 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3952 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3953 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3954
3955 /* 5150 Series Wifi/WiMax */
3956 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3957 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3958 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3959 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3960 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3961 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3962
3963 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3964 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3965 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3966 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
3967
3968 /* 6x00 Series */
3969 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3970 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3971 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3972 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3973 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3974 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3975 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3976 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3977 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3978 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3979
3980 /* 6x00 Series Gen2a */
3981 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
3982 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
3983 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
3984
3985 /* 6x50 WiFi/WiMax Series */
3986 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3987 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3988 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3989 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
3990 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3991 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3992
3993 /* 1000 Series WiFi */
3994 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3995 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3996 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3997 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3998 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3999 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4000 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4001 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4002 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4003 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4004 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4005 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4006 #endif /* CONFIG_IWL5000 */
4007
4008 {0}
4009 };
4010 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4011
4012 static struct pci_driver iwl_driver = {
4013 .name = DRV_NAME,
4014 .id_table = iwl_hw_card_ids,
4015 .probe = iwl_pci_probe,
4016 .remove = __devexit_p(iwl_pci_remove),
4017 #ifdef CONFIG_PM
4018 .suspend = iwl_pci_suspend,
4019 .resume = iwl_pci_resume,
4020 #endif
4021 };
4022
4023 static int __init iwl_init(void)
4024 {
4025
4026 int ret;
4027 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4028 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
4029
4030 ret = iwlagn_rate_control_register();
4031 if (ret) {
4032 printk(KERN_ERR DRV_NAME
4033 "Unable to register rate control algorithm: %d\n", ret);
4034 return ret;
4035 }
4036
4037 ret = pci_register_driver(&iwl_driver);
4038 if (ret) {
4039 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
4040 goto error_register;
4041 }
4042
4043 return ret;
4044
4045 error_register:
4046 iwlagn_rate_control_unregister();
4047 return ret;
4048 }
4049
4050 static void __exit iwl_exit(void)
4051 {
4052 pci_unregister_driver(&iwl_driver);
4053 iwlagn_rate_control_unregister();
4054 }
4055
4056 module_exit(iwl_exit);
4057 module_init(iwl_init);
4058
4059 #ifdef CONFIG_IWLWIFI_DEBUG
4060 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4061 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4062 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4063 MODULE_PARM_DESC(debug, "debug output mask");
4064 #endif
4065
4066 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4067 MODULE_PARM_DESC(swcrypto50,
4068 "using crypto in software (default 0 [hardware]) (deprecated)");
4069 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4070 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4071 module_param_named(queues_num50,
4072 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4073 MODULE_PARM_DESC(queues_num50,
4074 "number of hw queues in 50xx series (deprecated)");
4075 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4076 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4077 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4078 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4079 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4080 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4081 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4082 int, S_IRUGO);
4083 MODULE_PARM_DESC(amsdu_size_8K50,
4084 "enable 8K amsdu size in 50XX series (deprecated)");
4085 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4086 int, S_IRUGO);
4087 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4088 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4089 MODULE_PARM_DESC(fw_restart50,
4090 "restart firmware in case of error (deprecated)");
4091 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4092 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4093 module_param_named(
4094 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4095 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4096
4097 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4098 S_IRUGO);
4099 MODULE_PARM_DESC(ucode_alternative,
4100 "specify ucode alternative to use from ucode file");
kernel-based virtual machine