include/asm-arm/arch-ixp4xx/io.h

   1 /*
   2  * linux/include/asm-arm/arch-ixp4xx/io.h
   3  *
   4  * Author: Deepak Saxena <dsaxena@plexity.net>
   5  *
   6  * Copyright (C) 2002-2005  MontaVista Software, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ASM_ARM_ARCH_IO_H
  14 #define __ASM_ARM_ARCH_IO_H
  15
  16 #include <linux/bitops.h>
  17
  18 #include <asm/hardware.h>
  19
  20 #define IO_SPACE_LIMIT 0xffff0000
  21
  22 extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
  23 extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  24
  25
  26 /*
  27  * IXP4xx provides two methods of accessing PCI memory space:
  28  *
  29  * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
  30  *    To access PCI via this space, we simply ioremap() the BAR
  31  *    into the kernel and we can use the standard read[bwl]/write[bwl]
  32  *    macros. This is the preffered method due to speed but it
  33  *    limits the system to just 64MB of PCI memory. This can be
  34  *    problamatic if using video cards and other memory-heavy
  35  *    targets.
  36  *
  37  * 2) If > 64MB of memory space is required, the IXP4xx can be configured
  38  *    to use indirect registers to access PCI (as we do below for I/O
  39  *    transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
  40  *    of memory on the bus. The disadvantage of this is that every
  41  *    PCI access requires three local register accesses plus a spinlock,
  42  *    but in some cases the performance hit is acceptable. In addition,
  43  *    you cannot mmap() PCI devices in this case.
  44  *
  45  */
  46 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
  47
  48 #define __mem_pci(a)            (a)
  49
  50 #else
  51
  52 #include <linux/mm.h>
  53
  54 /*
  55  * In the case of using indirect PCI, we simply return the actual PCI
  56  * address and our read/write implementation use that to drive the
  57  * access registers. If something outside of PCI is ioremap'd, we
  58  * fallback to the default.
  59  */
  60 static inline void __iomem *
  61 __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
  62 {
  63         if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
  64                 return __arm_ioremap(addr, size, mtype);
  65
  66         return (void __iomem *)addr;
  67 }
  68
  69 static inline void
  70 __ixp4xx_iounmap(void __iomem *addr)
  71 {
  72         if ((__force u32)addr >= VMALLOC_START)
  73                 __iounmap(addr);
  74 }
  75
  76 #define __arch_ioremap(a, s, f)         __ixp4xx_ioremap(a, s, f)
  77 #define __arch_iounmap(a)               __ixp4xx_iounmap(a)
  78
  79 #define writeb(v, p)                    __ixp4xx_writeb(v, p)
  80 #define writew(v, p)                    __ixp4xx_writew(v, p)
  81 #define writel(v, p)                    __ixp4xx_writel(v, p)
  82
  83 #define writesb(p, v, l)                __ixp4xx_writesb(p, v, l)
  84 #define writesw(p, v, l)                __ixp4xx_writesw(p, v, l)
  85 #define writesl(p, v, l)                __ixp4xx_writesl(p, v, l)
  86
  87 #define readb(p)                        __ixp4xx_readb(p)
  88 #define readw(p)                        __ixp4xx_readw(p)
  89 #define readl(p)                        __ixp4xx_readl(p)
  90
  91 #define readsb(p, v, l)                 __ixp4xx_readsb(p, v, l)
  92 #define readsw(p, v, l)                 __ixp4xx_readsw(p, v, l)
  93 #define readsl(p, v, l)                 __ixp4xx_readsl(p, v, l)
  94
  95 static inline void
  96 __ixp4xx_writeb(u8 value, volatile void __iomem *p)
  97 {
  98         u32 addr = (u32)p;
  99         u32 n, byte_enables, data;
 100
 101         if (addr >= VMALLOC_START) {
 102                 __raw_writeb(value, addr);
 103                 return;
 104         }
 105
 106         n = addr % 4;
 107         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 108         data = value << (8*n);
 109         ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
 110 }
 111
 112 static inline void
 113 __ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
 114 {
 115         while (count--)
 116                 writeb(*vaddr++, bus_addr);
 117 }
 118
 119 static inline void
 120 __ixp4xx_writew(u16 value, volatile void __iomem *p)
 121 {
 122         u32 addr = (u32)p;
 123         u32 n, byte_enables, data;
 124
 125         if (addr >= VMALLOC_START) {
 126                 __raw_writew(value, addr);
 127                 return;
 128         }
 129
 130         n = addr % 4;
 131         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 132         data = value << (8*n);
 133         ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
 134 }
 135
 136 static inline void
 137 __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
 138 {
 139         while (count--)
 140                 writew(*vaddr++, bus_addr);
 141 }
 142
 143 static inline void
 144 __ixp4xx_writel(u32 value, volatile void __iomem *p)
 145 {
 146         u32 addr = (__force u32)p;
 147         if (addr >= VMALLOC_START) {
 148                 __raw_writel(value, p);
 149                 return;
 150         }
 151
 152         ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
 153 }
 154
 155 static inline void
 156 __ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
 157 {
 158         while (count--)
 159                 writel(*vaddr++, bus_addr);
 160 }
 161
 162 static inline unsigned char
 163 __ixp4xx_readb(const volatile void __iomem *p)
 164 {
 165         u32 addr = (u32)p;
 166         u32 n, byte_enables, data;
 167
 168         if (addr >= VMALLOC_START)
 169                 return __raw_readb(addr);
 170
 171         n = addr % 4;
 172         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 173         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
 174                 return 0xff;
 175
 176         return data >> (8*n);
 177 }
 178
 179 static inline void
 180 __ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
 181 {
 182         while (count--)
 183                 *vaddr++ = readb(bus_addr);
 184 }
 185
 186 static inline unsigned short
 187 __ixp4xx_readw(const volatile void __iomem *p)
 188 {
 189         u32 addr = (u32)p;
 190         u32 n, byte_enables, data;
 191
 192         if (addr >= VMALLOC_START)
 193                 return __raw_readw(addr);
 194
 195         n = addr % 4;
 196         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 197         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
 198                 return 0xffff;
 199
 200         return data>>(8*n);
 201 }
 202
 203 static inline void
 204 __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
 205 {
 206         while (count--)
 207                 *vaddr++ = readw(bus_addr);
 208 }
 209
 210 static inline unsigned long
 211 __ixp4xx_readl(const volatile void __iomem *p)
 212 {
 213         u32 addr = (__force u32)p;
 214         u32 data;
 215
 216         if (addr >= VMALLOC_START)
 217                 return __raw_readl(p);
 218
 219         if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
 220                 return 0xffffffff;
 221
 222         return data;
 223 }
 224
 225 static inline void
 226 __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
 227 {
 228         while (count--)
 229                 *vaddr++ = readl(bus_addr);
 230 }
 231
 232
 233 /*
 234  * We can use the built-in functions b/c they end up calling writeb/readb
 235  */
 236 #define memset_io(c,v,l)                _memset_io((c),(v),(l))
 237 #define memcpy_fromio(a,c,l)            _memcpy_fromio((a),(c),(l))
 238 #define memcpy_toio(c,a,l)              _memcpy_toio((c),(a),(l))
 239
 240 #endif
 241
 242 #ifndef CONFIG_PCI
 243
 244 #define __io(v)         v
 245
 246 #else
 247
 248 /*
 249  * IXP4xx does not have a transparent cpu -> PCI I/O translation
 250  * window.  Instead, it has a set of registers that must be tweaked
 251  * with the proper byte lanes, command types, and address for the
 252  * transaction.  This means that we need to override the default
 253  * I/O functions.
 254  */
 255 #define outb(p, v)                      __ixp4xx_outb(p, v)
 256 #define outw(p, v)                      __ixp4xx_outw(p, v)
 257 #define outl(p, v)                      __ixp4xx_outl(p, v)
 258
 259 #define outsb(p, v, l)                  __ixp4xx_outsb(p, v, l)
 260 #define outsw(p, v, l)                  __ixp4xx_outsw(p, v, l)
 261 #define outsl(p, v, l)                  __ixp4xx_outsl(p, v, l)
 262
 263 #define inb(p)                          __ixp4xx_inb(p)
 264 #define inw(p)                          __ixp4xx_inw(p)
 265 #define inl(p)                          __ixp4xx_inl(p)
 266
 267 #define insb(p, v, l)                   __ixp4xx_insb(p, v, l)
 268 #define insw(p, v, l)                   __ixp4xx_insw(p, v, l)
 269 #define insl(p, v, l)                   __ixp4xx_insl(p, v, l)
 270
 271
 272 static inline void
 273 __ixp4xx_outb(u8 value, u32 addr)
 274 {
 275         u32 n, byte_enables, data;
 276         n = addr % 4;
 277         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 278         data = value << (8*n);
 279         ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 280 }
 281
 282 static inline void
 283 __ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
 284 {
 285         while (count--)
 286                 outb(*vaddr++, io_addr);
 287 }
 288
 289 static inline void
 290 __ixp4xx_outw(u16 value, u32 addr)
 291 {
 292         u32 n, byte_enables, data;
 293         n = addr % 4;
 294         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 295         data = value << (8*n);
 296         ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 297 }
 298
 299 static inline void
 300 __ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
 301 {
 302         while (count--)
 303                 outw(cpu_to_le16(*vaddr++), io_addr);
 304 }
 305
 306 static inline void
 307 __ixp4xx_outl(u32 value, u32 addr)
 308 {
 309         ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
 310 }
 311
 312 static inline void
 313 __ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
 314 {
 315         while (count--)
 316                 outl(*vaddr++, io_addr);
 317 }
 318
 319 static inline u8
 320 __ixp4xx_inb(u32 addr)
 321 {
 322         u32 n, byte_enables, data;
 323         n = addr % 4;
 324         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 325         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
 326                 return 0xff;
 327
 328         return data >> (8*n);
 329 }
 330
 331 static inline void
 332 __ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
 333 {
 334         while (count--)
 335                 *vaddr++ = inb(io_addr);
 336 }
 337
 338 static inline u16
 339 __ixp4xx_inw(u32 addr)
 340 {
 341         u32 n, byte_enables, data;
 342         n = addr % 4;
 343         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 344         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
 345                 return 0xffff;
 346
 347         return data>>(8*n);
 348 }
 349
 350 static inline void
 351 __ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
 352 {
 353         while (count--)
 354                 *vaddr++ = le16_to_cpu(inw(io_addr));
 355 }
 356
 357 static inline u32
 358 __ixp4xx_inl(u32 addr)
 359 {
 360         u32 data;
 361         if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
 362                 return 0xffffffff;
 363
 364         return data;
 365 }
 366
 367 static inline void
 368 __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
 369 {
 370         while (count--)
 371                 *vaddr++ = inl(io_addr);
 372 }
 373
 374 #define PIO_OFFSET      0x10000UL
 375 #define PIO_MASK        0x0ffffUL
 376
 377 #define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
 378                                         ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
 379 static inline unsigned int
 380 __ixp4xx_ioread8(const void __iomem *addr)
 381 {
 382         unsigned long port = (unsigned long __force)addr;
 383         if (__is_io_address(port))
 384                 return  (unsigned int)__ixp4xx_inb(port & PIO_MASK);
 385         else
 386 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 387                 return (unsigned int)__raw_readb(port);
 388 #else
 389                 return (unsigned int)__ixp4xx_readb(addr);
 390 #endif
 391 }
 392
 393 static inline void
 394 __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
 395 {
 396         unsigned long port = (unsigned long __force)addr;
 397         if (__is_io_address(port))
 398                 __ixp4xx_insb(port & PIO_MASK, vaddr, count);
 399         else
 400 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 401                 __raw_readsb(addr, vaddr, count);
 402 #else
 403                 __ixp4xx_readsb(addr, vaddr, count);
 404 #endif
 405 }
 406
 407 static inline unsigned int
 408 __ixp4xx_ioread16(const void __iomem *addr)
 409 {
 410         unsigned long port = (unsigned long __force)addr;
 411         if (__is_io_address(port))
 412                 return  (unsigned int)__ixp4xx_inw(port & PIO_MASK);
 413         else
 414 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 415                 return le16_to_cpu(__raw_readw((u32)port));
 416 #else
 417                 return (unsigned int)__ixp4xx_readw(addr);
 418 #endif
 419 }
 420
 421 static inline void
 422 __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
 423 {
 424         unsigned long port = (unsigned long __force)addr;
 425         if (__is_io_address(port))
 426                 __ixp4xx_insw(port & PIO_MASK, vaddr, count);
 427         else
 428 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 429                 __raw_readsw(addr, vaddr, count);
 430 #else
 431                 __ixp4xx_readsw(addr, vaddr, count);
 432 #endif
 433 }
 434
 435 static inline unsigned int
 436 __ixp4xx_ioread32(const void __iomem *addr)
 437 {
 438         unsigned long port = (unsigned long __force)addr;
 439         if (__is_io_address(port))
 440                 return  (unsigned int)__ixp4xx_inl(port & PIO_MASK);
 441         else {
 442 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 443                 return le32_to_cpu((__force __le32)__raw_readl(addr));
 444 #else
 445                 return (unsigned int)__ixp4xx_readl(addr);
 446 #endif
 447         }
 448 }
 449
 450 static inline void
 451 __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
 452 {
 453         unsigned long port = (unsigned long __force)addr;
 454         if (__is_io_address(port))
 455                 __ixp4xx_insl(port & PIO_MASK, vaddr, count);
 456         else
 457 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 458                 __raw_readsl(addr, vaddr, count);
 459 #else
 460                 __ixp4xx_readsl(addr, vaddr, count);
 461 #endif
 462 }
 463
 464 static inline void
 465 __ixp4xx_iowrite8(u8 value, void __iomem *addr)
 466 {
 467         unsigned long port = (unsigned long __force)addr;
 468         if (__is_io_address(port))
 469                 __ixp4xx_outb(value, port & PIO_MASK);
 470         else
 471 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 472                 __raw_writeb(value, port);
 473 #else
 474                 __ixp4xx_writeb(value, addr);
 475 #endif
 476 }
 477
 478 static inline void
 479 __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
 480 {
 481         unsigned long port = (unsigned long __force)addr;
 482         if (__is_io_address(port))
 483                 __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
 484         else
 485 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 486                 __raw_writesb(addr, vaddr, count);
 487 #else
 488                 __ixp4xx_writesb(addr, vaddr, count);
 489 #endif
 490 }
 491
 492 static inline void
 493 __ixp4xx_iowrite16(u16 value, void __iomem *addr)
 494 {
 495         unsigned long port = (unsigned long __force)addr;
 496         if (__is_io_address(port))
 497                 __ixp4xx_outw(value, port & PIO_MASK);
 498         else
 499 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 500                 __raw_writew(cpu_to_le16(value), addr);
 501 #else
 502                 __ixp4xx_writew(value, addr);
 503 #endif
 504 }
 505
 506 static inline void
 507 __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
 508 {
 509         unsigned long port = (unsigned long __force)addr;
 510         if (__is_io_address(port))
 511                 __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
 512         else
 513 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 514                 __raw_writesw(addr, vaddr, count);
 515 #else
 516                 __ixp4xx_writesw(addr, vaddr, count);
 517 #endif
 518 }
 519
 520 static inline void
 521 __ixp4xx_iowrite32(u32 value, void __iomem *addr)
 522 {
 523         unsigned long port = (unsigned long __force)addr;
 524         if (__is_io_address(port))
 525                 __ixp4xx_outl(value, port & PIO_MASK);
 526         else
 527 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 528                 __raw_writel((u32 __force)cpu_to_le32(value), addr);
 529 #else
 530                 __ixp4xx_writel(value, addr);
 531 #endif
 532 }
 533
 534 static inline void
 535 __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
 536 {
 537         unsigned long port = (unsigned long __force)addr;
 538         if (__is_io_address(port))
 539                 __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
 540         else
 541 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 542                 __raw_writesl(addr, vaddr, count);
 543 #else
 544                 __ixp4xx_writesl(addr, vaddr, count);
 545 #endif
 546 }
 547
 548 #define ioread8(p)                      __ixp4xx_ioread8(p)
 549 #define ioread16(p)                     __ixp4xx_ioread16(p)
 550 #define ioread32(p)                     __ixp4xx_ioread32(p)
 551
 552 #define ioread8_rep(p, v, c)            __ixp4xx_ioread8_rep(p, v, c)
 553 #define ioread16_rep(p, v, c)           __ixp4xx_ioread16_rep(p, v, c)
 554 #define ioread32_rep(p, v, c)           __ixp4xx_ioread32_rep(p, v, c)
 555
 556 #define iowrite8(v,p)                   __ixp4xx_iowrite8(v,p)
 557 #define iowrite16(v,p)                  __ixp4xx_iowrite16(v,p)
 558 #define iowrite32(v,p)                  __ixp4xx_iowrite32(v,p)
 559
 560 #define iowrite8_rep(p, v, c)           __ixp4xx_iowrite8_rep(p, v, c)
 561 #define iowrite16_rep(p, v, c)          __ixp4xx_iowrite16_rep(p, v, c)
 562 #define iowrite32_rep(p, v, c)          __ixp4xx_iowrite32_rep(p, v, c)
 563
 564 #define ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
 565 #define ioport_unmap(addr)
 566 #endif  // !CONFIG_PCI
 567
 568 #endif  //  __ASM_ARM_ARCH_IO_H
 569