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Merge remote-tracking branch 'upstream/master' into kvm-devel
[linux-2.6/kvm.git] / drivers / gpu / drm / radeon / radeon_encoders.c
blobeb3f6dc6df835050dfacaae3a663f4a79f7f254c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39 {
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
56
57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72 }
73
74 void radeon_setup_encoder_clones(struct drm_device *dev)
75 {
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81 }
82
83 uint32_t
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85 {
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
103 else
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
109 else {
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
112 else*/
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
119 else
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
127 else
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
137 else
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
148 else
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
153 break;
154 }
155
156 return ret;
157 }
158
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160 {
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178 }
179
180 void
181 radeon_link_encoder_connector(struct drm_device *dev)
182 {
183 struct drm_connector *connector;
184 struct radeon_connector *radeon_connector;
185 struct drm_encoder *encoder;
186 struct radeon_encoder *radeon_encoder;
187
188 /* walk the list and link encoders to connectors */
189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
190 radeon_connector = to_radeon_connector(connector);
191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
192 radeon_encoder = to_radeon_encoder(encoder);
193 if (radeon_encoder->devices & radeon_connector->devices)
194 drm_mode_connector_attach_encoder(connector, encoder);
195 }
196 }
197 }
198
199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 {
201 struct drm_device *dev = encoder->dev;
202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
203 struct drm_connector *connector;
204
205 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
206 if (connector->encoder == encoder) {
207 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
208 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
210 radeon_encoder->active_device, radeon_encoder->devices,
211 radeon_connector->devices, encoder->encoder_type);
212 }
213 }
214 }
215
216 struct drm_connector *
217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 {
219 struct drm_device *dev = encoder->dev;
220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221 struct drm_connector *connector;
222 struct radeon_connector *radeon_connector;
223
224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
225 radeon_connector = to_radeon_connector(connector);
226 if (radeon_encoder->active_device & radeon_connector->devices)
227 return connector;
228 }
229 return NULL;
230 }
231
232 static struct drm_connector *
233 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
234 {
235 struct drm_device *dev = encoder->dev;
236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
237 struct drm_connector *connector;
238 struct radeon_connector *radeon_connector;
239
240 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
241 radeon_connector = to_radeon_connector(connector);
242 if (radeon_encoder->devices & radeon_connector->devices)
243 return connector;
244 }
245 return NULL;
246 }
247
248 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
249 {
250 struct drm_device *dev = encoder->dev;
251 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
252 struct drm_encoder *other_encoder;
253 struct radeon_encoder *other_radeon_encoder;
254
255 if (radeon_encoder->is_ext_encoder)
256 return NULL;
257
258 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
259 if (other_encoder == encoder)
260 continue;
261 other_radeon_encoder = to_radeon_encoder(other_encoder);
262 if (other_radeon_encoder->is_ext_encoder &&
263 (radeon_encoder->devices & other_radeon_encoder->devices))
264 return other_encoder;
265 }
266 return NULL;
267 }
268
269 bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
270 {
271 struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
272
273 if (other_encoder) {
274 struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
275
276 switch (radeon_encoder->encoder_id) {
277 case ENCODER_OBJECT_ID_TRAVIS:
278 case ENCODER_OBJECT_ID_NUTMEG:
279 return true;
280 default:
281 return false;
282 }
283 }
284
285 return false;
286 }
287
288 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
289 struct drm_display_mode *adjusted_mode)
290 {
291 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
292 struct drm_device *dev = encoder->dev;
293 struct radeon_device *rdev = dev->dev_private;
294 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
295 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
296 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
297 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
298 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
299 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
300 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
301
302 adjusted_mode->clock = native_mode->clock;
303 adjusted_mode->flags = native_mode->flags;
304
305 if (ASIC_IS_AVIVO(rdev)) {
306 adjusted_mode->hdisplay = native_mode->hdisplay;
307 adjusted_mode->vdisplay = native_mode->vdisplay;
308 }
309
310 adjusted_mode->htotal = native_mode->hdisplay + hblank;
311 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
312 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
313
314 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
315 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
316 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
317
318 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
319
320 if (ASIC_IS_AVIVO(rdev)) {
321 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
322 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
323 }
324
325 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
326 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
327 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
328
329 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
330 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
331 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
332
333 }
334
335 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
336 struct drm_display_mode *mode,
337 struct drm_display_mode *adjusted_mode)
338 {
339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
340 struct drm_device *dev = encoder->dev;
341 struct radeon_device *rdev = dev->dev_private;
342
343 /* set the active encoder to connector routing */
344 radeon_encoder_set_active_device(encoder);
345 drm_mode_set_crtcinfo(adjusted_mode, 0);
346
347 /* hw bug */
348 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
349 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
350 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
351
352 /* get the native mode for LVDS */
353 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
354 radeon_panel_mode_fixup(encoder, adjusted_mode);
355
356 /* get the native mode for TV */
357 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
358 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
359 if (tv_dac) {
360 if (tv_dac->tv_std == TV_STD_NTSC ||
361 tv_dac->tv_std == TV_STD_NTSC_J ||
362 tv_dac->tv_std == TV_STD_PAL_M)
363 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
364 else
365 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
366 }
367 }
368
369 if (ASIC_IS_DCE3(rdev) &&
370 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
371 radeon_encoder_is_dp_bridge(encoder))) {
372 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
373 radeon_dp_set_link_config(connector, mode);
374 }
375
376 return true;
377 }
378
379 static void
380 atombios_dac_setup(struct drm_encoder *encoder, int action)
381 {
382 struct drm_device *dev = encoder->dev;
383 struct radeon_device *rdev = dev->dev_private;
384 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
385 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
386 int index = 0;
387 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
388
389 memset(&args, 0, sizeof(args));
390
391 switch (radeon_encoder->encoder_id) {
392 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
393 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
394 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
395 break;
396 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
397 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
398 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
399 break;
400 }
401
402 args.ucAction = action;
403
404 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
405 args.ucDacStandard = ATOM_DAC1_PS2;
406 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
407 args.ucDacStandard = ATOM_DAC1_CV;
408 else {
409 switch (dac_info->tv_std) {
410 case TV_STD_PAL:
411 case TV_STD_PAL_M:
412 case TV_STD_SCART_PAL:
413 case TV_STD_SECAM:
414 case TV_STD_PAL_CN:
415 args.ucDacStandard = ATOM_DAC1_PAL;
416 break;
417 case TV_STD_NTSC:
418 case TV_STD_NTSC_J:
419 case TV_STD_PAL_60:
420 default:
421 args.ucDacStandard = ATOM_DAC1_NTSC;
422 break;
423 }
424 }
425 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
426
427 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
428
429 }
430
431 static void
432 atombios_tv_setup(struct drm_encoder *encoder, int action)
433 {
434 struct drm_device *dev = encoder->dev;
435 struct radeon_device *rdev = dev->dev_private;
436 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
437 TV_ENCODER_CONTROL_PS_ALLOCATION args;
438 int index = 0;
439 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
440
441 memset(&args, 0, sizeof(args));
442
443 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
444
445 args.sTVEncoder.ucAction = action;
446
447 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
448 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
449 else {
450 switch (dac_info->tv_std) {
451 case TV_STD_NTSC:
452 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
453 break;
454 case TV_STD_PAL:
455 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
456 break;
457 case TV_STD_PAL_M:
458 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
459 break;
460 case TV_STD_PAL_60:
461 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
462 break;
463 case TV_STD_NTSC_J:
464 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
465 break;
466 case TV_STD_SCART_PAL:
467 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
468 break;
469 case TV_STD_SECAM:
470 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
471 break;
472 case TV_STD_PAL_CN:
473 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
474 break;
475 default:
476 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
477 break;
478 }
479 }
480
481 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
482
483 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
484
485 }
486
487 union dvo_encoder_control {
488 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
489 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
490 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
491 };
492
493 void
494 atombios_dvo_setup(struct drm_encoder *encoder, int action)
495 {
496 struct drm_device *dev = encoder->dev;
497 struct radeon_device *rdev = dev->dev_private;
498 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
499 union dvo_encoder_control args;
500 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
501
502 memset(&args, 0, sizeof(args));
503
504 if (ASIC_IS_DCE3(rdev)) {
505 /* DCE3+ */
506 args.dvo_v3.ucAction = action;
507 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
508 args.dvo_v3.ucDVOConfig = 0; /* XXX */
509 } else if (ASIC_IS_DCE2(rdev)) {
510 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
511 args.dvo.sDVOEncoder.ucAction = action;
512 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
513 /* DFP1, CRT1, TV1 depending on the type of port */
514 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
515
516 if (radeon_encoder->pixel_clock > 165000)
517 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
518 } else {
519 /* R4xx, R5xx */
520 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
521
522 if (radeon_encoder->pixel_clock > 165000)
523 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
524
525 /*if (pScrn->rgbBits == 8)*/
526 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
527 }
528
529 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
530 }
531
532 union lvds_encoder_control {
533 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
534 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
535 };
536
537 void
538 atombios_digital_setup(struct drm_encoder *encoder, int action)
539 {
540 struct drm_device *dev = encoder->dev;
541 struct radeon_device *rdev = dev->dev_private;
542 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
543 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
544 union lvds_encoder_control args;
545 int index = 0;
546 int hdmi_detected = 0;
547 uint8_t frev, crev;
548
549 if (!dig)
550 return;
551
552 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
553 hdmi_detected = 1;
554
555 memset(&args, 0, sizeof(args));
556
557 switch (radeon_encoder->encoder_id) {
558 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
559 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
560 break;
561 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
563 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
564 break;
565 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
566 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
567 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
568 else
569 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
570 break;
571 }
572
573 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
574 return;
575
576 switch (frev) {
577 case 1:
578 case 2:
579 switch (crev) {
580 case 1:
581 args.v1.ucMisc = 0;
582 args.v1.ucAction = action;
583 if (hdmi_detected)
584 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
585 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
586 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
587 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
588 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
589 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
590 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
591 } else {
592 if (dig->linkb)
593 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
594 if (radeon_encoder->pixel_clock > 165000)
595 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
596 /*if (pScrn->rgbBits == 8) */
597 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
598 }
599 break;
600 case 2:
601 case 3:
602 args.v2.ucMisc = 0;
603 args.v2.ucAction = action;
604 if (crev == 3) {
605 if (dig->coherent_mode)
606 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
607 }
608 if (hdmi_detected)
609 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
610 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
611 args.v2.ucTruncate = 0;
612 args.v2.ucSpatial = 0;
613 args.v2.ucTemporal = 0;
614 args.v2.ucFRC = 0;
615 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
616 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
617 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
618 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
619 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
620 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
621 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
622 }
623 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
624 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
625 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
626 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
627 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
628 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
629 }
630 } else {
631 if (dig->linkb)
632 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
633 if (radeon_encoder->pixel_clock > 165000)
634 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
635 }
636 break;
637 default:
638 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
639 break;
640 }
641 break;
642 default:
643 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
644 break;
645 }
646
647 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
648 }
649
650 int
651 atombios_get_encoder_mode(struct drm_encoder *encoder)
652 {
653 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
654 struct drm_device *dev = encoder->dev;
655 struct radeon_device *rdev = dev->dev_private;
656 struct drm_connector *connector;
657 struct radeon_connector *radeon_connector;
658 struct radeon_connector_atom_dig *dig_connector;
659
660 /* dp bridges are always DP */
661 if (radeon_encoder_is_dp_bridge(encoder))
662 return ATOM_ENCODER_MODE_DP;
663
664 /* DVO is always DVO */
665 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
666 return ATOM_ENCODER_MODE_DVO;
667
668 connector = radeon_get_connector_for_encoder(encoder);
669 /* if we don't have an active device yet, just use one of
670 * the connectors tied to the encoder.
671 */
672 if (!connector)
673 connector = radeon_get_connector_for_encoder_init(encoder);
674 radeon_connector = to_radeon_connector(connector);
675
676 switch (connector->connector_type) {
677 case DRM_MODE_CONNECTOR_DVII:
678 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
679 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
680 /* fix me */
681 if (ASIC_IS_DCE4(rdev))
682 return ATOM_ENCODER_MODE_DVI;
683 else
684 return ATOM_ENCODER_MODE_HDMI;
685 } else if (radeon_connector->use_digital)
686 return ATOM_ENCODER_MODE_DVI;
687 else
688 return ATOM_ENCODER_MODE_CRT;
689 break;
690 case DRM_MODE_CONNECTOR_DVID:
691 case DRM_MODE_CONNECTOR_HDMIA:
692 default:
693 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
694 /* fix me */
695 if (ASIC_IS_DCE4(rdev))
696 return ATOM_ENCODER_MODE_DVI;
697 else
698 return ATOM_ENCODER_MODE_HDMI;
699 } else
700 return ATOM_ENCODER_MODE_DVI;
701 break;
702 case DRM_MODE_CONNECTOR_LVDS:
703 return ATOM_ENCODER_MODE_LVDS;
704 break;
705 case DRM_MODE_CONNECTOR_DisplayPort:
706 dig_connector = radeon_connector->con_priv;
707 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
708 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
709 return ATOM_ENCODER_MODE_DP;
710 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
711 /* fix me */
712 if (ASIC_IS_DCE4(rdev))
713 return ATOM_ENCODER_MODE_DVI;
714 else
715 return ATOM_ENCODER_MODE_HDMI;
716 } else
717 return ATOM_ENCODER_MODE_DVI;
718 break;
719 case DRM_MODE_CONNECTOR_eDP:
720 return ATOM_ENCODER_MODE_DP;
721 case DRM_MODE_CONNECTOR_DVIA:
722 case DRM_MODE_CONNECTOR_VGA:
723 return ATOM_ENCODER_MODE_CRT;
724 break;
725 case DRM_MODE_CONNECTOR_Composite:
726 case DRM_MODE_CONNECTOR_SVIDEO:
727 case DRM_MODE_CONNECTOR_9PinDIN:
728 /* fix me */
729 return ATOM_ENCODER_MODE_TV;
730 /*return ATOM_ENCODER_MODE_CV;*/
731 break;
732 }
733 }
734
735 /*
736 * DIG Encoder/Transmitter Setup
737 *
738 * DCE 3.0/3.1
739 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
740 * Supports up to 3 digital outputs
741 * - 2 DIG encoder blocks.
742 * DIG1 can drive UNIPHY link A or link B
743 * DIG2 can drive UNIPHY link B or LVTMA
744 *
745 * DCE 3.2
746 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
747 * Supports up to 5 digital outputs
748 * - 2 DIG encoder blocks.
749 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
750 *
751 * DCE 4.0/5.0
752 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
753 * Supports up to 6 digital outputs
754 * - 6 DIG encoder blocks.
755 * - DIG to PHY mapping is hardcoded
756 * DIG1 drives UNIPHY0 link A, A+B
757 * DIG2 drives UNIPHY0 link B
758 * DIG3 drives UNIPHY1 link A, A+B
759 * DIG4 drives UNIPHY1 link B
760 * DIG5 drives UNIPHY2 link A, A+B
761 * DIG6 drives UNIPHY2 link B
762 *
763 * DCE 4.1
764 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
765 * Supports up to 6 digital outputs
766 * - 2 DIG encoder blocks.
767 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
768 *
769 * Routing
770 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
771 * Examples:
772 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
773 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
774 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
775 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
776 */
777
778 union dig_encoder_control {
779 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
780 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
781 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
782 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
783 };
784
785 void
786 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
787 {
788 struct drm_device *dev = encoder->dev;
789 struct radeon_device *rdev = dev->dev_private;
790 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
791 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
792 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
793 union dig_encoder_control args;
794 int index = 0;
795 uint8_t frev, crev;
796 int dp_clock = 0;
797 int dp_lane_count = 0;
798 int hpd_id = RADEON_HPD_NONE;
799 int bpc = 8;
800
801 if (connector) {
802 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
803 struct radeon_connector_atom_dig *dig_connector =
804 radeon_connector->con_priv;
805
806 dp_clock = dig_connector->dp_clock;
807 dp_lane_count = dig_connector->dp_lane_count;
808 hpd_id = radeon_connector->hpd.hpd;
809 bpc = connector->display_info.bpc;
810 }
811
812 /* no dig encoder assigned */
813 if (dig->dig_encoder == -1)
814 return;
815
816 memset(&args, 0, sizeof(args));
817
818 if (ASIC_IS_DCE4(rdev))
819 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
820 else {
821 if (dig->dig_encoder)
822 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
823 else
824 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
825 }
826
827 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
828 return;
829
830 args.v1.ucAction = action;
831 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
832 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
833 args.v3.ucPanelMode = panel_mode;
834 else
835 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
836
837 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
838 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
839 args.v1.ucLaneNum = dp_lane_count;
840 else if (radeon_encoder->pixel_clock > 165000)
841 args.v1.ucLaneNum = 8;
842 else
843 args.v1.ucLaneNum = 4;
844
845 if (ASIC_IS_DCE5(rdev)) {
846 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
847 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
848 if (dp_clock == 270000)
849 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
850 else if (dp_clock == 540000)
851 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
852 }
853 args.v4.acConfig.ucDigSel = dig->dig_encoder;
854 switch (bpc) {
855 case 0:
856 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
857 break;
858 case 6:
859 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
860 break;
861 case 8:
862 default:
863 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
864 break;
865 case 10:
866 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
867 break;
868 case 12:
869 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
870 break;
871 case 16:
872 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
873 break;
874 }
875 if (hpd_id == RADEON_HPD_NONE)
876 args.v4.ucHPD_ID = 0;
877 else
878 args.v4.ucHPD_ID = hpd_id + 1;
879 } else if (ASIC_IS_DCE4(rdev)) {
880 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
881 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
882 args.v3.acConfig.ucDigSel = dig->dig_encoder;
883 switch (bpc) {
884 case 0:
885 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
886 break;
887 case 6:
888 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
889 break;
890 case 8:
891 default:
892 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
893 break;
894 case 10:
895 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
896 break;
897 case 12:
898 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
899 break;
900 case 16:
901 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
902 break;
903 }
904 } else {
905 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
906 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
907 switch (radeon_encoder->encoder_id) {
908 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
909 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
910 break;
911 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
912 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
913 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
914 break;
915 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
916 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
917 break;
918 }
919 if (dig->linkb)
920 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
921 else
922 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
923 }
924
925 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
926
927 }
928
929 union dig_transmitter_control {
930 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
931 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
932 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
933 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
934 };
935
936 void
937 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
938 {
939 struct drm_device *dev = encoder->dev;
940 struct radeon_device *rdev = dev->dev_private;
941 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
942 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
943 struct drm_connector *connector;
944 union dig_transmitter_control args;
945 int index = 0;
946 uint8_t frev, crev;
947 bool is_dp = false;
948 int pll_id = 0;
949 int dp_clock = 0;
950 int dp_lane_count = 0;
951 int connector_object_id = 0;
952 int igp_lane_info = 0;
953 int dig_encoder = dig->dig_encoder;
954
955 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
956 connector = radeon_get_connector_for_encoder_init(encoder);
957 /* just needed to avoid bailing in the encoder check. the encoder
958 * isn't used for init
959 */
960 dig_encoder = 0;
961 } else
962 connector = radeon_get_connector_for_encoder(encoder);
963
964 if (connector) {
965 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
966 struct radeon_connector_atom_dig *dig_connector =
967 radeon_connector->con_priv;
968
969 dp_clock = dig_connector->dp_clock;
970 dp_lane_count = dig_connector->dp_lane_count;
971 connector_object_id =
972 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
973 igp_lane_info = dig_connector->igp_lane_info;
974 }
975
976 /* no dig encoder assigned */
977 if (dig_encoder == -1)
978 return;
979
980 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
981 is_dp = true;
982
983 memset(&args, 0, sizeof(args));
984
985 switch (radeon_encoder->encoder_id) {
986 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
987 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
988 break;
989 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
990 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
991 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
992 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
993 break;
994 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
995 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
996 break;
997 }
998
999 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1000 return;
1001
1002 args.v1.ucAction = action;
1003 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1004 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1005 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1006 args.v1.asMode.ucLaneSel = lane_num;
1007 args.v1.asMode.ucLaneSet = lane_set;
1008 } else {
1009 if (is_dp)
1010 args.v1.usPixelClock =
1011 cpu_to_le16(dp_clock / 10);
1012 else if (radeon_encoder->pixel_clock > 165000)
1013 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1014 else
1015 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1016 }
1017 if (ASIC_IS_DCE4(rdev)) {
1018 if (is_dp)
1019 args.v3.ucLaneNum = dp_lane_count;
1020 else if (radeon_encoder->pixel_clock > 165000)
1021 args.v3.ucLaneNum = 8;
1022 else
1023 args.v3.ucLaneNum = 4;
1024
1025 if (dig->linkb)
1026 args.v3.acConfig.ucLinkSel = 1;
1027 if (dig_encoder & 1)
1028 args.v3.acConfig.ucEncoderSel = 1;
1029
1030 /* Select the PLL for the PHY
1031 * DP PHY should be clocked from external src if there is
1032 * one.
1033 */
1034 if (encoder->crtc) {
1035 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1036 pll_id = radeon_crtc->pll_id;
1037 }
1038
1039 if (ASIC_IS_DCE5(rdev)) {
1040 /* On DCE5 DCPLL usually generates the DP ref clock */
1041 if (is_dp) {
1042 if (rdev->clock.dp_extclk)
1043 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1044 else
1045 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1046 } else
1047 args.v4.acConfig.ucRefClkSource = pll_id;
1048 } else {
1049 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1050 if (is_dp && rdev->clock.dp_extclk)
1051 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1052 else
1053 args.v3.acConfig.ucRefClkSource = pll_id;
1054 }
1055
1056 switch (radeon_encoder->encoder_id) {
1057 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1058 args.v3.acConfig.ucTransmitterSel = 0;
1059 break;
1060 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1061 args.v3.acConfig.ucTransmitterSel = 1;
1062 break;
1063 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1064 args.v3.acConfig.ucTransmitterSel = 2;
1065 break;
1066 }
1067
1068 if (is_dp)
1069 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1070 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1071 if (dig->coherent_mode)
1072 args.v3.acConfig.fCoherentMode = 1;
1073 if (radeon_encoder->pixel_clock > 165000)
1074 args.v3.acConfig.fDualLinkConnector = 1;
1075 }
1076 } else if (ASIC_IS_DCE32(rdev)) {
1077 args.v2.acConfig.ucEncoderSel = dig_encoder;
1078 if (dig->linkb)
1079 args.v2.acConfig.ucLinkSel = 1;
1080
1081 switch (radeon_encoder->encoder_id) {
1082 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1083 args.v2.acConfig.ucTransmitterSel = 0;
1084 break;
1085 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1086 args.v2.acConfig.ucTransmitterSel = 1;
1087 break;
1088 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1089 args.v2.acConfig.ucTransmitterSel = 2;
1090 break;
1091 }
1092
1093 if (is_dp) {
1094 args.v2.acConfig.fCoherentMode = 1;
1095 args.v2.acConfig.fDPConnector = 1;
1096 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1097 if (dig->coherent_mode)
1098 args.v2.acConfig.fCoherentMode = 1;
1099 if (radeon_encoder->pixel_clock > 165000)
1100 args.v2.acConfig.fDualLinkConnector = 1;
1101 }
1102 } else {
1103 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1104
1105 if (dig_encoder)
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1107 else
1108 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1109
1110 if ((rdev->flags & RADEON_IS_IGP) &&
1111 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1112 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
1113 if (igp_lane_info & 0x1)
1114 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1115 else if (igp_lane_info & 0x2)
1116 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1117 else if (igp_lane_info & 0x4)
1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1119 else if (igp_lane_info & 0x8)
1120 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1121 } else {
1122 if (igp_lane_info & 0x3)
1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1124 else if (igp_lane_info & 0xc)
1125 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1126 }
1127 }
1128
1129 if (dig->linkb)
1130 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1131 else
1132 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1133
1134 if (is_dp)
1135 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1136 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1137 if (dig->coherent_mode)
1138 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1139 if (radeon_encoder->pixel_clock > 165000)
1140 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1141 }
1142 }
1143
1144 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1145 }
1146
1147 bool
1148 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1149 {
1150 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1151 struct drm_device *dev = radeon_connector->base.dev;
1152 struct radeon_device *rdev = dev->dev_private;
1153 union dig_transmitter_control args;
1154 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1155 uint8_t frev, crev;
1156
1157 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1158 goto done;
1159
1160 if (!ASIC_IS_DCE4(rdev))
1161 goto done;
1162
1163 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1164 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1165 goto done;
1166
1167 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1168 goto done;
1169
1170 memset(&args, 0, sizeof(args));
1171
1172 args.v1.ucAction = action;
1173
1174 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1175
1176 /* wait for the panel to power up */
1177 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1178 int i;
1179
1180 for (i = 0; i < 300; i++) {
1181 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1182 return true;
1183 mdelay(1);
1184 }
1185 return false;
1186 }
1187 done:
1188 return true;
1189 }
1190
1191 union external_encoder_control {
1192 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1193 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1194 };
1195
1196 static void
1197 atombios_external_encoder_setup(struct drm_encoder *encoder,
1198 struct drm_encoder *ext_encoder,
1199 int action)
1200 {
1201 struct drm_device *dev = encoder->dev;
1202 struct radeon_device *rdev = dev->dev_private;
1203 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1204 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1205 union external_encoder_control args;
1206 struct drm_connector *connector;
1207 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1208 u8 frev, crev;
1209 int dp_clock = 0;
1210 int dp_lane_count = 0;
1211 int connector_object_id = 0;
1212 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1213 int bpc = 8;
1214
1215 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1216 connector = radeon_get_connector_for_encoder_init(encoder);
1217 else
1218 connector = radeon_get_connector_for_encoder(encoder);
1219
1220 if (connector) {
1221 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1222 struct radeon_connector_atom_dig *dig_connector =
1223 radeon_connector->con_priv;
1224
1225 dp_clock = dig_connector->dp_clock;
1226 dp_lane_count = dig_connector->dp_lane_count;
1227 connector_object_id =
1228 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1229 bpc = connector->display_info.bpc;
1230 }
1231
1232 memset(&args, 0, sizeof(args));
1233
1234 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1235 return;
1236
1237 switch (frev) {
1238 case 1:
1239 /* no params on frev 1 */
1240 break;
1241 case 2:
1242 switch (crev) {
1243 case 1:
1244 case 2:
1245 args.v1.sDigEncoder.ucAction = action;
1246 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1247 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1248
1249 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1250 if (dp_clock == 270000)
1251 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1252 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1253 } else if (radeon_encoder->pixel_clock > 165000)
1254 args.v1.sDigEncoder.ucLaneNum = 8;
1255 else
1256 args.v1.sDigEncoder.ucLaneNum = 4;
1257 break;
1258 case 3:
1259 args.v3.sExtEncoder.ucAction = action;
1260 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1261 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1262 else
1263 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1264 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1265
1266 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1267 if (dp_clock == 270000)
1268 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1269 else if (dp_clock == 540000)
1270 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1271 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1272 } else if (radeon_encoder->pixel_clock > 165000)
1273 args.v3.sExtEncoder.ucLaneNum = 8;
1274 else
1275 args.v3.sExtEncoder.ucLaneNum = 4;
1276 switch (ext_enum) {
1277 case GRAPH_OBJECT_ENUM_ID1:
1278 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1279 break;
1280 case GRAPH_OBJECT_ENUM_ID2:
1281 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1282 break;
1283 case GRAPH_OBJECT_ENUM_ID3:
1284 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1285 break;
1286 }
1287 switch (bpc) {
1288 case 0:
1289 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1290 break;
1291 case 6:
1292 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1293 break;
1294 case 8:
1295 default:
1296 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1297 break;
1298 case 10:
1299 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1300 break;
1301 case 12:
1302 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1303 break;
1304 case 16:
1305 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1306 break;
1307 }
1308 break;
1309 default:
1310 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1311 return;
1312 }
1313 break;
1314 default:
1315 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1316 return;
1317 }
1318 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1319 }
1320
1321 static void
1322 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1323 {
1324 struct drm_device *dev = encoder->dev;
1325 struct radeon_device *rdev = dev->dev_private;
1326 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1327 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1328 ENABLE_YUV_PS_ALLOCATION args;
1329 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1330 uint32_t temp, reg;
1331
1332 memset(&args, 0, sizeof(args));
1333
1334 if (rdev->family >= CHIP_R600)
1335 reg = R600_BIOS_3_SCRATCH;
1336 else
1337 reg = RADEON_BIOS_3_SCRATCH;
1338
1339 /* XXX: fix up scratch reg handling */
1340 temp = RREG32(reg);
1341 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1342 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1343 (radeon_crtc->crtc_id << 18)));
1344 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1345 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1346 else
1347 WREG32(reg, 0);
1348
1349 if (enable)
1350 args.ucEnable = ATOM_ENABLE;
1351 args.ucCRTC = radeon_crtc->crtc_id;
1352
1353 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1354
1355 WREG32(reg, temp);
1356 }
1357
1358 static void
1359 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1360 {
1361 struct drm_device *dev = encoder->dev;
1362 struct radeon_device *rdev = dev->dev_private;
1363 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1364 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1365 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1366 int index = 0;
1367 bool is_dig = false;
1368 bool is_dce5_dac = false;
1369 bool is_dce5_dvo = false;
1370
1371 memset(&args, 0, sizeof(args));
1372
1373 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1374 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1375 radeon_encoder->active_device);
1376 switch (radeon_encoder->encoder_id) {
1377 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1378 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1379 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1380 break;
1381 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1382 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1383 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1384 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1385 is_dig = true;
1386 break;
1387 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1388 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1389 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1390 break;
1391 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1392 if (ASIC_IS_DCE5(rdev))
1393 is_dce5_dvo = true;
1394 else if (ASIC_IS_DCE3(rdev))
1395 is_dig = true;
1396 else
1397 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1398 break;
1399 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1400 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1401 break;
1402 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1403 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1404 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1405 else
1406 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1407 break;
1408 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1409 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1410 if (ASIC_IS_DCE5(rdev))
1411 is_dce5_dac = true;
1412 else {
1413 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1414 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1415 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1416 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1417 else
1418 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1419 }
1420 break;
1421 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1422 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1423 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1424 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1425 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1426 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1427 else
1428 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1429 break;
1430 }
1431
1432 if (is_dig) {
1433 switch (mode) {
1434 case DRM_MODE_DPMS_ON:
1435 /* some early dce3.2 boards have a bug in their transmitter control table */
1436 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1437 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1438 else
1439 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1440 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1441 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1442
1443 if (connector &&
1444 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1445 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1446 struct radeon_connector_atom_dig *radeon_dig_connector =
1447 radeon_connector->con_priv;
1448 atombios_set_edp_panel_power(connector,
1449 ATOM_TRANSMITTER_ACTION_POWER_ON);
1450 radeon_dig_connector->edp_on = true;
1451 }
1452 if (ASIC_IS_DCE4(rdev))
1453 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1454 radeon_dp_link_train(encoder, connector);
1455 if (ASIC_IS_DCE4(rdev))
1456 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1457 }
1458 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1459 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1460 break;
1461 case DRM_MODE_DPMS_STANDBY:
1462 case DRM_MODE_DPMS_SUSPEND:
1463 case DRM_MODE_DPMS_OFF:
1464 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1465 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1466 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1467
1468 if (ASIC_IS_DCE4(rdev))
1469 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1470 if (connector &&
1471 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1472 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1473 struct radeon_connector_atom_dig *radeon_dig_connector =
1474 radeon_connector->con_priv;
1475 atombios_set_edp_panel_power(connector,
1476 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1477 radeon_dig_connector->edp_on = false;
1478 }
1479 }
1480 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1481 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1482 break;
1483 }
1484 } else if (is_dce5_dac) {
1485 switch (mode) {
1486 case DRM_MODE_DPMS_ON:
1487 atombios_dac_setup(encoder, ATOM_ENABLE);
1488 break;
1489 case DRM_MODE_DPMS_STANDBY:
1490 case DRM_MODE_DPMS_SUSPEND:
1491 case DRM_MODE_DPMS_OFF:
1492 atombios_dac_setup(encoder, ATOM_DISABLE);
1493 break;
1494 }
1495 } else if (is_dce5_dvo) {
1496 switch (mode) {
1497 case DRM_MODE_DPMS_ON:
1498 atombios_dvo_setup(encoder, ATOM_ENABLE);
1499 break;
1500 case DRM_MODE_DPMS_STANDBY:
1501 case DRM_MODE_DPMS_SUSPEND:
1502 case DRM_MODE_DPMS_OFF:
1503 atombios_dvo_setup(encoder, ATOM_DISABLE);
1504 break;
1505 }
1506 } else {
1507 switch (mode) {
1508 case DRM_MODE_DPMS_ON:
1509 args.ucAction = ATOM_ENABLE;
1510 /* workaround for DVOOutputControl on some RS690 systems */
1511 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1512 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1513 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1514 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1515 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1516 } else
1517 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1518 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1519 args.ucAction = ATOM_LCD_BLON;
1520 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1521 }
1522 break;
1523 case DRM_MODE_DPMS_STANDBY:
1524 case DRM_MODE_DPMS_SUSPEND:
1525 case DRM_MODE_DPMS_OFF:
1526 args.ucAction = ATOM_DISABLE;
1527 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1528 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1529 args.ucAction = ATOM_LCD_BLOFF;
1530 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1531 }
1532 break;
1533 }
1534 }
1535
1536 if (ext_encoder) {
1537 switch (mode) {
1538 case DRM_MODE_DPMS_ON:
1539 default:
1540 if (ASIC_IS_DCE41(rdev)) {
1541 atombios_external_encoder_setup(encoder, ext_encoder,
1542 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1543 atombios_external_encoder_setup(encoder, ext_encoder,
1544 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1545 } else
1546 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1547 break;
1548 case DRM_MODE_DPMS_STANDBY:
1549 case DRM_MODE_DPMS_SUSPEND:
1550 case DRM_MODE_DPMS_OFF:
1551 if (ASIC_IS_DCE41(rdev)) {
1552 atombios_external_encoder_setup(encoder, ext_encoder,
1553 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1554 atombios_external_encoder_setup(encoder, ext_encoder,
1555 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1556 } else
1557 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1558 break;
1559 }
1560 }
1561
1562 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1563
1564 }
1565
1566 union crtc_source_param {
1567 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1568 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1569 };
1570
1571 static void
1572 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1573 {
1574 struct drm_device *dev = encoder->dev;
1575 struct radeon_device *rdev = dev->dev_private;
1576 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1577 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1578 union crtc_source_param args;
1579 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1580 uint8_t frev, crev;
1581 struct radeon_encoder_atom_dig *dig;
1582
1583 memset(&args, 0, sizeof(args));
1584
1585 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1586 return;
1587
1588 switch (frev) {
1589 case 1:
1590 switch (crev) {
1591 case 1:
1592 default:
1593 if (ASIC_IS_AVIVO(rdev))
1594 args.v1.ucCRTC = radeon_crtc->crtc_id;
1595 else {
1596 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1597 args.v1.ucCRTC = radeon_crtc->crtc_id;
1598 } else {
1599 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1600 }
1601 }
1602 switch (radeon_encoder->encoder_id) {
1603 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1604 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1605 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1606 break;
1607 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1608 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1609 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1610 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1611 else
1612 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1613 break;
1614 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1615 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1616 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1617 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1618 break;
1619 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1620 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1621 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1622 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1623 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1624 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1625 else
1626 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1627 break;
1628 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1629 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1630 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1631 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1632 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1633 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1634 else
1635 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1636 break;
1637 }
1638 break;
1639 case 2:
1640 args.v2.ucCRTC = radeon_crtc->crtc_id;
1641 if (radeon_encoder_is_dp_bridge(encoder)) {
1642 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1643
1644 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1645 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1646 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1647 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1648 else
1649 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1650 } else
1651 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1652 switch (radeon_encoder->encoder_id) {
1653 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1654 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1655 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1656 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1657 dig = radeon_encoder->enc_priv;
1658 switch (dig->dig_encoder) {
1659 case 0:
1660 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1661 break;
1662 case 1:
1663 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1664 break;
1665 case 2:
1666 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1667 break;
1668 case 3:
1669 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1670 break;
1671 case 4:
1672 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1673 break;
1674 case 5:
1675 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1676 break;
1677 }
1678 break;
1679 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1680 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1681 break;
1682 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1683 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1684 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1685 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1686 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1687 else
1688 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1689 break;
1690 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1691 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1692 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1693 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1694 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1695 else
1696 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1697 break;
1698 }
1699 break;
1700 }
1701 break;
1702 default:
1703 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1704 return;
1705 }
1706
1707 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1708
1709 /* update scratch regs with new routing */
1710 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1711 }
1712
1713 static void
1714 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1715 struct drm_display_mode *mode)
1716 {
1717 struct drm_device *dev = encoder->dev;
1718 struct radeon_device *rdev = dev->dev_private;
1719 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1720 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1721
1722 /* Funky macbooks */
1723 if ((dev->pdev->device == 0x71C5) &&
1724 (dev->pdev->subsystem_vendor == 0x106b) &&
1725 (dev->pdev->subsystem_device == 0x0080)) {
1726 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1727 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1728
1729 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1730 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1731
1732 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1733 }
1734 }
1735
1736 /* set scaler clears this on some chips */
1737 if (ASIC_IS_AVIVO(rdev) &&
1738 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1739 if (ASIC_IS_DCE4(rdev)) {
1740 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1741 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1742 EVERGREEN_INTERLEAVE_EN);
1743 else
1744 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1745 } else {
1746 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1747 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1748 AVIVO_D1MODE_INTERLEAVE_EN);
1749 else
1750 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1751 }
1752 }
1753 }
1754
1755 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1756 {
1757 struct drm_device *dev = encoder->dev;
1758 struct radeon_device *rdev = dev->dev_private;
1759 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1760 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1761 struct drm_encoder *test_encoder;
1762 struct radeon_encoder_atom_dig *dig;
1763 uint32_t dig_enc_in_use = 0;
1764
1765 /* DCE4/5 */
1766 if (ASIC_IS_DCE4(rdev)) {
1767 dig = radeon_encoder->enc_priv;
1768 if (ASIC_IS_DCE41(rdev)) {
1769 /* ontario follows DCE4 */
1770 if (rdev->family == CHIP_PALM) {
1771 if (dig->linkb)
1772 return 1;
1773 else
1774 return 0;
1775 } else
1776 /* llano follows DCE3.2 */
1777 return radeon_crtc->crtc_id;
1778 } else {
1779 switch (radeon_encoder->encoder_id) {
1780 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1781 if (dig->linkb)
1782 return 1;
1783 else
1784 return 0;
1785 break;
1786 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1787 if (dig->linkb)
1788 return 3;
1789 else
1790 return 2;
1791 break;
1792 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1793 if (dig->linkb)
1794 return 5;
1795 else
1796 return 4;
1797 break;
1798 }
1799 }
1800 }
1801
1802 /* on DCE32 and encoder can driver any block so just crtc id */
1803 if (ASIC_IS_DCE32(rdev)) {
1804 return radeon_crtc->crtc_id;
1805 }
1806
1807 /* on DCE3 - LVTMA can only be driven by DIGB */
1808 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1809 struct radeon_encoder *radeon_test_encoder;
1810
1811 if (encoder == test_encoder)
1812 continue;
1813
1814 if (!radeon_encoder_is_digital(test_encoder))
1815 continue;
1816
1817 radeon_test_encoder = to_radeon_encoder(test_encoder);
1818 dig = radeon_test_encoder->enc_priv;
1819
1820 if (dig->dig_encoder >= 0)
1821 dig_enc_in_use |= (1 << dig->dig_encoder);
1822 }
1823
1824 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1825 if (dig_enc_in_use & 0x2)
1826 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1827 return 1;
1828 }
1829 if (!(dig_enc_in_use & 1))
1830 return 0;
1831 return 1;
1832 }
1833
1834 /* This only needs to be called once at startup */
1835 void
1836 radeon_atom_encoder_init(struct radeon_device *rdev)
1837 {
1838 struct drm_device *dev = rdev->ddev;
1839 struct drm_encoder *encoder;
1840
1841 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1842 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1843 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1844
1845 switch (radeon_encoder->encoder_id) {
1846 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1847 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1848 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1849 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1850 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1851 break;
1852 default:
1853 break;
1854 }
1855
1856 if (ext_encoder && ASIC_IS_DCE41(rdev))
1857 atombios_external_encoder_setup(encoder, ext_encoder,
1858 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1859 }
1860 }
1861
1862 static void
1863 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1864 struct drm_display_mode *mode,
1865 struct drm_display_mode *adjusted_mode)
1866 {
1867 struct drm_device *dev = encoder->dev;
1868 struct radeon_device *rdev = dev->dev_private;
1869 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1870 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1871
1872 radeon_encoder->pixel_clock = adjusted_mode->clock;
1873
1874 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1875 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1876 atombios_yuv_setup(encoder, true);
1877 else
1878 atombios_yuv_setup(encoder, false);
1879 }
1880
1881 switch (radeon_encoder->encoder_id) {
1882 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1883 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1884 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1885 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1886 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1887 break;
1888 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1889 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1890 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1891 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1892 if (ASIC_IS_DCE4(rdev)) {
1893 /* disable the transmitter */
1894 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1895 /* setup and enable the encoder */
1896 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1897
1898 /* enable the transmitter */
1899 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1900 } else {
1901 /* disable the encoder and transmitter */
1902 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1903 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1904
1905 /* setup and enable the encoder and transmitter */
1906 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1907 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1908 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1909 }
1910 break;
1911 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1912 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1913 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1914 atombios_dvo_setup(encoder, ATOM_ENABLE);
1915 break;
1916 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1917 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1918 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1919 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1920 atombios_dac_setup(encoder, ATOM_ENABLE);
1921 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1922 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1923 atombios_tv_setup(encoder, ATOM_ENABLE);
1924 else
1925 atombios_tv_setup(encoder, ATOM_DISABLE);
1926 }
1927 break;
1928 }
1929
1930 if (ext_encoder) {
1931 if (ASIC_IS_DCE41(rdev))
1932 atombios_external_encoder_setup(encoder, ext_encoder,
1933 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1934 else
1935 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1936 }
1937
1938 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1939
1940 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1941 r600_hdmi_enable(encoder);
1942 r600_hdmi_setmode(encoder, adjusted_mode);
1943 }
1944 }
1945
1946 static bool
1947 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1948 {
1949 struct drm_device *dev = encoder->dev;
1950 struct radeon_device *rdev = dev->dev_private;
1951 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1952 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1953
1954 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1955 ATOM_DEVICE_CV_SUPPORT |
1956 ATOM_DEVICE_CRT_SUPPORT)) {
1957 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1958 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1959 uint8_t frev, crev;
1960
1961 memset(&args, 0, sizeof(args));
1962
1963 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1964 return false;
1965
1966 args.sDacload.ucMisc = 0;
1967
1968 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1969 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1970 args.sDacload.ucDacType = ATOM_DAC_A;
1971 else
1972 args.sDacload.ucDacType = ATOM_DAC_B;
1973
1974 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1975 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1976 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1977 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1978 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1979 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1980 if (crev >= 3)
1981 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1982 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1983 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1984 if (crev >= 3)
1985 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1986 }
1987
1988 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1989
1990 return true;
1991 } else
1992 return false;
1993 }
1994
1995 static enum drm_connector_status
1996 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1997 {
1998 struct drm_device *dev = encoder->dev;
1999 struct radeon_device *rdev = dev->dev_private;
2000 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2001 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2002 uint32_t bios_0_scratch;
2003
2004 if (!atombios_dac_load_detect(encoder, connector)) {
2005 DRM_DEBUG_KMS("detect returned false \n");
2006 return connector_status_unknown;
2007 }
2008
2009 if (rdev->family >= CHIP_R600)
2010 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2011 else
2012 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2013
2014 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2015 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2016 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2017 return connector_status_connected;
2018 }
2019 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2020 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2021 return connector_status_connected;
2022 }
2023 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2024 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2025 return connector_status_connected;
2026 }
2027 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2028 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2029 return connector_status_connected; /* CTV */
2030 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2031 return connector_status_connected; /* STV */
2032 }
2033 return connector_status_disconnected;
2034 }
2035
2036 static enum drm_connector_status
2037 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2038 {
2039 struct drm_device *dev = encoder->dev;
2040 struct radeon_device *rdev = dev->dev_private;
2041 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2042 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2043 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2044 u32 bios_0_scratch;
2045
2046 if (!ASIC_IS_DCE4(rdev))
2047 return connector_status_unknown;
2048
2049 if (!ext_encoder)
2050 return connector_status_unknown;
2051
2052 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2053 return connector_status_unknown;
2054
2055 /* load detect on the dp bridge */
2056 atombios_external_encoder_setup(encoder, ext_encoder,
2057 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2058
2059 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2060
2061 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2062 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2063 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2064 return connector_status_connected;
2065 }
2066 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2067 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2068 return connector_status_connected;
2069 }
2070 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2071 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2072 return connector_status_connected;
2073 }
2074 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2075 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2076 return connector_status_connected; /* CTV */
2077 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2078 return connector_status_connected; /* STV */
2079 }
2080 return connector_status_disconnected;
2081 }
2082
2083 void
2084 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2085 {
2086 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2087
2088 if (ext_encoder)
2089 /* ddc_setup on the dp bridge */
2090 atombios_external_encoder_setup(encoder, ext_encoder,
2091 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2092
2093 }
2094
2095 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2096 {
2097 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2098 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2099
2100 if ((radeon_encoder->active_device &
2101 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2102 radeon_encoder_is_dp_bridge(encoder)) {
2103 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2104 if (dig)
2105 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2106 }
2107
2108 radeon_atom_output_lock(encoder, true);
2109 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2110
2111 if (connector) {
2112 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2113
2114 /* select the clock/data port if it uses a router */
2115 if (radeon_connector->router.cd_valid)
2116 radeon_router_select_cd_port(radeon_connector);
2117
2118 /* turn eDP panel on for mode set */
2119 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2120 atombios_set_edp_panel_power(connector,
2121 ATOM_TRANSMITTER_ACTION_POWER_ON);
2122 }
2123
2124 /* this is needed for the pll/ss setup to work correctly in some cases */
2125 atombios_set_encoder_crtc_source(encoder);
2126 }
2127
2128 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2129 {
2130 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2131 radeon_atom_output_lock(encoder, false);
2132 }
2133
2134 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2135 {
2136 struct drm_device *dev = encoder->dev;
2137 struct radeon_device *rdev = dev->dev_private;
2138 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2139 struct radeon_encoder_atom_dig *dig;
2140
2141 /* check for pre-DCE3 cards with shared encoders;
2142 * can't really use the links individually, so don't disable
2143 * the encoder if it's in use by another connector
2144 */
2145 if (!ASIC_IS_DCE3(rdev)) {
2146 struct drm_encoder *other_encoder;
2147 struct radeon_encoder *other_radeon_encoder;
2148
2149 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2150 other_radeon_encoder = to_radeon_encoder(other_encoder);
2151 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2152 drm_helper_encoder_in_use(other_encoder))
2153 goto disable_done;
2154 }
2155 }
2156
2157 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2158
2159 switch (radeon_encoder->encoder_id) {
2160 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2161 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2162 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2163 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2164 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2165 break;
2166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2167 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2168 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2169 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2170 if (ASIC_IS_DCE4(rdev))
2171 /* disable the transmitter */
2172 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2173 else {
2174 /* disable the encoder and transmitter */
2175 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2176 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2177 }
2178 break;
2179 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2180 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2181 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2182 atombios_dvo_setup(encoder, ATOM_DISABLE);
2183 break;
2184 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2185 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2186 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2187 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2188 atombios_dac_setup(encoder, ATOM_DISABLE);
2189 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2190 atombios_tv_setup(encoder, ATOM_DISABLE);
2191 break;
2192 }
2193
2194 disable_done:
2195 if (radeon_encoder_is_digital(encoder)) {
2196 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2197 r600_hdmi_disable(encoder);
2198 dig = radeon_encoder->enc_priv;
2199 dig->dig_encoder = -1;
2200 }
2201 radeon_encoder->active_device = 0;
2202 }
2203
2204 /* these are handled by the primary encoders */
2205 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2206 {
2207
2208 }
2209
2210 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2211 {
2212
2213 }
2214
2215 static void
2216 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2217 struct drm_display_mode *mode,
2218 struct drm_display_mode *adjusted_mode)
2219 {
2220
2221 }
2222
2223 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2224 {
2225
2226 }
2227
2228 static void
2229 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2230 {
2231
2232 }
2233
2234 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2235 struct drm_display_mode *mode,
2236 struct drm_display_mode *adjusted_mode)
2237 {
2238 return true;
2239 }
2240
2241 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2242 .dpms = radeon_atom_ext_dpms,
2243 .mode_fixup = radeon_atom_ext_mode_fixup,
2244 .prepare = radeon_atom_ext_prepare,
2245 .mode_set = radeon_atom_ext_mode_set,
2246 .commit = radeon_atom_ext_commit,
2247 .disable = radeon_atom_ext_disable,
2248 /* no detect for TMDS/LVDS yet */
2249 };
2250
2251 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2252 .dpms = radeon_atom_encoder_dpms,
2253 .mode_fixup = radeon_atom_mode_fixup,
2254 .prepare = radeon_atom_encoder_prepare,
2255 .mode_set = radeon_atom_encoder_mode_set,
2256 .commit = radeon_atom_encoder_commit,
2257 .disable = radeon_atom_encoder_disable,
2258 .detect = radeon_atom_dig_detect,
2259 };
2260
2261 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2262 .dpms = radeon_atom_encoder_dpms,
2263 .mode_fixup = radeon_atom_mode_fixup,
2264 .prepare = radeon_atom_encoder_prepare,
2265 .mode_set = radeon_atom_encoder_mode_set,
2266 .commit = radeon_atom_encoder_commit,
2267 .detect = radeon_atom_dac_detect,
2268 };
2269
2270 void radeon_enc_destroy(struct drm_encoder *encoder)
2271 {
2272 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2273 kfree(radeon_encoder->enc_priv);
2274 drm_encoder_cleanup(encoder);
2275 kfree(radeon_encoder);
2276 }
2277
2278 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2279 .destroy = radeon_enc_destroy,
2280 };
2281
2282 struct radeon_encoder_atom_dac *
2283 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2284 {
2285 struct drm_device *dev = radeon_encoder->base.dev;
2286 struct radeon_device *rdev = dev->dev_private;
2287 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2288
2289 if (!dac)
2290 return NULL;
2291
2292 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2293 return dac;
2294 }
2295
2296 struct radeon_encoder_atom_dig *
2297 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2298 {
2299 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2300 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2301
2302 if (!dig)
2303 return NULL;
2304
2305 /* coherent mode by default */
2306 dig->coherent_mode = true;
2307 dig->dig_encoder = -1;
2308
2309 if (encoder_enum == 2)
2310 dig->linkb = true;
2311 else
2312 dig->linkb = false;
2313
2314 return dig;
2315 }
2316
2317 void
2318 radeon_add_atom_encoder(struct drm_device *dev,
2319 uint32_t encoder_enum,
2320 uint32_t supported_device,
2321 u16 caps)
2322 {
2323 struct radeon_device *rdev = dev->dev_private;
2324 struct drm_encoder *encoder;
2325 struct radeon_encoder *radeon_encoder;
2326
2327 /* see if we already added it */
2328 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2329 radeon_encoder = to_radeon_encoder(encoder);
2330 if (radeon_encoder->encoder_enum == encoder_enum) {
2331 radeon_encoder->devices |= supported_device;
2332 return;
2333 }
2334
2335 }
2336
2337 /* add a new one */
2338 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2339 if (!radeon_encoder)
2340 return;
2341
2342 encoder = &radeon_encoder->base;
2343 switch (rdev->num_crtc) {
2344 case 1:
2345 encoder->possible_crtcs = 0x1;
2346 break;
2347 case 2:
2348 default:
2349 encoder->possible_crtcs = 0x3;
2350 break;
2351 case 4:
2352 encoder->possible_crtcs = 0xf;
2353 break;
2354 case 6:
2355 encoder->possible_crtcs = 0x3f;
2356 break;
2357 }
2358
2359 radeon_encoder->enc_priv = NULL;
2360
2361 radeon_encoder->encoder_enum = encoder_enum;
2362 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2363 radeon_encoder->devices = supported_device;
2364 radeon_encoder->rmx_type = RMX_OFF;
2365 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2366 radeon_encoder->is_ext_encoder = false;
2367 radeon_encoder->caps = caps;
2368
2369 switch (radeon_encoder->encoder_id) {
2370 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2371 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2372 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2373 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2374 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2375 radeon_encoder->rmx_type = RMX_FULL;
2376 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2377 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2378 } else {
2379 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2380 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2381 }
2382 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2383 break;
2384 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2385 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2386 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2387 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2388 break;
2389 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2390 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2391 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2392 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2393 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2394 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2395 break;
2396 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2397 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2398 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2399 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2400 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2401 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2402 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2403 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2404 radeon_encoder->rmx_type = RMX_FULL;
2405 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2406 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2407 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2408 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2409 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2410 } else {
2411 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2412 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2413 }
2414 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2415 break;
2416 case ENCODER_OBJECT_ID_SI170B:
2417 case ENCODER_OBJECT_ID_CH7303:
2418 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2419 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2420 case ENCODER_OBJECT_ID_TITFP513:
2421 case ENCODER_OBJECT_ID_VT1623:
2422 case ENCODER_OBJECT_ID_HDMI_SI1930:
2423 case ENCODER_OBJECT_ID_TRAVIS:
2424 case ENCODER_OBJECT_ID_NUTMEG:
2425 /* these are handled by the primary encoders */
2426 radeon_encoder->is_ext_encoder = true;
2427 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2428 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2429 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2430 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2431 else
2432 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2433 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2434 break;
2435 }
2436 }
kernel-based virtual machine