arch/arm/mach-pxa/pxa27x.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/pxa27x.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Nov 05, 2002
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code specific to PXA27x aka Bulverde.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/gpio.h>
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/suspend.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/syscore_ops.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/i2c/pxa-i2c.h>
  24 #include <linux/gpio.h>
  25
  26 #include <asm/mach/map.h>
  27 #include <mach/hardware.h>
  28 #include <asm/irq.h>
  29 #include <asm/suspend.h>
  30 #include <mach/irqs.h>
  31 #include <mach/pxa27x.h>
  32 #include <mach/reset.h>
  33 #include <mach/ohci.h>
  34 #include <mach/pm.h>
  35 #include <mach/dma.h>
  36 #include <mach/smemc.h>
  37
  38 #include "generic.h"
  39 #include "devices.h"
  40 #include "clock.h"
  41
  42 void pxa27x_clear_otgph(void)
  43 {
  44         if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
  45                 PSSR |= PSSR_OTGPH;
  46 }
  47 EXPORT_SYMBOL(pxa27x_clear_otgph);
  48
  49 static unsigned long ac97_reset_config[] = {
  50         GPIO113_GPIO,
  51         GPIO113_AC97_nRESET,
  52         GPIO95_GPIO,
  53         GPIO95_AC97_nRESET,
  54 };
  55
  56 void pxa27x_assert_ac97reset(int reset_gpio, int on)
  57 {
  58         if (reset_gpio == 113)
  59                 pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
  60                                        &ac97_reset_config[1], 1);
  61
  62         if (reset_gpio == 95)
  63                 pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
  64                                        &ac97_reset_config[3], 1);
  65 }
  66 EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
  67
  68 /* Crystal clock: 13MHz */
  69 #define BASE_CLK        13000000
  70
  71 /*
  72  * Get the clock frequency as reflected by CCSR and the turbo flag.
  73  * We assume these values have been applied via a fcs.
  74  * If info is not 0 we also display the current settings.
  75  */
  76 unsigned int pxa27x_get_clk_frequency_khz(int info)
  77 {
  78         unsigned long ccsr, clkcfg;
  79         unsigned int l, L, m, M, n2, N, S;
  80         int cccr_a, t, ht, b;
  81
  82         ccsr = CCSR;
  83         cccr_a = CCCR & (1 << 25);
  84
  85         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
  86         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
  87         t  = clkcfg & (1 << 0);
  88         ht = clkcfg & (1 << 2);
  89         b  = clkcfg & (1 << 3);
  90
  91         l  = ccsr & 0x1f;
  92         n2 = (ccsr>>7) & 0xf;
  93         m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
  94
  95         L  = l * BASE_CLK;
  96         N  = (L * n2) / 2;
  97         M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
  98         S  = (b) ? L : (L/2);
  99
 100         if (info) {
 101                 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
 102                         L / 1000000, (L % 1000000) / 10000, l );
 103                 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
 104                         N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
 105                         (t) ? "" : "in" );
 106                 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
 107                         M / 1000000, (M % 1000000) / 10000, m );
 108                 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
 109                         S / 1000000, (S % 1000000) / 10000 );
 110         }
 111
 112         return (t) ? (N/1000) : (L/1000);
 113 }
 114
 115 /*
 116  * Return the current mem clock frequency as reflected by CCCR[A], B, and L
 117  */
 118 static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
 119 {
 120         unsigned long ccsr, clkcfg;
 121         unsigned int l, L, m, M;
 122         int cccr_a, b;
 123
 124         ccsr = CCSR;
 125         cccr_a = CCCR & (1 << 25);
 126
 127         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
 128         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
 129         b = clkcfg & (1 << 3);
 130
 131         l = ccsr & 0x1f;
 132         m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
 133
 134         L = l * BASE_CLK;
 135         M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
 136
 137         return M;
 138 }
 139
 140 static const struct clkops clk_pxa27x_mem_ops = {
 141         .enable         = clk_dummy_enable,
 142         .disable        = clk_dummy_disable,
 143         .getrate        = clk_pxa27x_mem_getrate,
 144 };
 145
 146 /*
 147  * Return the current LCD clock frequency in units of 10kHz as
 148  */
 149 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
 150 {
 151         unsigned long ccsr;
 152         unsigned int l, L, k, K;
 153
 154         ccsr = CCSR;
 155
 156         l = ccsr & 0x1f;
 157         k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
 158
 159         L = l * BASE_CLK;
 160         K = L / k;
 161
 162         return (K / 10000);
 163 }
 164
 165 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
 166 {
 167         return pxa27x_get_lcdclk_frequency_10khz() * 10000;
 168 }
 169
 170 static const struct clkops clk_pxa27x_lcd_ops = {
 171         .enable         = clk_pxa2xx_cken_enable,
 172         .disable        = clk_pxa2xx_cken_disable,
 173         .getrate        = clk_pxa27x_lcd_getrate,
 174 };
 175
 176 static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
 177 static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
 178 static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
 179 static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
 180 static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
 181 static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
 182 static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
 183 static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
 184 static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
 185 static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
 186 static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
 187 static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
 188 static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
 189 static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
 190 static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
 191 static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
 192 static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
 193 static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
 194 static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
 195 static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
 196 static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
 197 static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
 198 static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
 199
 200 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
 201 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
 202 static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
 203
 204 static struct clk_lookup pxa27x_clkregs[] = {
 205         INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
 206         INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
 207         INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
 208         INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
 209         INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
 210         INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
 211         INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
 212         INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
 213         INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
 214         INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
 215         INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
 216         INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
 217         INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
 218         INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
 219         INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
 220         INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
 221         INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
 222         INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
 223         INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
 224         INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
 225         INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
 226         INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
 227         INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
 228         INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
 229         INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
 230         INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
 231         INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
 232 };
 233
 234 #ifdef CONFIG_PM
 235
 236 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 237 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 238
 239 /*
 240  * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
 241  */
 242 static unsigned int pwrmode = PWRMODE_SLEEP;
 243
 244 int __init pxa27x_set_pwrmode(unsigned int mode)
 245 {
 246         switch (mode) {
 247         case PWRMODE_SLEEP:
 248         case PWRMODE_DEEPSLEEP:
 249                 pwrmode = mode;
 250                 return 0;
 251         }
 252
 253         return -EINVAL;
 254 }
 255
 256 /*
 257  * List of global PXA peripheral registers to preserve.
 258  * More ones like CP and general purpose register values are preserved
 259  * with the stack pointer in sleep.S.
 260  */
 261 enum {
 262         SLEEP_SAVE_PSTR,
 263         SLEEP_SAVE_MDREFR,
 264         SLEEP_SAVE_PCFR,
 265         SLEEP_SAVE_COUNT
 266 };
 267
 268 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
 269 {
 270         sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
 271         SAVE(PCFR);
 272
 273         SAVE(PSTR);
 274 }
 275
 276 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 277 {
 278         __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
 279         RESTORE(PCFR);
 280
 281         PSSR = PSSR_RDH | PSSR_PH;
 282
 283         RESTORE(PSTR);
 284 }
 285
 286 void pxa27x_cpu_pm_enter(suspend_state_t state)
 287 {
 288         extern void pxa_cpu_standby(void);
 289 #ifndef CONFIG_IWMMXT
 290         u64 acc0;
 291
 292         asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
 293 #endif
 294
 295         /* ensure voltage-change sequencer not initiated, which hangs */
 296         PCFR &= ~PCFR_FVC;
 297
 298         /* Clear edge-detect status register. */
 299         PEDR = 0xDF12FE1B;
 300
 301         /* Clear reset status */
 302         RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
 303
 304         switch (state) {
 305         case PM_SUSPEND_STANDBY:
 306                 pxa_cpu_standby();
 307                 break;
 308         case PM_SUSPEND_MEM:
 309                 cpu_suspend(pwrmode, pxa27x_finish_suspend);
 310 #ifndef CONFIG_IWMMXT
 311                 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
 312 #endif
 313                 break;
 314         }
 315 }
 316
 317 static int pxa27x_cpu_pm_valid(suspend_state_t state)
 318 {
 319         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 320 }
 321
 322 static int pxa27x_cpu_pm_prepare(void)
 323 {
 324         /* set resume return address */
 325         PSPR = virt_to_phys(cpu_resume);
 326         return 0;
 327 }
 328
 329 static void pxa27x_cpu_pm_finish(void)
 330 {
 331         /* ensure not to come back here if it wasn't intended */
 332         PSPR = 0;
 333 }
 334
 335 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
 336         .save_count     = SLEEP_SAVE_COUNT,
 337         .save           = pxa27x_cpu_pm_save,
 338         .restore        = pxa27x_cpu_pm_restore,
 339         .valid          = pxa27x_cpu_pm_valid,
 340         .enter          = pxa27x_cpu_pm_enter,
 341         .prepare        = pxa27x_cpu_pm_prepare,
 342         .finish         = pxa27x_cpu_pm_finish,
 343 };
 344
 345 static void __init pxa27x_init_pm(void)
 346 {
 347         pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
 348 }
 349 #else
 350 static inline void pxa27x_init_pm(void) {}
 351 #endif
 352
 353 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
 354  * handles the simple cases, not the WEMUX2 and WEMUX3 options
 355  */
 356 static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
 357 {
 358         int gpio = irq_to_gpio(d->irq);
 359         uint32_t mask;
 360
 361         if (gpio >= 0 && gpio < 128)
 362                 return gpio_set_wake(gpio, on);
 363
 364         if (d->irq == IRQ_KEYPAD)
 365                 return keypad_set_wake(on);
 366
 367         switch (d->irq) {
 368         case IRQ_RTCAlrm:
 369                 mask = PWER_RTC;
 370                 break;
 371         case IRQ_USB:
 372                 mask = 1u << 26;
 373                 break;
 374         default:
 375                 return -EINVAL;
 376         }
 377
 378         if (on)
 379                 PWER |= mask;
 380         else
 381                 PWER &=~mask;
 382
 383         return 0;
 384 }
 385
 386 void __init pxa27x_init_irq(void)
 387 {
 388         pxa_init_irq(34, pxa27x_set_wake);
 389         pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
 390 }
 391
 392 static struct map_desc pxa27x_io_desc[] __initdata = {
 393         {       /* Mem Ctl */
 394                 .virtual        = SMEMC_VIRT,
 395                 .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
 396                 .length         = 0x00200000,
 397                 .type           = MT_DEVICE
 398         }, {    /* IMem ctl */
 399                 .virtual        =  0xfe000000,
 400                 .pfn            = __phys_to_pfn(0x58000000),
 401                 .length         = 0x00100000,
 402                 .type           = MT_DEVICE
 403         },
 404 };
 405
 406 void __init pxa27x_map_io(void)
 407 {
 408         pxa_map_io();
 409         iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
 410         pxa27x_get_clk_frequency_khz(1);
 411 }
 412
 413 /*
 414  * device registration specific to PXA27x.
 415  */
 416 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 417 {
 418         local_irq_disable();
 419         PCFR |= PCFR_PI2CEN;
 420         local_irq_enable();
 421         pxa_register_device(&pxa27x_device_i2c_power, info);
 422 }
 423
 424 static struct platform_device *devices[] __initdata = {
 425         &pxa27x_device_udc,
 426         &pxa_device_pmu,
 427         &pxa_device_i2s,
 428         &pxa_device_asoc_ssp1,
 429         &pxa_device_asoc_ssp2,
 430         &pxa_device_asoc_ssp3,
 431         &pxa_device_asoc_platform,
 432         &sa1100_device_rtc,
 433         &pxa_device_rtc,
 434         &pxa27x_device_ssp1,
 435         &pxa27x_device_ssp2,
 436         &pxa27x_device_ssp3,
 437         &pxa27x_device_pwm0,
 438         &pxa27x_device_pwm1,
 439 };
 440
 441 static int __init pxa27x_init(void)
 442 {
 443         int ret = 0;
 444
 445         if (cpu_is_pxa27x()) {
 446
 447                 reset_status = RCSR;
 448
 449                 clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
 450
 451                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
 452                         return ret;
 453
 454                 pxa27x_init_pm();
 455
 456                 register_syscore_ops(&pxa_irq_syscore_ops);
 457                 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
 458                 register_syscore_ops(&pxa_gpio_syscore_ops);
 459                 register_syscore_ops(&pxa2xx_clock_syscore_ops);
 460
 461                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 462         }
 463
 464         return ret;
 465 }
 466
 467 postcore_initcall(pxa27x_init);