arch/sh/kernel/cpu/sh4/setup-sh7750.c

   1 /*
   2  * SH7750/SH7751 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2006  Jamie Lenehan
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/io.h>
  15 #include <asm/sci.h>
  16
  17 static struct resource rtc_resources[] = {
  18         [0] = {
  19                 .start  = 0xffc80000,
  20                 .end    = 0xffc80000 + 0x58 - 1,
  21                 .flags  = IORESOURCE_IO,
  22         },
  23         [1] = {
  24                 /* Period IRQ */
  25                 .start  = 21,
  26                 .flags  = IORESOURCE_IRQ,
  27         },
  28         [2] = {
  29                 /* Carry IRQ */
  30                 .start  = 22,
  31                 .flags  = IORESOURCE_IRQ,
  32         },
  33         [3] = {
  34                 /* Alarm IRQ */
  35                 .start  = 20,
  36                 .flags  = IORESOURCE_IRQ,
  37         },
  38 };
  39
  40 static struct platform_device rtc_device = {
  41         .name           = "sh-rtc",
  42         .id             = -1,
  43         .num_resources  = ARRAY_SIZE(rtc_resources),
  44         .resource       = rtc_resources,
  45 };
  46
  47 static struct plat_sci_port sci_platform_data[] = {
  48         {
  49                 .mapbase        = 0xffe00000,
  50                 .flags          = UPF_BOOT_AUTOCONF,
  51                 .type           = PORT_SCI,
  52                 .irqs           = { 23, 24, 25, 0 },
  53         }, {
  54                 .mapbase        = 0xffe80000,
  55                 .flags          = UPF_BOOT_AUTOCONF,
  56                 .type           = PORT_SCIF,
  57                 .irqs           = { 40, 41, 43, 42 },
  58         }, {
  59                 .flags = 0,
  60         }
  61 };
  62
  63 static struct platform_device sci_device = {
  64         .name           = "sh-sci",
  65         .id             = -1,
  66         .dev            = {
  67                 .platform_data  = sci_platform_data,
  68         },
  69 };
  70
  71 static struct platform_device *sh7750_devices[] __initdata = {
  72         &rtc_device,
  73         &sci_device,
  74 };
  75
  76 static int __init sh7750_devices_setup(void)
  77 {
  78         return platform_add_devices(sh7750_devices,
  79                                     ARRAY_SIZE(sh7750_devices));
  80 }
  81 __initcall(sh7750_devices_setup);
  82
  83 static struct ipr_data sh7750_ipr_map[] = {
  84         /* IRQ, IPR-idx, shift, priority */
  85         { 16, 0, 12, 2 }, /* TMU0 TUNI*/
  86         { 17, 0, 12, 2 }, /* TMU1 TUNI */
  87         { 18, 0,  4, 2 }, /* TMU2 TUNI */
  88         { 19, 0,  4, 2 }, /* TMU2 TIPCI */
  89         { 27, 1, 12, 2 }, /* WDT ITI */
  90         { 20, 0,  0, 2 }, /* RTC ATI (alarm) */
  91         { 21, 0,  0, 2 }, /* RTC PRI (period) */
  92         { 22, 0,  0, 2 }, /* RTC CUI (carry) */
  93         { 23, 1,  4, 3 }, /* SCI ERI */
  94         { 24, 1,  4, 3 }, /* SCI RXI */
  95         { 25, 1,  4, 3 }, /* SCI TXI */
  96         { 40, 2,  4, 3 }, /* SCIF ERI */
  97         { 41, 2,  4, 3 }, /* SCIF RXI */
  98         { 42, 2,  4, 3 }, /* SCIF BRI */
  99         { 43, 2,  4, 3 }, /* SCIF TXI */
 100         { 34, 2,  8, 7 }, /* DMAC DMTE0 */
 101         { 35, 2,  8, 7 }, /* DMAC DMTE1 */
 102         { 36, 2,  8, 7 }, /* DMAC DMTE2 */
 103         { 37, 2,  8, 7 }, /* DMAC DMTE3 */
 104         { 38, 2,  8, 7 }, /* DMAC DMAE */
 105 };
 106
 107 static struct ipr_data sh7751_ipr_map[] = {
 108         { 44, 2,  8, 7 }, /* DMAC DMTE4 */
 109         { 45, 2,  8, 7 }, /* DMAC DMTE5 */
 110         { 46, 2,  8, 7 }, /* DMAC DMTE6 */
 111         { 47, 2,  8, 7 }, /* DMAC DMTE7 */
 112         /* The following use INTC_INPRI00 for masking, which is a 32-bit
 113            register, not a 16-bit register like the IPRx registers, so it
 114            would need special support */
 115         /*{ 72, INTPRI00,  8, ? },*/ /* TMU3 TUNI */
 116         /*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */
 117 };
 118
 119 static unsigned long ipr_offsets[] = {
 120         0xffd00004UL,   /* 0: IPRA */
 121         0xffd00008UL,   /* 1: IPRB */
 122         0xffd0000cUL,   /* 2: IPRC */
 123         0xffd00010UL,   /* 3: IPRD */
 124 };
 125
 126 /* given the IPR index return the address of the IPR register */
 127 unsigned int map_ipridx_to_addr(int idx)
 128 {
 129         if (idx >= ARRAY_SIZE(ipr_offsets))
 130                 return 0;
 131         return ipr_offsets[idx];
 132 }
 133
 134 #define INTC_ICR        0xffd00000UL
 135 #define INTC_ICR_IRLM   (1<<7)
 136
 137 /* enable individual interrupt mode for external interupts */
 138 void ipr_irq_enable_irlm(void)
 139 {
 140         ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 141 }
 142
 143 void __init init_IRQ_ipr()
 144 {
 145         make_ipr_irq(sh7750_ipr_map, ARRAY_SIZE(sh7750_ipr_map));
 146 #ifdef CONFIG_CPU_SUBTYPE_SH7751
 147         make_ipr_irq(sh7751_ipr_map, ARRAY_SIZE(sh7751_ipr_map));
 148 #endif
 149 }