include/asm-powerpc/dma-mapping.h

   1 /*
   2  * Copyright (C) 2004 IBM
   3  *
   4  * Implements the generic device dma API for powerpc.
   5  * the pci and vio busses
   6  */
   7 #ifndef _ASM_DMA_MAPPING_H
   8 #define _ASM_DMA_MAPPING_H
   9 #ifdef __KERNEL__
  10
  11 #include <linux/types.h>
  12 #include <linux/cache.h>
  13 /* need struct page definitions */
  14 #include <linux/mm.h>
  15 #include <asm/scatterlist.h>
  16 #include <asm/io.h>
  17
  18 #define DMA_ERROR_CODE          (~(dma_addr_t)0x0)
  19
  20 #ifdef CONFIG_NOT_COHERENT_CACHE
  21 /*
  22  * DMA-consistent mapping functions for PowerPCs that don't support
  23  * cache snooping.  These allocate/free a region of uncached mapped
  24  * memory space for use with DMA devices.  Alternatively, you could
  25  * allocate the space "normally" and use the cache management functions
  26  * to ensure it is consistent.
  27  */
  28 extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp);
  29 extern void __dma_free_coherent(size_t size, void *vaddr);
  30 extern void __dma_sync(void *vaddr, size_t size, int direction);
  31 extern void __dma_sync_page(struct page *page, unsigned long offset,
  32                                  size_t size, int direction);
  33
  34 #else /* ! CONFIG_NOT_COHERENT_CACHE */
  35 /*
  36  * Cache coherent cores.
  37  */
  38
  39 #define __dma_alloc_coherent(gfp, size, handle) NULL
  40 #define __dma_free_coherent(size, addr)         do { } while (0)
  41 #define __dma_sync(addr, size, rw)              do { } while (0)
  42 #define __dma_sync_page(pg, off, sz, rw)        do { } while (0)
  43
  44 #endif /* ! CONFIG_NOT_COHERENT_CACHE */
  45
  46 #ifdef CONFIG_PPC64
  47
  48 extern int dma_supported(struct device *dev, u64 mask);
  49 extern int dma_set_mask(struct device *dev, u64 dma_mask);
  50 extern void *dma_alloc_coherent(struct device *dev, size_t size,
  51                 dma_addr_t *dma_handle, gfp_t flag);
  52 extern void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
  53                 dma_addr_t dma_handle);
  54 extern dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
  55                 size_t size, enum dma_data_direction direction);
  56 extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
  57                 size_t size, enum dma_data_direction direction);
  58 extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
  59                 unsigned long offset, size_t size,
  60                 enum dma_data_direction direction);
  61 extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
  62                 size_t size, enum dma_data_direction direction);
  63 extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
  64                 enum dma_data_direction direction);
  65 extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
  66                 int nhwentries, enum dma_data_direction direction);
  67
  68 #else /* CONFIG_PPC64 */
  69
  70 #define dma_supported(dev, mask)        (1)
  71
  72 static inline int dma_set_mask(struct device *dev, u64 dma_mask)
  73 {
  74         if (!dev->dma_mask || !dma_supported(dev, mask))
  75                 return -EIO;
  76
  77         *dev->dma_mask = dma_mask;
  78
  79         return 0;
  80 }
  81
  82 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
  83                                        dma_addr_t * dma_handle,
  84                                        gfp_t gfp)
  85 {
  86 #ifdef CONFIG_NOT_COHERENT_CACHE
  87         return __dma_alloc_coherent(size, dma_handle, gfp);
  88 #else
  89         void *ret;
  90         /* ignore region specifiers */
  91         gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
  92
  93         if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
  94                 gfp |= GFP_DMA;
  95
  96         ret = (void *)__get_free_pages(gfp, get_order(size));
  97
  98         if (ret != NULL) {
  99                 memset(ret, 0, size);
 100                 *dma_handle = virt_to_bus(ret);
 101         }
 102
 103         return ret;
 104 #endif
 105 }
 106
 107 static inline void
 108 dma_free_coherent(struct device *dev, size_t size, void *vaddr,
 109                   dma_addr_t dma_handle)
 110 {
 111 #ifdef CONFIG_NOT_COHERENT_CACHE
 112         __dma_free_coherent(size, vaddr);
 113 #else
 114         free_pages((unsigned long)vaddr, get_order(size));
 115 #endif
 116 }
 117
 118 static inline dma_addr_t
 119 dma_map_single(struct device *dev, void *ptr, size_t size,
 120                enum dma_data_direction direction)
 121 {
 122         BUG_ON(direction == DMA_NONE);
 123
 124         __dma_sync(ptr, size, direction);
 125
 126         return virt_to_bus(ptr);
 127 }
 128
 129 /* We do nothing. */
 130 #define dma_unmap_single(dev, addr, size, dir)  do { } while (0)
 131
 132 static inline dma_addr_t
 133 dma_map_page(struct device *dev, struct page *page,
 134              unsigned long offset, size_t size,
 135              enum dma_data_direction direction)
 136 {
 137         BUG_ON(direction == DMA_NONE);
 138
 139         __dma_sync_page(page, offset, size, direction);
 140
 141         return page_to_bus(page) + offset;
 142 }
 143
 144 /* We do nothing. */
 145 #define dma_unmap_page(dev, handle, size, dir)  do { } while (0)
 146
 147 static inline int
 148 dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 149            enum dma_data_direction direction)
 150 {
 151         int i;
 152
 153         BUG_ON(direction == DMA_NONE);
 154
 155         for (i = 0; i < nents; i++, sg++) {
 156                 BUG_ON(!sg->page);
 157                 __dma_sync_page(sg->page, sg->offset, sg->length, direction);
 158                 sg->dma_address = page_to_bus(sg->page) + sg->offset;
 159         }
 160
 161         return nents;
 162 }
 163
 164 /* We don't do anything here. */
 165 #define dma_unmap_sg(dev, sg, nents, dir)       do { } while (0)
 166
 167 #endif /* CONFIG_PPC64 */
 168
 169 static inline void dma_sync_single_for_cpu(struct device *dev,
 170                 dma_addr_t dma_handle, size_t size,
 171                 enum dma_data_direction direction)
 172 {
 173         BUG_ON(direction == DMA_NONE);
 174         __dma_sync(bus_to_virt(dma_handle), size, direction);
 175 }
 176
 177 static inline void dma_sync_single_for_device(struct device *dev,
 178                 dma_addr_t dma_handle, size_t size,
 179                 enum dma_data_direction direction)
 180 {
 181         BUG_ON(direction == DMA_NONE);
 182         __dma_sync(bus_to_virt(dma_handle), size, direction);
 183 }
 184
 185 static inline void dma_sync_sg_for_cpu(struct device *dev,
 186                 struct scatterlist *sg, int nents,
 187                 enum dma_data_direction direction)
 188 {
 189         int i;
 190
 191         BUG_ON(direction == DMA_NONE);
 192
 193         for (i = 0; i < nents; i++, sg++)
 194                 __dma_sync_page(sg->page, sg->offset, sg->length, direction);
 195 }
 196
 197 static inline void dma_sync_sg_for_device(struct device *dev,
 198                 struct scatterlist *sg, int nents,
 199                 enum dma_data_direction direction)
 200 {
 201         int i;
 202
 203         BUG_ON(direction == DMA_NONE);
 204
 205         for (i = 0; i < nents; i++, sg++)
 206                 __dma_sync_page(sg->page, sg->offset, sg->length, direction);
 207 }
 208
 209 static inline int dma_mapping_error(dma_addr_t dma_addr)
 210 {
 211 #ifdef CONFIG_PPC64
 212         return (dma_addr == DMA_ERROR_CODE);
 213 #else
 214         return 0;
 215 #endif
 216 }
 217
 218 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 219 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
 220 #ifdef CONFIG_NOT_COHERENT_CACHE
 221 #define dma_is_consistent(d)    (0)
 222 #else
 223 #define dma_is_consistent(d)    (1)
 224 #endif
 225
 226 static inline int dma_get_cache_alignment(void)
 227 {
 228 #ifdef CONFIG_PPC64
 229         /* no easy way to get cache size on all processors, so return
 230          * the maximum possible, to be safe */
 231         return (1 << INTERNODE_CACHE_SHIFT);
 232 #else
 233         /*
 234          * Each processor family will define its own L1_CACHE_SHIFT,
 235          * L1_CACHE_BYTES wraps to this, so this is always safe.
 236          */
 237         return L1_CACHE_BYTES;
 238 #endif
 239 }
 240
 241 static inline void dma_sync_single_range_for_cpu(struct device *dev,
 242                 dma_addr_t dma_handle, unsigned long offset, size_t size,
 243                 enum dma_data_direction direction)
 244 {
 245         /* just sync everything for now */
 246         dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
 247 }
 248
 249 static inline void dma_sync_single_range_for_device(struct device *dev,
 250                 dma_addr_t dma_handle, unsigned long offset, size_t size,
 251                 enum dma_data_direction direction)
 252 {
 253         /* just sync everything for now */
 254         dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
 255 }
 256
 257 static inline void dma_cache_sync(void *vaddr, size_t size,
 258                 enum dma_data_direction direction)
 259 {
 260         BUG_ON(direction == DMA_NONE);
 261         __dma_sync(vaddr, size, (int)direction);
 262 }
 263
 264 /*
 265  * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
 266  */
 267 struct dma_mapping_ops {
 268         void *          (*alloc_coherent)(struct device *dev, size_t size,
 269                                 dma_addr_t *dma_handle, gfp_t flag);
 270         void            (*free_coherent)(struct device *dev, size_t size,
 271                                 void *vaddr, dma_addr_t dma_handle);
 272         dma_addr_t      (*map_single)(struct device *dev, void *ptr,
 273                                 size_t size, enum dma_data_direction direction);
 274         void            (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
 275                                 size_t size, enum dma_data_direction direction);
 276         int             (*map_sg)(struct device *dev, struct scatterlist *sg,
 277                                 int nents, enum dma_data_direction direction);
 278         void            (*unmap_sg)(struct device *dev, struct scatterlist *sg,
 279                                 int nents, enum dma_data_direction direction);
 280         int             (*dma_supported)(struct device *dev, u64 mask);
 281         int             (*dac_dma_supported)(struct device *dev, u64 mask);
 282 };
 283
 284 #endif /* __KERNEL__ */
 285 #endif  /* _ASM_DMA_MAPPING_H */