2 * Support for IDE interfaces on Celleb platform
4 * (C) Copyright 2006 TOSHIBA CORPORATION
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/init.h>
32 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
34 #define SCC_PATA_NAME "scc IDE"
36 #define TDVHSEL_MASTER 0x00000001
37 #define TDVHSEL_SLAVE 0x00000004
39 #define MODE_JCUSFEN 0x00000080
41 #define CCKCTRL_ATARESET 0x00040000
42 #define CCKCTRL_BUFCNT 0x00020000
43 #define CCKCTRL_CRST 0x00010000
44 #define CCKCTRL_OCLKEN 0x00000100
45 #define CCKCTRL_ATACLKOEN 0x00000002
46 #define CCKCTRL_LCLKEN 0x00000001
48 #define QCHCD_IOS_SS 0x00000001
50 #define QCHSD_STPDIAG 0x00020000
52 #define INTMASK_MSK 0xD1000012
53 #define INTSTS_SERROR 0x80000000
54 #define INTSTS_PRERR 0x40000000
55 #define INTSTS_RERR 0x10000000
56 #define INTSTS_ICERR 0x01000000
57 #define INTSTS_BMSINT 0x00000010
58 #define INTSTS_BMHE 0x00000008
59 #define INTSTS_IOIRQS 0x00000004
60 #define INTSTS_INTRQ 0x00000002
61 #define INTSTS_ACTEINT 0x00000001
63 #define ECMODE_VALUE 0x01
65 static struct scc_ports
{
66 unsigned long ctl
, dma
;
67 struct ide_host
*host
; /* for removing port from system */
68 } scc_ports
[MAX_HWIFS
];
70 /* PIO transfer mode table */
72 static unsigned long JCHSTtbl
[2][7] = {
73 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
74 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
78 static unsigned long JCHHTtbl
[2][7] = {
79 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
80 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
84 static unsigned long JCHCTtbl
[2][7] = {
85 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
86 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
90 /* DMA transfer mode table */
92 static unsigned long JCHDCTxtbl
[2][7] = {
93 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
94 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
98 static unsigned long JCSTWTxtbl
[2][7] = {
99 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
100 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
104 static unsigned long JCTSStbl
[2][7] = {
105 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
110 static unsigned long JCENVTtbl
[2][7] = {
111 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
112 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
115 /* JCACTSELS/JCACTSELM */
116 static unsigned long JCACTSELtbl
[2][7] = {
117 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
118 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
122 static u8
scc_ide_inb(unsigned long port
)
124 u32 data
= in_be32((void*)port
);
128 static void scc_exec_command(ide_hwif_t
*hwif
, u8 cmd
)
130 out_be32((void *)hwif
->io_ports
.command_addr
, cmd
);
132 in_be32((void *)(hwif
->dma_base
+ 0x01c));
136 static u8
scc_read_status(ide_hwif_t
*hwif
)
138 return (u8
)in_be32((void *)hwif
->io_ports
.status_addr
);
141 static u8
scc_read_altstatus(ide_hwif_t
*hwif
)
143 return (u8
)in_be32((void *)hwif
->io_ports
.ctl_addr
);
146 static u8
scc_dma_sff_read_status(ide_hwif_t
*hwif
)
148 return (u8
)in_be32((void *)(hwif
->dma_base
+ 4));
151 static void scc_write_devctl(ide_hwif_t
*hwif
, u8 ctl
)
153 out_be32((void *)hwif
->io_ports
.ctl_addr
, ctl
);
155 in_be32((void *)(hwif
->dma_base
+ 0x01c));
159 static void scc_ide_insw(unsigned long port
, void *addr
, u32 count
)
161 u16
*ptr
= (u16
*)addr
;
163 *ptr
++ = le16_to_cpu(in_be32((void*)port
));
167 static void scc_ide_insl(unsigned long port
, void *addr
, u32 count
)
169 u16
*ptr
= (u16
*)addr
;
171 *ptr
++ = le16_to_cpu(in_be32((void*)port
));
172 *ptr
++ = le16_to_cpu(in_be32((void*)port
));
176 static void scc_ide_outb(u8 addr
, unsigned long port
)
178 out_be32((void*)port
, addr
);
182 scc_ide_outsw(unsigned long port
, void *addr
, u32 count
)
184 u16
*ptr
= (u16
*)addr
;
186 out_be32((void*)port
, cpu_to_le16(*ptr
++));
191 scc_ide_outsl(unsigned long port
, void *addr
, u32 count
)
193 u16
*ptr
= (u16
*)addr
;
195 out_be32((void*)port
, cpu_to_le16(*ptr
++));
196 out_be32((void*)port
, cpu_to_le16(*ptr
++));
201 * scc_set_pio_mode - set host controller for PIO mode
203 * @pio: PIO mode number
205 * Load the timing settings for this device mode into the
209 static void scc_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
211 ide_hwif_t
*hwif
= drive
->hwif
;
212 struct scc_ports
*ports
= ide_get_hwifdata(hwif
);
213 unsigned long ctl_base
= ports
->ctl
;
214 unsigned long cckctrl_port
= ctl_base
+ 0xff0;
215 unsigned long piosht_port
= ctl_base
+ 0x000;
216 unsigned long pioct_port
= ctl_base
+ 0x004;
220 reg
= in_be32((void __iomem
*)cckctrl_port
);
221 if (reg
& CCKCTRL_ATACLKOEN
) {
222 offset
= 1; /* 133MHz */
224 offset
= 0; /* 100MHz */
226 reg
= JCHSTtbl
[offset
][pio
] << 16 | JCHHTtbl
[offset
][pio
];
227 out_be32((void __iomem
*)piosht_port
, reg
);
228 reg
= JCHCTtbl
[offset
][pio
];
229 out_be32((void __iomem
*)pioct_port
, reg
);
233 * scc_set_dma_mode - set host controller for DMA mode
237 * Load the timing settings for this device mode into the
241 static void scc_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
243 ide_hwif_t
*hwif
= drive
->hwif
;
244 struct scc_ports
*ports
= ide_get_hwifdata(hwif
);
245 unsigned long ctl_base
= ports
->ctl
;
246 unsigned long cckctrl_port
= ctl_base
+ 0xff0;
247 unsigned long mdmact_port
= ctl_base
+ 0x008;
248 unsigned long mcrcst_port
= ctl_base
+ 0x00c;
249 unsigned long sdmact_port
= ctl_base
+ 0x010;
250 unsigned long scrcst_port
= ctl_base
+ 0x014;
251 unsigned long udenvt_port
= ctl_base
+ 0x018;
252 unsigned long tdvhsel_port
= ctl_base
+ 0x020;
253 int is_slave
= drive
->dn
& 1;
256 unsigned long jcactsel
;
258 reg
= in_be32((void __iomem
*)cckctrl_port
);
259 if (reg
& CCKCTRL_ATACLKOEN
) {
260 offset
= 1; /* 133MHz */
262 offset
= 0; /* 100MHz */
265 idx
= speed
- XFER_UDMA_0
;
267 jcactsel
= JCACTSELtbl
[offset
][idx
];
269 out_be32((void __iomem
*)sdmact_port
, JCHDCTxtbl
[offset
][idx
]);
270 out_be32((void __iomem
*)scrcst_port
, JCSTWTxtbl
[offset
][idx
]);
271 jcactsel
= jcactsel
<< 2;
272 out_be32((void __iomem
*)tdvhsel_port
, (in_be32((void __iomem
*)tdvhsel_port
) & ~TDVHSEL_SLAVE
) | jcactsel
);
274 out_be32((void __iomem
*)mdmact_port
, JCHDCTxtbl
[offset
][idx
]);
275 out_be32((void __iomem
*)mcrcst_port
, JCSTWTxtbl
[offset
][idx
]);
276 out_be32((void __iomem
*)tdvhsel_port
, (in_be32((void __iomem
*)tdvhsel_port
) & ~TDVHSEL_MASTER
) | jcactsel
);
278 reg
= JCTSStbl
[offset
][idx
] << 16 | JCENVTtbl
[offset
][idx
];
279 out_be32((void __iomem
*)udenvt_port
, reg
);
282 static void scc_dma_host_set(ide_drive_t
*drive
, int on
)
284 ide_hwif_t
*hwif
= drive
->hwif
;
285 u8 unit
= drive
->dn
& 1;
286 u8 dma_stat
= scc_dma_sff_read_status(hwif
);
289 dma_stat
|= (1 << (5 + unit
));
291 dma_stat
&= ~(1 << (5 + unit
));
293 scc_ide_outb(dma_stat
, hwif
->dma_base
+ 4);
297 * scc_dma_setup - begin a DMA phase
298 * @drive: target device
301 * Build an IDE DMA PRD (IDE speak for scatter gather table)
302 * and then set up the DMA transfer registers.
304 * Returns 0 on success. If a PIO fallback is required then 1
308 static int scc_dma_setup(ide_drive_t
*drive
, struct ide_cmd
*cmd
)
310 ide_hwif_t
*hwif
= drive
->hwif
;
311 u32 rw
= (cmd
->tf_flags
& IDE_TFLAG_WRITE
) ? 0 : ATA_DMA_WR
;
314 /* fall back to pio! */
315 if (ide_build_dmatable(drive
, cmd
) == 0)
319 out_be32((void __iomem
*)(hwif
->dma_base
+ 8), hwif
->dmatable_dma
);
322 out_be32((void __iomem
*)hwif
->dma_base
, rw
);
324 /* read DMA status for INTR & ERROR flags */
325 dma_stat
= scc_dma_sff_read_status(hwif
);
327 /* clear INTR & ERROR flags */
328 out_be32((void __iomem
*)(hwif
->dma_base
+ 4), dma_stat
| 6);
333 static void scc_dma_start(ide_drive_t
*drive
)
335 ide_hwif_t
*hwif
= drive
->hwif
;
336 u8 dma_cmd
= scc_ide_inb(hwif
->dma_base
);
339 scc_ide_outb(dma_cmd
| 1, hwif
->dma_base
);
343 static int __scc_dma_end(ide_drive_t
*drive
)
345 ide_hwif_t
*hwif
= drive
->hwif
;
346 u8 dma_stat
, dma_cmd
;
348 /* get DMA command mode */
349 dma_cmd
= scc_ide_inb(hwif
->dma_base
);
351 scc_ide_outb(dma_cmd
& ~1, hwif
->dma_base
);
353 dma_stat
= scc_dma_sff_read_status(hwif
);
354 /* clear the INTR & ERROR bits */
355 scc_ide_outb(dma_stat
| 6, hwif
->dma_base
+ 4);
356 /* verify good DMA status */
358 return (dma_stat
& 7) != 4 ? (0x10 | dma_stat
) : 0;
362 * scc_dma_end - Stop DMA
365 * Check and clear INT Status register.
366 * Then call __scc_dma_end().
369 static int scc_dma_end(ide_drive_t
*drive
)
371 ide_hwif_t
*hwif
= drive
->hwif
;
372 void __iomem
*dma_base
= (void __iomem
*)hwif
->dma_base
;
373 unsigned long intsts_port
= hwif
->dma_base
+ 0x014;
375 int dma_stat
, data_loss
= 0;
376 static int retry
= 0;
378 /* errata A308 workaround: Step5 (check data loss) */
379 /* We don't check non ide_disk because it is limited to UDMA4 */
380 if (!(in_be32((void __iomem
*)hwif
->io_ports
.ctl_addr
)
382 drive
->media
== ide_disk
&& drive
->current_speed
> XFER_UDMA_4
) {
383 reg
= in_be32((void __iomem
*)intsts_port
);
384 if (!(reg
& INTSTS_ACTEINT
)) {
385 printk(KERN_WARNING
"%s: operation failed (transfer data loss)\n",
389 struct request
*rq
= hwif
->rq
;
393 /* ERROR_RESET and drive->crc_count are needed
394 * to reduce DMA transfer mode in retry process.
397 rq
->errors
|= ERROR_RESET
;
399 ide_port_for_each_dev(i
, drive
, hwif
)
406 reg
= in_be32((void __iomem
*)intsts_port
);
408 if (reg
& INTSTS_SERROR
) {
409 printk(KERN_WARNING
"%s: SERROR\n", SCC_PATA_NAME
);
410 out_be32((void __iomem
*)intsts_port
, INTSTS_SERROR
|INTSTS_BMSINT
);
412 out_be32(dma_base
, in_be32(dma_base
) & ~QCHCD_IOS_SS
);
416 if (reg
& INTSTS_PRERR
) {
418 unsigned long ctl_base
= hwif
->config_data
;
420 maea0
= in_be32((void __iomem
*)(ctl_base
+ 0xF50));
421 maec0
= in_be32((void __iomem
*)(ctl_base
+ 0xF54));
423 printk(KERN_WARNING
"%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME
, maea0
, maec0
);
425 out_be32((void __iomem
*)intsts_port
, INTSTS_PRERR
|INTSTS_BMSINT
);
427 out_be32(dma_base
, in_be32(dma_base
) & ~QCHCD_IOS_SS
);
431 if (reg
& INTSTS_RERR
) {
432 printk(KERN_WARNING
"%s: Response Error\n", SCC_PATA_NAME
);
433 out_be32((void __iomem
*)intsts_port
, INTSTS_RERR
|INTSTS_BMSINT
);
435 out_be32(dma_base
, in_be32(dma_base
) & ~QCHCD_IOS_SS
);
439 if (reg
& INTSTS_ICERR
) {
440 out_be32(dma_base
, in_be32(dma_base
) & ~QCHCD_IOS_SS
);
442 printk(KERN_WARNING
"%s: Illegal Configuration\n", SCC_PATA_NAME
);
443 out_be32((void __iomem
*)intsts_port
, INTSTS_ICERR
|INTSTS_BMSINT
);
447 if (reg
& INTSTS_BMSINT
) {
448 printk(KERN_WARNING
"%s: Internal Bus Error\n", SCC_PATA_NAME
);
449 out_be32((void __iomem
*)intsts_port
, INTSTS_BMSINT
);
455 if (reg
& INTSTS_BMHE
) {
456 out_be32((void __iomem
*)intsts_port
, INTSTS_BMHE
);
460 if (reg
& INTSTS_ACTEINT
) {
461 out_be32((void __iomem
*)intsts_port
, INTSTS_ACTEINT
);
465 if (reg
& INTSTS_IOIRQS
) {
466 out_be32((void __iomem
*)intsts_port
, INTSTS_IOIRQS
);
472 dma_stat
= __scc_dma_end(drive
);
474 dma_stat
|= 2; /* emulate DMA error (to retry command) */
478 /* returns 1 if dma irq issued, 0 otherwise */
479 static int scc_dma_test_irq(ide_drive_t
*drive
)
481 ide_hwif_t
*hwif
= drive
->hwif
;
482 u32 int_stat
= in_be32((void __iomem
*)hwif
->dma_base
+ 0x014);
484 /* SCC errata A252,A308 workaround: Step4 */
485 if ((in_be32((void __iomem
*)hwif
->io_ports
.ctl_addr
)
487 (int_stat
& INTSTS_INTRQ
))
490 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
491 if (int_stat
& INTSTS_IOIRQS
)
497 static u8
scc_udma_filter(ide_drive_t
*drive
)
499 ide_hwif_t
*hwif
= drive
->hwif
;
500 u8 mask
= hwif
->ultra_mask
;
502 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
503 if ((drive
->media
!= ide_disk
) && (mask
& 0xE0)) {
504 printk(KERN_INFO
"%s: limit %s to UDMA4\n",
505 SCC_PATA_NAME
, drive
->name
);
513 * setup_mmio_scc - map CTRL/BMID region
514 * @dev: PCI device we are configuring
519 static int setup_mmio_scc (struct pci_dev
*dev
, const char *name
)
521 void __iomem
*ctl_addr
;
522 void __iomem
*dma_addr
;
525 for (i
= 0; i
< MAX_HWIFS
; i
++) {
526 if (scc_ports
[i
].ctl
== 0)
532 ret
= pci_request_selected_regions(dev
, (1 << 2) - 1, name
);
534 printk(KERN_ERR
"%s: can't reserve resources\n", name
);
538 ctl_addr
= pci_ioremap_bar(dev
, 0);
542 dma_addr
= pci_ioremap_bar(dev
, 1);
547 scc_ports
[i
].ctl
= (unsigned long)ctl_addr
;
548 scc_ports
[i
].dma
= (unsigned long)dma_addr
;
549 pci_set_drvdata(dev
, (void *) &scc_ports
[i
]);
559 static int scc_ide_setup_pci_device(struct pci_dev
*dev
,
560 const struct ide_port_info
*d
)
562 struct scc_ports
*ports
= pci_get_drvdata(dev
);
563 struct ide_host
*host
;
564 hw_regs_t hw
, *hws
[] = { &hw
, NULL
, NULL
, NULL
};
567 memset(&hw
, 0, sizeof(hw
));
568 for (i
= 0; i
<= 8; i
++)
569 hw
.io_ports_array
[i
] = ports
->dma
+ 0x20 + i
* 4;
572 hw
.chipset
= ide_pci
;
574 rc
= ide_host_add(d
, hws
, &host
);
584 * init_setup_scc - set up an SCC PATA Controller
588 * Perform the initial set up for this device.
591 static int __devinit
init_setup_scc(struct pci_dev
*dev
,
592 const struct ide_port_info
*d
)
594 unsigned long ctl_base
;
595 unsigned long dma_base
;
596 unsigned long cckctrl_port
;
597 unsigned long intmask_port
;
598 unsigned long mode_port
;
599 unsigned long ecmode_port
;
601 struct scc_ports
*ports
;
604 rc
= pci_enable_device(dev
);
608 rc
= setup_mmio_scc(dev
, d
->name
);
612 ports
= pci_get_drvdata(dev
);
613 ctl_base
= ports
->ctl
;
614 dma_base
= ports
->dma
;
615 cckctrl_port
= ctl_base
+ 0xff0;
616 intmask_port
= dma_base
+ 0x010;
617 mode_port
= ctl_base
+ 0x024;
618 ecmode_port
= ctl_base
+ 0xf00;
620 /* controller initialization */
622 out_be32((void*)cckctrl_port
, reg
);
623 reg
|= CCKCTRL_ATACLKOEN
;
624 out_be32((void*)cckctrl_port
, reg
);
625 reg
|= CCKCTRL_LCLKEN
| CCKCTRL_OCLKEN
;
626 out_be32((void*)cckctrl_port
, reg
);
628 out_be32((void*)cckctrl_port
, reg
);
631 reg
= in_be32((void*)cckctrl_port
);
632 if (reg
& CCKCTRL_CRST
)
637 reg
|= CCKCTRL_ATARESET
;
638 out_be32((void*)cckctrl_port
, reg
);
640 out_be32((void*)ecmode_port
, ECMODE_VALUE
);
641 out_be32((void*)mode_port
, MODE_JCUSFEN
);
642 out_be32((void*)intmask_port
, INTMASK_MSK
);
644 rc
= scc_ide_setup_pci_device(dev
, d
);
650 static void scc_tf_load(ide_drive_t
*drive
, struct ide_cmd
*cmd
)
652 struct ide_io_ports
*io_ports
= &drive
->hwif
->io_ports
;
653 struct ide_taskfile
*tf
= &cmd
->tf
;
654 u8 HIHI
= (cmd
->tf_flags
& IDE_TFLAG_LBA48
) ? 0xE0 : 0xEF;
656 if (cmd
->ftf_flags
& IDE_FTFLAG_FLAGGED
)
659 if (cmd
->tf_flags
& IDE_TFLAG_OUT_HOB_FEATURE
)
660 scc_ide_outb(tf
->hob_feature
, io_ports
->feature_addr
);
661 if (cmd
->tf_flags
& IDE_TFLAG_OUT_HOB_NSECT
)
662 scc_ide_outb(tf
->hob_nsect
, io_ports
->nsect_addr
);
663 if (cmd
->tf_flags
& IDE_TFLAG_OUT_HOB_LBAL
)
664 scc_ide_outb(tf
->hob_lbal
, io_ports
->lbal_addr
);
665 if (cmd
->tf_flags
& IDE_TFLAG_OUT_HOB_LBAM
)
666 scc_ide_outb(tf
->hob_lbam
, io_ports
->lbam_addr
);
667 if (cmd
->tf_flags
& IDE_TFLAG_OUT_HOB_LBAH
)
668 scc_ide_outb(tf
->hob_lbah
, io_ports
->lbah_addr
);
670 if (cmd
->tf_flags
& IDE_TFLAG_OUT_FEATURE
)
671 scc_ide_outb(tf
->feature
, io_ports
->feature_addr
);
672 if (cmd
->tf_flags
& IDE_TFLAG_OUT_NSECT
)
673 scc_ide_outb(tf
->nsect
, io_ports
->nsect_addr
);
674 if (cmd
->tf_flags
& IDE_TFLAG_OUT_LBAL
)
675 scc_ide_outb(tf
->lbal
, io_ports
->lbal_addr
);
676 if (cmd
->tf_flags
& IDE_TFLAG_OUT_LBAM
)
677 scc_ide_outb(tf
->lbam
, io_ports
->lbam_addr
);
678 if (cmd
->tf_flags
& IDE_TFLAG_OUT_LBAH
)
679 scc_ide_outb(tf
->lbah
, io_ports
->lbah_addr
);
681 if (cmd
->tf_flags
& IDE_TFLAG_OUT_DEVICE
)
682 scc_ide_outb((tf
->device
& HIHI
) | drive
->select
,
683 io_ports
->device_addr
);
686 static void scc_tf_read(ide_drive_t
*drive
, struct ide_cmd
*cmd
)
688 struct ide_io_ports
*io_ports
= &drive
->hwif
->io_ports
;
689 struct ide_taskfile
*tf
= &cmd
->tf
;
691 /* be sure we're looking at the low order bits */
692 scc_ide_outb(ATA_DEVCTL_OBS
, io_ports
->ctl_addr
);
694 if (cmd
->tf_flags
& IDE_TFLAG_IN_ERROR
)
695 tf
->error
= scc_ide_inb(io_ports
->feature_addr
);
696 if (cmd
->tf_flags
& IDE_TFLAG_IN_NSECT
)
697 tf
->nsect
= scc_ide_inb(io_ports
->nsect_addr
);
698 if (cmd
->tf_flags
& IDE_TFLAG_IN_LBAL
)
699 tf
->lbal
= scc_ide_inb(io_ports
->lbal_addr
);
700 if (cmd
->tf_flags
& IDE_TFLAG_IN_LBAM
)
701 tf
->lbam
= scc_ide_inb(io_ports
->lbam_addr
);
702 if (cmd
->tf_flags
& IDE_TFLAG_IN_LBAH
)
703 tf
->lbah
= scc_ide_inb(io_ports
->lbah_addr
);
704 if (cmd
->tf_flags
& IDE_TFLAG_IN_DEVICE
)
705 tf
->device
= scc_ide_inb(io_ports
->device_addr
);
707 if (cmd
->tf_flags
& IDE_TFLAG_LBA48
) {
708 scc_ide_outb(ATA_HOB
| ATA_DEVCTL_OBS
, io_ports
->ctl_addr
);
710 if (cmd
->tf_flags
& IDE_TFLAG_IN_HOB_ERROR
)
711 tf
->hob_error
= scc_ide_inb(io_ports
->feature_addr
);
712 if (cmd
->tf_flags
& IDE_TFLAG_IN_HOB_NSECT
)
713 tf
->hob_nsect
= scc_ide_inb(io_ports
->nsect_addr
);
714 if (cmd
->tf_flags
& IDE_TFLAG_IN_HOB_LBAL
)
715 tf
->hob_lbal
= scc_ide_inb(io_ports
->lbal_addr
);
716 if (cmd
->tf_flags
& IDE_TFLAG_IN_HOB_LBAM
)
717 tf
->hob_lbam
= scc_ide_inb(io_ports
->lbam_addr
);
718 if (cmd
->tf_flags
& IDE_TFLAG_IN_HOB_LBAH
)
719 tf
->hob_lbah
= scc_ide_inb(io_ports
->lbah_addr
);
723 static void scc_input_data(ide_drive_t
*drive
, struct ide_cmd
*cmd
,
724 void *buf
, unsigned int len
)
726 unsigned long data_addr
= drive
->hwif
->io_ports
.data_addr
;
730 if (drive
->io_32bit
) {
731 scc_ide_insl(data_addr
, buf
, len
/ 4);
734 scc_ide_insw(data_addr
, (u8
*)buf
+ (len
& ~3), 1);
736 scc_ide_insw(data_addr
, buf
, len
/ 2);
739 static void scc_output_data(ide_drive_t
*drive
, struct ide_cmd
*cmd
,
740 void *buf
, unsigned int len
)
742 unsigned long data_addr
= drive
->hwif
->io_ports
.data_addr
;
746 if (drive
->io_32bit
) {
747 scc_ide_outsl(data_addr
, buf
, len
/ 4);
750 scc_ide_outsw(data_addr
, (u8
*)buf
+ (len
& ~3), 1);
752 scc_ide_outsw(data_addr
, buf
, len
/ 2);
756 * init_mmio_iops_scc - set up the iops for MMIO
757 * @hwif: interface to set up
761 static void __devinit
init_mmio_iops_scc(ide_hwif_t
*hwif
)
763 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
764 struct scc_ports
*ports
= pci_get_drvdata(dev
);
765 unsigned long dma_base
= ports
->dma
;
767 ide_set_hwifdata(hwif
, ports
);
769 hwif
->dma_base
= dma_base
;
770 hwif
->config_data
= ports
->ctl
;
774 * init_iops_scc - set up iops
775 * @hwif: interface to set up
777 * Do the basic setup for the SCC hardware interface
778 * and then do the MMIO setup.
781 static void __devinit
init_iops_scc(ide_hwif_t
*hwif
)
783 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
785 hwif
->hwif_data
= NULL
;
786 if (pci_get_drvdata(dev
) == NULL
)
788 init_mmio_iops_scc(hwif
);
791 static int __devinit
scc_init_dma(ide_hwif_t
*hwif
,
792 const struct ide_port_info
*d
)
794 return ide_allocate_dma_engine(hwif
);
797 static u8
scc_cable_detect(ide_hwif_t
*hwif
)
799 return ATA_CBL_PATA80
;
803 * init_hwif_scc - set up hwif
804 * @hwif: interface to set up
806 * We do the basic set up of the interface structure. The SCC
807 * requires several custom handlers so we override the default
808 * ide DMA handlers appropriately.
811 static void __devinit
init_hwif_scc(ide_hwif_t
*hwif
)
814 out_be32((void __iomem
*)(hwif
->dma_base
+ 0x018), hwif
->dmatable_dma
);
816 if (in_be32((void __iomem
*)(hwif
->config_data
+ 0xff0)) & CCKCTRL_ATACLKOEN
)
817 hwif
->ultra_mask
= ATA_UDMA6
; /* 133MHz */
819 hwif
->ultra_mask
= ATA_UDMA5
; /* 100MHz */
822 static const struct ide_tp_ops scc_tp_ops
= {
823 .exec_command
= scc_exec_command
,
824 .read_status
= scc_read_status
,
825 .read_altstatus
= scc_read_altstatus
,
826 .write_devctl
= scc_write_devctl
,
828 .dev_select
= ide_dev_select
,
829 .tf_load
= scc_tf_load
,
830 .tf_read
= scc_tf_read
,
832 .input_data
= scc_input_data
,
833 .output_data
= scc_output_data
,
836 static const struct ide_port_ops scc_port_ops
= {
837 .set_pio_mode
= scc_set_pio_mode
,
838 .set_dma_mode
= scc_set_dma_mode
,
839 .udma_filter
= scc_udma_filter
,
840 .cable_detect
= scc_cable_detect
,
843 static const struct ide_dma_ops scc_dma_ops
= {
844 .dma_host_set
= scc_dma_host_set
,
845 .dma_setup
= scc_dma_setup
,
846 .dma_start
= scc_dma_start
,
847 .dma_end
= scc_dma_end
,
848 .dma_test_irq
= scc_dma_test_irq
,
849 .dma_lost_irq
= ide_dma_lost_irq
,
850 .dma_timer_expiry
= ide_dma_sff_timer_expiry
,
851 .dma_sff_read_status
= scc_dma_sff_read_status
,
854 static const struct ide_port_info scc_chipset __devinitdata
= {
856 .init_iops
= init_iops_scc
,
857 .init_dma
= scc_init_dma
,
858 .init_hwif
= init_hwif_scc
,
859 .tp_ops
= &scc_tp_ops
,
860 .port_ops
= &scc_port_ops
,
861 .dma_ops
= &scc_dma_ops
,
862 .host_flags
= IDE_HFLAG_SINGLE
,
863 .irq_flags
= IRQF_SHARED
,
864 .pio_mask
= ATA_PIO4
,
868 * scc_init_one - pci layer discovery entry
870 * @id: ident table entry
872 * Called by the PCI code when it finds an SCC PATA controller.
873 * We then use the IDE PCI generic helper to do most of the work.
876 static int __devinit
scc_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
878 return init_setup_scc(dev
, &scc_chipset
);
882 * scc_remove - pci layer remove entry
885 * Called by the PCI code when it removes an SCC PATA controller.
888 static void __devexit
scc_remove(struct pci_dev
*dev
)
890 struct scc_ports
*ports
= pci_get_drvdata(dev
);
891 struct ide_host
*host
= ports
->host
;
893 ide_host_remove(host
);
895 iounmap((void*)ports
->dma
);
896 iounmap((void*)ports
->ctl
);
897 pci_release_selected_regions(dev
, (1 << 2) - 1);
898 memset(ports
, 0, sizeof(*ports
));
901 static const struct pci_device_id scc_pci_tbl
[] = {
902 { PCI_VDEVICE(TOSHIBA_2
, PCI_DEVICE_ID_TOSHIBA_SCC_ATA
), 0 },
905 MODULE_DEVICE_TABLE(pci
, scc_pci_tbl
);
907 static struct pci_driver scc_pci_driver
= {
909 .id_table
= scc_pci_tbl
,
910 .probe
= scc_init_one
,
911 .remove
= __devexit_p(scc_remove
),
914 static int scc_ide_init(void)
916 return ide_pci_register_driver(&scc_pci_driver
);
919 module_init(scc_ide_init
);
921 static void scc_ide_exit(void)
923 ide_pci_unregister_driver(&scc_pci_driver);
925 module_exit(scc_ide_exit);
929 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
930 MODULE_LICENSE("GPL");