2 * pata_it821x.c - IT821x PATA for new ATA layer
4 * Alan Cox <alan@lxorguk.ukuu.org.uk>
5 * (C) 2007 Bartlomiej Zolnierkiewicz
11 * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
13 * Copyright (C) 2004 Red Hat
15 * May be copied or modified under the terms of the GNU General Public License
16 * Based in part on the ITE vendor provided SCSI driver.
18 * Documentation available from
19 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
20 * Some other documents are NDA.
22 * The ITE8212 isn't exactly a standard IDE controller. It has two
23 * modes. In pass through mode then it is an IDE controller. In its smart
24 * mode its actually quite a capable hardware raid controller disguised
25 * as an IDE controller. Smart mode only understands DMA read/write and
26 * identify, none of the fancier commands apply. The IT8211 is identical
27 * in other respects but lacks the raid mode.
30 * o Rev 0x10 also requires master/slave hold the same DMA timings and
31 * cannot do ATAPI MWDMA.
32 * o The identify data for raid volumes lacks CHS info (technically ok)
33 * but also fails to set the LBA28 and other bits. We fix these in
34 * the IDE probe quirk code.
35 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
36 * raid then the controller firmware dies
37 * o Smart mode without RAID doesn't clear all the necessary identify
38 * bits to reduce the command set to the one used
40 * This has a few impacts on the driver
41 * - In pass through mode we do all the work you would expect
42 * - In smart mode the clocking set up is done by the controller generally
43 * but we must watch the other limits and filter.
44 * - There are a few extra vendor commands that actually talk to the
45 * controller but only work PIO with no IRQ.
47 * Vendor areas of the identify block in smart mode are used for the
48 * timing and policy set up. Each HDD in raid mode also has a serial
49 * block on the disk. The hardware extra commands are get/set chip status,
50 * rebuild, get rebuild status.
52 * In Linux the driver supports pass through mode as if the device was
53 * just another IDE controller. If the smart mode is running then
54 * volumes are managed by the controller firmware and each IDE "disk"
55 * is a raid volume. Even more cute - the controller can do automated
56 * hotplug and rebuild.
58 * The pass through controller itself is a little demented. It has a
59 * flaw that it has a single set of PIO/MWDMA timings per channel so
60 * non UDMA devices restrict each others performance. It also has a
61 * single clock source per channel so mixed UDMA100/133 performance
62 * isn't perfect and we have to pick a clock. Thankfully none of this
63 * matters in smart mode. ATAPI DMA is not currently supported.
65 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
68 * - ATAPI and other speed filtering
69 * - RAID configuration ioctls
72 #include <linux/kernel.h>
73 #include <linux/module.h>
74 #include <linux/pci.h>
75 #include <linux/init.h>
76 #include <linux/blkdev.h>
77 #include <linux/delay.h>
78 #include <scsi/scsi_host.h>
79 #include <linux/libata.h>
82 #define DRV_NAME "pata_it821x"
83 #define DRV_VERSION "0.4.0"
87 unsigned int smart
:1, /* Are we in smart raid mode */
88 timing10
:1; /* Rev 0x10 */
89 u8 clock_mode
; /* 0, ATA_50 or ATA_66 */
90 u8 want
[2][2]; /* Mode/Pri log for master slave */
91 /* We need these for switching the clock when DMA goes on/off
92 The high byte is the 66Mhz timing */
93 u16 pio
[2]; /* Cached PIO values */
94 u16 mwdma
[2]; /* Cached MWDMA values */
95 u16 udma
[2]; /* Cached UDMA values (per drive) */
96 u16 last_device
; /* Master or slave loaded ? */
107 * We allow users to force the card into non raid mode without
108 * flashing the alternative BIOS. This is also necessary right now
109 * for embedded platforms that cannot run a PC BIOS but are using this
113 static int it8212_noraid
;
116 * it821x_program - program the PIO/MWDMA registers
118 * @adev: Device to program
119 * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8)
121 * Program the PIO/MWDMA timing for this channel according to the
122 * current clock. These share the same register so are managed by
123 * the DMA start/stop sequence as with the old driver.
126 static void it821x_program(struct ata_port
*ap
, struct ata_device
*adev
, u16 timing
)
128 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
129 struct it821x_dev
*itdev
= ap
->private_data
;
130 int channel
= ap
->port_no
;
133 /* Program PIO/MWDMA timing bits */
134 if (itdev
->clock_mode
== ATA_66
)
137 conf
= timing
& 0xFF;
138 pci_write_config_byte(pdev
, 0x54 + 4 * channel
, conf
);
143 * it821x_program_udma - program the UDMA registers
145 * @adev: ATA device to update
146 * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz
148 * Program the UDMA timing for this drive according to the
149 * current clock. Handles the dual clocks and also knows about
150 * the errata on the 0x10 revision. The UDMA errata is partly handled
151 * here and partly in start_dma.
154 static void it821x_program_udma(struct ata_port
*ap
, struct ata_device
*adev
, u16 timing
)
156 struct it821x_dev
*itdev
= ap
->private_data
;
157 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
158 int channel
= ap
->port_no
;
159 int unit
= adev
->devno
;
162 /* Program UDMA timing bits */
163 if (itdev
->clock_mode
== ATA_66
)
166 conf
= timing
& 0xFF;
167 if (itdev
->timing10
== 0)
168 pci_write_config_byte(pdev
, 0x56 + 4 * channel
+ unit
, conf
);
170 /* Early revision must be programmed for both together */
171 pci_write_config_byte(pdev
, 0x56 + 4 * channel
, conf
);
172 pci_write_config_byte(pdev
, 0x56 + 4 * channel
+ 1, conf
);
177 * it821x_clock_strategy
179 * @adev: ATA device being updated
181 * Select between the 50 and 66Mhz base clocks to get the best
182 * results for this interface.
185 static void it821x_clock_strategy(struct ata_port
*ap
, struct ata_device
*adev
)
187 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
188 struct it821x_dev
*itdev
= ap
->private_data
;
189 u8 unit
= adev
->devno
;
190 struct ata_device
*pair
= ata_dev_pair(adev
);
196 /* Look for the most wanted clocking */
197 if (itdev
->want
[0][0] > itdev
->want
[1][0]) {
198 clock
= itdev
->want
[0][1];
199 altclock
= itdev
->want
[1][1];
201 clock
= itdev
->want
[1][1];
202 altclock
= itdev
->want
[0][1];
205 /* Master doesn't care does the slave ? */
206 if (clock
== ATA_ANY
)
209 /* Nobody cares - keep the same clock */
210 if (clock
== ATA_ANY
)
213 if (clock
== itdev
->clock_mode
)
216 /* Load this into the controller */
218 itdev
->clock_mode
= ATA_66
;
220 itdev
->clock_mode
= ATA_50
;
223 pci_read_config_byte(pdev
, 0x50, &v
);
224 v
&= ~(1 << (1 + ap
->port_no
));
225 v
|= sel
<< (1 + ap
->port_no
);
226 pci_write_config_byte(pdev
, 0x50, v
);
229 * Reprogram the UDMA/PIO of the pair drive for the switch
230 * MWDMA will be dealt with by the dma switcher
232 if (pair
&& itdev
->udma
[1-unit
] != UDMA_OFF
) {
233 it821x_program_udma(ap
, pair
, itdev
->udma
[1-unit
]);
234 it821x_program(ap
, pair
, itdev
->pio
[1-unit
]);
237 * Reprogram the UDMA/PIO of our drive for the switch.
238 * MWDMA will be dealt with by the dma switcher
240 if (itdev
->udma
[unit
] != UDMA_OFF
) {
241 it821x_program_udma(ap
, adev
, itdev
->udma
[unit
]);
242 it821x_program(ap
, adev
, itdev
->pio
[unit
]);
247 * it821x_passthru_set_piomode - set PIO mode data
251 * Configure for PIO mode. This is complicated as the register is
252 * shared by PIO and MWDMA and for both channels.
255 static void it821x_passthru_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
257 /* Spec says 89 ref driver uses 88 */
258 static const u16 pio
[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
259 static const u8 pio_want
[] = { ATA_66
, ATA_66
, ATA_66
, ATA_66
, ATA_ANY
};
261 struct it821x_dev
*itdev
= ap
->private_data
;
262 int unit
= adev
->devno
;
263 int mode_wanted
= adev
->pio_mode
- XFER_PIO_0
;
265 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
266 itdev
->want
[unit
][1] = pio_want
[mode_wanted
];
267 itdev
->want
[unit
][0] = 1; /* PIO is lowest priority */
268 itdev
->pio
[unit
] = pio
[mode_wanted
];
269 it821x_clock_strategy(ap
, adev
);
270 it821x_program(ap
, adev
, itdev
->pio
[unit
]);
274 * it821x_passthru_set_dmamode - set initial DMA mode data
278 * Set up the DMA modes. The actions taken depend heavily on the mode
279 * to use. If UDMA is used as is hopefully the usual case then the
280 * timing register is private and we need only consider the clock. If
281 * we are using MWDMA then we have to manage the setting ourself as
282 * we switch devices and mode.
285 static void it821x_passthru_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
287 static const u16 dma
[] = { 0x8866, 0x3222, 0x3121 };
288 static const u8 mwdma_want
[] = { ATA_ANY
, ATA_66
, ATA_ANY
};
289 static const u16 udma
[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
290 static const u8 udma_want
[] = { ATA_ANY
, ATA_50
, ATA_ANY
, ATA_66
, ATA_66
, ATA_50
, ATA_66
};
292 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
293 struct it821x_dev
*itdev
= ap
->private_data
;
294 int channel
= ap
->port_no
;
295 int unit
= adev
->devno
;
298 if (adev
->dma_mode
>= XFER_UDMA_0
) {
299 int mode_wanted
= adev
->dma_mode
- XFER_UDMA_0
;
301 itdev
->want
[unit
][1] = udma_want
[mode_wanted
];
302 itdev
->want
[unit
][0] = 3; /* UDMA is high priority */
303 itdev
->mwdma
[unit
] = MWDMA_OFF
;
304 itdev
->udma
[unit
] = udma
[mode_wanted
];
305 if (mode_wanted
>= 5)
306 itdev
->udma
[unit
] |= 0x8080; /* UDMA 5/6 select on */
308 /* UDMA on. Again revision 0x10 must do the pair */
309 pci_read_config_byte(pdev
, 0x50, &conf
);
311 conf
&= channel
? 0x9F: 0xE7;
313 conf
&= ~ (1 << (3 + 2 * channel
+ unit
));
314 pci_write_config_byte(pdev
, 0x50, conf
);
315 it821x_clock_strategy(ap
, adev
);
316 it821x_program_udma(ap
, adev
, itdev
->udma
[unit
]);
318 int mode_wanted
= adev
->dma_mode
- XFER_MW_DMA_0
;
320 itdev
->want
[unit
][1] = mwdma_want
[mode_wanted
];
321 itdev
->want
[unit
][0] = 2; /* MWDMA is low priority */
322 itdev
->mwdma
[unit
] = dma
[mode_wanted
];
323 itdev
->udma
[unit
] = UDMA_OFF
;
325 /* UDMA bits off - Revision 0x10 do them in pairs */
326 pci_read_config_byte(pdev
, 0x50, &conf
);
328 conf
|= channel
? 0x60: 0x18;
330 conf
|= 1 << (3 + 2 * channel
+ unit
);
331 pci_write_config_byte(pdev
, 0x50, conf
);
332 it821x_clock_strategy(ap
, adev
);
337 * it821x_passthru_dma_start - DMA start callback
338 * @qc: Command in progress
340 * Usually drivers set the DMA timing at the point the set_dmamode call
341 * is made. IT821x however requires we load new timings on the
342 * transitions in some cases.
345 static void it821x_passthru_bmdma_start(struct ata_queued_cmd
*qc
)
347 struct ata_port
*ap
= qc
->ap
;
348 struct ata_device
*adev
= qc
->dev
;
349 struct it821x_dev
*itdev
= ap
->private_data
;
350 int unit
= adev
->devno
;
352 if (itdev
->mwdma
[unit
] != MWDMA_OFF
)
353 it821x_program(ap
, adev
, itdev
->mwdma
[unit
]);
354 else if (itdev
->udma
[unit
] != UDMA_OFF
&& itdev
->timing10
)
355 it821x_program_udma(ap
, adev
, itdev
->udma
[unit
]);
360 * it821x_passthru_dma_stop - DMA stop callback
363 * We loaded new timings in dma_start, as a result we need to restore
364 * the PIO timings in dma_stop so that the next command issue gets the
365 * right clock values.
368 static void it821x_passthru_bmdma_stop(struct ata_queued_cmd
*qc
)
370 struct ata_port
*ap
= qc
->ap
;
371 struct ata_device
*adev
= qc
->dev
;
372 struct it821x_dev
*itdev
= ap
->private_data
;
373 int unit
= adev
->devno
;
376 if (itdev
->mwdma
[unit
] != MWDMA_OFF
)
377 it821x_program(ap
, adev
, itdev
->pio
[unit
]);
382 * it821x_passthru_dev_select - Select master/slave
384 * @device: Device number (not pointer)
386 * Device selection hook. If necessary perform clock switching
389 static void it821x_passthru_dev_select(struct ata_port
*ap
,
392 struct it821x_dev
*itdev
= ap
->private_data
;
393 if (itdev
&& device
!= itdev
->last_device
) {
394 struct ata_device
*adev
= &ap
->link
.device
[device
];
395 it821x_program(ap
, adev
, itdev
->pio
[adev
->devno
]);
396 itdev
->last_device
= device
;
398 ata_sff_dev_select(ap
, device
);
402 * it821x_smart_qc_issue - wrap qc issue prot
405 * Wrap the command issue sequence for the IT821x. We need to
406 * perform out own device selection timing loads before the
407 * usual happenings kick off
410 static unsigned int it821x_smart_qc_issue(struct ata_queued_cmd
*qc
)
412 switch(qc
->tf
.command
)
414 /* Commands the firmware supports */
416 case ATA_CMD_READ_EXT
:
418 case ATA_CMD_WRITE_EXT
:
419 case ATA_CMD_PIO_READ
:
420 case ATA_CMD_PIO_READ_EXT
:
421 case ATA_CMD_PIO_WRITE
:
422 case ATA_CMD_PIO_WRITE_EXT
:
423 case ATA_CMD_READ_MULTI
:
424 case ATA_CMD_READ_MULTI_EXT
:
425 case ATA_CMD_WRITE_MULTI
:
426 case ATA_CMD_WRITE_MULTI_EXT
:
428 case ATA_CMD_INIT_DEV_PARAMS
:
429 case 0xFC: /* Internal 'report rebuild state' */
430 /* Arguably should just no-op this one */
431 case ATA_CMD_SET_FEATURES
:
432 return ata_sff_qc_issue(qc
);
434 printk(KERN_DEBUG
"it821x: can't process command 0x%02X\n", qc
->tf
.command
);
439 * it821x_passthru_qc_issue - wrap qc issue prot
442 * Wrap the command issue sequence for the IT821x. We need to
443 * perform out own device selection timing loads before the
444 * usual happenings kick off
447 static unsigned int it821x_passthru_qc_issue(struct ata_queued_cmd
*qc
)
449 it821x_passthru_dev_select(qc
->ap
, qc
->dev
->devno
);
450 return ata_sff_qc_issue(qc
);
454 * it821x_smart_set_mode - mode setting
455 * @link: interface to set up
456 * @unused: device that failed (error only)
458 * Use a non standard set_mode function. We don't want to be tuned.
459 * The BIOS configured everything. Our job is not to fiddle. We
460 * read the dma enabled bits from the PCI configuration of the device
464 static int it821x_smart_set_mode(struct ata_link
*link
, struct ata_device
**unused
)
466 struct ata_device
*dev
;
468 ata_for_each_dev(dev
, link
, ENABLED
) {
469 /* We don't really care */
470 dev
->pio_mode
= XFER_PIO_0
;
471 dev
->dma_mode
= XFER_MW_DMA_0
;
472 /* We do need the right mode information for DMA or PIO
473 and this comes from the current configuration flags */
474 if (ata_id_has_dma(dev
->id
)) {
475 ata_dev_printk(dev
, KERN_INFO
, "configured for DMA\n");
476 dev
->xfer_mode
= XFER_MW_DMA_0
;
477 dev
->xfer_shift
= ATA_SHIFT_MWDMA
;
478 dev
->flags
&= ~ATA_DFLAG_PIO
;
480 ata_dev_printk(dev
, KERN_INFO
, "configured for PIO\n");
481 dev
->xfer_mode
= XFER_PIO_0
;
482 dev
->xfer_shift
= ATA_SHIFT_PIO
;
483 dev
->flags
|= ATA_DFLAG_PIO
;
490 * it821x_dev_config - Called each device identify
491 * @adev: Device that has just been identified
493 * Perform the initial setup needed for each device that is chip
494 * special. In our case we need to lock the sector count to avoid
495 * blowing the brains out of the firmware with large LBA48 requests
497 * FIXME: When FUA appears we need to block FUA too. And SMART and
498 * basically we need to filter commands for this chip.
501 static void it821x_dev_config(struct ata_device
*adev
)
503 unsigned char model_num
[ATA_ID_PROD_LEN
+ 1];
505 ata_id_c_string(adev
->id
, model_num
, ATA_ID_PROD
, sizeof(model_num
));
507 if (adev
->max_sectors
> 255)
508 adev
->max_sectors
= 255;
510 if (strstr(model_num
, "Integrated Technology Express")) {
512 ata_dev_printk(adev
, KERN_INFO
, "%sRAID%d volume",
513 adev
->id
[147]?"Bootable ":"",
515 if (adev
->id
[129] != 1)
516 printk("(%dK stripe)", adev
->id
[146]);
519 /* This is a controller firmware triggered funny, don't
520 report the drive faulty! */
521 adev
->horkage
&= ~ATA_HORKAGE_DIAGNOSTIC
;
522 /* No HPA in 'smart' mode */
523 adev
->horkage
|= ATA_HORKAGE_BROKEN_HPA
;
527 * it821x_read_id - Hack identify data up
528 * @adev: device to read
529 * @tf: proposed taskfile
530 * @id: buffer for returned ident data
532 * Query the devices on this firmware driven port and slightly
533 * mash the identify data to stop us and common tools trying to
534 * use features not firmware supported. The firmware itself does
535 * some masking (eg SMART) but not enough.
538 static unsigned int it821x_read_id(struct ata_device
*adev
,
539 struct ata_taskfile
*tf
, u16
*id
)
541 unsigned int err_mask
;
542 unsigned char model_num
[ATA_ID_PROD_LEN
+ 1];
544 err_mask
= ata_do_dev_read_id(adev
, tf
, id
);
547 ata_id_c_string(id
, model_num
, ATA_ID_PROD
, sizeof(model_num
));
549 id
[83] &= ~(1 << 12); /* Cache flush is firmware handled */
550 id
[83] &= ~(1 << 13); /* Ditto for LBA48 flushes */
551 id
[84] &= ~(1 << 6); /* No FUA */
552 id
[85] &= ~(1 << 10); /* No HPA */
553 id
[76] = 0; /* No NCQ/AN etc */
555 if (strstr(model_num
, "Integrated Technology Express")) {
556 /* Set feature bits the firmware neglects */
557 id
[49] |= 0x0300; /* LBA, DMA */
559 id
[83] |= 0x4400; /* Word 83 is valid and LBA48 */
560 id
[86] |= 0x0400; /* LBA48 on */
561 id
[ATA_ID_MAJOR_VER
] |= 0x1F;
567 * it821x_check_atapi_dma - ATAPI DMA handler
568 * @qc: Command we are about to issue
570 * Decide if this ATAPI command can be issued by DMA on this
571 * controller. Return 0 if it can be.
574 static int it821x_check_atapi_dma(struct ata_queued_cmd
*qc
)
576 struct ata_port
*ap
= qc
->ap
;
577 struct it821x_dev
*itdev
= ap
->private_data
;
579 /* Only use dma for transfers to/from the media. */
580 if (ata_qc_raw_nbytes(qc
) < 2048)
583 /* No ATAPI DMA in smart mode */
586 /* No ATAPI DMA on rev 10 */
594 * it821x_display_disk - display disk setup
596 * @buf: Buffer block from firmware
598 * Produce a nice informative display of the device setup as provided
602 static void it821x_display_disk(int n
, u8
*buf
)
604 unsigned char id
[41];
608 char *cbl
= "(40 wire cable)";
610 static const char *types
[5] = {
611 "RAID0", "RAID1" "RAID 0+1", "JBOD", "DISK"
614 if (buf
[52] > 4) /* No Disk */
617 ata_id_c_string((u16
*)buf
, id
, 0, 41);
622 } else if (buf
[49]) {
631 snprintf(mbuf
, 8, "%5s%d", mtype
, mode
- 1);
635 printk(KERN_INFO
"%d: %-6s %-8s %s %s\n",
636 n
, mbuf
, types
[buf
[52]], id
, cbl
);
638 printk(KERN_INFO
"%d: %-6s %-8s Volume: %1d %s %s\n",
639 n
, mbuf
, types
[buf
[52]], buf
[53], id
, cbl
);
641 printk(KERN_INFO
"%d: Rebuilding: %d%%\n", n
, buf
[125]);
645 * it821x_firmware_command - issue firmware command
646 * @ap: IT821x port to interrogate
650 * Issue firmware commands expecting data back from the controller. We
651 * use this to issue commands that do not go via the normal paths. Other
652 * commands such as 0xFC can be issued normally.
655 static u8
*it821x_firmware_command(struct ata_port
*ap
, u8 cmd
, int len
)
659 u16
*buf
= kmalloc(len
, GFP_KERNEL
);
661 printk(KERN_ERR
"it821x_firmware_command: Out of memory\n");
664 /* This isn't quite a normal ATA command as we are talking to the
665 firmware not the drives */
667 iowrite8(ap
->ctl
, ap
->ioaddr
.ctl_addr
);
669 iowrite8(ATA_DEVICE_OBS
, ap
->ioaddr
.device_addr
);
670 iowrite8(cmd
, ap
->ioaddr
.command_addr
);
672 /* This should be almost immediate but a little paranoia goes a long
675 status
= ioread8(ap
->ioaddr
.status_addr
);
676 if (status
& ATA_ERR
) {
678 printk(KERN_ERR
"it821x_firmware_command: rejected\n");
681 if (status
& ATA_DRQ
) {
682 ioread16_rep(ap
->ioaddr
.data_addr
, buf
, len
/2);
688 printk(KERN_ERR
"it821x_firmware_command: timeout\n");
693 * it821x_probe_firmware - firmware reporting/setup
694 * @ap: IT821x port being probed
696 * Probe the firmware of the controller by issuing firmware command
697 * 0xFA and analysing the returned data.
700 static void it821x_probe_firmware(struct ata_port
*ap
)
705 /* This is a bit ugly as we can't just issue a task file to a device
706 as this is controller magic */
708 buf
= it821x_firmware_command(ap
, 0xFA, 512);
711 printk(KERN_INFO
"pata_it821x: Firmware %02X/%02X/%02X%02X\n",
716 for (i
= 0; i
< 4; i
++)
717 it821x_display_disk(i
, buf
+ 128 * i
);
725 * it821x_port_start - port setup
726 * @ap: ATA port being set up
728 * The it821x needs to maintain private data structures and also to
729 * use the standard PCI interface which lacks support for this
730 * functionality. We instead set up the private data on the port
731 * start hook, and tear it down on port stop
734 static int it821x_port_start(struct ata_port
*ap
)
736 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
737 struct it821x_dev
*itdev
;
740 int ret
= ata_sff_port_start(ap
);
744 itdev
= devm_kzalloc(&pdev
->dev
, sizeof(struct it821x_dev
), GFP_KERNEL
);
747 ap
->private_data
= itdev
;
749 pci_read_config_byte(pdev
, 0x50, &conf
);
753 /* Long I/O's although allowed in LBA48 space cause the
754 onboard firmware to enter the twighlight zone */
755 /* No ATAPI DMA in this mode either */
756 if (ap
->port_no
== 0)
757 it821x_probe_firmware(ap
);
759 /* Pull the current clocks from 0x50 */
760 if (conf
& (1 << (1 + ap
->port_no
)))
761 itdev
->clock_mode
= ATA_50
;
763 itdev
->clock_mode
= ATA_66
;
765 itdev
->want
[0][1] = ATA_ANY
;
766 itdev
->want
[1][1] = ATA_ANY
;
767 itdev
->last_device
= -1;
769 if (pdev
->revision
== 0x10) {
771 /* Need to disable ATAPI DMA for this case */
773 printk(KERN_WARNING DRV_NAME
": Revision 0x10, workarounds activated.\n");
780 * it821x_rdc_cable - Cable detect for RDC1010
781 * @ap: port we are checking
783 * Return the RDC1010 cable type. Unlike the IT821x we know how to do
784 * this and can do host side cable detect
787 static int it821x_rdc_cable(struct ata_port
*ap
)
790 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
792 pci_read_config_word(pdev
, 0x40, &r40
);
793 if (r40
& (1 << (2 + ap
->port_no
)))
794 return ATA_CBL_PATA40
;
795 return ATA_CBL_PATA80
;
798 static struct scsi_host_template it821x_sht
= {
799 ATA_BMDMA_SHT(DRV_NAME
),
802 static struct ata_port_operations it821x_smart_port_ops
= {
803 .inherits
= &ata_bmdma_port_ops
,
805 .check_atapi_dma
= it821x_check_atapi_dma
,
806 .qc_issue
= it821x_smart_qc_issue
,
808 .cable_detect
= ata_cable_80wire
,
809 .set_mode
= it821x_smart_set_mode
,
810 .dev_config
= it821x_dev_config
,
811 .read_id
= it821x_read_id
,
813 .port_start
= it821x_port_start
,
816 static struct ata_port_operations it821x_passthru_port_ops
= {
817 .inherits
= &ata_bmdma_port_ops
,
819 .check_atapi_dma
= it821x_check_atapi_dma
,
820 .sff_dev_select
= it821x_passthru_dev_select
,
821 .bmdma_start
= it821x_passthru_bmdma_start
,
822 .bmdma_stop
= it821x_passthru_bmdma_stop
,
823 .qc_issue
= it821x_passthru_qc_issue
,
825 .cable_detect
= ata_cable_unknown
,
826 .set_piomode
= it821x_passthru_set_piomode
,
827 .set_dmamode
= it821x_passthru_set_dmamode
,
829 .port_start
= it821x_port_start
,
832 static struct ata_port_operations it821x_rdc_port_ops
= {
833 .inherits
= &ata_bmdma_port_ops
,
835 .check_atapi_dma
= it821x_check_atapi_dma
,
836 .sff_dev_select
= it821x_passthru_dev_select
,
837 .bmdma_start
= it821x_passthru_bmdma_start
,
838 .bmdma_stop
= it821x_passthru_bmdma_stop
,
839 .qc_issue
= it821x_passthru_qc_issue
,
841 .cable_detect
= it821x_rdc_cable
,
842 .set_piomode
= it821x_passthru_set_piomode
,
843 .set_dmamode
= it821x_passthru_set_dmamode
,
845 .port_start
= it821x_port_start
,
848 static void it821x_disable_raid(struct pci_dev
*pdev
)
850 /* Neither the RDC nor the IT8211 */
851 if (pdev
->vendor
!= PCI_VENDOR_ID_ITE
||
852 pdev
->device
!= PCI_DEVICE_ID_ITE_8212
)
855 /* Reset local CPU, and set BIOS not ready */
856 pci_write_config_byte(pdev
, 0x5E, 0x01);
858 /* Set to bypass mode, and reset PCI bus */
859 pci_write_config_byte(pdev
, 0x50, 0x00);
860 pci_write_config_word(pdev
, PCI_COMMAND
,
861 PCI_COMMAND_PARITY
| PCI_COMMAND_IO
|
862 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
863 pci_write_config_word(pdev
, 0x40, 0xA0F3);
865 pci_write_config_dword(pdev
,0x4C, 0x02040204);
866 pci_write_config_byte(pdev
, 0x42, 0x36);
867 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0x20);
871 static int it821x_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
875 static const struct ata_port_info info_smart
= {
876 .flags
= ATA_FLAG_SLAVE_POSS
,
879 .udma_mask
= ATA_UDMA6
,
880 .port_ops
= &it821x_smart_port_ops
882 static const struct ata_port_info info_passthru
= {
883 .flags
= ATA_FLAG_SLAVE_POSS
,
886 .udma_mask
= ATA_UDMA6
,
887 .port_ops
= &it821x_passthru_port_ops
889 static const struct ata_port_info info_rdc
= {
890 .flags
= ATA_FLAG_SLAVE_POSS
,
894 .port_ops
= &it821x_rdc_port_ops
897 const struct ata_port_info
*ppi
[] = { NULL
, NULL
};
898 static char *mode
[2] = { "pass through", "smart" };
901 rc
= pcim_enable_device(pdev
);
905 if (pdev
->vendor
== PCI_VENDOR_ID_RDC
) {
908 /* Force the card into bypass mode if so requested */
910 printk(KERN_INFO DRV_NAME
": forcing bypass mode.\n");
911 it821x_disable_raid(pdev
);
913 pci_read_config_byte(pdev
, 0x50, &conf
);
916 printk(KERN_INFO DRV_NAME
": controller in %s mode.\n",
919 ppi
[0] = &info_passthru
;
921 ppi
[0] = &info_smart
;
923 return ata_pci_sff_init_one(pdev
, ppi
, &it821x_sht
, NULL
);
927 static int it821x_reinit_one(struct pci_dev
*pdev
)
929 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
932 rc
= ata_pci_device_do_resume(pdev
);
935 /* Resume - turn raid back off if need be */
937 it821x_disable_raid(pdev
);
938 ata_host_resume(host
);
943 static const struct pci_device_id it821x
[] = {
944 { PCI_VDEVICE(ITE
, PCI_DEVICE_ID_ITE_8211
), },
945 { PCI_VDEVICE(ITE
, PCI_DEVICE_ID_ITE_8212
), },
946 { PCI_VDEVICE(RDC
, 0x1010), },
951 static struct pci_driver it821x_pci_driver
= {
954 .probe
= it821x_init_one
,
955 .remove
= ata_pci_remove_one
,
957 .suspend
= ata_pci_device_suspend
,
958 .resume
= it821x_reinit_one
,
962 static int __init
it821x_init(void)
964 return pci_register_driver(&it821x_pci_driver
);
967 static void __exit
it821x_exit(void)
969 pci_unregister_driver(&it821x_pci_driver
);
972 MODULE_AUTHOR("Alan Cox");
973 MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller");
974 MODULE_LICENSE("GPL");
975 MODULE_DEVICE_TABLE(pci
, it821x
);
976 MODULE_VERSION(DRV_VERSION
);
979 module_param_named(noraid
, it8212_noraid
, int, S_IRUGO
);
980 MODULE_PARM_DESC(noraid
, "Force card into bypass mode");
982 module_init(it821x_init
);
983 module_exit(it821x_exit
);