include/asm-mips/cpu-features.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003, 2004 Ralf Baechle
   7  * Copyright (C) 2004  Maciej W. Rozycki
   8  */
   9 #ifndef __ASM_CPU_FEATURES_H
  10 #define __ASM_CPU_FEATURES_H
  11
  12 #include <linux/config.h>
  13
  14 #include <asm/cpu.h>
  15 #include <asm/cpu-info.h>
  16 #include <cpu-feature-overrides.h>
  17
  18 /*
  19  * SMP assumption: Options of CPU 0 are a superset of all processors.
  20  * This is true for all known MIPS systems.
  21  */
  22 #ifndef cpu_has_tlb
  23 #define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
  24 #endif
  25 #ifndef cpu_has_4kex
  26 #define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
  27 #endif
  28 #ifndef cpu_has_4ktlb
  29 #define cpu_has_4ktlb           (cpu_data[0].options & MIPS_CPU_4KTLB)
  30 #endif
  31 #ifndef cpu_has_fpu
  32 #define cpu_has_fpu             (cpu_data[0].options & MIPS_CPU_FPU)
  33 #endif
  34 #ifndef cpu_has_32fpr
  35 #define cpu_has_32fpr           (cpu_data[0].options & MIPS_CPU_32FPR)
  36 #endif
  37 #ifndef cpu_has_counter
  38 #define cpu_has_counter         (cpu_data[0].options & MIPS_CPU_COUNTER)
  39 #endif
  40 #ifndef cpu_has_watch
  41 #define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
  42 #endif
  43 #ifndef cpu_has_divec
  44 #define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
  45 #endif
  46 #ifndef cpu_has_vce
  47 #define cpu_has_vce             (cpu_data[0].options & MIPS_CPU_VCE)
  48 #endif
  49 #ifndef cpu_has_cache_cdex_p
  50 #define cpu_has_cache_cdex_p    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
  51 #endif
  52 #ifndef cpu_has_cache_cdex_s
  53 #define cpu_has_cache_cdex_s    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
  54 #endif
  55 #ifndef cpu_has_prefetch
  56 #define cpu_has_prefetch        (cpu_data[0].options & MIPS_CPU_PREFETCH)
  57 #endif
  58 #ifndef cpu_has_mcheck
  59 #define cpu_has_mcheck          (cpu_data[0].options & MIPS_CPU_MCHECK)
  60 #endif
  61 #ifndef cpu_has_ejtag
  62 #define cpu_has_ejtag           (cpu_data[0].options & MIPS_CPU_EJTAG)
  63 #endif
  64 #ifndef cpu_has_llsc
  65 #define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
  66 #endif
  67 #ifndef cpu_has_mips16
  68 #define cpu_has_mips16          (cpu_data[0].ases & MIPS_ASE_MIPS16)
  69 #endif
  70 #ifndef cpu_has_mdmx
  71 #define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
  72 #endif
  73 #ifndef cpu_has_mips3d
  74 #define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
  75 #endif
  76 #ifndef cpu_has_smartmips
  77 #define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
  78 #endif
  79 #ifndef cpu_has_vtag_icache
  80 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
  81 #endif
  82 #ifndef cpu_has_dc_aliases
  83 #define cpu_has_dc_aliases      (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
  84 #endif
  85 #ifndef cpu_has_ic_fills_f_dc
  86 #define cpu_has_ic_fills_f_dc   (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
  87 #endif
  88
  89 /*
  90  * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
  91  * such as the R10000 have I-Caches that snoop local stores; the embedded ones
  92  * don't.  For maintaining I-cache coherency this means we need to flush the
  93  * D-cache all the way back to whever the I-cache does refills from, so the
  94  * I-cache has a chance to see the new data at all.  Then we have to flush the
  95  * I-cache also.
  96  * Note we may have been rescheduled and may no longer be running on the CPU
  97  * that did the store so we can't optimize this into only doing the flush on
  98  * the local CPU.
  99  */
 100 #ifndef cpu_icache_snoops_remote_store
 101 #ifdef CONFIG_SMP
 102 #define cpu_icache_snoops_remote_store  (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
 103 #else
 104 #define cpu_icache_snoops_remote_store  1
 105 #endif
 106 #endif
 107
 108 #ifndef cpu_has_dsp
 109 #define cpu_has_dsp             (cpu_data[0].ases & MIPS_ASE_DSP)
 110 #endif
 111
 112 #ifdef CONFIG_MIPS_MT
 113 #ifndef cpu_has_mipsmt
 114 # define cpu_has_mipsmt         (cpu_data[0].ases & MIPS_ASE_MIPSMT)
 115 #endif
 116 #else
 117 # define cpu_has_mipsmt         0
 118 #endif
 119
 120 #ifdef CONFIG_32BIT
 121 # ifndef cpu_has_nofpuex
 122 # define cpu_has_nofpuex        (cpu_data[0].options & MIPS_CPU_NOFPUEX)
 123 # endif
 124 # ifndef cpu_has_64bits
 125 # define cpu_has_64bits         (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 126 # endif
 127 # ifndef cpu_has_64bit_zero_reg
 128 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 129 # endif
 130 # ifndef cpu_has_64bit_gp_regs
 131 # define cpu_has_64bit_gp_regs          0
 132 # endif
 133 # ifndef cpu_has_64bit_addresses
 134 # define cpu_has_64bit_addresses        0
 135 # endif
 136 #endif
 137
 138 #ifdef CONFIG_64BIT
 139 # ifndef cpu_has_nofpuex
 140 # define cpu_has_nofpuex                0
 141 # endif
 142 # ifndef cpu_has_64bits
 143 # define cpu_has_64bits                 1
 144 # endif
 145 # ifndef cpu_has_64bit_zero_reg
 146 # define cpu_has_64bit_zero_reg         1
 147 # endif
 148 # ifndef cpu_has_64bit_gp_regs
 149 # define cpu_has_64bit_gp_regs          1
 150 # endif
 151 # ifndef cpu_has_64bit_addresses
 152 # define cpu_has_64bit_addresses        1
 153 # endif
 154 #endif
 155
 156 #ifdef CONFIG_CPU_MIPSR2
 157 # if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
 158 #  define cpu_has_vint          (cpu_data[0].options & MIPS_CPU_VINT)
 159 # else
 160 #  define cpu_has_vint                  0
 161 # endif
 162 # if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
 163 #  define cpu_has_veic          (cpu_data[0].options & MIPS_CPU_VEIC)
 164 # else
 165 #  define cpu_has_veic                  0
 166 # endif
 167 #else
 168 # define cpu_has_vint                   0
 169 # define cpu_has_veic                   0
 170 #endif
 171
 172 #ifndef cpu_has_subset_pcaches
 173 #define cpu_has_subset_pcaches  (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
 174 #endif
 175
 176 #ifndef cpu_dcache_line_size
 177 #define cpu_dcache_line_size()  current_cpu_data.dcache.linesz
 178 #endif
 179 #ifndef cpu_icache_line_size
 180 #define cpu_icache_line_size()  current_cpu_data.icache.linesz
 181 #endif
 182 #ifndef cpu_scache_line_size
 183 #define cpu_scache_line_size()  current_cpu_data.scache.linesz
 184 #endif
 185
 186 #endif /* __ASM_CPU_FEATURES_H */