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omap: McBSP: Modify macros/functions API for easy cache access
[linux-2.6/kvm.git] / arch / arm / plat-omap / mcbsp.c
blobf8245f25825b9996c25275a61b8b18d672ec6ee8
1 /*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26
27 #include <plat/dma.h>
28 #include <plat/mcbsp.h>
29
30 struct omap_mcbsp **mcbsp_ptr;
31 int omap_mcbsp_count;
32
33 void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
34 {
35 if (cpu_class_is_omap1() || cpu_is_omap2420())
36 __raw_writew((u16)val, mcbsp->io_base + reg);
37 else
38 __raw_writel(val, mcbsp->io_base + reg);
39 }
40
41 int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg)
42 {
43 if (cpu_class_is_omap1() || cpu_is_omap2420())
44 return __raw_readw(mcbsp->io_base + reg);
45 else
46 return __raw_readl(mcbsp->io_base + reg);
47 }
48
49 #define MCBSP_READ(mcbsp, reg) \
50 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg)
51 #define MCBSP_WRITE(mcbsp, reg, val) \
52 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
53
54 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
55 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
56
57 static void omap_mcbsp_dump_reg(u8 id)
58 {
59 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
60
61 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
62 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
63 MCBSP_READ(mcbsp, DRR2));
64 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
65 MCBSP_READ(mcbsp, DRR1));
66 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
67 MCBSP_READ(mcbsp, DXR2));
68 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
69 MCBSP_READ(mcbsp, DXR1));
70 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
71 MCBSP_READ(mcbsp, SPCR2));
72 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
73 MCBSP_READ(mcbsp, SPCR1));
74 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
75 MCBSP_READ(mcbsp, RCR2));
76 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
77 MCBSP_READ(mcbsp, RCR1));
78 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
79 MCBSP_READ(mcbsp, XCR2));
80 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
81 MCBSP_READ(mcbsp, XCR1));
82 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
83 MCBSP_READ(mcbsp, SRGR2));
84 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
85 MCBSP_READ(mcbsp, SRGR1));
86 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
87 MCBSP_READ(mcbsp, PCR0));
88 dev_dbg(mcbsp->dev, "***********************\n");
89 }
90
91 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
92 {
93 struct omap_mcbsp *mcbsp_tx = dev_id;
94 u16 irqst_spcr2;
95
96 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
97 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
98
99 if (irqst_spcr2 & XSYNC_ERR) {
100 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
101 irqst_spcr2);
102 /* Writing zero to XSYNC_ERR clears the IRQ */
103 MCBSP_WRITE(mcbsp_tx, SPCR2, irqst_spcr2 & ~(XSYNC_ERR));
104 } else {
105 complete(&mcbsp_tx->tx_irq_completion);
106 }
107
108 return IRQ_HANDLED;
109 }
110
111 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
112 {
113 struct omap_mcbsp *mcbsp_rx = dev_id;
114 u16 irqst_spcr1;
115
116 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
117 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
118
119 if (irqst_spcr1 & RSYNC_ERR) {
120 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
121 irqst_spcr1);
122 /* Writing zero to RSYNC_ERR clears the IRQ */
123 MCBSP_WRITE(mcbsp_rx, SPCR1, irqst_spcr1 & ~(RSYNC_ERR));
124 } else {
125 complete(&mcbsp_rx->tx_irq_completion);
126 }
127
128 return IRQ_HANDLED;
129 }
130
131 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
132 {
133 struct omap_mcbsp *mcbsp_dma_tx = data;
134
135 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
136 MCBSP_READ(mcbsp_dma_tx, SPCR2));
137
138 /* We can free the channels */
139 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
140 mcbsp_dma_tx->dma_tx_lch = -1;
141
142 complete(&mcbsp_dma_tx->tx_dma_completion);
143 }
144
145 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
146 {
147 struct omap_mcbsp *mcbsp_dma_rx = data;
148
149 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
150 MCBSP_READ(mcbsp_dma_rx, SPCR2));
151
152 /* We can free the channels */
153 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
154 mcbsp_dma_rx->dma_rx_lch = -1;
155
156 complete(&mcbsp_dma_rx->rx_dma_completion);
157 }
158
159 /*
160 * omap_mcbsp_config simply write a config to the
161 * appropriate McBSP.
162 * You either call this function or set the McBSP registers
163 * by yourself before calling omap_mcbsp_start().
164 */
165 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
166 {
167 struct omap_mcbsp *mcbsp;
168
169 if (!omap_mcbsp_check_valid_id(id)) {
170 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
171 return;
172 }
173 mcbsp = id_to_mcbsp_ptr(id);
174
175 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
176 mcbsp->id, mcbsp->phys_base);
177
178 /* We write the given config */
179 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
180 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
181 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
182 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
183 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
184 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
185 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
186 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
187 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
188 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
189 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
190 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
191 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
192 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
193 }
194 }
195 EXPORT_SYMBOL(omap_mcbsp_config);
196
197 #ifdef CONFIG_ARCH_OMAP3
198 /*
199 * omap_mcbsp_set_tx_threshold configures how to deal
200 * with transmit threshold. the threshold value and handler can be
201 * configure in here.
202 */
203 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
204 {
205 struct omap_mcbsp *mcbsp;
206
207 if (!cpu_is_omap34xx())
208 return;
209
210 if (!omap_mcbsp_check_valid_id(id)) {
211 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
212 return;
213 }
214 mcbsp = id_to_mcbsp_ptr(id);
215
216 MCBSP_WRITE(mcbsp, THRSH2, threshold);
217 }
218 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
219
220 /*
221 * omap_mcbsp_set_rx_threshold configures how to deal
222 * with receive threshold. the threshold value and handler can be
223 * configure in here.
224 */
225 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
226 {
227 struct omap_mcbsp *mcbsp;
228
229 if (!cpu_is_omap34xx())
230 return;
231
232 if (!omap_mcbsp_check_valid_id(id)) {
233 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
234 return;
235 }
236 mcbsp = id_to_mcbsp_ptr(id);
237
238 MCBSP_WRITE(mcbsp, THRSH1, threshold);
239 }
240 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
241
242 /*
243 * omap_mcbsp_get_max_tx_thres just return the current configured
244 * maximum threshold for transmission
245 */
246 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
247 {
248 struct omap_mcbsp *mcbsp;
249
250 if (!omap_mcbsp_check_valid_id(id)) {
251 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
252 return -ENODEV;
253 }
254 mcbsp = id_to_mcbsp_ptr(id);
255
256 return mcbsp->max_tx_thres;
257 }
258 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
259
260 /*
261 * omap_mcbsp_get_max_rx_thres just return the current configured
262 * maximum threshold for reception
263 */
264 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
265 {
266 struct omap_mcbsp *mcbsp;
267
268 if (!omap_mcbsp_check_valid_id(id)) {
269 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
270 return -ENODEV;
271 }
272 mcbsp = id_to_mcbsp_ptr(id);
273
274 return mcbsp->max_rx_thres;
275 }
276 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
277
278 /*
279 * omap_mcbsp_get_dma_op_mode just return the current configured
280 * operating mode for the mcbsp channel
281 */
282 int omap_mcbsp_get_dma_op_mode(unsigned int id)
283 {
284 struct omap_mcbsp *mcbsp;
285 int dma_op_mode;
286
287 if (!omap_mcbsp_check_valid_id(id)) {
288 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
289 return -ENODEV;
290 }
291 mcbsp = id_to_mcbsp_ptr(id);
292
293 dma_op_mode = mcbsp->dma_op_mode;
294
295 return dma_op_mode;
296 }
297 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
298
299 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
300 {
301 /*
302 * Enable wakup behavior, smart idle and all wakeups
303 * REVISIT: some wakeups may be unnecessary
304 */
305 if (cpu_is_omap34xx()) {
306 u16 syscon;
307
308 syscon = MCBSP_READ(mcbsp, SYSCON);
309 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
310
311 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
312 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
313 CLOCKACTIVITY(0x02));
314 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
315 } else {
316 syscon |= SIDLEMODE(0x01);
317 }
318
319 MCBSP_WRITE(mcbsp, SYSCON, syscon);
320 }
321 }
322
323 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
324 {
325 /*
326 * Disable wakup behavior, smart idle and all wakeups
327 */
328 if (cpu_is_omap34xx()) {
329 u16 syscon;
330
331 syscon = MCBSP_READ(mcbsp, SYSCON);
332 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
333 /*
334 * HW bug workaround - If no_idle mode is taken, we need to
335 * go to smart_idle before going to always_idle, or the
336 * device will not hit retention anymore.
337 */
338 syscon |= SIDLEMODE(0x02);
339 MCBSP_WRITE(mcbsp, SYSCON, syscon);
340
341 syscon &= ~(SIDLEMODE(0x03));
342 MCBSP_WRITE(mcbsp, SYSCON, syscon);
343
344 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
345 }
346 }
347 #else
348 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
349 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
350 #endif
351
352 /*
353 * We can choose between IRQ based or polled IO.
354 * This needs to be called before omap_mcbsp_request().
355 */
356 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
357 {
358 struct omap_mcbsp *mcbsp;
359
360 if (!omap_mcbsp_check_valid_id(id)) {
361 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
362 return -ENODEV;
363 }
364 mcbsp = id_to_mcbsp_ptr(id);
365
366 spin_lock(&mcbsp->lock);
367
368 if (!mcbsp->free) {
369 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
370 mcbsp->id);
371 spin_unlock(&mcbsp->lock);
372 return -EINVAL;
373 }
374
375 mcbsp->io_type = io_type;
376
377 spin_unlock(&mcbsp->lock);
378
379 return 0;
380 }
381 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
382
383 int omap_mcbsp_request(unsigned int id)
384 {
385 struct omap_mcbsp *mcbsp;
386 int err;
387
388 if (!omap_mcbsp_check_valid_id(id)) {
389 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
390 return -ENODEV;
391 }
392 mcbsp = id_to_mcbsp_ptr(id);
393
394 spin_lock(&mcbsp->lock);
395 if (!mcbsp->free) {
396 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
397 mcbsp->id);
398 spin_unlock(&mcbsp->lock);
399 return -EBUSY;
400 }
401
402 mcbsp->free = 0;
403 spin_unlock(&mcbsp->lock);
404
405 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
406 mcbsp->pdata->ops->request(id);
407
408 clk_enable(mcbsp->iclk);
409 clk_enable(mcbsp->fclk);
410
411 /* Do procedure specific to omap34xx arch, if applicable */
412 omap34xx_mcbsp_request(mcbsp);
413
414 /*
415 * Make sure that transmitter, receiver and sample-rate generator are
416 * not running before activating IRQs.
417 */
418 MCBSP_WRITE(mcbsp, SPCR1, 0);
419 MCBSP_WRITE(mcbsp, SPCR2, 0);
420
421 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
422 /* We need to get IRQs here */
423 init_completion(&mcbsp->tx_irq_completion);
424 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
425 0, "McBSP", (void *)mcbsp);
426 if (err != 0) {
427 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
428 "for McBSP%d\n", mcbsp->tx_irq,
429 mcbsp->id);
430 goto error;
431 }
432
433 init_completion(&mcbsp->rx_irq_completion);
434 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
435 0, "McBSP", (void *)mcbsp);
436 if (err != 0) {
437 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
438 "for McBSP%d\n", mcbsp->rx_irq,
439 mcbsp->id);
440 goto tx_irq;
441 }
442 }
443
444 return 0;
445 tx_irq:
446 free_irq(mcbsp->tx_irq, (void *)mcbsp);
447 error:
448 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
449 mcbsp->pdata->ops->free(id);
450
451 /* Do procedure specific to omap34xx arch, if applicable */
452 omap34xx_mcbsp_free(mcbsp);
453
454 clk_disable(mcbsp->fclk);
455 clk_disable(mcbsp->iclk);
456
457 mcbsp->free = 1;
458
459 return err;
460 }
461 EXPORT_SYMBOL(omap_mcbsp_request);
462
463 void omap_mcbsp_free(unsigned int id)
464 {
465 struct omap_mcbsp *mcbsp;
466
467 if (!omap_mcbsp_check_valid_id(id)) {
468 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
469 return;
470 }
471 mcbsp = id_to_mcbsp_ptr(id);
472
473 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
474 mcbsp->pdata->ops->free(id);
475
476 /* Do procedure specific to omap34xx arch, if applicable */
477 omap34xx_mcbsp_free(mcbsp);
478
479 clk_disable(mcbsp->fclk);
480 clk_disable(mcbsp->iclk);
481
482 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
483 /* Free IRQs */
484 free_irq(mcbsp->rx_irq, (void *)mcbsp);
485 free_irq(mcbsp->tx_irq, (void *)mcbsp);
486 }
487
488 spin_lock(&mcbsp->lock);
489 if (mcbsp->free) {
490 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
491 mcbsp->id);
492 spin_unlock(&mcbsp->lock);
493 return;
494 }
495
496 mcbsp->free = 1;
497 spin_unlock(&mcbsp->lock);
498 }
499 EXPORT_SYMBOL(omap_mcbsp_free);
500
501 /*
502 * Here we start the McBSP, by enabling transmitter, receiver or both.
503 * If no transmitter or receiver is active prior calling, then sample-rate
504 * generator and frame sync are started.
505 */
506 void omap_mcbsp_start(unsigned int id, int tx, int rx)
507 {
508 struct omap_mcbsp *mcbsp;
509 int idle;
510 u16 w;
511
512 if (!omap_mcbsp_check_valid_id(id)) {
513 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
514 return;
515 }
516 mcbsp = id_to_mcbsp_ptr(id);
517
518 mcbsp->rx_word_length = (MCBSP_READ(mcbsp, RCR1) >> 5) & 0x7;
519 mcbsp->tx_word_length = (MCBSP_READ(mcbsp, XCR1) >> 5) & 0x7;
520
521 idle = !((MCBSP_READ(mcbsp, SPCR2) | MCBSP_READ(mcbsp, SPCR1)) & 1);
522
523 if (idle) {
524 /* Start the sample generator */
525 w = MCBSP_READ(mcbsp, SPCR2);
526 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
527 }
528
529 /* Enable transmitter and receiver */
530 tx &= 1;
531 w = MCBSP_READ(mcbsp, SPCR2);
532 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
533
534 rx &= 1;
535 w = MCBSP_READ(mcbsp, SPCR1);
536 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
537
538 /*
539 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
540 * REVISIT: 100us may give enough time for two CLKSRG, however
541 * due to some unknown PM related, clock gating etc. reason it
542 * is now at 500us.
543 */
544 udelay(500);
545
546 if (idle) {
547 /* Start frame sync */
548 w = MCBSP_READ(mcbsp, SPCR2);
549 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
550 }
551
552 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
553 /* Release the transmitter and receiver */
554 w = MCBSP_READ(mcbsp, XCCR);
555 w &= ~(tx ? XDISABLE : 0);
556 MCBSP_WRITE(mcbsp, XCCR, w);
557 w = MCBSP_READ(mcbsp, RCCR);
558 w &= ~(rx ? RDISABLE : 0);
559 MCBSP_WRITE(mcbsp, RCCR, w);
560 }
561
562 /* Dump McBSP Regs */
563 omap_mcbsp_dump_reg(id);
564 }
565 EXPORT_SYMBOL(omap_mcbsp_start);
566
567 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
568 {
569 struct omap_mcbsp *mcbsp;
570 int idle;
571 u16 w;
572
573 if (!omap_mcbsp_check_valid_id(id)) {
574 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
575 return;
576 }
577
578 mcbsp = id_to_mcbsp_ptr(id);
579
580 /* Reset transmitter */
581 tx &= 1;
582 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
583 w = MCBSP_READ(mcbsp, XCCR);
584 w |= (tx ? XDISABLE : 0);
585 MCBSP_WRITE(mcbsp, XCCR, w);
586 }
587 w = MCBSP_READ(mcbsp, SPCR2);
588 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
589
590 /* Reset receiver */
591 rx &= 1;
592 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
593 w = MCBSP_READ(mcbsp, RCCR);
594 w |= (rx ? RDISABLE : 0);
595 MCBSP_WRITE(mcbsp, RCCR, w);
596 }
597 w = MCBSP_READ(mcbsp, SPCR1);
598 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
599
600 idle = !((MCBSP_READ(mcbsp, SPCR2) | MCBSP_READ(mcbsp, SPCR1)) & 1);
601
602 if (idle) {
603 /* Reset the sample rate generator */
604 w = MCBSP_READ(mcbsp, SPCR2);
605 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
606 }
607 }
608 EXPORT_SYMBOL(omap_mcbsp_stop);
609
610 /* polled mcbsp i/o operations */
611 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
612 {
613 struct omap_mcbsp *mcbsp;
614
615 if (!omap_mcbsp_check_valid_id(id)) {
616 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
617 return -ENODEV;
618 }
619
620 mcbsp = id_to_mcbsp_ptr(id);
621
622 MCBSP_WRITE(mcbsp, DXR1, buf);
623 /* if frame sync error - clear the error */
624 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
625 /* clear error */
626 MCBSP_WRITE(mcbsp, SPCR2,
627 MCBSP_READ(mcbsp, SPCR2) & (~XSYNC_ERR));
628 /* resend */
629 return -1;
630 } else {
631 /* wait for transmit confirmation */
632 int attemps = 0;
633 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
634 if (attemps++ > 1000) {
635 MCBSP_WRITE(mcbsp, SPCR2,
636 MCBSP_READ(mcbsp, SPCR2) & (~XRST));
637 udelay(10);
638 MCBSP_WRITE(mcbsp, SPCR2,
639 MCBSP_READ(mcbsp, SPCR2) | (XRST));
640 udelay(10);
641 dev_err(mcbsp->dev, "Could not write to"
642 " McBSP%d Register\n", mcbsp->id);
643 return -2;
644 }
645 }
646 }
647
648 return 0;
649 }
650 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
651
652 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
653 {
654 struct omap_mcbsp *mcbsp;
655
656 if (!omap_mcbsp_check_valid_id(id)) {
657 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
658 return -ENODEV;
659 }
660 mcbsp = id_to_mcbsp_ptr(id);
661
662 /* if frame sync error - clear the error */
663 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
664 /* clear error */
665 MCBSP_WRITE(mcbsp, SPCR1,
666 MCBSP_READ(mcbsp, SPCR1) & (~RSYNC_ERR));
667 /* resend */
668 return -1;
669 } else {
670 /* wait for recieve confirmation */
671 int attemps = 0;
672 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
673 if (attemps++ > 1000) {
674 MCBSP_WRITE(mcbsp, SPCR1,
675 MCBSP_READ(mcbsp, SPCR1) & (~RRST));
676 udelay(10);
677 MCBSP_WRITE(mcbsp, SPCR1,
678 MCBSP_READ(mcbsp, SPCR1) | (RRST));
679 udelay(10);
680 dev_err(mcbsp->dev, "Could not read from"
681 " McBSP%d Register\n", mcbsp->id);
682 return -2;
683 }
684 }
685 }
686 *buf = MCBSP_READ(mcbsp, DRR1);
687
688 return 0;
689 }
690 EXPORT_SYMBOL(omap_mcbsp_pollread);
691
692 /*
693 * IRQ based word transmission.
694 */
695 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
696 {
697 struct omap_mcbsp *mcbsp;
698 omap_mcbsp_word_length word_length;
699
700 if (!omap_mcbsp_check_valid_id(id)) {
701 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
702 return;
703 }
704
705 mcbsp = id_to_mcbsp_ptr(id);
706 word_length = mcbsp->tx_word_length;
707
708 wait_for_completion(&mcbsp->tx_irq_completion);
709
710 if (word_length > OMAP_MCBSP_WORD_16)
711 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
712 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
713 }
714 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
715
716 u32 omap_mcbsp_recv_word(unsigned int id)
717 {
718 struct omap_mcbsp *mcbsp;
719 u16 word_lsb, word_msb = 0;
720 omap_mcbsp_word_length word_length;
721
722 if (!omap_mcbsp_check_valid_id(id)) {
723 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
724 return -ENODEV;
725 }
726 mcbsp = id_to_mcbsp_ptr(id);
727
728 word_length = mcbsp->rx_word_length;
729
730 wait_for_completion(&mcbsp->rx_irq_completion);
731
732 if (word_length > OMAP_MCBSP_WORD_16)
733 word_msb = MCBSP_READ(mcbsp, DRR2);
734 word_lsb = MCBSP_READ(mcbsp, DRR1);
735
736 return (word_lsb | (word_msb << 16));
737 }
738 EXPORT_SYMBOL(omap_mcbsp_recv_word);
739
740 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
741 {
742 struct omap_mcbsp *mcbsp;
743 omap_mcbsp_word_length tx_word_length;
744 omap_mcbsp_word_length rx_word_length;
745 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
746
747 if (!omap_mcbsp_check_valid_id(id)) {
748 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
749 return -ENODEV;
750 }
751 mcbsp = id_to_mcbsp_ptr(id);
752 tx_word_length = mcbsp->tx_word_length;
753 rx_word_length = mcbsp->rx_word_length;
754
755 if (tx_word_length != rx_word_length)
756 return -EINVAL;
757
758 /* First we wait for the transmitter to be ready */
759 spcr2 = MCBSP_READ(mcbsp, SPCR2);
760 while (!(spcr2 & XRDY)) {
761 spcr2 = MCBSP_READ(mcbsp, SPCR2);
762 if (attempts++ > 1000) {
763 /* We must reset the transmitter */
764 MCBSP_WRITE(mcbsp, SPCR2, spcr2 & (~XRST));
765 udelay(10);
766 MCBSP_WRITE(mcbsp, SPCR2, spcr2 | XRST);
767 udelay(10);
768 dev_err(mcbsp->dev, "McBSP%d transmitter not "
769 "ready\n", mcbsp->id);
770 return -EAGAIN;
771 }
772 }
773
774 /* Now we can push the data */
775 if (tx_word_length > OMAP_MCBSP_WORD_16)
776 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
777 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
778
779 /* We wait for the receiver to be ready */
780 spcr1 = MCBSP_READ(mcbsp, SPCR1);
781 while (!(spcr1 & RRDY)) {
782 spcr1 = MCBSP_READ(mcbsp, SPCR1);
783 if (attempts++ > 1000) {
784 /* We must reset the receiver */
785 MCBSP_WRITE(mcbsp, SPCR1, spcr1 & (~RRST));
786 udelay(10);
787 MCBSP_WRITE(mcbsp, SPCR1, spcr1 | RRST);
788 udelay(10);
789 dev_err(mcbsp->dev, "McBSP%d receiver not "
790 "ready\n", mcbsp->id);
791 return -EAGAIN;
792 }
793 }
794
795 /* Receiver is ready, let's read the dummy data */
796 if (rx_word_length > OMAP_MCBSP_WORD_16)
797 word_msb = MCBSP_READ(mcbsp, DRR2);
798 word_lsb = MCBSP_READ(mcbsp, DRR1);
799
800 return 0;
801 }
802 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
803
804 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
805 {
806 struct omap_mcbsp *mcbsp;
807 u32 clock_word = 0;
808 omap_mcbsp_word_length tx_word_length;
809 omap_mcbsp_word_length rx_word_length;
810 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
811
812 if (!omap_mcbsp_check_valid_id(id)) {
813 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
814 return -ENODEV;
815 }
816
817 mcbsp = id_to_mcbsp_ptr(id);
818
819 tx_word_length = mcbsp->tx_word_length;
820 rx_word_length = mcbsp->rx_word_length;
821
822 if (tx_word_length != rx_word_length)
823 return -EINVAL;
824
825 /* First we wait for the transmitter to be ready */
826 spcr2 = MCBSP_READ(mcbsp, SPCR2);
827 while (!(spcr2 & XRDY)) {
828 spcr2 = MCBSP_READ(mcbsp, SPCR2);
829 if (attempts++ > 1000) {
830 /* We must reset the transmitter */
831 MCBSP_WRITE(mcbsp, SPCR2, spcr2 & (~XRST));
832 udelay(10);
833 MCBSP_WRITE(mcbsp, SPCR2, spcr2 | XRST);
834 udelay(10);
835 dev_err(mcbsp->dev, "McBSP%d transmitter not "
836 "ready\n", mcbsp->id);
837 return -EAGAIN;
838 }
839 }
840
841 /* We first need to enable the bus clock */
842 if (tx_word_length > OMAP_MCBSP_WORD_16)
843 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
844 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
845
846 /* We wait for the receiver to be ready */
847 spcr1 = MCBSP_READ(mcbsp, SPCR1);
848 while (!(spcr1 & RRDY)) {
849 spcr1 = MCBSP_READ(mcbsp, SPCR1);
850 if (attempts++ > 1000) {
851 /* We must reset the receiver */
852 MCBSP_WRITE(mcbsp, SPCR1, spcr1 & (~RRST));
853 udelay(10);
854 MCBSP_WRITE(mcbsp, SPCR1, spcr1 | RRST);
855 udelay(10);
856 dev_err(mcbsp->dev, "McBSP%d receiver not "
857 "ready\n", mcbsp->id);
858 return -EAGAIN;
859 }
860 }
861
862 /* Receiver is ready, there is something for us */
863 if (rx_word_length > OMAP_MCBSP_WORD_16)
864 word_msb = MCBSP_READ(mcbsp, DRR2);
865 word_lsb = MCBSP_READ(mcbsp, DRR1);
866
867 word[0] = (word_lsb | (word_msb << 16));
868
869 return 0;
870 }
871 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
872
873 /*
874 * Simple DMA based buffer rx/tx routines.
875 * Nothing fancy, just a single buffer tx/rx through DMA.
876 * The DMA resources are released once the transfer is done.
877 * For anything fancier, you should use your own customized DMA
878 * routines and callbacks.
879 */
880 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
881 unsigned int length)
882 {
883 struct omap_mcbsp *mcbsp;
884 int dma_tx_ch;
885 int src_port = 0;
886 int dest_port = 0;
887 int sync_dev = 0;
888
889 if (!omap_mcbsp_check_valid_id(id)) {
890 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
891 return -ENODEV;
892 }
893 mcbsp = id_to_mcbsp_ptr(id);
894
895 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
896 omap_mcbsp_tx_dma_callback,
897 mcbsp,
898 &dma_tx_ch)) {
899 dev_err(mcbsp->dev, " Unable to request DMA channel for "
900 "McBSP%d TX. Trying IRQ based TX\n",
901 mcbsp->id);
902 return -EAGAIN;
903 }
904 mcbsp->dma_tx_lch = dma_tx_ch;
905
906 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
907 dma_tx_ch);
908
909 init_completion(&mcbsp->tx_dma_completion);
910
911 if (cpu_class_is_omap1()) {
912 src_port = OMAP_DMA_PORT_TIPB;
913 dest_port = OMAP_DMA_PORT_EMIFF;
914 }
915 if (cpu_class_is_omap2())
916 sync_dev = mcbsp->dma_tx_sync;
917
918 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
919 OMAP_DMA_DATA_TYPE_S16,
920 length >> 1, 1,
921 OMAP_DMA_SYNC_ELEMENT,
922 sync_dev, 0);
923
924 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
925 src_port,
926 OMAP_DMA_AMODE_CONSTANT,
927 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
928 0, 0);
929
930 omap_set_dma_src_params(mcbsp->dma_tx_lch,
931 dest_port,
932 OMAP_DMA_AMODE_POST_INC,
933 buffer,
934 0, 0);
935
936 omap_start_dma(mcbsp->dma_tx_lch);
937 wait_for_completion(&mcbsp->tx_dma_completion);
938
939 return 0;
940 }
941 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
942
943 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
944 unsigned int length)
945 {
946 struct omap_mcbsp *mcbsp;
947 int dma_rx_ch;
948 int src_port = 0;
949 int dest_port = 0;
950 int sync_dev = 0;
951
952 if (!omap_mcbsp_check_valid_id(id)) {
953 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
954 return -ENODEV;
955 }
956 mcbsp = id_to_mcbsp_ptr(id);
957
958 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
959 omap_mcbsp_rx_dma_callback,
960 mcbsp,
961 &dma_rx_ch)) {
962 dev_err(mcbsp->dev, "Unable to request DMA channel for "
963 "McBSP%d RX. Trying IRQ based RX\n",
964 mcbsp->id);
965 return -EAGAIN;
966 }
967 mcbsp->dma_rx_lch = dma_rx_ch;
968
969 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
970 dma_rx_ch);
971
972 init_completion(&mcbsp->rx_dma_completion);
973
974 if (cpu_class_is_omap1()) {
975 src_port = OMAP_DMA_PORT_TIPB;
976 dest_port = OMAP_DMA_PORT_EMIFF;
977 }
978 if (cpu_class_is_omap2())
979 sync_dev = mcbsp->dma_rx_sync;
980
981 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
982 OMAP_DMA_DATA_TYPE_S16,
983 length >> 1, 1,
984 OMAP_DMA_SYNC_ELEMENT,
985 sync_dev, 0);
986
987 omap_set_dma_src_params(mcbsp->dma_rx_lch,
988 src_port,
989 OMAP_DMA_AMODE_CONSTANT,
990 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
991 0, 0);
992
993 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
994 dest_port,
995 OMAP_DMA_AMODE_POST_INC,
996 buffer,
997 0, 0);
998
999 omap_start_dma(mcbsp->dma_rx_lch);
1000 wait_for_completion(&mcbsp->rx_dma_completion);
1001
1002 return 0;
1003 }
1004 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1005
1006 /*
1007 * SPI wrapper.
1008 * Since SPI setup is much simpler than the generic McBSP one,
1009 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1010 * Once this is done, you can call omap_mcbsp_start().
1011 */
1012 void omap_mcbsp_set_spi_mode(unsigned int id,
1013 const struct omap_mcbsp_spi_cfg *spi_cfg)
1014 {
1015 struct omap_mcbsp *mcbsp;
1016 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1017
1018 if (!omap_mcbsp_check_valid_id(id)) {
1019 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1020 return;
1021 }
1022 mcbsp = id_to_mcbsp_ptr(id);
1023
1024 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1025
1026 /* SPI has only one frame */
1027 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1028 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1029
1030 /* Clock stop mode */
1031 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1032 mcbsp_cfg.spcr1 |= (1 << 12);
1033 else
1034 mcbsp_cfg.spcr1 |= (3 << 11);
1035
1036 /* Set clock parities */
1037 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1038 mcbsp_cfg.pcr0 |= CLKRP;
1039 else
1040 mcbsp_cfg.pcr0 &= ~CLKRP;
1041
1042 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1043 mcbsp_cfg.pcr0 &= ~CLKXP;
1044 else
1045 mcbsp_cfg.pcr0 |= CLKXP;
1046
1047 /* Set SCLKME to 0 and CLKSM to 1 */
1048 mcbsp_cfg.pcr0 &= ~SCLKME;
1049 mcbsp_cfg.srgr2 |= CLKSM;
1050
1051 /* Set FSXP */
1052 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1053 mcbsp_cfg.pcr0 &= ~FSXP;
1054 else
1055 mcbsp_cfg.pcr0 |= FSXP;
1056
1057 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1058 mcbsp_cfg.pcr0 |= CLKXM;
1059 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1060 mcbsp_cfg.pcr0 |= FSXM;
1061 mcbsp_cfg.srgr2 &= ~FSGM;
1062 mcbsp_cfg.xcr2 |= XDATDLY(1);
1063 mcbsp_cfg.rcr2 |= RDATDLY(1);
1064 } else {
1065 mcbsp_cfg.pcr0 &= ~CLKXM;
1066 mcbsp_cfg.srgr1 |= CLKGDV(1);
1067 mcbsp_cfg.pcr0 &= ~FSXM;
1068 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1069 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1070 }
1071
1072 mcbsp_cfg.xcr2 &= ~XPHASE;
1073 mcbsp_cfg.rcr2 &= ~RPHASE;
1074
1075 omap_mcbsp_config(id, &mcbsp_cfg);
1076 }
1077 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1078
1079 #ifdef CONFIG_ARCH_OMAP3
1080 #define max_thres(m) (mcbsp->pdata->buffer_size)
1081 #define valid_threshold(m, val) ((val) <= max_thres(m))
1082 #define THRESHOLD_PROP_BUILDER(prop) \
1083 static ssize_t prop##_show(struct device *dev, \
1084 struct device_attribute *attr, char *buf) \
1085 { \
1086 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1087 \
1088 return sprintf(buf, "%u\n", mcbsp->prop); \
1089 } \
1090 \
1091 static ssize_t prop##_store(struct device *dev, \
1092 struct device_attribute *attr, \
1093 const char *buf, size_t size) \
1094 { \
1095 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1096 unsigned long val; \
1097 int status; \
1098 \
1099 status = strict_strtoul(buf, 0, &val); \
1100 if (status) \
1101 return status; \
1102 \
1103 if (!valid_threshold(mcbsp, val)) \
1104 return -EDOM; \
1105 \
1106 mcbsp->prop = val; \
1107 return size; \
1108 } \
1109 \
1110 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1111
1112 THRESHOLD_PROP_BUILDER(max_tx_thres);
1113 THRESHOLD_PROP_BUILDER(max_rx_thres);
1114
1115 static const char *dma_op_modes[] = {
1116 "element", "threshold", "frame",
1117 };
1118
1119 static ssize_t dma_op_mode_show(struct device *dev,
1120 struct device_attribute *attr, char *buf)
1121 {
1122 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1123 int dma_op_mode, i = 0;
1124 ssize_t len = 0;
1125 const char * const *s;
1126
1127 dma_op_mode = mcbsp->dma_op_mode;
1128
1129 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1130 if (dma_op_mode == i)
1131 len += sprintf(buf + len, "[%s] ", *s);
1132 else
1133 len += sprintf(buf + len, "%s ", *s);
1134 }
1135 len += sprintf(buf + len, "\n");
1136
1137 return len;
1138 }
1139
1140 static ssize_t dma_op_mode_store(struct device *dev,
1141 struct device_attribute *attr,
1142 const char *buf, size_t size)
1143 {
1144 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1145 const char * const *s;
1146 int i = 0;
1147
1148 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1149 if (sysfs_streq(buf, *s))
1150 break;
1151
1152 if (i == ARRAY_SIZE(dma_op_modes))
1153 return -EINVAL;
1154
1155 spin_lock_irq(&mcbsp->lock);
1156 if (!mcbsp->free) {
1157 size = -EBUSY;
1158 goto unlock;
1159 }
1160 mcbsp->dma_op_mode = i;
1161
1162 unlock:
1163 spin_unlock_irq(&mcbsp->lock);
1164
1165 return size;
1166 }
1167
1168 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1169
1170 static const struct attribute *additional_attrs[] = {
1171 &dev_attr_max_tx_thres.attr,
1172 &dev_attr_max_rx_thres.attr,
1173 &dev_attr_dma_op_mode.attr,
1174 NULL,
1175 };
1176
1177 static const struct attribute_group additional_attr_group = {
1178 .attrs = (struct attribute **)additional_attrs,
1179 };
1180
1181 static inline int __devinit omap_additional_add(struct device *dev)
1182 {
1183 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1184 }
1185
1186 static inline void __devexit omap_additional_remove(struct device *dev)
1187 {
1188 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1189 }
1190
1191 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1192 {
1193 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1194 if (cpu_is_omap34xx()) {
1195 mcbsp->max_tx_thres = max_thres(mcbsp);
1196 mcbsp->max_rx_thres = max_thres(mcbsp);
1197 /*
1198 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1199 * for mcbsp2 instances.
1200 */
1201 if (omap_additional_add(mcbsp->dev))
1202 dev_warn(mcbsp->dev,
1203 "Unable to create additional controls\n");
1204 } else {
1205 mcbsp->max_tx_thres = -EINVAL;
1206 mcbsp->max_rx_thres = -EINVAL;
1207 }
1208 }
1209
1210 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1211 {
1212 if (cpu_is_omap34xx())
1213 omap_additional_remove(mcbsp->dev);
1214 }
1215 #else
1216 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1217 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1218 #endif /* CONFIG_ARCH_OMAP3 */
1219
1220 /*
1221 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1222 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1223 */
1224 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1225 {
1226 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1227 struct omap_mcbsp *mcbsp;
1228 int id = pdev->id - 1;
1229 int ret = 0;
1230
1231 if (!pdata) {
1232 dev_err(&pdev->dev, "McBSP device initialized without"
1233 "platform data\n");
1234 ret = -EINVAL;
1235 goto exit;
1236 }
1237
1238 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1239
1240 if (id >= omap_mcbsp_count) {
1241 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1242 ret = -EINVAL;
1243 goto exit;
1244 }
1245
1246 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1247 if (!mcbsp) {
1248 ret = -ENOMEM;
1249 goto exit;
1250 }
1251
1252 spin_lock_init(&mcbsp->lock);
1253 mcbsp->id = id + 1;
1254 mcbsp->free = 1;
1255 mcbsp->dma_tx_lch = -1;
1256 mcbsp->dma_rx_lch = -1;
1257
1258 mcbsp->phys_base = pdata->phys_base;
1259 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1260 if (!mcbsp->io_base) {
1261 ret = -ENOMEM;
1262 goto err_ioremap;
1263 }
1264
1265 /* Default I/O is IRQ based */
1266 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1267 mcbsp->tx_irq = pdata->tx_irq;
1268 mcbsp->rx_irq = pdata->rx_irq;
1269 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1270 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1271
1272 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1273 if (IS_ERR(mcbsp->iclk)) {
1274 ret = PTR_ERR(mcbsp->iclk);
1275 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1276 goto err_iclk;
1277 }
1278
1279 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1280 if (IS_ERR(mcbsp->fclk)) {
1281 ret = PTR_ERR(mcbsp->fclk);
1282 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1283 goto err_fclk;
1284 }
1285
1286 mcbsp->pdata = pdata;
1287 mcbsp->dev = &pdev->dev;
1288 mcbsp_ptr[id] = mcbsp;
1289 platform_set_drvdata(pdev, mcbsp);
1290
1291 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1292 omap34xx_device_init(mcbsp);
1293
1294 return 0;
1295
1296 err_fclk:
1297 clk_put(mcbsp->iclk);
1298 err_iclk:
1299 iounmap(mcbsp->io_base);
1300 err_ioremap:
1301 kfree(mcbsp);
1302 exit:
1303 return ret;
1304 }
1305
1306 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1307 {
1308 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1309
1310 platform_set_drvdata(pdev, NULL);
1311 if (mcbsp) {
1312
1313 if (mcbsp->pdata && mcbsp->pdata->ops &&
1314 mcbsp->pdata->ops->free)
1315 mcbsp->pdata->ops->free(mcbsp->id);
1316
1317 omap34xx_device_exit(mcbsp);
1318
1319 clk_disable(mcbsp->fclk);
1320 clk_disable(mcbsp->iclk);
1321 clk_put(mcbsp->fclk);
1322 clk_put(mcbsp->iclk);
1323
1324 iounmap(mcbsp->io_base);
1325
1326 mcbsp->fclk = NULL;
1327 mcbsp->iclk = NULL;
1328 mcbsp->free = 0;
1329 mcbsp->dev = NULL;
1330 }
1331
1332 return 0;
1333 }
1334
1335 static struct platform_driver omap_mcbsp_driver = {
1336 .probe = omap_mcbsp_probe,
1337 .remove = __devexit_p(omap_mcbsp_remove),
1338 .driver = {
1339 .name = "omap-mcbsp",
1340 },
1341 };
1342
1343 int __init omap_mcbsp_init(void)
1344 {
1345 /* Register the McBSP driver */
1346 return platform_driver_register(&omap_mcbsp_driver);
1347 }
kernel-based virtual machine