arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/cpuidle.h>
  26
  27 #include <plat/prcm.h>
  28 #include <plat/irqs.h>
  29 #include <plat/powerdomain.h>
  30 #include <plat/clockdomain.h>
  31 #include <plat/control.h>
  32 #include <plat/serial.h>
  33
  34 #include "pm.h"
  35
  36 #ifdef CONFIG_CPU_IDLE
  37
  38 #define OMAP3_MAX_STATES 7
  39 #define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
  40 #define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
  41 #define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
  42 #define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
  43 #define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
  44 #define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
  45 #define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
  46
  47 struct omap3_processor_cx {
  48         u8 valid;
  49         u8 type;
  50         u32 sleep_latency;
  51         u32 wakeup_latency;
  52         u32 mpu_state;
  53         u32 core_state;
  54         u32 threshold;
  55         u32 flags;
  56 };
  57
  58 struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
  59 struct omap3_processor_cx current_cx_state;
  60 struct powerdomain *mpu_pd, *core_pd;
  61
  62 static int omap3_idle_bm_check(void)
  63 {
  64         if (!omap3_can_sleep())
  65                 return 1;
  66         return 0;
  67 }
  68
  69 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
  70                                 struct clockdomain *clkdm)
  71 {
  72         omap2_clkdm_allow_idle(clkdm);
  73         return 0;
  74 }
  75
  76 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
  77                                 struct clockdomain *clkdm)
  78 {
  79         omap2_clkdm_deny_idle(clkdm);
  80         return 0;
  81 }
  82
  83 /**
  84  * omap3_enter_idle - Programs OMAP3 to enter the specified state
  85  * @dev: cpuidle device
  86  * @state: The target state to be programmed
  87  *
  88  * Called from the CPUidle framework to program the device to the
  89  * specified target state selected by the governor.
  90  */
  91 static int omap3_enter_idle(struct cpuidle_device *dev,
  92                         struct cpuidle_state *state)
  93 {
  94         struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
  95         struct timespec ts_preidle, ts_postidle, ts_idle;
  96         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
  97
  98         current_cx_state = *cx;
  99
 100         /* Used to keep track of the total time in idle */
 101         getnstimeofday(&ts_preidle);
 102
 103         local_irq_disable();
 104         local_fiq_disable();
 105
 106         if (!enable_off_mode) {
 107                 if (mpu_state < PWRDM_POWER_RET)
 108                         mpu_state = PWRDM_POWER_RET;
 109                 if (core_state < PWRDM_POWER_RET)
 110                         core_state = PWRDM_POWER_RET;
 111         }
 112
 113         set_pwrdm_state(mpu_pd, mpu_state);
 114         set_pwrdm_state(core_pd, core_state);
 115
 116         if (omap_irq_pending())
 117                 goto return_sleep_time;
 118
 119         if (cx->type == OMAP3_STATE_C1) {
 120                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
 121                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
 122         }
 123
 124         /* Execute ARM wfi */
 125         omap_sram_idle();
 126
 127         if (cx->type == OMAP3_STATE_C1) {
 128                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
 129                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
 130         }
 131
 132 return_sleep_time:
 133         getnstimeofday(&ts_postidle);
 134         ts_idle = timespec_sub(ts_postidle, ts_preidle);
 135
 136         local_irq_enable();
 137         local_fiq_enable();
 138
 139         return (u32)timespec_to_ns(&ts_idle)/1000;
 140 }
 141
 142 /**
 143  * omap3_enter_idle_bm - Checks for any bus activity
 144  * @dev: cpuidle device
 145  * @state: The target state to be programmed
 146  *
 147  * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
 148  * function checks for any pending activity and then programs the
 149  * device to the specified or a safer state.
 150  */
 151 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 152                                struct cpuidle_state *state)
 153 {
 154         struct cpuidle_state *new_state = state;
 155
 156         if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
 157                 BUG_ON(!dev->safe_state);
 158                 new_state = dev->safe_state;
 159         }
 160
 161         dev->last_state = new_state;
 162         return omap3_enter_idle(dev, new_state);
 163 }
 164
 165 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 166
 167 /* omap3_init_power_states - Initialises the OMAP3 specific C states.
 168  *
 169  * Below is the desciption of each C state.
 170  *      C1 . MPU WFI + Core active
 171  *      C2 . MPU WFI + Core inactive
 172  *      C3 . MPU CSWR + Core inactive
 173  *      C4 . MPU OFF + Core inactive
 174  *      C5 . MPU CSWR + Core CSWR
 175  *      C6 . MPU OFF + Core CSWR
 176  *      C7 . MPU OFF + Core OFF
 177  */
 178 void omap_init_power_states(void)
 179 {
 180         /* C1 . MPU WFI + Core active */
 181         omap3_power_states[OMAP3_STATE_C1].valid = 1;
 182         omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
 183         omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2;
 184         omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2;
 185         omap3_power_states[OMAP3_STATE_C1].threshold = 5;
 186         omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
 187         omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
 188         omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
 189
 190         /* C2 . MPU WFI + Core inactive */
 191         omap3_power_states[OMAP3_STATE_C2].valid = 1;
 192         omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
 193         omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10;
 194         omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10;
 195         omap3_power_states[OMAP3_STATE_C2].threshold = 30;
 196         omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
 197         omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
 198         omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
 199
 200         /* C3 . MPU CSWR + Core inactive */
 201         omap3_power_states[OMAP3_STATE_C3].valid = 1;
 202         omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
 203         omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50;
 204         omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50;
 205         omap3_power_states[OMAP3_STATE_C3].threshold = 300;
 206         omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
 207         omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
 208         omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
 209                                 CPUIDLE_FLAG_CHECK_BM;
 210
 211         /* C4 . MPU OFF + Core inactive */
 212         omap3_power_states[OMAP3_STATE_C4].valid = 1;
 213         omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
 214         omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500;
 215         omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800;
 216         omap3_power_states[OMAP3_STATE_C4].threshold = 4000;
 217         omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
 218         omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
 219         omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
 220                                 CPUIDLE_FLAG_CHECK_BM;
 221
 222         /* C5 . MPU CSWR + Core CSWR*/
 223         omap3_power_states[OMAP3_STATE_C5].valid = 1;
 224         omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
 225         omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500;
 226         omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500;
 227         omap3_power_states[OMAP3_STATE_C5].threshold = 12000;
 228         omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
 229         omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
 230         omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
 231                                 CPUIDLE_FLAG_CHECK_BM;
 232
 233         /* C6 . MPU OFF + Core CSWR */
 234         omap3_power_states[OMAP3_STATE_C6].valid = 1;
 235         omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
 236         omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000;
 237         omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500;
 238         omap3_power_states[OMAP3_STATE_C6].threshold = 15000;
 239         omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
 240         omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
 241         omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
 242                                 CPUIDLE_FLAG_CHECK_BM;
 243
 244         /* C7 . MPU OFF + Core OFF */
 245         omap3_power_states[OMAP3_STATE_C7].valid = 1;
 246         omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
 247         omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000;
 248         omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000;
 249         omap3_power_states[OMAP3_STATE_C7].threshold = 300000;
 250         omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
 251         omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
 252         omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
 253                                 CPUIDLE_FLAG_CHECK_BM;
 254 }
 255
 256 struct cpuidle_driver omap3_idle_driver = {
 257         .name =         "omap3_idle",
 258         .owner =        THIS_MODULE,
 259 };
 260
 261 /**
 262  * omap3_idle_init - Init routine for OMAP3 idle
 263  *
 264  * Registers the OMAP3 specific cpuidle driver with the cpuidle
 265  * framework with the valid set of states.
 266  */
 267 int __init omap3_idle_init(void)
 268 {
 269         int i, count = 0;
 270         struct omap3_processor_cx *cx;
 271         struct cpuidle_state *state;
 272         struct cpuidle_device *dev;
 273
 274         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 275         core_pd = pwrdm_lookup("core_pwrdm");
 276
 277         omap_init_power_states();
 278         cpuidle_register_driver(&omap3_idle_driver);
 279
 280         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 281
 282         for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
 283                 cx = &omap3_power_states[i];
 284                 state = &dev->states[count];
 285
 286                 if (!cx->valid)
 287                         continue;
 288                 cpuidle_set_statedata(state, cx);
 289                 state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
 290                 state->target_residency = cx->threshold;
 291                 state->flags = cx->flags;
 292                 state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
 293                         omap3_enter_idle_bm : omap3_enter_idle;
 294                 if (cx->type == OMAP3_STATE_C1)
 295                         dev->safe_state = state;
 296                 sprintf(state->name, "C%d", count+1);
 297                 count++;
 298         }
 299
 300         if (!count)
 301                 return -EINVAL;
 302         dev->state_count = count;
 303
 304         if (cpuidle_register_device(dev)) {
 305                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 306                        __func__);
 307                 return -EIO;
 308         }
 309
 310         return 0;
 311 }
 312 #else
 313 int __init omap3_idle_init(void)
 314 {
 315         return 0;
 316 }
 317 #endif /* CONFIG_CPU_IDLE */