drivers/net/wireless/ath5k/ath5k.h

   1 /*
   2  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
   4  *
   5  * Permission to use, copy, modify, and distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #ifndef _ATH5K_H
  19 #define _ATH5K_H
  20
  21 /* Set this to 1 to disable regulatory domain restrictions for channel tests.
  22  * WARNING: This is for debuging only and has side effects (eg. scan takes too
  23  * long and results timeouts). It's also illegal to tune to some of the
  24  * supported frequencies in some countries, so use this at your own risk,
  25  * you've been warned. */
  26 #define CHAN_DEBUG      0
  27
  28 #include <linux/io.h>
  29 #include <linux/types.h>
  30 #include <net/mac80211.h>
  31
  32 #include "hw.h"
  33
  34 /* PCI IDs */
  35 #define PCI_DEVICE_ID_ATHEROS_AR5210            0x0007 /* AR5210 */
  36 #define PCI_DEVICE_ID_ATHEROS_AR5311            0x0011 /* AR5311 */
  37 #define PCI_DEVICE_ID_ATHEROS_AR5211            0x0012 /* AR5211 */
  38 #define PCI_DEVICE_ID_ATHEROS_AR5212            0x0013 /* AR5212 */
  39 #define PCI_DEVICE_ID_3COM_3CRDAG675            0x0013 /* 3CRDAG675 (Atheros AR5212) */
  40 #define PCI_DEVICE_ID_3COM_2_3CRPAG175          0x0013 /* 3CRPAG175 (Atheros AR5212) */
  41 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP         0x0207 /* AR5210 (Early) */
  42 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM        0x1014 /* AR5212 (IBM MiniPCI) */
  43 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT    0x1107 /* AR5210 (no eeprom) */
  44 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT    0x1113 /* AR5212 (no eeprom) */
  45 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT    0x1112 /* AR5211 (no eeprom) */
  46 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA       0xf013 /* AR5212 (emulation board) */
  47 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY     0xff12 /* AR5211 (emulation board) */
  48 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B    0xf11b /* AR5211 (emulation board) */
  49 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2       0x0052 /* AR5312 WMAC (AP31) */
  50 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7       0x0057 /* AR5312 WMAC (AP30-040) */
  51 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8       0x0058 /* AR5312 WMAC (AP43-030) */
  52 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014       0x0014 /* AR5212 compatible */
  53 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015       0x0015 /* AR5212 compatible */
  54 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016       0x0016 /* AR5212 compatible */
  55 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017       0x0017 /* AR5212 compatible */
  56 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018       0x0018 /* AR5212 compatible */
  57 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019       0x0019 /* AR5212 compatible */
  58 #define PCI_DEVICE_ID_ATHEROS_AR2413            0x001a /* AR2413 (Griffin-lite) */
  59 #define PCI_DEVICE_ID_ATHEROS_AR5413            0x001b /* AR5413 (Eagle) */
  60 #define PCI_DEVICE_ID_ATHEROS_AR5424            0x001c /* AR5424 (Condor PCI-E) */
  61 #define PCI_DEVICE_ID_ATHEROS_AR5416            0x0023 /* AR5416 */
  62 #define PCI_DEVICE_ID_ATHEROS_AR5418            0x0024 /* AR5418 */
  63
  64 /****************************\
  65   GENERIC DRIVER DEFINITIONS
  66 \****************************/
  67
  68 #define ATH5K_PRINTF(fmt, ...)   printk("%s: " fmt, __func__, ##__VA_ARGS__)
  69
  70 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
  71         printk(_level "ath5k %s: " _fmt, \
  72                 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
  73                 ##__VA_ARGS__)
  74
  75 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
  76         if (net_ratelimit()) \
  77                 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
  78         } while (0)
  79
  80 #define ATH5K_INFO(_sc, _fmt, ...) \
  81         ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
  82
  83 #define ATH5K_WARN(_sc, _fmt, ...) \
  84         ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
  85
  86 #define ATH5K_ERR(_sc, _fmt, ...) \
  87         ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
  88
  89 /*
  90  * Some tuneable values (these should be changeable by the user)
  91  */
  92 #define AR5K_TUNE_DMA_BEACON_RESP               2
  93 #define AR5K_TUNE_SW_BEACON_RESP                10
  94 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF       0
  95 #define AR5K_TUNE_RADAR_ALERT                   false
  96 #define AR5K_TUNE_MIN_TX_FIFO_THRES             1
  97 #define AR5K_TUNE_MAX_TX_FIFO_THRES             ((IEEE80211_MAX_LEN / 64) + 1)
  98 #define AR5K_TUNE_REGISTER_TIMEOUT              20000
  99 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
 100  * be the max value. */
 101 #define AR5K_TUNE_RSSI_THRES                   129
 102 /* This must be set when setting the RSSI threshold otherwise it can
 103  * prevent a reset. If AR5K_RSSI_THR is read after writing to it
 104  * the BMISS_THRES will be seen as 0, seems harware doesn't keep
 105  * track of it. Max value depends on harware. For AR5210 this is just 7.
 106  * For AR5211+ this seems to be up to 255. */
 107 #define AR5K_TUNE_BMISS_THRES                  7
 108 #define AR5K_TUNE_REGISTER_DWELL_TIME           20000
 109 #define AR5K_TUNE_BEACON_INTERVAL               100
 110 #define AR5K_TUNE_AIFS                          2
 111 #define AR5K_TUNE_AIFS_11B                      2
 112 #define AR5K_TUNE_AIFS_XR                       0
 113 #define AR5K_TUNE_CWMIN                         15
 114 #define AR5K_TUNE_CWMIN_11B                     31
 115 #define AR5K_TUNE_CWMIN_XR                      3
 116 #define AR5K_TUNE_CWMAX                         1023
 117 #define AR5K_TUNE_CWMAX_11B                     1023
 118 #define AR5K_TUNE_CWMAX_XR                      7
 119 #define AR5K_TUNE_NOISE_FLOOR                   -72
 120 #define AR5K_TUNE_MAX_TXPOWER                   60
 121 #define AR5K_TUNE_DEFAULT_TXPOWER               30
 122 #define AR5K_TUNE_TPC_TXPOWER                   true
 123 #define AR5K_TUNE_ANT_DIVERSITY                 true
 124 #define AR5K_TUNE_HWTXTRIES                     4
 125
 126 /* token to use for aifs, cwmin, cwmax in MadWiFi */
 127 #define AR5K_TXQ_USEDEFAULT     ((u32) -1)
 128
 129 /* GENERIC CHIPSET DEFINITIONS */
 130
 131 /* MAC Chips */
 132 enum ath5k_version {
 133         AR5K_AR5210     = 0,
 134         AR5K_AR5211     = 1,
 135         AR5K_AR5212     = 2,
 136 };
 137
 138 /* PHY Chips */
 139 enum ath5k_radio {
 140         AR5K_RF5110     = 0,
 141         AR5K_RF5111     = 1,
 142         AR5K_RF5112     = 2,
 143         AR5K_RF2413     = 3,
 144         AR5K_RF5413     = 4,
 145 };
 146
 147 /*
 148  * Common silicon revision/version values
 149  */
 150
 151 enum ath5k_srev_type {
 152         AR5K_VERSION_VER,
 153         AR5K_VERSION_RAD,
 154 };
 155
 156 struct ath5k_srev_name {
 157         const char              *sr_name;
 158         enum ath5k_srev_type    sr_type;
 159         u_int                   sr_val;
 160 };
 161
 162 #define AR5K_SREV_UNKNOWN       0xffff
 163
 164 #define AR5K_SREV_VER_AR5210    0x00
 165 #define AR5K_SREV_VER_AR5311    0x10
 166 #define AR5K_SREV_VER_AR5311A   0x20
 167 #define AR5K_SREV_VER_AR5311B   0x30
 168 #define AR5K_SREV_VER_AR5211    0x40
 169 #define AR5K_SREV_VER_AR5212    0x50
 170 #define AR5K_SREV_VER_AR5213    0x55
 171 #define AR5K_SREV_VER_AR5213A   0x59
 172 #define AR5K_SREV_VER_AR2413    0x78
 173 #define AR5K_SREV_VER_AR2414    0x79
 174 #define AR5K_SREV_VER_AR2424    0xa0
 175 #define AR5K_SREV_VER_AR5424    0xa3
 176 #define AR5K_SREV_VER_AR5413    0xa4
 177 #define AR5K_SREV_VER_AR5414    0xa5
 178 #define AR5K_SREV_VER_AR5416    0xc0    /* ? */
 179 #define AR5K_SREV_VER_AR5418    0xca
 180 #define AR5K_SREV_VER_AR2425    0xe2
 181
 182 #define AR5K_SREV_RAD_5110      0x00
 183 #define AR5K_SREV_RAD_5111      0x10
 184 #define AR5K_SREV_RAD_5111A     0x15
 185 #define AR5K_SREV_RAD_2111      0x20
 186 #define AR5K_SREV_RAD_5112      0x30
 187 #define AR5K_SREV_RAD_5112A     0x35
 188 #define AR5K_SREV_RAD_2112      0x40
 189 #define AR5K_SREV_RAD_2112A     0x45
 190 #define AR5K_SREV_RAD_SC0       0x56    /* Found on 2413/2414 */
 191 #define AR5K_SREV_RAD_SC1       0x63    /* Found on 5413/5414 */
 192 #define AR5K_SREV_RAD_SC2       0xa2    /* Found on 2424-5/5424 */
 193 #define AR5K_SREV_RAD_5133      0xc0    /* MIMO found on 5418 */
 194
 195 /* IEEE defs */
 196
 197 #define IEEE80211_MAX_LEN       2500
 198
 199 /* TODO add support to mac80211 for vendor-specific rates and modes */
 200
 201 /*
 202  * Some of this information is based on Documentation from:
 203  *
 204  * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
 205  *
 206  * Modulation for Atheros' eXtended Range - range enhancing extension that is
 207  * supposed to double the distance an Atheros client device can keep a
 208  * connection with an Atheros access point. This is achieved by increasing
 209  * the receiver sensitivity up to, -105dBm, which is about 20dB above what
 210  * the 802.11 specifications demand. In addition, new (proprietary) data rates
 211  * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
 212  *
 213  * Please note that can you either use XR or TURBO but you cannot use both,
 214  * they are exclusive.
 215  *
 216  */
 217 #define MODULATION_XR           0x00000200
 218 /*
 219  * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
 220  * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
 221  * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
 222  * channels. To use this feature your Access Point must also suport it.
 223  * There is also a distinction between "static" and "dynamic" turbo modes:
 224  *
 225  * - Static: is the dumb version: devices set to this mode stick to it until
 226  *     the mode is turned off.
 227  * - Dynamic: is the intelligent version, the network decides itself if it
 228  *     is ok to use turbo. As soon as traffic is detected on adjacent channels
 229  *     (which would get used in turbo mode), or when a non-turbo station joins
 230  *     the network, turbo mode won't be used until the situation changes again.
 231  *     Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
 232  *     monitors the used radio band in order to decide whether turbo mode may
 233  *     be used or not.
 234  *
 235  * This article claims Super G sticks to bonding of channels 5 and 6 for
 236  * USA:
 237  *
 238  * http://www.pcworld.com/article/id,113428-page,1/article.html
 239  *
 240  * The channel bonding seems to be driver specific though. In addition to
 241  * deciding what channels will be used, these "Turbo" modes are accomplished
 242  * by also enabling the following features:
 243  *
 244  * - Bursting: allows multiple frames to be sent at once, rather than pausing
 245  *     after each frame. Bursting is a standards-compliant feature that can be
 246  *     used with any Access Point.
 247  * - Fast frames: increases the amount of information that can be sent per
 248  *     frame, also resulting in a reduction of transmission overhead. It is a
 249  *     proprietary feature that needs to be supported by the Access Point.
 250  * - Compression: data frames are compressed in real time using a Lempel Ziv
 251  *     algorithm. This is done transparently. Once this feature is enabled,
 252  *     compression and decompression takes place inside the chipset, without
 253  *     putting additional load on the host CPU.
 254  *
 255  */
 256 #define MODULATION_TURBO        0x00000080
 257
 258 enum ath5k_driver_mode {
 259         AR5K_MODE_11A           =       0,
 260         AR5K_MODE_11A_TURBO     =       1,
 261         AR5K_MODE_11B           =       2,
 262         AR5K_MODE_11G           =       3,
 263         AR5K_MODE_11G_TURBO     =       4,
 264         AR5K_MODE_XR            =       0,
 265         AR5K_MODE_MAX           =       5
 266 };
 267
 268 /* adding this flag to rate_code enables short preamble, see ar5212_reg.h */
 269 #define AR5K_SET_SHORT_PREAMBLE 0x04
 270
 271 #define HAS_SHPREAMBLE(_ix) \
 272         (rt->rates[_ix].modulation == IEEE80211_RATE_SHORT_PREAMBLE)
 273 #define SHPREAMBLE_FLAG(_ix) \
 274         (HAS_SHPREAMBLE(_ix) ? AR5K_SET_SHORT_PREAMBLE : 0)
 275
 276 /****************\
 277   TX DEFINITIONS
 278 \****************/
 279
 280 /*
 281  * Tx Descriptor
 282  */
 283 struct ath5k_tx_status {
 284         u16     ts_seqnum;
 285         u16     ts_tstamp;
 286         u8      ts_status;
 287         u8      ts_rate;
 288         s8      ts_rssi;
 289         u8      ts_shortretry;
 290         u8      ts_longretry;
 291         u8      ts_virtcol;
 292         u8      ts_antenna;
 293 };
 294
 295 #define AR5K_TXSTAT_ALTRATE     0x80
 296 #define AR5K_TXERR_XRETRY       0x01
 297 #define AR5K_TXERR_FILT         0x02
 298 #define AR5K_TXERR_FIFO         0x04
 299
 300 /**
 301  * enum ath5k_tx_queue - Queue types used to classify tx queues.
 302  * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
 303  * @AR5K_TX_QUEUE_DATA: A normal data queue
 304  * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
 305  * @AR5K_TX_QUEUE_BEACON: The beacon queue
 306  * @AR5K_TX_QUEUE_CAB: The after-beacon queue
 307  * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
 308  */
 309 enum ath5k_tx_queue {
 310         AR5K_TX_QUEUE_INACTIVE = 0,
 311         AR5K_TX_QUEUE_DATA,
 312         AR5K_TX_QUEUE_XR_DATA,
 313         AR5K_TX_QUEUE_BEACON,
 314         AR5K_TX_QUEUE_CAB,
 315         AR5K_TX_QUEUE_UAPSD,
 316 };
 317
 318 #define AR5K_NUM_TX_QUEUES              10
 319 #define AR5K_NUM_TX_QUEUES_NOQCU        2
 320
 321 /*
 322  * Queue syb-types to classify normal data queues.
 323  * These are the 4 Access Categories as defined in
 324  * WME spec. 0 is the lowest priority and 4 is the
 325  * highest. Normal data that hasn't been classified
 326  * goes to the Best Effort AC.
 327  */
 328 enum ath5k_tx_queue_subtype {
 329         AR5K_WME_AC_BK = 0,     /*Background traffic*/
 330         AR5K_WME_AC_BE,         /*Best-effort (normal) traffic)*/
 331         AR5K_WME_AC_VI,         /*Video traffic*/
 332         AR5K_WME_AC_VO,         /*Voice traffic*/
 333 };
 334
 335 /*
 336  * Queue ID numbers as returned by the hw functions, each number
 337  * represents a hw queue. If hw does not support hw queues
 338  * (eg 5210) all data goes in one queue. These match
 339  * d80211 definitions (net80211/MadWiFi don't use them).
 340  */
 341 enum ath5k_tx_queue_id {
 342         AR5K_TX_QUEUE_ID_NOQCU_DATA     = 0,
 343         AR5K_TX_QUEUE_ID_NOQCU_BEACON   = 1,
 344         AR5K_TX_QUEUE_ID_DATA_MIN       = 0, /*IEEE80211_TX_QUEUE_DATA0*/
 345         AR5K_TX_QUEUE_ID_DATA_MAX       = 4, /*IEEE80211_TX_QUEUE_DATA4*/
 346         AR5K_TX_QUEUE_ID_DATA_SVP       = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
 347         AR5K_TX_QUEUE_ID_CAB            = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
 348         AR5K_TX_QUEUE_ID_BEACON         = 7, /*IEEE80211_TX_QUEUE_BEACON*/
 349         AR5K_TX_QUEUE_ID_UAPSD          = 8,
 350         AR5K_TX_QUEUE_ID_XR_DATA        = 9,
 351 };
 352
 353
 354 /*
 355  * Flags to set hw queue's parameters...
 356  */
 357 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE            0x0001  /* Enable TXOK interrupt */
 358 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE           0x0002  /* Enable TXERR interrupt */
 359 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE           0x0004  /* Enable TXEOL interrupt -not used- */
 360 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE          0x0008  /* Enable TXDESC interrupt -not used- */
 361 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE           0x0010  /* Enable TXURN interrupt */
 362 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE           0x0020  /* Disable random post-backoff */
 363 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0040  /* Enable ready time expiry policy (?)*/
 364 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0080  /* Enable backoff while bursting */
 365 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS         0x0100  /* Disable backoff while bursting */
 366 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE        0x0200  /* Enable hw compression -not implemented-*/
 367
 368 /*
 369  * A struct to hold tx queue's parameters
 370  */
 371 struct ath5k_txq_info {
 372         enum ath5k_tx_queue tqi_type;
 373         enum ath5k_tx_queue_subtype tqi_subtype;
 374         u16     tqi_flags;      /* Tx queue flags (see above) */
 375         u32     tqi_aifs;       /* Arbitrated Interframe Space */
 376         s32     tqi_cw_min;     /* Minimum Contention Window */
 377         s32     tqi_cw_max;     /* Maximum Contention Window */
 378         u32     tqi_cbr_period; /* Constant bit rate period */
 379         u32     tqi_cbr_overflow_limit;
 380         u32     tqi_burst_time;
 381         u32     tqi_ready_time; /* Not used */
 382 };
 383
 384 /*
 385  * Transmit packet types.
 386  * These are not fully used inside OpenHAL yet
 387  */
 388 enum ath5k_pkt_type {
 389         AR5K_PKT_TYPE_NORMAL            = 0,
 390         AR5K_PKT_TYPE_ATIM              = 1,
 391         AR5K_PKT_TYPE_PSPOLL            = 2,
 392         AR5K_PKT_TYPE_BEACON            = 3,
 393         AR5K_PKT_TYPE_PROBE_RESP        = 4,
 394         AR5K_PKT_TYPE_PIFS              = 5,
 395 };
 396
 397 /*
 398  * TX power and TPC settings
 399  */
 400 #define AR5K_TXPOWER_OFDM(_r, _v)       (                       \
 401         ((0 & 1) << ((_v) + 6)) |                               \
 402         (((ah->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v))     \
 403 )
 404
 405 #define AR5K_TXPOWER_CCK(_r, _v)        (                       \
 406         (ah->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
 407 )
 408
 409 /*
 410  * DMA size definitions (2^n+2)
 411  */
 412 enum ath5k_dmasize {
 413         AR5K_DMASIZE_4B = 0,
 414         AR5K_DMASIZE_8B,
 415         AR5K_DMASIZE_16B,
 416         AR5K_DMASIZE_32B,
 417         AR5K_DMASIZE_64B,
 418         AR5K_DMASIZE_128B,
 419         AR5K_DMASIZE_256B,
 420         AR5K_DMASIZE_512B
 421 };
 422
 423
 424 /****************\
 425   RX DEFINITIONS
 426 \****************/
 427
 428 /*
 429  * Rx Descriptor
 430  */
 431 struct ath5k_rx_status {
 432         u16     rs_datalen;
 433         u16     rs_tstamp;
 434         u8      rs_status;
 435         u8      rs_phyerr;
 436         s8      rs_rssi;
 437         u8      rs_keyix;
 438         u8      rs_rate;
 439         u8      rs_antenna;
 440         u8      rs_more;
 441 };
 442
 443 #define AR5K_RXERR_CRC          0x01
 444 #define AR5K_RXERR_PHY          0x02
 445 #define AR5K_RXERR_FIFO         0x04
 446 #define AR5K_RXERR_DECRYPT      0x08
 447 #define AR5K_RXERR_MIC          0x10
 448 #define AR5K_RXKEYIX_INVALID    ((u8) - 1)
 449 #define AR5K_TXKEYIX_INVALID    ((u32) - 1)
 450
 451 struct ath5k_mib_stats {
 452         u32     ackrcv_bad;
 453         u32     rts_bad;
 454         u32     rts_good;
 455         u32     fcs_bad;
 456         u32     beacons;
 457 };
 458
 459
 460
 461
 462 /**************************\
 463  BEACON TIMERS DEFINITIONS
 464 \**************************/
 465
 466 #define AR5K_BEACON_PERIOD      0x0000ffff
 467 #define AR5K_BEACON_ENA         0x00800000 /*enable beacon xmit*/
 468 #define AR5K_BEACON_RESET_TSF   0x01000000 /*force a TSF reset*/
 469
 470 #if 0
 471 /**
 472  * struct ath5k_beacon_state - Per-station beacon timer state.
 473  * @bs_interval: in TU's, can also include the above flags
 474  * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
 475  *      Point Coordination Function capable AP
 476  */
 477 struct ath5k_beacon_state {
 478         u32     bs_next_beacon;
 479         u32     bs_next_dtim;
 480         u32     bs_interval;
 481         u8      bs_dtim_period;
 482         u8      bs_cfp_period;
 483         u16     bs_cfp_max_duration;
 484         u16     bs_cfp_du_remain;
 485         u16     bs_tim_offset;
 486         u16     bs_sleep_duration;
 487         u16     bs_bmiss_threshold;
 488         u32     bs_cfp_next;
 489 };
 490 #endif
 491
 492
 493 /*
 494  * TSF to TU conversion:
 495  *
 496  * TSF is a 64bit value in usec (microseconds).
 497  * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
 498  * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
 499  */
 500 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
 501
 502
 503
 504 /********************\
 505   COMMON DEFINITIONS
 506 \********************/
 507
 508 /*
 509  * Atheros descriptor
 510  */
 511 struct ath5k_desc {
 512         u32     ds_link;
 513         u32     ds_data;
 514         u32     ds_ctl0;
 515         u32     ds_ctl1;
 516         u32     ds_hw[4];
 517
 518         union {
 519                 struct ath5k_rx_status rx;
 520                 struct ath5k_tx_status tx;
 521         } ds_us;
 522
 523 #define ds_rxstat ds_us.rx
 524 #define ds_txstat ds_us.tx
 525
 526 } __packed;
 527
 528 #define AR5K_RXDESC_INTREQ      0x0020
 529
 530 #define AR5K_TXDESC_CLRDMASK    0x0001
 531 #define AR5K_TXDESC_NOACK       0x0002  /*[5211+]*/
 532 #define AR5K_TXDESC_RTSENA      0x0004
 533 #define AR5K_TXDESC_CTSENA      0x0008
 534 #define AR5K_TXDESC_INTREQ      0x0010
 535 #define AR5K_TXDESC_VEOL        0x0020  /*[5211+]*/
 536
 537 #define AR5K_SLOT_TIME_9        396
 538 #define AR5K_SLOT_TIME_20       880
 539 #define AR5K_SLOT_TIME_MAX      0xffff
 540
 541 /* channel_flags */
 542 #define CHANNEL_CW_INT  0x0008  /* Contention Window interference detected */
 543 #define CHANNEL_TURBO   0x0010  /* Turbo Channel */
 544 #define CHANNEL_CCK     0x0020  /* CCK channel */
 545 #define CHANNEL_OFDM    0x0040  /* OFDM channel */
 546 #define CHANNEL_2GHZ    0x0080  /* 2GHz channel. */
 547 #define CHANNEL_5GHZ    0x0100  /* 5GHz channel */
 548 #define CHANNEL_PASSIVE 0x0200  /* Only passive scan allowed */
 549 #define CHANNEL_DYN     0x0400  /* Dynamic CCK-OFDM channel (for g operation) */
 550 #define CHANNEL_XR      0x0800  /* XR channel */
 551
 552 #define CHANNEL_A       (CHANNEL_5GHZ|CHANNEL_OFDM)
 553 #define CHANNEL_B       (CHANNEL_2GHZ|CHANNEL_CCK)
 554 #define CHANNEL_G       (CHANNEL_2GHZ|CHANNEL_OFDM)
 555 #define CHANNEL_T       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 556 #define CHANNEL_TG      (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 557 #define CHANNEL_108A    CHANNEL_T
 558 #define CHANNEL_108G    CHANNEL_TG
 559 #define CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
 560
 561 #define CHANNEL_ALL     (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
 562                 CHANNEL_TURBO)
 563
 564 #define CHANNEL_ALL_NOTURBO     (CHANNEL_ALL & ~CHANNEL_TURBO)
 565 #define CHANNEL_MODES           CHANNEL_ALL
 566
 567 /*
 568  * Used internaly in OpenHAL (ar5211.c/ar5212.c
 569  * for reset_tx_queue). Also see struct struct ieee80211_channel.
 570  */
 571 #define IS_CHAN_XR(_c)  ((_c.hw_value & CHANNEL_XR) != 0)
 572 #define IS_CHAN_B(_c)   ((_c.hw_value & CHANNEL_B) != 0)
 573
 574 /*
 575  * The following structure will be used to map 2GHz channels to
 576  * 5GHz Atheros channels.
 577  */
 578 struct ath5k_athchan_2ghz {
 579         u32     a2_flags;
 580         u16     a2_athchan;
 581 };
 582
 583 /*
 584  * Rate definitions
 585  * TODO: Clean them up or move them on mac80211 -most of these infos are
 586  *       used by the rate control algorytm on MadWiFi.
 587  */
 588
 589 /* Max number of rates on the rate table and what it seems
 590  * Atheros hardware supports */
 591 #define AR5K_MAX_RATES 32
 592
 593 /**
 594  * struct ath5k_rate - rate structure
 595  * @valid: is this a valid rate for rate control (remove)
 596  * @modulation: respective mac80211 modulation
 597  * @rate_kbps: rate in kbit/s
 598  * @rate_code: hardware rate value, used in &struct ath5k_desc, on RX on
 599  *     &struct ath5k_rx_status.rs_rate and on TX on
 600  *     &struct ath5k_tx_status.ts_rate. Seems the ar5xxx harware supports
 601  *     up to 32 rates, indexed by 1-32. This means we really only need
 602  *     6 bits for the rate_code.
 603  * @dot11_rate: respective IEEE-802.11 rate value
 604  * @control_rate: index of rate assumed to be used to send control frames.
 605  *     This can be used to set override the value on the rate duration
 606  *     registers. This is only useful if we can override in the harware at
 607  *     what rate we want to send control frames at. Note that IEEE-802.11
 608  *     Ch. 9.6 (after IEEE 802.11g changes) defines the rate at which we
 609  *     should send ACK/CTS, if we change this value we can be breaking
 610  *     the spec.
 611  *
 612  * This structure is used to get the RX rate or set the TX rate on the
 613  * hardware descriptors. It is also used for internal modulation control
 614  * and settings.
 615  *
 616  * On RX after the &struct ath5k_desc is parsed by the appropriate
 617  * ah_proc_rx_desc() the respective hardware rate value is set in
 618  * &struct ath5k_rx_status.rs_rate. On TX the desired rate is set in
 619  * &struct ath5k_tx_status.ts_rate which is later used to setup the
 620  * &struct ath5k_desc correctly. This is the hardware rate map we are
 621  * aware of:
 622  *
 623  * rate_code   1       2       3       4       5       6       7       8
 624  * rate_kbps   3000    1000    ?       ?       ?       2000    500     48000
 625  *
 626  * rate_code   9       10      11      12      13      14      15      16
 627  * rate_kbps   24000   12000   6000    54000   36000   18000   9000    ?
 628  *
 629  * rate_code   17      18      19      20      21      22      23      24
 630  * rate_kbps   ?       ?       ?       ?       ?       ?       ?       11000
 631  *
 632  * rate_code   25      26      27      28      29      30      31      32
 633  * rate_kbps   5500    2000    1000    ?       ?       ?       ?       ?
 634  *
 635  */
 636 struct ath5k_rate {
 637         u8      valid;
 638         u32     modulation;
 639         u16     rate_kbps;
 640         u8      rate_code;
 641         u8      dot11_rate;
 642         u8      control_rate;
 643 };
 644
 645 /* XXX: GRR all this stuff to get leds blinking ??? (check out setcurmode) */
 646 struct ath5k_rate_table {
 647         u16     rate_count;
 648         u8      rate_code_to_index[AR5K_MAX_RATES];     /* Back-mapping */
 649         struct ath5k_rate rates[AR5K_MAX_RATES];
 650 };
 651
 652 /*
 653  * Rate tables...
 654  * TODO: CLEAN THIS !!!
 655  */
 656 #define AR5K_RATES_11A { 8, {                                   \
 657         255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0,     \
 658         7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255,     \
 659         255, 255, 255, 255, 255, 255, 255, 255 }, {             \
 660         { 1, 0, 6000, 11, 140, 0 },             \
 661         { 1, 0, 9000, 15, 18, 0 },              \
 662         { 1, 0, 12000, 10, 152, 2 },            \
 663         { 1, 0, 18000, 14, 36, 2 },             \
 664         { 1, 0, 24000, 9, 176, 4 },             \
 665         { 1, 0, 36000, 13, 72, 4 },             \
 666         { 1, 0, 48000, 8, 96, 4 },              \
 667         { 1, 0, 54000, 12, 108, 4 } }           \
 668 }
 669
 670 #define AR5K_RATES_11B { 4, {                                           \
 671         255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,     \
 672         255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,     \
 673         3, 2, 1, 0, 255, 255, 255, 255 }, {                             \
 674         { 1, 0, 1000, 27, 130, 0 },     \
 675         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 2000, 26, 132, 1 }, \
 676         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 5500, 25, 139, 1 }, \
 677         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 11000, 24, 150, 1 } }       \
 678 }
 679
 680 #define AR5K_RATES_11G { 12, {                                  \
 681         255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4,    \
 682         11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255,    \
 683         3, 2, 1, 0, 255, 255, 255, 255 }, {                     \
 684         { 1, 0, 1000, 27, 2, 0 },               \
 685         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 2000, 26, 4, 1 },           \
 686         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 5500, 25, 11, 1 },          \
 687         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 11000, 24, 22, 1 }, \
 688         { 0, 0, 6000, 11, 12, 4 },      \
 689         { 0, 0, 9000, 15, 18, 4 },      \
 690         { 1, 0, 12000, 10, 24, 6 },     \
 691         { 1, 0, 18000, 14, 36, 6 },     \
 692         { 1, 0, 24000, 9, 48, 8 },      \
 693         { 1, 0, 36000, 13, 72, 8 },     \
 694         { 1, 0, 48000, 8, 96, 8 },      \
 695         { 1, 0, 54000, 12, 108, 8 } }   \
 696 }
 697
 698 #define AR5K_RATES_TURBO { 8, {                                 \
 699         255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0,     \
 700         7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255,     \
 701         255, 255, 255, 255, 255, 255, 255, 255 }, {             \
 702         { 1, MODULATION_TURBO, 6000, 11, 140, 0 },      \
 703         { 1, MODULATION_TURBO, 9000, 15, 18, 0 },       \
 704         { 1, MODULATION_TURBO, 12000, 10, 152, 2 },     \
 705         { 1, MODULATION_TURBO, 18000, 14, 36, 2 },      \
 706         { 1, MODULATION_TURBO, 24000, 9, 176, 4 },      \
 707         { 1, MODULATION_TURBO, 36000, 13, 72, 4 },      \
 708         { 1, MODULATION_TURBO, 48000, 8, 96, 4 },       \
 709         { 1, MODULATION_TURBO, 54000, 12, 108, 4 } }    \
 710 }
 711
 712 #define AR5K_RATES_XR { 12, {                                   \
 713         255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4,            \
 714         11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255,    \
 715         255, 255, 255, 255, 255, 255, 255, 255 }, {             \
 716         { 1, MODULATION_XR, 500, 7, 129, 0 },           \
 717         { 1, MODULATION_XR, 1000, 2, 139, 1 },          \
 718         { 1, MODULATION_XR, 2000, 6, 150, 2 },          \
 719         { 1, MODULATION_XR, 3000, 1, 150, 3 },          \
 720         { 1, 0, 6000, 11, 140, 4 },     \
 721         { 1, 0, 9000, 15, 18, 4 },      \
 722         { 1, 0, 12000, 10, 152, 6 },    \
 723         { 1, 0, 18000, 14, 36, 6 },     \
 724         { 1, 0, 24000, 9, 176, 8 },     \
 725         { 1, 0, 36000, 13, 72, 8 },     \
 726         { 1, 0, 48000, 8, 96, 8 },      \
 727         { 1, 0, 54000, 12, 108, 8 } }   \
 728 }
 729
 730 /*
 731  * Crypto definitions
 732  */
 733
 734 #define AR5K_KEYCACHE_SIZE      8
 735
 736 /***********************\
 737  HW RELATED DEFINITIONS
 738 \***********************/
 739
 740 /*
 741  * Misc definitions
 742  */
 743 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
 744
 745 #define AR5K_ASSERT_ENTRY(_e, _s) do {          \
 746         if (_e >= _s)                           \
 747                 return (false);                 \
 748 } while (0)
 749
 750
 751 enum ath5k_ant_setting {
 752         AR5K_ANT_VARIABLE       = 0,    /* variable by programming */
 753         AR5K_ANT_FIXED_A        = 1,    /* fixed to 11a frequencies */
 754         AR5K_ANT_FIXED_B        = 2,    /* fixed to 11b frequencies */
 755         AR5K_ANT_MAX            = 3,
 756 };
 757
 758 /*
 759  * Hardware interrupt abstraction
 760  */
 761
 762 /**
 763  * enum ath5k_int - Hardware interrupt masks helpers
 764  *
 765  * @AR5K_INT_RX: mask to identify received frame interrupts, of type
 766  *      AR5K_ISR_RXOK or AR5K_ISR_RXERR
 767  * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
 768  * @AR5K_INT_RXNOFRM: No frame received (?)
 769  * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
 770  *      Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
 771  *      LinkPtr is NULL. For more details, refer to:
 772  *      http://www.freepatentsonline.com/20030225739.html
 773  * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
 774  *      Note that Rx overrun is not always fatal, on some chips we can continue
 775  *      operation without reseting the card, that's why int_fatal is not
 776  *      common for all chips.
 777  * @AR5K_INT_TX: mask to identify received frame interrupts, of type
 778  *      AR5K_ISR_TXOK or AR5K_ISR_TXERR
 779  * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
 780  * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
 781  *      We currently do increments on interrupt by
 782  *      (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
 783  * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
 784  *      checked. We should do this with ath5k_hw_update_mib_counters() but
 785  *      it seems we should also then do some noise immunity work.
 786  * @AR5K_INT_RXPHY: RX PHY Error
 787  * @AR5K_INT_RXKCM: ??
 788  * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
 789  *      beacon that must be handled in software. The alternative is if you
 790  *      have VEOL support, in that case you let the hardware deal with things.
 791  * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
 792  *      beacons from the AP have associated with, we should probably try to
 793  *      reassociate. When in IBSS mode this might mean we have not received
 794  *      any beacons from any local stations. Note that every station in an
 795  *      IBSS schedules to send beacons at the Target Beacon Transmission Time
 796  *      (TBTT) with a random backoff.
 797  * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
 798  * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
 799  *      until properly handled
 800  * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
 801  *      errors. These types of errors we can enable seem to be of type
 802  *      AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
 803  * @AR5K_INT_GLOBAL: Seems to be used to clear and set the IER
 804  * @AR5K_INT_NOCARD: signals the card has been removed
 805  * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
 806  *      bit value
 807  *
 808  * These are mapped to take advantage of some common bits
 809  * between the MACs, to be able to set intr properties
 810  * easier. Some of them are not used yet inside hw.c. Most map
 811  * to the respective hw interrupt value as they are common amogst different
 812  * MACs.
 813  */
 814 enum ath5k_int {
 815         AR5K_INT_RX     = 0x00000001, /* Not common */
 816         AR5K_INT_RXDESC = 0x00000002,
 817         AR5K_INT_RXNOFRM = 0x00000008,
 818         AR5K_INT_RXEOL  = 0x00000010,
 819         AR5K_INT_RXORN  = 0x00000020,
 820         AR5K_INT_TX     = 0x00000040, /* Not common */
 821         AR5K_INT_TXDESC = 0x00000080,
 822         AR5K_INT_TXURN  = 0x00000800,
 823         AR5K_INT_MIB    = 0x00001000,
 824         AR5K_INT_RXPHY  = 0x00004000,
 825         AR5K_INT_RXKCM  = 0x00008000,
 826         AR5K_INT_SWBA   = 0x00010000,
 827         AR5K_INT_BMISS  = 0x00040000,
 828         AR5K_INT_BNR    = 0x00100000, /* Not common */
 829         AR5K_INT_GPIO   = 0x01000000,
 830         AR5K_INT_FATAL  = 0x40000000, /* Not common */
 831         AR5K_INT_GLOBAL = 0x80000000,
 832
 833         AR5K_INT_COMMON  = AR5K_INT_RXNOFRM
 834                         | AR5K_INT_RXDESC
 835                         | AR5K_INT_RXEOL
 836                         | AR5K_INT_RXORN
 837                         | AR5K_INT_TXURN
 838                         | AR5K_INT_TXDESC
 839                         | AR5K_INT_MIB
 840                         | AR5K_INT_RXPHY
 841                         | AR5K_INT_RXKCM
 842                         | AR5K_INT_SWBA
 843                         | AR5K_INT_BMISS
 844                         | AR5K_INT_GPIO,
 845         AR5K_INT_NOCARD = 0xffffffff
 846 };
 847
 848 /*
 849  * Power management
 850  */
 851 enum ath5k_power_mode {
 852         AR5K_PM_UNDEFINED = 0,
 853         AR5K_PM_AUTO,
 854         AR5K_PM_AWAKE,
 855         AR5K_PM_FULL_SLEEP,
 856         AR5K_PM_NETWORK_SLEEP,
 857 };
 858
 859 /*
 860  * These match net80211 definitions (not used in
 861  * d80211).
 862  */
 863 #define AR5K_LED_INIT   0 /*IEEE80211_S_INIT*/
 864 #define AR5K_LED_SCAN   1 /*IEEE80211_S_SCAN*/
 865 #define AR5K_LED_AUTH   2 /*IEEE80211_S_AUTH*/
 866 #define AR5K_LED_ASSOC  3 /*IEEE80211_S_ASSOC*/
 867 #define AR5K_LED_RUN    4 /*IEEE80211_S_RUN*/
 868
 869 /* GPIO-controlled software LED */
 870 #define AR5K_SOFTLED_PIN        0
 871 #define AR5K_SOFTLED_ON         0
 872 #define AR5K_SOFTLED_OFF        1
 873
 874 /*
 875  * Chipset capabilities -see ath5k_hw_get_capability-
 876  * get_capability function is not yet fully implemented
 877  * in OpenHAL so most of these don't work yet...
 878  */
 879 enum ath5k_capability_type {
 880         AR5K_CAP_REG_DMN                = 0,    /* Used to get current reg. domain id */
 881         AR5K_CAP_TKIP_MIC               = 2,    /* Can handle TKIP MIC in hardware */
 882         AR5K_CAP_TKIP_SPLIT             = 3,    /* TKIP uses split keys */
 883         AR5K_CAP_PHYCOUNTERS            = 4,    /* PHY error counters */
 884         AR5K_CAP_DIVERSITY              = 5,    /* Supports fast diversity */
 885         AR5K_CAP_NUM_TXQUEUES           = 6,    /* Used to get max number of hw txqueues */
 886         AR5K_CAP_VEOL                   = 7,    /* Supports virtual EOL */
 887         AR5K_CAP_COMPRESSION            = 8,    /* Supports compression */
 888         AR5K_CAP_BURST                  = 9,    /* Supports packet bursting */
 889         AR5K_CAP_FASTFRAME              = 10,   /* Supports fast frames */
 890         AR5K_CAP_TXPOW                  = 11,   /* Used to get global tx power limit */
 891         AR5K_CAP_TPC                    = 12,   /* Can do per-packet tx power control (needed for 802.11a) */
 892         AR5K_CAP_BSSIDMASK              = 13,   /* Supports bssid mask */
 893         AR5K_CAP_MCAST_KEYSRCH          = 14,   /* Supports multicast key search */
 894         AR5K_CAP_TSF_ADJUST             = 15,   /* Supports beacon tsf adjust */
 895         AR5K_CAP_XR                     = 16,   /* Supports XR mode */
 896         AR5K_CAP_WME_TKIPMIC            = 17,   /* Supports TKIP MIC when using WMM */
 897         AR5K_CAP_CHAN_HALFRATE          = 18,   /* Supports half rate channels */
 898         AR5K_CAP_CHAN_QUARTERRATE       = 19,   /* Supports quarter rate channels */
 899         AR5K_CAP_RFSILENT               = 20,   /* Supports RFsilent */
 900 };
 901
 902
 903 /* XXX: we *may* move cap_range stuff to struct wiphy */
 904 struct ath5k_capabilities {
 905         /*
 906          * Supported PHY modes
 907          * (ie. CHANNEL_A, CHANNEL_B, ...)
 908          */
 909         DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
 910
 911         /*
 912          * Frequency range (without regulation restrictions)
 913          */
 914         struct {
 915                 u16     range_2ghz_min;
 916                 u16     range_2ghz_max;
 917                 u16     range_5ghz_min;
 918                 u16     range_5ghz_max;
 919         } cap_range;
 920
 921         /*
 922          * Values stored in the EEPROM (some of them...)
 923          */
 924         struct ath5k_eeprom_info        cap_eeprom;
 925
 926         /*
 927          * Queue information
 928          */
 929         struct {
 930                 u8      q_tx_num;
 931         } cap_queues;
 932 };
 933
 934
 935 /***************************************\
 936   HARDWARE ABSTRACTION LAYER STRUCTURE
 937 \***************************************/
 938
 939 /*
 940  * Misc defines
 941  */
 942
 943 #define AR5K_MAX_GPIO           10
 944 #define AR5K_MAX_RF_BANKS       8
 945
 946 struct ath5k_hw {
 947         u32                     ah_magic;
 948
 949         struct ath5k_softc      *ah_sc;
 950         void __iomem            *ah_iobase;
 951
 952         enum ath5k_int          ah_imr;
 953
 954         enum ieee80211_if_types ah_op_mode;
 955         enum ath5k_power_mode   ah_power_mode;
 956         struct ieee80211_channel ah_current_channel;
 957         bool                    ah_turbo;
 958         bool                    ah_calibration;
 959         bool                    ah_running;
 960         bool                    ah_single_chip;
 961         enum ath5k_rfgain       ah_rf_gain;
 962
 963         u32                     ah_mac_srev;
 964         u16                     ah_mac_version;
 965         u16                     ah_mac_revision;
 966         u16                     ah_phy_revision;
 967         u16                     ah_radio_5ghz_revision;
 968         u16                     ah_radio_2ghz_revision;
 969
 970         enum ath5k_version      ah_version;
 971         enum ath5k_radio        ah_radio;
 972         u32                     ah_phy;
 973
 974         bool                    ah_5ghz;
 975         bool                    ah_2ghz;
 976
 977 #define ah_regdomain            ah_capabilities.cap_regdomain.reg_current
 978 #define ah_regdomain_hw         ah_capabilities.cap_regdomain.reg_hw
 979 #define ah_modes                ah_capabilities.cap_mode
 980 #define ah_ee_version           ah_capabilities.cap_eeprom.ee_version
 981
 982         u32                     ah_atim_window;
 983         u32                     ah_aifs;
 984         u32                     ah_cw_min;
 985         u32                     ah_cw_max;
 986         bool                    ah_software_retry;
 987         u32                     ah_limit_tx_retries;
 988
 989         u32                     ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
 990         bool                    ah_ant_diversity;
 991
 992         u8                      ah_sta_id[ETH_ALEN];
 993
 994         /* Current BSSID we are trying to assoc to / creating.
 995          * This is passed by mac80211 on config_interface() and cached here for
 996          * use in resets */
 997         u8                      ah_bssid[ETH_ALEN];
 998
 999         u32                     ah_gpio[AR5K_MAX_GPIO];
1000         int                     ah_gpio_npins;
1001
1002         struct ath5k_capabilities ah_capabilities;
1003
1004         struct ath5k_txq_info   ah_txq[AR5K_NUM_TX_QUEUES];
1005         u32                     ah_txq_status;
1006         u32                     ah_txq_imr_txok;
1007         u32                     ah_txq_imr_txerr;
1008         u32                     ah_txq_imr_txurn;
1009         u32                     ah_txq_imr_txdesc;
1010         u32                     ah_txq_imr_txeol;
1011         u32                     *ah_rf_banks;
1012         size_t                  ah_rf_banks_size;
1013         struct ath5k_gain       ah_gain;
1014         u32                     ah_offset[AR5K_MAX_RF_BANKS];
1015
1016         struct {
1017                 u16             txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
1018                 u16             txp_rates[AR5K_MAX_RATES];
1019                 s16             txp_min;
1020                 s16             txp_max;
1021                 bool            txp_tpc;
1022                 s16             txp_ofdm;
1023         } ah_txpower;
1024
1025         struct {
1026                 bool            r_enabled;
1027                 int             r_last_alert;
1028                 struct ieee80211_channel r_last_channel;
1029         } ah_radar;
1030
1031         /* noise floor from last periodic calibration */
1032         s32                     ah_noise_floor;
1033
1034         /*
1035          * Function pointers
1036          */
1037         int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1038                 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1039                 unsigned int, unsigned int, unsigned int, unsigned int,
1040                 unsigned int, unsigned int, unsigned int);
1041         int (*ah_setup_xtx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1042                 unsigned int, unsigned int, unsigned int, unsigned int,
1043                 unsigned int, unsigned int);
1044         int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *);
1045         int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *);
1046 };
1047
1048 /*
1049  * Prototypes
1050  */
1051
1052 /* General Functions */
1053 extern int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, bool is_set);
1054 /* Attach/Detach Functions */
1055 extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version);
1056 extern const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah, unsigned int mode);
1057 extern void ath5k_hw_detach(struct ath5k_hw *ah);
1058 /* Reset Functions */
1059 extern int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel);
1060 /* Power management functions */
1061 extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
1062 /* DMA Related Functions */
1063 extern void ath5k_hw_start_rx(struct ath5k_hw *ah);
1064 extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1065 extern u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah);
1066 extern void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr);
1067 extern int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue);
1068 extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1069 extern u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue);
1070 extern int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr);
1071 extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1072 /* Interrupt handling */
1073 extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1074 extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1075 extern enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1076 /* EEPROM access functions */
1077 extern int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain);
1078 /* Protocol Control Unit Functions */
1079 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1080 /* BSSID Functions */
1081 extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1082 extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1083 extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1084 extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1085 /* Receive start/stop functions */
1086 extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1087 extern void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah);
1088 /* RX Filter functions */
1089 extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1090 extern int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index);
1091 extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1092 extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1093 extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1094 /* Beacon related functions */
1095 extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
1096 extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1097 extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1098 extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1099 #if 0
1100 extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1101 extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1102 extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1103 #endif
1104 extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ath5k_mib_stats *statistics);
1105 /* ACK bit rate */
1106 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1107 /* ACK/CTS Timeouts */
1108 extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1109 extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1110 extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1111 extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1112 /* Key table (WEP) functions */
1113 extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1114 extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
1115 extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac);
1116 extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
1117 /* Queue Control Unit, DFS Control Unit Functions */
1118 extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info);
1119 extern int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue, const struct ath5k_txq_info *queue_info);
1120 extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
1121 extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1122 extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1123 extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1124 extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1125 extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
1126 /* Hardware Descriptor Functions */
1127 extern int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, u32 size, unsigned int flags);
1128 /* GPIO Functions */
1129 extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1130 extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1131 extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1132 extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1133 extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1134 extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
1135 /* Misc functions */
1136 extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
1137
1138
1139 /* Initial register settings functions */
1140 extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1141 /* Initialize RF */
1142 extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int mode);
1143 extern int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq);
1144 extern enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah);
1145 extern int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah);
1146
1147
1148 /* PHY/RF channel functions */
1149 extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1150 extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1151 /* PHY calibration */
1152 extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1153 extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1154 /* Misc PHY functions */
1155 extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1156 extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
1157 extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
1158 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
1159 /* TX power setup */
1160 extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int txpower);
1161 extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
1162
1163
1164 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1165 {
1166         return ioread32(ah->ah_iobase + reg);
1167 }
1168
1169 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1170 {
1171         iowrite32(val, ah->ah_iobase + reg);
1172 }
1173
1174 #endif