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[PATCH] acpi hotplug: decouple slot power state changes from physical hotplug
[linux-2.6/kvm.git] / sound / oss / es1371.c
blob9266b777387b058b95f90c014672aa2e76fc668c
1 /*****************************************************************************/
2
3 /*
4 * es1371.c -- Creative Ensoniq ES1371.
5 *
6 * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Special thanks to Ensoniq
23 *
24 * Supported devices:
25 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
26 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
27 * /dev/dsp1 additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting
28 * /dev/midi simple MIDI UART interface, no ioctl
29 *
30 * NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed
31 * to be done in software. That is what /dev/dac is for. By now (Q2 1998)
32 * there are several MIDI to PCM (WAV) packages, one of them is timidity.
33 *
34 * Revision history
35 * 04.06.1998 0.1 Initial release
36 * Mixer stuff should be overhauled; especially optional AC97 mixer bits
37 * should be detected. This results in strange behaviour of some mixer
38 * settings, like master volume and mic.
39 * 08.06.1998 0.2 First release using Alan Cox' soundcore instead of miscdevice
40 * 03.08.1998 0.3 Do not include modversions.h
41 * Now mixer behaviour can basically be selected between
42 * "OSS documented" and "OSS actual" behaviour
43 * 31.08.1998 0.4 Fix realplayer problems - dac.count issues
44 * 27.10.1998 0.5 Fix joystick support
45 * -- Oliver Neukum (c188@org.chemie.uni-muenchen.de)
46 * 10.12.1998 0.6 Fix drain_dac trying to wait on not yet initialized DMA
47 * 23.12.1998 0.7 Fix a few f_file & FMODE_ bugs
48 * Don't wake up app until there are fragsize bytes to read/write
49 * 06.01.1999 0.8 remove the silly SA_INTERRUPT flag.
50 * hopefully killed the egcs section type conflict
51 * 12.03.1999 0.9 cinfo.blocks should be reset after GETxPTR ioctl.
52 * reported by Johan Maes <joma@telindus.be>
53 * 22.03.1999 0.10 return EAGAIN instead of EBUSY when O_NONBLOCK
54 * read/write cannot be executed
55 * 07.04.1999 0.11 implemented the following ioctl's: SOUND_PCM_READ_RATE,
56 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
57 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
58 * Another Alpha fix (wait_src_ready in init routine)
59 * reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru>
60 * Note: joystick address handling might still be wrong on archs
61 * other than i386
62 * 15.06.1999 0.12 Fix bad allocation bug.
63 * Thanks to Deti Fliegl <fliegl@in.tum.de>
64 * 28.06.1999 0.13 Add pci_set_master
65 * 03.08.1999 0.14 adapt to Linus' new __setup/__initcall
66 * added kernel command line option "es1371=joystickaddr"
67 * removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge
68 * 10.08.1999 0.15 (Re)added S/PDIF module option for cards revision >= 4.
69 * Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>.
70 * module_init/__setup fixes
71 * 08.16.1999 0.16 Joe Cotellese <joec@ensoniq.com>
72 * Added detection for ES1371 revision ID so that we can
73 * detect the ES1373 and later parts.
74 * added AC97 #defines for readability
75 * added a /proc file system for dumping hardware state
76 * updated SRC and CODEC w/r functions to accommodate bugs
77 * in some versions of the ES137x chips.
78 * 31.08.1999 0.17 add spin_lock_init
79 * replaced current->state = x with set_current_state(x)
80 * 03.09.1999 0.18 change read semantics for MIDI to match
81 * OSS more closely; remove possible wakeup race
82 * 21.10.1999 0.19 Round sampling rates, requested by
83 * Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp>
84 * 27.10.1999 0.20 Added SigmaTel 3D enhancement string
85 * Codec ID printing changes
86 * 28.10.1999 0.21 More waitqueue races fixed
87 * Joe Cotellese <joec@ensoniq.com>
88 * Changed PCI detection routine so we can more easily
89 * detect ES137x chip and derivatives.
90 * 05.01.2000 0.22 Should now work with rev7 boards; patch by
91 * Eric Lemar, elemar@cs.washington.edu
92 * 08.01.2000 0.23 Prevent some ioctl's from returning bad count values on underrun/overrun;
93 * Tim Janik's BSE (Bedevilled Sound Engine) found this
94 * 07.02.2000 0.24 Use pci_alloc_consistent and pci_register_driver
95 * 07.02.2000 0.25 Use ac97_codec
96 * 01.03.2000 0.26 SPDIF patch by Mikael Bouillot <mikael.bouillot@bigfoot.com>
97 * Use pci_module_init
98 * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
99 * 12.12.2000 0.28 More dma buffer initializations, patch from
100 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
101 * 05.01.2001 0.29 Hopefully updates will not be required anymore when Creative bumps
102 * the CT5880 revision.
103 * suggested by Stephan Müller <smueller@chronox.de>
104 * 31.01.2001 0.30 Register/Unregister gameport
105 * Fix SETTRIGGER non OSS API conformity
106 * 14.07.2001 0.31 Add list of laptops needing amplifier control
107 * 03.01.2003 0.32 open_mode fixes from Georg Acher <acher@in.tum.de>
108 */
109
110 /*****************************************************************************/
111
112 #include <linux/interrupt.h>
113 #include <linux/module.h>
114 #include <linux/string.h>
115 #include <linux/ioport.h>
116 #include <linux/sched.h>
117 #include <linux/delay.h>
118 #include <linux/sound.h>
119 #include <linux/slab.h>
120 #include <linux/soundcard.h>
121 #include <linux/pci.h>
122 #include <linux/init.h>
123 #include <linux/poll.h>
124 #include <linux/bitops.h>
125 #include <linux/proc_fs.h>
126 #include <linux/spinlock.h>
127 #include <linux/smp_lock.h>
128 #include <linux/ac97_codec.h>
129 #include <linux/gameport.h>
130 #include <linux/wait.h>
131 #include <linux/dma-mapping.h>
132
133 #include <asm/io.h>
134 #include <asm/page.h>
135 #include <asm/uaccess.h>
136
137 /* --------------------------------------------------------------------- */
138
139 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
140 #define ES1371_DEBUG
141 #define DBG(x) {}
142 /*#define DBG(x) {x}*/
143
144 /* --------------------------------------------------------------------- */
145
146 #ifndef PCI_VENDOR_ID_ENSONIQ
147 #define PCI_VENDOR_ID_ENSONIQ 0x1274
148 #endif
149
150 #ifndef PCI_VENDOR_ID_ECTIVA
151 #define PCI_VENDOR_ID_ECTIVA 0x1102
152 #endif
153
154 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
155 #define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
156 #endif
157
158 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
159 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
160 #endif
161
162 #ifndef PCI_DEVICE_ID_ECTIVA_EV1938
163 #define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
164 #endif
165
166 /* ES1371 chip ID */
167 /* This is a little confusing because all ES1371 compatible chips have the
168 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
169 This is only significant if you want to enable features on the later parts.
170 Yes, I know it's stupid and why didn't we use the sub IDs?
171 */
172 #define ES1371REV_ES1373_A 0x04
173 #define ES1371REV_ES1373_B 0x06
174 #define ES1371REV_CT5880_A 0x07
175 #define CT5880REV_CT5880_C 0x02
176 #define CT5880REV_CT5880_D 0x03
177 #define ES1371REV_ES1371_B 0x09
178 #define EV1938REV_EV1938_A 0x00
179 #define ES1371REV_ES1373_8 0x08
180
181 #define ES1371_MAGIC ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371)
182
183 #define ES1371_EXTENT 0x40
184 #define JOY_EXTENT 8
185
186 #define ES1371_REG_CONTROL 0x00
187 #define ES1371_REG_STATUS 0x04 /* on the 5880 it is control/status */
188 #define ES1371_REG_UART_DATA 0x08
189 #define ES1371_REG_UART_STATUS 0x09
190 #define ES1371_REG_UART_CONTROL 0x09
191 #define ES1371_REG_UART_TEST 0x0a
192 #define ES1371_REG_MEMPAGE 0x0c
193 #define ES1371_REG_SRCONV 0x10
194 #define ES1371_REG_CODEC 0x14
195 #define ES1371_REG_LEGACY 0x18
196 #define ES1371_REG_SERIAL_CONTROL 0x20
197 #define ES1371_REG_DAC1_SCOUNT 0x24
198 #define ES1371_REG_DAC2_SCOUNT 0x28
199 #define ES1371_REG_ADC_SCOUNT 0x2c
200
201 #define ES1371_REG_DAC1_FRAMEADR 0xc30
202 #define ES1371_REG_DAC1_FRAMECNT 0xc34
203 #define ES1371_REG_DAC2_FRAMEADR 0xc38
204 #define ES1371_REG_DAC2_FRAMECNT 0xc3c
205 #define ES1371_REG_ADC_FRAMEADR 0xd30
206 #define ES1371_REG_ADC_FRAMECNT 0xd34
207
208 #define ES1371_FMT_U8_MONO 0
209 #define ES1371_FMT_U8_STEREO 1
210 #define ES1371_FMT_S16_MONO 2
211 #define ES1371_FMT_S16_STEREO 3
212 #define ES1371_FMT_STEREO 1
213 #define ES1371_FMT_S16 2
214 #define ES1371_FMT_MASK 3
215
216 static const unsigned sample_size[] = { 1, 2, 2, 4 };
217 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
218
219 #define CTRL_RECEN_B 0x08000000 /* 1 = don't mix analog in to digital out */
220 #define CTRL_SPDIFEN_B 0x04000000
221 #define CTRL_JOY_SHIFT 24
222 #define CTRL_JOY_MASK 3
223 #define CTRL_JOY_200 0x00000000 /* joystick base address */
224 #define CTRL_JOY_208 0x01000000
225 #define CTRL_JOY_210 0x02000000
226 #define CTRL_JOY_218 0x03000000
227 #define CTRL_GPIO_IN0 0x00100000 /* general purpose inputs/outputs */
228 #define CTRL_GPIO_IN1 0x00200000
229 #define CTRL_GPIO_IN2 0x00400000
230 #define CTRL_GPIO_IN3 0x00800000
231 #define CTRL_GPIO_OUT0 0x00010000
232 #define CTRL_GPIO_OUT1 0x00020000
233 #define CTRL_GPIO_OUT2 0x00040000
234 #define CTRL_GPIO_OUT3 0x00080000
235 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
236 #define CTRL_SYNCRES 0x00004000 /* AC97 warm reset */
237 #define CTRL_ADCSTOP 0x00002000 /* stop ADC transfers */
238 #define CTRL_PWR_INTRM 0x00001000 /* 1 = power level ints enabled */
239 #define CTRL_M_CB 0x00000800 /* recording source: 0 = ADC, 1 = MPEG */
240 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
241 #define CTRL_PDLEV0 0x00000000 /* power down level */
242 #define CTRL_PDLEV1 0x00000100
243 #define CTRL_PDLEV2 0x00000200
244 #define CTRL_PDLEV3 0x00000300
245 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
246 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
247 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
248 #define CTRL_ADC_EN 0x00000010 /* enable ADC */
249 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
250 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port */
251 #define CTRL_XTALCLKDIS 0x00000002 /* 1 = disable crystal clock input */
252 #define CTRL_PCICLKDIS 0x00000001 /* 1 = disable PCI clock distribution */
253
254
255 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
256 #define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */
257 #define STAT_EN_SPDIF 0x00040000 /* enable S/PDIF circuitry */
258 #define STAT_TS_SPDIF 0x00020000 /* test S/PDIF circuitry */
259 #define STAT_TESTMODE 0x00010000 /* test ASIC */
260 #define STAT_SYNC_ERR 0x00000100 /* 1 = codec sync error */
261 #define STAT_VC 0x000000c0 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
262 #define STAT_SH_VC 6
263 #define STAT_MPWR 0x00000020 /* power level interrupt */
264 #define STAT_MCCB 0x00000010 /* CCB int pending */
265 #define STAT_UART 0x00000008 /* UART int pending */
266 #define STAT_DAC1 0x00000004 /* DAC1 int pending */
267 #define STAT_DAC2 0x00000002 /* DAC2 int pending */
268 #define STAT_ADC 0x00000001 /* ADC int pending */
269
270 #define USTAT_RXINT 0x80 /* UART rx int pending */
271 #define USTAT_TXINT 0x04 /* UART tx int pending */
272 #define USTAT_TXRDY 0x02 /* UART tx ready */
273 #define USTAT_RXRDY 0x01 /* UART rx ready */
274
275 #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
276 #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
277 #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
278 #define UCTRL_CNTRL 0x03 /* control field */
279 #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
280
281 /* sample rate converter */
282 #define SRC_OKSTATE 1
283
284 #define SRC_RAMADDR_MASK 0xfe000000
285 #define SRC_RAMADDR_SHIFT 25
286 #define SRC_DAC1FREEZE (1UL << 21)
287 #define SRC_DAC2FREEZE (1UL << 20)
288 #define SRC_ADCFREEZE (1UL << 19)
289
290
291 #define SRC_WE 0x01000000 /* read/write control for SRC RAM */
292 #define SRC_BUSY 0x00800000 /* SRC busy */
293 #define SRC_DIS 0x00400000 /* 1 = disable SRC */
294 #define SRC_DDAC1 0x00200000 /* 1 = disable accum update for DAC1 */
295 #define SRC_DDAC2 0x00100000 /* 1 = disable accum update for DAC2 */
296 #define SRC_DADC 0x00080000 /* 1 = disable accum update for ADC2 */
297 #define SRC_CTLMASK 0x00780000
298 #define SRC_RAMDATA_MASK 0x0000ffff
299 #define SRC_RAMDATA_SHIFT 0
300
301 #define SRCREG_ADC 0x78
302 #define SRCREG_DAC1 0x70
303 #define SRCREG_DAC2 0x74
304 #define SRCREG_VOL_ADC 0x6c
305 #define SRCREG_VOL_DAC1 0x7c
306 #define SRCREG_VOL_DAC2 0x7e
307
308 #define SRCREG_TRUNC_N 0x00
309 #define SRCREG_INT_REGS 0x01
310 #define SRCREG_ACCUM_FRAC 0x02
311 #define SRCREG_VFREQ_FRAC 0x03
312
313 #define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
314 #define CODEC_PIADD_MASK 0x007f0000
315 #define CODEC_PIADD_SHIFT 16
316 #define CODEC_PIDAT_MASK 0x0000ffff
317 #define CODEC_PIDAT_SHIFT 0
318
319 #define CODEC_RDY 0x80000000 /* AC97 read data valid */
320 #define CODEC_WIP 0x40000000 /* AC97 write in progress */
321 #define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
322 #define CODEC_POADD_MASK 0x007f0000
323 #define CODEC_POADD_SHIFT 16
324 #define CODEC_PODAT_MASK 0x0000ffff
325 #define CODEC_PODAT_SHIFT 0
326
327
328 #define LEGACY_JFAST 0x80000000 /* fast joystick timing */
329 #define LEGACY_FIRQ 0x01000000 /* force IRQ */
330
331 #define SCTRL_DACTEST 0x00400000 /* 1 = DAC test, test vector generation purposes */
332 #define SCTRL_P2ENDINC 0x00380000 /* */
333 #define SCTRL_SH_P2ENDINC 19
334 #define SCTRL_P2STINC 0x00070000 /* */
335 #define SCTRL_SH_P2STINC 16
336 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
337 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
338 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
339 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
340 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
341 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
342 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
343 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
344 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
345 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
346 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
347 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
348 #define SCTRL_R1FMT 0x00000030 /* format mask */
349 #define SCTRL_SH_R1FMT 4
350 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
351 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
352 #define SCTRL_P2FMT 0x0000000c /* format mask */
353 #define SCTRL_SH_P2FMT 2
354 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
355 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
356 #define SCTRL_P1FMT 0x00000003 /* format mask */
357 #define SCTRL_SH_P1FMT 0
358
359
360 /* misc stuff */
361 #define POLL_COUNT 0x1000
362 #define FMODE_DAC 4 /* slight misuse of mode_t */
363
364 /* MIDI buffer sizes */
365
366 #define MIDIINBUF 256
367 #define MIDIOUTBUF 256
368
369 #define FMODE_MIDI_SHIFT 3
370 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
371 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
372
373 #define ES1371_MODULE_NAME "es1371"
374 #define PFX ES1371_MODULE_NAME ": "
375
376 /* --------------------------------------------------------------------- */
377
378 struct es1371_state {
379 /* magic */
380 unsigned int magic;
381
382 /* list of es1371 devices */
383 struct list_head devs;
384
385 /* the corresponding pci_dev structure */
386 struct pci_dev *dev;
387
388 /* soundcore stuff */
389 int dev_audio;
390 int dev_dac;
391 int dev_midi;
392
393 /* hardware resources */
394 unsigned long io; /* long for SPARC */
395 unsigned int irq;
396
397 /* PCI ID's */
398 u16 vendor;
399 u16 device;
400 u8 rev; /* the chip revision */
401
402 /* options */
403 int spdif_volume; /* S/PDIF output is enabled if != -1 */
404
405 #ifdef ES1371_DEBUG
406 /* debug /proc entry */
407 struct proc_dir_entry *ps;
408 #endif /* ES1371_DEBUG */
409
410 struct ac97_codec *codec;
411
412 /* wave stuff */
413 unsigned ctrl;
414 unsigned sctrl;
415 unsigned dac1rate, dac2rate, adcrate;
416
417 spinlock_t lock;
418 struct semaphore open_sem;
419 mode_t open_mode;
420 wait_queue_head_t open_wait;
421
422 struct dmabuf {
423 void *rawbuf;
424 dma_addr_t dmaaddr;
425 unsigned buforder;
426 unsigned numfrag;
427 unsigned fragshift;
428 unsigned hwptr, swptr;
429 unsigned total_bytes;
430 int count;
431 unsigned error; /* over/underrun */
432 wait_queue_head_t wait;
433 /* redundant, but makes calculations easier */
434 unsigned fragsize;
435 unsigned dmasize;
436 unsigned fragsamples;
437 /* OSS stuff */
438 unsigned mapped:1;
439 unsigned ready:1;
440 unsigned endcleared:1;
441 unsigned enabled:1;
442 unsigned ossfragshift;
443 int ossmaxfrags;
444 unsigned subdivision;
445 } dma_dac1, dma_dac2, dma_adc;
446
447 /* midi stuff */
448 struct {
449 unsigned ird, iwr, icnt;
450 unsigned ord, owr, ocnt;
451 wait_queue_head_t iwait;
452 wait_queue_head_t owait;
453 unsigned char ibuf[MIDIINBUF];
454 unsigned char obuf[MIDIOUTBUF];
455 } midi;
456
457 struct gameport *gameport;
458 struct semaphore sem;
459 };
460
461 /* --------------------------------------------------------------------- */
462
463 static LIST_HEAD(devs);
464
465 /* --------------------------------------------------------------------- */
466
467 static inline unsigned ld2(unsigned int x)
468 {
469 unsigned r = 0;
470
471 if (x >= 0x10000) {
472 x >>= 16;
473 r += 16;
474 }
475 if (x >= 0x100) {
476 x >>= 8;
477 r += 8;
478 }
479 if (x >= 0x10) {
480 x >>= 4;
481 r += 4;
482 }
483 if (x >= 4) {
484 x >>= 2;
485 r += 2;
486 }
487 if (x >= 2)
488 r++;
489 return r;
490 }
491
492 /* --------------------------------------------------------------------- */
493
494 static unsigned wait_src_ready(struct es1371_state *s)
495 {
496 unsigned int t, r;
497
498 for (t = 0; t < POLL_COUNT; t++) {
499 if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY))
500 return r;
501 udelay(1);
502 }
503 printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r);
504 return r;
505 }
506
507 static unsigned src_read(struct es1371_state *s, unsigned reg)
508 {
509 unsigned int temp,i,orig;
510
511 /* wait for ready */
512 temp = wait_src_ready (s);
513
514 /* we can only access the SRC at certain times, make sure
515 we're allowed to before we read */
516
517 orig = temp;
518 /* expose the SRC state bits */
519 outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL,
520 s->io + ES1371_REG_SRCONV);
521
522 /* now, wait for busy and the correct time to read */
523 temp = wait_src_ready (s);
524
525 if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){
526 /* wait for the right state */
527 for (i=0; i<POLL_COUNT; i++){
528 temp = inl (s->io + ES1371_REG_SRCONV);
529 if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 ))
530 break;
531 }
532 }
533
534 /* hide the state bits */
535 outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV);
536 return temp;
537
538
539 }
540
541 static void src_write(struct es1371_state *s, unsigned reg, unsigned data)
542 {
543
544 unsigned int r;
545
546 r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC);
547 r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK;
548 r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK;
549 outl(r | SRC_WE, s->io + ES1371_REG_SRCONV);
550
551 }
552
553 /* --------------------------------------------------------------------- */
554
555 /* most of the following here is black magic */
556 static void set_adc_rate(struct es1371_state *s, unsigned rate)
557 {
558 unsigned long flags;
559 unsigned int n, truncm, freq;
560
561 if (rate > 48000)
562 rate = 48000;
563 if (rate < 4000)
564 rate = 4000;
565 n = rate / 3000;
566 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
567 n--;
568 truncm = (21 * n - 1) | 1;
569 freq = ((48000UL << 15) / rate) * n;
570 s->adcrate = (48000UL << 15) / (freq / n);
571 spin_lock_irqsave(&s->lock, flags);
572 if (rate >= 24000) {
573 if (truncm > 239)
574 truncm = 239;
575 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
576 (((239 - truncm) >> 1) << 9) | (n << 4));
577 } else {
578 if (truncm > 119)
579 truncm = 119;
580 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
581 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
582 }
583 src_write(s, SRCREG_ADC+SRCREG_INT_REGS,
584 (src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) |
585 ((freq >> 5) & 0xfc00));
586 src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff);
587 src_write(s, SRCREG_VOL_ADC, n << 8);
588 src_write(s, SRCREG_VOL_ADC+1, n << 8);
589 spin_unlock_irqrestore(&s->lock, flags);
590 }
591
592
593 static void set_dac1_rate(struct es1371_state *s, unsigned rate)
594 {
595 unsigned long flags;
596 unsigned int freq, r;
597
598 if (rate > 48000)
599 rate = 48000;
600 if (rate < 4000)
601 rate = 4000;
602 freq = ((rate << 15) + 1500) / 3000;
603 s->dac1rate = (freq * 3000 + 16384) >> 15;
604 spin_lock_irqsave(&s->lock, flags);
605 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1;
606 outl(r, s->io + ES1371_REG_SRCONV);
607 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS,
608 (src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) |
609 ((freq >> 5) & 0xfc00));
610 src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff);
611 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC));
612 outl(r, s->io + ES1371_REG_SRCONV);
613 spin_unlock_irqrestore(&s->lock, flags);
614 }
615
616 static void set_dac2_rate(struct es1371_state *s, unsigned rate)
617 {
618 unsigned long flags;
619 unsigned int freq, r;
620
621 if (rate > 48000)
622 rate = 48000;
623 if (rate < 4000)
624 rate = 4000;
625 freq = ((rate << 15) + 1500) / 3000;
626 s->dac2rate = (freq * 3000 + 16384) >> 15;
627 spin_lock_irqsave(&s->lock, flags);
628 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2;
629 outl(r, s->io + ES1371_REG_SRCONV);
630 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS,
631 (src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) |
632 ((freq >> 5) & 0xfc00));
633 src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff);
634 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC));
635 outl(r, s->io + ES1371_REG_SRCONV);
636 spin_unlock_irqrestore(&s->lock, flags);
637 }
638
639 /* --------------------------------------------------------------------- */
640
641 static void __devinit src_init(struct es1371_state *s)
642 {
643 unsigned int i;
644
645 /* before we enable or disable the SRC we need
646 to wait for it to become ready */
647 wait_src_ready(s);
648
649 outl(SRC_DIS, s->io + ES1371_REG_SRCONV);
650
651 for (i = 0; i < 0x80; i++)
652 src_write(s, i, 0);
653
654 src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4);
655 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10);
656 src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4);
657 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10);
658 src_write(s, SRCREG_VOL_ADC, 1 << 12);
659 src_write(s, SRCREG_VOL_ADC+1, 1 << 12);
660 src_write(s, SRCREG_VOL_DAC1, 1 << 12);
661 src_write(s, SRCREG_VOL_DAC1+1, 1 << 12);
662 src_write(s, SRCREG_VOL_DAC2, 1 << 12);
663 src_write(s, SRCREG_VOL_DAC2+1, 1 << 12);
664 set_adc_rate(s, 22050);
665 set_dac1_rate(s, 22050);
666 set_dac2_rate(s, 22050);
667
668 /* WARNING:
669 * enabling the sample rate converter without properly programming
670 * its parameters causes the chip to lock up (the SRC busy bit will
671 * be stuck high, and I've found no way to rectify this other than
672 * power cycle)
673 */
674 wait_src_ready(s);
675 outl(0, s->io+ES1371_REG_SRCONV);
676 }
677
678 /* --------------------------------------------------------------------- */
679
680 static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
681 {
682 struct es1371_state *s = (struct es1371_state *)codec->private_data;
683 unsigned long flags;
684 unsigned t, x;
685
686 spin_lock_irqsave(&s->lock, flags);
687 for (t = 0; t < POLL_COUNT; t++)
688 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
689 break;
690
691 /* save the current state for later */
692 x = wait_src_ready(s);
693
694 /* enable SRC state data in SRC mux */
695 outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000,
696 s->io+ES1371_REG_SRCONV);
697
698 /* wait for not busy (state 0) first to avoid
699 transition states */
700 for (t=0; t<POLL_COUNT; t++){
701 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
702 break;
703 udelay(1);
704 }
705
706 /* wait for a SAFE time to write addr/data and then do it, dammit */
707 for (t=0; t<POLL_COUNT; t++){
708 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
709 break;
710 udelay(1);
711 }
712
713 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
714 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC);
715
716 /* restore SRC reg */
717 wait_src_ready(s);
718 outl(x, s->io+ES1371_REG_SRCONV);
719 spin_unlock_irqrestore(&s->lock, flags);
720 }
721
722 static u16 rdcodec(struct ac97_codec *codec, u8 addr)
723 {
724 struct es1371_state *s = (struct es1371_state *)codec->private_data;
725 unsigned long flags;
726 unsigned t, x;
727
728 spin_lock_irqsave(&s->lock, flags);
729
730 /* wait for WIP to go away */
731 for (t = 0; t < 0x1000; t++)
732 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
733 break;
734
735 /* save the current state for later */
736 x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC));
737
738 /* enable SRC state data in SRC mux */
739 outl( x | 0x00010000,
740 s->io+ES1371_REG_SRCONV);
741
742 /* wait for not busy (state 0) first to avoid
743 transition states */
744 for (t=0; t<POLL_COUNT; t++){
745 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
746 break;
747 udelay(1);
748 }
749
750 /* wait for a SAFE time to write addr/data and then do it, dammit */
751 for (t=0; t<POLL_COUNT; t++){
752 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
753 break;
754 udelay(1);
755 }
756
757 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC);
758 /* restore SRC reg */
759 wait_src_ready(s);
760 outl(x, s->io+ES1371_REG_SRCONV);
761
762 /* wait for WIP again */
763 for (t = 0; t < 0x1000; t++)
764 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
765 break;
766
767 /* now wait for the stinkin' data (RDY) */
768 for (t = 0; t < POLL_COUNT; t++)
769 if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY)
770 break;
771
772 spin_unlock_irqrestore(&s->lock, flags);
773 return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
774 }
775
776 /* --------------------------------------------------------------------- */
777
778 static inline void stop_adc(struct es1371_state *s)
779 {
780 unsigned long flags;
781
782 spin_lock_irqsave(&s->lock, flags);
783 s->ctrl &= ~CTRL_ADC_EN;
784 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
785 spin_unlock_irqrestore(&s->lock, flags);
786 }
787
788 static inline void stop_dac1(struct es1371_state *s)
789 {
790 unsigned long flags;
791
792 spin_lock_irqsave(&s->lock, flags);
793 s->ctrl &= ~CTRL_DAC1_EN;
794 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
795 spin_unlock_irqrestore(&s->lock, flags);
796 }
797
798 static inline void stop_dac2(struct es1371_state *s)
799 {
800 unsigned long flags;
801
802 spin_lock_irqsave(&s->lock, flags);
803 s->ctrl &= ~CTRL_DAC2_EN;
804 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
805 spin_unlock_irqrestore(&s->lock, flags);
806 }
807
808 static void start_dac1(struct es1371_state *s)
809 {
810 unsigned long flags;
811 unsigned fragremain, fshift;
812
813 spin_lock_irqsave(&s->lock, flags);
814 if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0)
815 && s->dma_dac1.ready) {
816 s->ctrl |= CTRL_DAC1_EN;
817 s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN;
818 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
819 fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1));
820 fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
821 if (fragremain < 2*fshift)
822 fragremain = s->dma_dac1.fragsize;
823 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
824 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
825 outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
826 }
827 spin_unlock_irqrestore(&s->lock, flags);
828 }
829
830 static void start_dac2(struct es1371_state *s)
831 {
832 unsigned long flags;
833 unsigned fragremain, fshift;
834
835 spin_lock_irqsave(&s->lock, flags);
836 if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0)
837 && s->dma_dac2.ready) {
838 s->ctrl |= CTRL_DAC2_EN;
839 s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN |
840 SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN |
841 (((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) |
842 (0 << SCTRL_SH_P2STINC);
843 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
844 fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1));
845 fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
846 if (fragremain < 2*fshift)
847 fragremain = s->dma_dac2.fragsize;
848 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
849 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
850 outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
851 }
852 spin_unlock_irqrestore(&s->lock, flags);
853 }
854
855 static void start_adc(struct es1371_state *s)
856 {
857 unsigned long flags;
858 unsigned fragremain, fshift;
859
860 spin_lock_irqsave(&s->lock, flags);
861 if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
862 && s->dma_adc.ready) {
863 s->ctrl |= CTRL_ADC_EN;
864 s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN;
865 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
866 fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1));
867 fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT];
868 if (fragremain < 2*fshift)
869 fragremain = s->dma_adc.fragsize;
870 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
871 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
872 outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
873 }
874 spin_unlock_irqrestore(&s->lock, flags);
875 }
876
877 /* --------------------------------------------------------------------- */
878
879 #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
880 #define DMABUF_MINORDER 1
881
882
883 static inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db)
884 {
885 struct page *page, *pend;
886
887 if (db->rawbuf) {
888 /* undo marking the pages as reserved */
889 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
890 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
891 ClearPageReserved(page);
892 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
893 }
894 db->rawbuf = NULL;
895 db->mapped = db->ready = 0;
896 }
897
898 static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg)
899 {
900 int order;
901 unsigned bytepersec;
902 unsigned bufs;
903 struct page *page, *pend;
904
905 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
906 if (!db->rawbuf) {
907 db->ready = db->mapped = 0;
908 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
909 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
910 break;
911 if (!db->rawbuf)
912 return -ENOMEM;
913 db->buforder = order;
914 /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
915 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
916 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
917 SetPageReserved(page);
918 }
919 fmt &= ES1371_FMT_MASK;
920 bytepersec = rate << sample_shift[fmt];
921 bufs = PAGE_SIZE << db->buforder;
922 if (db->ossfragshift) {
923 if ((1000 << db->ossfragshift) < bytepersec)
924 db->fragshift = ld2(bytepersec/1000);
925 else
926 db->fragshift = db->ossfragshift;
927 } else {
928 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
929 if (db->fragshift < 3)
930 db->fragshift = 3;
931 }
932 db->numfrag = bufs >> db->fragshift;
933 while (db->numfrag < 4 && db->fragshift > 3) {
934 db->fragshift--;
935 db->numfrag = bufs >> db->fragshift;
936 }
937 db->fragsize = 1 << db->fragshift;
938 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
939 db->numfrag = db->ossmaxfrags;
940 db->fragsamples = db->fragsize >> sample_shift[fmt];
941 db->dmasize = db->numfrag << db->fragshift;
942 memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize);
943 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
944 outl(db->dmaaddr, s->io+(reg & 0xff));
945 outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff));
946 db->enabled = 1;
947 db->ready = 1;
948 return 0;
949 }
950
951 static inline int prog_dmabuf_adc(struct es1371_state *s)
952 {
953 stop_adc(s);
954 return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK,
955 ES1371_REG_ADC_FRAMEADR);
956 }
957
958 static inline int prog_dmabuf_dac2(struct es1371_state *s)
959 {
960 stop_dac2(s);
961 return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK,
962 ES1371_REG_DAC2_FRAMEADR);
963 }
964
965 static inline int prog_dmabuf_dac1(struct es1371_state *s)
966 {
967 stop_dac1(s);
968 return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK,
969 ES1371_REG_DAC1_FRAMEADR);
970 }
971
972 static inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg)
973 {
974 unsigned hwptr, diff;
975
976 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
977 hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc;
978 diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize;
979 db->hwptr = hwptr;
980 return diff;
981 }
982
983 static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
984 {
985 if (bptr + len > bsize) {
986 unsigned x = bsize - bptr;
987 memset(((char *)buf) + bptr, c, x);
988 bptr = 0;
989 len -= x;
990 }
991 memset(((char *)buf) + bptr, c, len);
992 }
993
994 /* call with spinlock held! */
995 static void es1371_update_ptr(struct es1371_state *s)
996 {
997 int diff;
998
999 /* update ADC pointer */
1000 if (s->ctrl & CTRL_ADC_EN) {
1001 diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT);
1002 s->dma_adc.total_bytes += diff;
1003 s->dma_adc.count += diff;
1004 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1005 wake_up(&s->dma_adc.wait);
1006 if (!s->dma_adc.mapped) {
1007 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1008 s->ctrl &= ~CTRL_ADC_EN;
1009 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1010 s->dma_adc.error++;
1011 }
1012 }
1013 }
1014 /* update DAC1 pointer */
1015 if (s->ctrl & CTRL_DAC1_EN) {
1016 diff = get_hwptr(s, &s->dma_dac1, ES1371_REG_DAC1_FRAMECNT);
1017 s->dma_dac1.total_bytes += diff;
1018 if (s->dma_dac1.mapped) {
1019 s->dma_dac1.count += diff;
1020 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
1021 wake_up(&s->dma_dac1.wait);
1022 } else {
1023 s->dma_dac1.count -= diff;
1024 if (s->dma_dac1.count <= 0) {
1025 s->ctrl &= ~CTRL_DAC1_EN;
1026 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1027 s->dma_dac1.error++;
1028 } else if (s->dma_dac1.count <= (signed)s->dma_dac1.fragsize && !s->dma_dac1.endcleared) {
1029 clear_advance(s->dma_dac1.rawbuf, s->dma_dac1.dmasize, s->dma_dac1.swptr,
1030 s->dma_dac1.fragsize, (s->sctrl & SCTRL_P1SEB) ? 0 : 0x80);
1031 s->dma_dac1.endcleared = 1;
1032 }
1033 if (s->dma_dac1.count + (signed)s->dma_dac1.fragsize <= (signed)s->dma_dac1.dmasize)
1034 wake_up(&s->dma_dac1.wait);
1035 }
1036 }
1037 /* update DAC2 pointer */
1038 if (s->ctrl & CTRL_DAC2_EN) {
1039 diff = get_hwptr(s, &s->dma_dac2, ES1371_REG_DAC2_FRAMECNT);
1040 s->dma_dac2.total_bytes += diff;
1041 if (s->dma_dac2.mapped) {
1042 s->dma_dac2.count += diff;
1043 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1044 wake_up(&s->dma_dac2.wait);
1045 } else {
1046 s->dma_dac2.count -= diff;
1047 if (s->dma_dac2.count <= 0) {
1048 s->ctrl &= ~CTRL_DAC2_EN;
1049 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1050 s->dma_dac2.error++;
1051 } else if (s->dma_dac2.count <= (signed)s->dma_dac2.fragsize && !s->dma_dac2.endcleared) {
1052 clear_advance(s->dma_dac2.rawbuf, s->dma_dac2.dmasize, s->dma_dac2.swptr,
1053 s->dma_dac2.fragsize, (s->sctrl & SCTRL_P2SEB) ? 0 : 0x80);
1054 s->dma_dac2.endcleared = 1;
1055 }
1056 if (s->dma_dac2.count + (signed)s->dma_dac2.fragsize <= (signed)s->dma_dac2.dmasize)
1057 wake_up(&s->dma_dac2.wait);
1058 }
1059 }
1060 }
1061
1062 /* hold spinlock for the following! */
1063 static void es1371_handle_midi(struct es1371_state *s)
1064 {
1065 unsigned char ch;
1066 int wake;
1067
1068 if (!(s->ctrl & CTRL_UART_EN))
1069 return;
1070 wake = 0;
1071 while (inb(s->io+ES1371_REG_UART_STATUS) & USTAT_RXRDY) {
1072 ch = inb(s->io+ES1371_REG_UART_DATA);
1073 if (s->midi.icnt < MIDIINBUF) {
1074 s->midi.ibuf[s->midi.iwr] = ch;
1075 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1076 s->midi.icnt++;
1077 }
1078 wake = 1;
1079 }
1080 if (wake)
1081 wake_up(&s->midi.iwait);
1082 wake = 0;
1083 while ((inb(s->io+ES1371_REG_UART_STATUS) & USTAT_TXRDY) && s->midi.ocnt > 0) {
1084 outb(s->midi.obuf[s->midi.ord], s->io+ES1371_REG_UART_DATA);
1085 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1086 s->midi.ocnt--;
1087 if (s->midi.ocnt < MIDIOUTBUF-16)
1088 wake = 1;
1089 }
1090 if (wake)
1091 wake_up(&s->midi.owait);
1092 outb((s->midi.ocnt > 0) ? UCTRL_RXINTEN | UCTRL_ENA_TXINT : UCTRL_RXINTEN, s->io+ES1371_REG_UART_CONTROL);
1093 }
1094
1095 static irqreturn_t es1371_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1096 {
1097 struct es1371_state *s = (struct es1371_state *)dev_id;
1098 unsigned int intsrc, sctl;
1099
1100 /* fastpath out, to ease interrupt sharing */
1101 intsrc = inl(s->io+ES1371_REG_STATUS);
1102 if (!(intsrc & 0x80000000))
1103 return IRQ_NONE;
1104 spin_lock(&s->lock);
1105 /* clear audio interrupts first */
1106 sctl = s->sctrl;
1107 if (intsrc & STAT_ADC)
1108 sctl &= ~SCTRL_R1INTEN;
1109 if (intsrc & STAT_DAC1)
1110 sctl &= ~SCTRL_P1INTEN;
1111 if (intsrc & STAT_DAC2)
1112 sctl &= ~SCTRL_P2INTEN;
1113 outl(sctl, s->io+ES1371_REG_SERIAL_CONTROL);
1114 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1115 es1371_update_ptr(s);
1116 es1371_handle_midi(s);
1117 spin_unlock(&s->lock);
1118 return IRQ_HANDLED;
1119 }
1120
1121 /* --------------------------------------------------------------------- */
1122
1123 static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n";
1124
1125 #define VALIDATE_STATE(s) \
1126 ({ \
1127 if (!(s) || (s)->magic != ES1371_MAGIC) { \
1128 printk(invalid_magic); \
1129 return -ENXIO; \
1130 } \
1131 })
1132
1133 /* --------------------------------------------------------------------- */
1134
1135 /* Conversion table for S/PDIF PCM volume emulation through the SRC */
1136 /* dB-linear table of DAC vol values; -0dB to -46.5dB with mute */
1137 static const unsigned short DACVolTable[101] =
1138 {
1139 0x1000, 0x0f2a, 0x0e60, 0x0da0, 0x0cea, 0x0c3e, 0x0b9a, 0x0aff,
1140 0x0a6d, 0x09e1, 0x095e, 0x08e1, 0x086a, 0x07fa, 0x078f, 0x072a,
1141 0x06cb, 0x0670, 0x061a, 0x05c9, 0x057b, 0x0532, 0x04ed, 0x04ab,
1142 0x046d, 0x0432, 0x03fa, 0x03c5, 0x0392, 0x0363, 0x0335, 0x030b,
1143 0x02e2, 0x02bc, 0x0297, 0x0275, 0x0254, 0x0235, 0x0217, 0x01fb,
1144 0x01e1, 0x01c8, 0x01b0, 0x0199, 0x0184, 0x0170, 0x015d, 0x014b,
1145 0x0139, 0x0129, 0x0119, 0x010b, 0x00fd, 0x00f0, 0x00e3, 0x00d7,
1146 0x00cc, 0x00c1, 0x00b7, 0x00ae, 0x00a5, 0x009c, 0x0094, 0x008c,
1147 0x0085, 0x007e, 0x0077, 0x0071, 0x006b, 0x0066, 0x0060, 0x005b,
1148 0x0057, 0x0052, 0x004e, 0x004a, 0x0046, 0x0042, 0x003f, 0x003c,
1149 0x0038, 0x0036, 0x0033, 0x0030, 0x002e, 0x002b, 0x0029, 0x0027,
1150 0x0025, 0x0023, 0x0021, 0x001f, 0x001e, 0x001c, 0x001b, 0x0019,
1151 0x0018, 0x0017, 0x0016, 0x0014, 0x0000
1152 };
1153
1154 /*
1155 * when we are in S/PDIF mode, we want to disable any analog output so
1156 * we filter the mixer ioctls
1157 */
1158 static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, unsigned long arg)
1159 {
1160 struct es1371_state *s = (struct es1371_state *)codec->private_data;
1161 int val;
1162 unsigned long flags;
1163 unsigned int left, right;
1164
1165 VALIDATE_STATE(s);
1166 /* filter mixer ioctls to catch PCM and MASTER volume when in S/PDIF mode */
1167 if (s->spdif_volume == -1)
1168 return codec->mixer_ioctl(codec, cmd, arg);
1169 switch (cmd) {
1170 case SOUND_MIXER_WRITE_VOLUME:
1171 return 0;
1172
1173 case SOUND_MIXER_WRITE_PCM: /* use SRC for PCM volume */
1174 if (get_user(val, (int __user *)arg))
1175 return -EFAULT;
1176 right = ((val >> 8) & 0xff);
1177 left = (val & 0xff);
1178 if (right > 100)
1179 right = 100;
1180 if (left > 100)
1181 left = 100;
1182 s->spdif_volume = (right << 8) | left;
1183 spin_lock_irqsave(&s->lock, flags);
1184 src_write(s, SRCREG_VOL_DAC2, DACVolTable[100 - left]);
1185 src_write(s, SRCREG_VOL_DAC2+1, DACVolTable[100 - right]);
1186 spin_unlock_irqrestore(&s->lock, flags);
1187 return 0;
1188
1189 case SOUND_MIXER_READ_PCM:
1190 return put_user(s->spdif_volume, (int __user *)arg);
1191 }
1192 return codec->mixer_ioctl(codec, cmd, arg);
1193 }
1194
1195 /* --------------------------------------------------------------------- */
1196
1197 /*
1198 * AC97 Mixer Register to Connections mapping of the Concert 97 board
1199 *
1200 * AC97_MASTER_VOL_STEREO Line Out
1201 * AC97_MASTER_VOL_MONO TAD Output
1202 * AC97_PCBEEP_VOL none
1203 * AC97_PHONE_VOL TAD Input (mono)
1204 * AC97_MIC_VOL MIC Input (mono)
1205 * AC97_LINEIN_VOL Line Input (stereo)
1206 * AC97_CD_VOL CD Input (stereo)
1207 * AC97_VIDEO_VOL none
1208 * AC97_AUX_VOL Aux Input (stereo)
1209 * AC97_PCMOUT_VOL Wave Output (stereo)
1210 */
1211
1212 static int es1371_open_mixdev(struct inode *inode, struct file *file)
1213 {
1214 int minor = iminor(inode);
1215 struct list_head *list;
1216 struct es1371_state *s;
1217
1218 for (list = devs.next; ; list = list->next) {
1219 if (list == &devs)
1220 return -ENODEV;
1221 s = list_entry(list, struct es1371_state, devs);
1222 if (s->codec->dev_mixer == minor)
1223 break;
1224 }
1225 VALIDATE_STATE(s);
1226 file->private_data = s;
1227 return nonseekable_open(inode, file);
1228 }
1229
1230 static int es1371_release_mixdev(struct inode *inode, struct file *file)
1231 {
1232 struct es1371_state *s = (struct es1371_state *)file->private_data;
1233
1234 VALIDATE_STATE(s);
1235 return 0;
1236 }
1237
1238 static int es1371_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1239 {
1240 struct es1371_state *s = (struct es1371_state *)file->private_data;
1241 struct ac97_codec *codec = s->codec;
1242
1243 return mixdev_ioctl(codec, cmd, arg);
1244 }
1245
1246 static /*const*/ struct file_operations es1371_mixer_fops = {
1247 .owner = THIS_MODULE,
1248 .llseek = no_llseek,
1249 .ioctl = es1371_ioctl_mixdev,
1250 .open = es1371_open_mixdev,
1251 .release = es1371_release_mixdev,
1252 };
1253
1254 /* --------------------------------------------------------------------- */
1255
1256 static int drain_dac1(struct es1371_state *s, int nonblock)
1257 {
1258 DECLARE_WAITQUEUE(wait, current);
1259 unsigned long flags;
1260 int count, tmo;
1261
1262 if (s->dma_dac1.mapped || !s->dma_dac1.ready)
1263 return 0;
1264 add_wait_queue(&s->dma_dac1.wait, &wait);
1265 for (;;) {
1266 __set_current_state(TASK_INTERRUPTIBLE);
1267 spin_lock_irqsave(&s->lock, flags);
1268 count = s->dma_dac1.count;
1269 spin_unlock_irqrestore(&s->lock, flags);
1270 if (count <= 0)
1271 break;
1272 if (signal_pending(current))
1273 break;
1274 if (nonblock) {
1275 remove_wait_queue(&s->dma_dac1.wait, &wait);
1276 set_current_state(TASK_RUNNING);
1277 return -EBUSY;
1278 }
1279 tmo = 3 * HZ * (count + s->dma_dac1.fragsize) / 2 / s->dac1rate;
1280 tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
1281 if (!schedule_timeout(tmo + 1))
1282 DBG(printk(KERN_DEBUG PFX "dac1 dma timed out??\n");)
1283 }
1284 remove_wait_queue(&s->dma_dac1.wait, &wait);
1285 set_current_state(TASK_RUNNING);
1286 if (signal_pending(current))
1287 return -ERESTARTSYS;
1288 return 0;
1289 }
1290
1291 static int drain_dac2(struct es1371_state *s, int nonblock)
1292 {
1293 DECLARE_WAITQUEUE(wait, current);
1294 unsigned long flags;
1295 int count, tmo;
1296
1297 if (s->dma_dac2.mapped || !s->dma_dac2.ready)
1298 return 0;
1299 add_wait_queue(&s->dma_dac2.wait, &wait);
1300 for (;;) {
1301 __set_current_state(TASK_UNINTERRUPTIBLE);
1302 spin_lock_irqsave(&s->lock, flags);
1303 count = s->dma_dac2.count;
1304 spin_unlock_irqrestore(&s->lock, flags);
1305 if (count <= 0)
1306 break;
1307 if (signal_pending(current))
1308 break;
1309 if (nonblock) {
1310 remove_wait_queue(&s->dma_dac2.wait, &wait);
1311 set_current_state(TASK_RUNNING);
1312 return -EBUSY;
1313 }
1314 tmo = 3 * HZ * (count + s->dma_dac2.fragsize) / 2 / s->dac2rate;
1315 tmo >>= sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
1316 if (!schedule_timeout(tmo + 1))
1317 DBG(printk(KERN_DEBUG PFX "dac2 dma timed out??\n");)
1318 }
1319 remove_wait_queue(&s->dma_dac2.wait, &wait);
1320 set_current_state(TASK_RUNNING);
1321 if (signal_pending(current))
1322 return -ERESTARTSYS;
1323 return 0;
1324 }
1325
1326 /* --------------------------------------------------------------------- */
1327
1328 static ssize_t es1371_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1329 {
1330 struct es1371_state *s = (struct es1371_state *)file->private_data;
1331 DECLARE_WAITQUEUE(wait, current);
1332 ssize_t ret = 0;
1333 unsigned long flags;
1334 unsigned swptr;
1335 int cnt;
1336
1337 VALIDATE_STATE(s);
1338 if (s->dma_adc.mapped)
1339 return -ENXIO;
1340 if (!access_ok(VERIFY_WRITE, buffer, count))
1341 return -EFAULT;
1342 down(&s->sem);
1343 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1344 goto out2;
1345
1346 add_wait_queue(&s->dma_adc.wait, &wait);
1347 while (count > 0) {
1348 spin_lock_irqsave(&s->lock, flags);
1349 swptr = s->dma_adc.swptr;
1350 cnt = s->dma_adc.dmasize-swptr;
1351 if (s->dma_adc.count < cnt)
1352 cnt = s->dma_adc.count;
1353 if (cnt <= 0)
1354 __set_current_state(TASK_INTERRUPTIBLE);
1355 spin_unlock_irqrestore(&s->lock, flags);
1356 if (cnt > count)
1357 cnt = count;
1358 if (cnt <= 0) {
1359 if (s->dma_adc.enabled)
1360 start_adc(s);
1361 if (file->f_flags & O_NONBLOCK) {
1362 if (!ret)
1363 ret = -EAGAIN;
1364 goto out;
1365 }
1366 up(&s->sem);
1367 schedule();
1368 if (signal_pending(current)) {
1369 if (!ret)
1370 ret = -ERESTARTSYS;
1371 goto out2;
1372 }
1373 down(&s->sem);
1374 if (s->dma_adc.mapped)
1375 {
1376 ret = -ENXIO;
1377 goto out;
1378 }
1379 continue;
1380 }
1381 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1382 if (!ret)
1383 ret = -EFAULT;
1384 goto out;
1385 }
1386 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1387 spin_lock_irqsave(&s->lock, flags);
1388 s->dma_adc.swptr = swptr;
1389 s->dma_adc.count -= cnt;
1390 spin_unlock_irqrestore(&s->lock, flags);
1391 count -= cnt;
1392 buffer += cnt;
1393 ret += cnt;
1394 if (s->dma_adc.enabled)
1395 start_adc(s);
1396 }
1397 out:
1398 up(&s->sem);
1399 out2:
1400 remove_wait_queue(&s->dma_adc.wait, &wait);
1401 set_current_state(TASK_RUNNING);
1402 return ret;
1403 }
1404
1405 static ssize_t es1371_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1406 {
1407 struct es1371_state *s = (struct es1371_state *)file->private_data;
1408 DECLARE_WAITQUEUE(wait, current);
1409 ssize_t ret;
1410 unsigned long flags;
1411 unsigned swptr;
1412 int cnt;
1413
1414 VALIDATE_STATE(s);
1415 if (s->dma_dac2.mapped)
1416 return -ENXIO;
1417 if (!access_ok(VERIFY_READ, buffer, count))
1418 return -EFAULT;
1419 down(&s->sem);
1420 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1421 goto out3;
1422 ret = 0;
1423 add_wait_queue(&s->dma_dac2.wait, &wait);
1424 while (count > 0) {
1425 spin_lock_irqsave(&s->lock, flags);
1426 if (s->dma_dac2.count < 0) {
1427 s->dma_dac2.count = 0;
1428 s->dma_dac2.swptr = s->dma_dac2.hwptr;
1429 }
1430 swptr = s->dma_dac2.swptr;
1431 cnt = s->dma_dac2.dmasize-swptr;
1432 if (s->dma_dac2.count + cnt > s->dma_dac2.dmasize)
1433 cnt = s->dma_dac2.dmasize - s->dma_dac2.count;
1434 if (cnt <= 0)
1435 __set_current_state(TASK_INTERRUPTIBLE);
1436 spin_unlock_irqrestore(&s->lock, flags);
1437 if (cnt > count)
1438 cnt = count;
1439 if (cnt <= 0) {
1440 if (s->dma_dac2.enabled)
1441 start_dac2(s);
1442 if (file->f_flags & O_NONBLOCK) {
1443 if (!ret)
1444 ret = -EAGAIN;
1445 goto out;
1446 }
1447 up(&s->sem);
1448 schedule();
1449 if (signal_pending(current)) {
1450 if (!ret)
1451 ret = -ERESTARTSYS;
1452 goto out2;
1453 }
1454 down(&s->sem);
1455 if (s->dma_dac2.mapped)
1456 {
1457 ret = -ENXIO;
1458 goto out;
1459 }
1460 continue;
1461 }
1462 if (copy_from_user(s->dma_dac2.rawbuf + swptr, buffer, cnt)) {
1463 if (!ret)
1464 ret = -EFAULT;
1465 goto out;
1466 }
1467 swptr = (swptr + cnt) % s->dma_dac2.dmasize;
1468 spin_lock_irqsave(&s->lock, flags);
1469 s->dma_dac2.swptr = swptr;
1470 s->dma_dac2.count += cnt;
1471 s->dma_dac2.endcleared = 0;
1472 spin_unlock_irqrestore(&s->lock, flags);
1473 count -= cnt;
1474 buffer += cnt;
1475 ret += cnt;
1476 if (s->dma_dac2.enabled)
1477 start_dac2(s);
1478 }
1479 out:
1480 up(&s->sem);
1481 out2:
1482 remove_wait_queue(&s->dma_dac2.wait, &wait);
1483 out3:
1484 set_current_state(TASK_RUNNING);
1485 return ret;
1486 }
1487
1488 /* No kernel lock - we have our own spinlock */
1489 static unsigned int es1371_poll(struct file *file, struct poll_table_struct *wait)
1490 {
1491 struct es1371_state *s = (struct es1371_state *)file->private_data;
1492 unsigned long flags;
1493 unsigned int mask = 0;
1494
1495 VALIDATE_STATE(s);
1496 if (file->f_mode & FMODE_WRITE) {
1497 if (!s->dma_dac2.ready && prog_dmabuf_dac2(s))
1498 return 0;
1499 poll_wait(file, &s->dma_dac2.wait, wait);
1500 }
1501 if (file->f_mode & FMODE_READ) {
1502 if (!s->dma_adc.ready && prog_dmabuf_adc(s))
1503 return 0;
1504 poll_wait(file, &s->dma_adc.wait, wait);
1505 }
1506 spin_lock_irqsave(&s->lock, flags);
1507 es1371_update_ptr(s);
1508 if (file->f_mode & FMODE_READ) {
1509 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1510 mask |= POLLIN | POLLRDNORM;
1511 }
1512 if (file->f_mode & FMODE_WRITE) {
1513 if (s->dma_dac2.mapped) {
1514 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1515 mask |= POLLOUT | POLLWRNORM;
1516 } else {
1517 if ((signed)s->dma_dac2.dmasize >= s->dma_dac2.count + (signed)s->dma_dac2.fragsize)
1518 mask |= POLLOUT | POLLWRNORM;
1519 }
1520 }
1521 spin_unlock_irqrestore(&s->lock, flags);
1522 return mask;
1523 }
1524
1525 static int es1371_mmap(struct file *file, struct vm_area_struct *vma)
1526 {
1527 struct es1371_state *s = (struct es1371_state *)file->private_data;
1528 struct dmabuf *db;
1529 int ret = 0;
1530 unsigned long size;
1531
1532 VALIDATE_STATE(s);
1533 lock_kernel();
1534 down(&s->sem);
1535
1536 if (vma->vm_flags & VM_WRITE) {
1537 if ((ret = prog_dmabuf_dac2(s)) != 0) {
1538 goto out;
1539 }
1540 db = &s->dma_dac2;
1541 } else if (vma->vm_flags & VM_READ) {
1542 if ((ret = prog_dmabuf_adc(s)) != 0) {
1543 goto out;
1544 }
1545 db = &s->dma_adc;
1546 } else {
1547 ret = -EINVAL;
1548 goto out;
1549 }
1550 if (vma->vm_pgoff != 0) {
1551 ret = -EINVAL;
1552 goto out;
1553 }
1554 size = vma->vm_end - vma->vm_start;
1555 if (size > (PAGE_SIZE << db->buforder)) {
1556 ret = -EINVAL;
1557 goto out;
1558 }
1559 if (remap_pfn_range(vma, vma->vm_start,
1560 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1561 size, vma->vm_page_prot)) {
1562 ret = -EAGAIN;
1563 goto out;
1564 }
1565 db->mapped = 1;
1566 out:
1567 up(&s->sem);
1568 unlock_kernel();
1569 return ret;
1570 }
1571
1572 static int es1371_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1573 {
1574 struct es1371_state *s = (struct es1371_state *)file->private_data;
1575 unsigned long flags;
1576 audio_buf_info abinfo;
1577 count_info cinfo;
1578 int count;
1579 int val, mapped, ret;
1580 void __user *argp = (void __user *)arg;
1581 int __user *p = argp;
1582
1583 VALIDATE_STATE(s);
1584 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac2.mapped) ||
1585 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1586 switch (cmd) {
1587 case OSS_GETVERSION:
1588 return put_user(SOUND_VERSION, p);
1589
1590 case SNDCTL_DSP_SYNC:
1591 if (file->f_mode & FMODE_WRITE)
1592 return drain_dac2(s, 0/*file->f_flags & O_NONBLOCK*/);
1593 return 0;
1594
1595 case SNDCTL_DSP_SETDUPLEX:
1596 return 0;
1597
1598 case SNDCTL_DSP_GETCAPS:
1599 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
1600
1601 case SNDCTL_DSP_RESET:
1602 if (file->f_mode & FMODE_WRITE) {
1603 stop_dac2(s);
1604 synchronize_irq(s->irq);
1605 s->dma_dac2.swptr = s->dma_dac2.hwptr = s->dma_dac2.count = s->dma_dac2.total_bytes = 0;
1606 }
1607 if (file->f_mode & FMODE_READ) {
1608 stop_adc(s);
1609 synchronize_irq(s->irq);
1610 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1611 }
1612 return 0;
1613
1614 case SNDCTL_DSP_SPEED:
1615 if (get_user(val, p))
1616 return -EFAULT;
1617 if (val >= 0) {
1618 if (file->f_mode & FMODE_READ) {
1619 stop_adc(s);
1620 s->dma_adc.ready = 0;
1621 set_adc_rate(s, val);
1622 }
1623 if (file->f_mode & FMODE_WRITE) {
1624 stop_dac2(s);
1625 s->dma_dac2.ready = 0;
1626 set_dac2_rate(s, val);
1627 }
1628 }
1629 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
1630
1631 case SNDCTL_DSP_STEREO:
1632 if (get_user(val, p))
1633 return -EFAULT;
1634 if (file->f_mode & FMODE_READ) {
1635 stop_adc(s);
1636 s->dma_adc.ready = 0;
1637 spin_lock_irqsave(&s->lock, flags);
1638 if (val)
1639 s->sctrl |= SCTRL_R1SMB;
1640 else
1641 s->sctrl &= ~SCTRL_R1SMB;
1642 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1643 spin_unlock_irqrestore(&s->lock, flags);
1644 }
1645 if (file->f_mode & FMODE_WRITE) {
1646 stop_dac2(s);
1647 s->dma_dac2.ready = 0;
1648 spin_lock_irqsave(&s->lock, flags);
1649 if (val)
1650 s->sctrl |= SCTRL_P2SMB;
1651 else
1652 s->sctrl &= ~SCTRL_P2SMB;
1653 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1654 spin_unlock_irqrestore(&s->lock, flags);
1655 }
1656 return 0;
1657
1658 case SNDCTL_DSP_CHANNELS:
1659 if (get_user(val, p))
1660 return -EFAULT;
1661 if (val != 0) {
1662 if (file->f_mode & FMODE_READ) {
1663 stop_adc(s);
1664 s->dma_adc.ready = 0;
1665 spin_lock_irqsave(&s->lock, flags);
1666 if (val >= 2)
1667 s->sctrl |= SCTRL_R1SMB;
1668 else
1669 s->sctrl &= ~SCTRL_R1SMB;
1670 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1671 spin_unlock_irqrestore(&s->lock, flags);
1672 }
1673 if (file->f_mode & FMODE_WRITE) {
1674 stop_dac2(s);
1675 s->dma_dac2.ready = 0;
1676 spin_lock_irqsave(&s->lock, flags);
1677 if (val >= 2)
1678 s->sctrl |= SCTRL_P2SMB;
1679 else
1680 s->sctrl &= ~SCTRL_P2SMB;
1681 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1682 spin_unlock_irqrestore(&s->lock, flags);
1683 }
1684 }
1685 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
1686
1687 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1688 return put_user(AFMT_S16_LE|AFMT_U8, p);
1689
1690 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1691 if (get_user(val, p))
1692 return -EFAULT;
1693 if (val != AFMT_QUERY) {
1694 if (file->f_mode & FMODE_READ) {
1695 stop_adc(s);
1696 s->dma_adc.ready = 0;
1697 spin_lock_irqsave(&s->lock, flags);
1698 if (val == AFMT_S16_LE)
1699 s->sctrl |= SCTRL_R1SEB;
1700 else
1701 s->sctrl &= ~SCTRL_R1SEB;
1702 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1703 spin_unlock_irqrestore(&s->lock, flags);
1704 }
1705 if (file->f_mode & FMODE_WRITE) {
1706 stop_dac2(s);
1707 s->dma_dac2.ready = 0;
1708 spin_lock_irqsave(&s->lock, flags);
1709 if (val == AFMT_S16_LE)
1710 s->sctrl |= SCTRL_P2SEB;
1711 else
1712 s->sctrl &= ~SCTRL_P2SEB;
1713 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1714 spin_unlock_irqrestore(&s->lock, flags);
1715 }
1716 }
1717 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ?
1718 AFMT_S16_LE : AFMT_U8, p);
1719
1720 case SNDCTL_DSP_POST:
1721 return 0;
1722
1723 case SNDCTL_DSP_GETTRIGGER:
1724 val = 0;
1725 if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN)
1726 val |= PCM_ENABLE_INPUT;
1727 if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC2_EN)
1728 val |= PCM_ENABLE_OUTPUT;
1729 return put_user(val, p);
1730
1731 case SNDCTL_DSP_SETTRIGGER:
1732 if (get_user(val, p))
1733 return -EFAULT;
1734 if (file->f_mode & FMODE_READ) {
1735 if (val & PCM_ENABLE_INPUT) {
1736 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1737 return ret;
1738 s->dma_adc.enabled = 1;
1739 start_adc(s);
1740 } else {
1741 s->dma_adc.enabled = 0;
1742 stop_adc(s);
1743 }
1744 }
1745 if (file->f_mode & FMODE_WRITE) {
1746 if (val & PCM_ENABLE_OUTPUT) {
1747 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1748 return ret;
1749 s->dma_dac2.enabled = 1;
1750 start_dac2(s);
1751 } else {
1752 s->dma_dac2.enabled = 0;
1753 stop_dac2(s);
1754 }
1755 }
1756 return 0;
1757
1758 case SNDCTL_DSP_GETOSPACE:
1759 if (!(file->f_mode & FMODE_WRITE))
1760 return -EINVAL;
1761 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1762 return val;
1763 spin_lock_irqsave(&s->lock, flags);
1764 es1371_update_ptr(s);
1765 abinfo.fragsize = s->dma_dac2.fragsize;
1766 count = s->dma_dac2.count;
1767 if (count < 0)
1768 count = 0;
1769 abinfo.bytes = s->dma_dac2.dmasize - count;
1770 abinfo.fragstotal = s->dma_dac2.numfrag;
1771 abinfo.fragments = abinfo.bytes >> s->dma_dac2.fragshift;
1772 spin_unlock_irqrestore(&s->lock, flags);
1773 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1774
1775 case SNDCTL_DSP_GETISPACE:
1776 if (!(file->f_mode & FMODE_READ))
1777 return -EINVAL;
1778 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1779 return val;
1780 spin_lock_irqsave(&s->lock, flags);
1781 es1371_update_ptr(s);
1782 abinfo.fragsize = s->dma_adc.fragsize;
1783 count = s->dma_adc.count;
1784 if (count < 0)
1785 count = 0;
1786 abinfo.bytes = count;
1787 abinfo.fragstotal = s->dma_adc.numfrag;
1788 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1789 spin_unlock_irqrestore(&s->lock, flags);
1790 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1791
1792 case SNDCTL_DSP_NONBLOCK:
1793 file->f_flags |= O_NONBLOCK;
1794 return 0;
1795
1796 case SNDCTL_DSP_GETODELAY:
1797 if (!(file->f_mode & FMODE_WRITE))
1798 return -EINVAL;
1799 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1800 return val;
1801 spin_lock_irqsave(&s->lock, flags);
1802 es1371_update_ptr(s);
1803 count = s->dma_dac2.count;
1804 spin_unlock_irqrestore(&s->lock, flags);
1805 if (count < 0)
1806 count = 0;
1807 return put_user(count, p);
1808
1809 case SNDCTL_DSP_GETIPTR:
1810 if (!(file->f_mode & FMODE_READ))
1811 return -EINVAL;
1812 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1813 return val;
1814 spin_lock_irqsave(&s->lock, flags);
1815 es1371_update_ptr(s);
1816 cinfo.bytes = s->dma_adc.total_bytes;
1817 count = s->dma_adc.count;
1818 if (count < 0)
1819 count = 0;
1820 cinfo.blocks = count >> s->dma_adc.fragshift;
1821 cinfo.ptr = s->dma_adc.hwptr;
1822 if (s->dma_adc.mapped)
1823 s->dma_adc.count &= s->dma_adc.fragsize-1;
1824 spin_unlock_irqrestore(&s->lock, flags);
1825 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1826 return -EFAULT;
1827 return 0;
1828
1829 case SNDCTL_DSP_GETOPTR:
1830 if (!(file->f_mode & FMODE_WRITE))
1831 return -EINVAL;
1832 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1833 return val;
1834 spin_lock_irqsave(&s->lock, flags);
1835 es1371_update_ptr(s);
1836 cinfo.bytes = s->dma_dac2.total_bytes;
1837 count = s->dma_dac2.count;
1838 if (count < 0)
1839 count = 0;
1840 cinfo.blocks = count >> s->dma_dac2.fragshift;
1841 cinfo.ptr = s->dma_dac2.hwptr;
1842 if (s->dma_dac2.mapped)
1843 s->dma_dac2.count &= s->dma_dac2.fragsize-1;
1844 spin_unlock_irqrestore(&s->lock, flags);
1845 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1846 return -EFAULT;
1847 return 0;
1848
1849 case SNDCTL_DSP_GETBLKSIZE:
1850 if (file->f_mode & FMODE_WRITE) {
1851 if ((val = prog_dmabuf_dac2(s)))
1852 return val;
1853 return put_user(s->dma_dac2.fragsize, p);
1854 }
1855 if ((val = prog_dmabuf_adc(s)))
1856 return val;
1857 return put_user(s->dma_adc.fragsize, p);
1858
1859 case SNDCTL_DSP_SETFRAGMENT:
1860 if (get_user(val, p))
1861 return -EFAULT;
1862 if (file->f_mode & FMODE_READ) {
1863 s->dma_adc.ossfragshift = val & 0xffff;
1864 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1865 if (s->dma_adc.ossfragshift < 4)
1866 s->dma_adc.ossfragshift = 4;
1867 if (s->dma_adc.ossfragshift > 15)
1868 s->dma_adc.ossfragshift = 15;
1869 if (s->dma_adc.ossmaxfrags < 4)
1870 s->dma_adc.ossmaxfrags = 4;
1871 }
1872 if (file->f_mode & FMODE_WRITE) {
1873 s->dma_dac2.ossfragshift = val & 0xffff;
1874 s->dma_dac2.ossmaxfrags = (val >> 16) & 0xffff;
1875 if (s->dma_dac2.ossfragshift < 4)
1876 s->dma_dac2.ossfragshift = 4;
1877 if (s->dma_dac2.ossfragshift > 15)
1878 s->dma_dac2.ossfragshift = 15;
1879 if (s->dma_dac2.ossmaxfrags < 4)
1880 s->dma_dac2.ossmaxfrags = 4;
1881 }
1882 return 0;
1883
1884 case SNDCTL_DSP_SUBDIVIDE:
1885 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1886 (file->f_mode & FMODE_WRITE && s->dma_dac2.subdivision))
1887 return -EINVAL;
1888 if (get_user(val, p))
1889 return -EFAULT;
1890 if (val != 1 && val != 2 && val != 4)
1891 return -EINVAL;
1892 if (file->f_mode & FMODE_READ)
1893 s->dma_adc.subdivision = val;
1894 if (file->f_mode & FMODE_WRITE)
1895 s->dma_dac2.subdivision = val;
1896 return 0;
1897
1898 case SOUND_PCM_READ_RATE:
1899 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
1900
1901 case SOUND_PCM_READ_CHANNELS:
1902 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
1903
1904 case SOUND_PCM_READ_BITS:
1905 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 16 : 8, p);
1906
1907 case SOUND_PCM_WRITE_FILTER:
1908 case SNDCTL_DSP_SETSYNCRO:
1909 case SOUND_PCM_READ_FILTER:
1910 return -EINVAL;
1911
1912 }
1913 return mixdev_ioctl(s->codec, cmd, arg);
1914 }
1915
1916 static int es1371_open(struct inode *inode, struct file *file)
1917 {
1918 int minor = iminor(inode);
1919 DECLARE_WAITQUEUE(wait, current);
1920 unsigned long flags;
1921 struct list_head *list;
1922 struct es1371_state *s;
1923
1924 for (list = devs.next; ; list = list->next) {
1925 if (list == &devs)
1926 return -ENODEV;
1927 s = list_entry(list, struct es1371_state, devs);
1928 if (!((s->dev_audio ^ minor) & ~0xf))
1929 break;
1930 }
1931 VALIDATE_STATE(s);
1932 file->private_data = s;
1933 /* wait for device to become free */
1934 down(&s->open_sem);
1935 while (s->open_mode & file->f_mode) {
1936 if (file->f_flags & O_NONBLOCK) {
1937 up(&s->open_sem);
1938 return -EBUSY;
1939 }
1940 add_wait_queue(&s->open_wait, &wait);
1941 __set_current_state(TASK_INTERRUPTIBLE);
1942 up(&s->open_sem);
1943 schedule();
1944 remove_wait_queue(&s->open_wait, &wait);
1945 set_current_state(TASK_RUNNING);
1946 if (signal_pending(current))
1947 return -ERESTARTSYS;
1948 down(&s->open_sem);
1949 }
1950 if (file->f_mode & FMODE_READ) {
1951 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1952 s->dma_adc.enabled = 1;
1953 set_adc_rate(s, 8000);
1954 }
1955 if (file->f_mode & FMODE_WRITE) {
1956 s->dma_dac2.ossfragshift = s->dma_dac2.ossmaxfrags = s->dma_dac2.subdivision = 0;
1957 s->dma_dac2.enabled = 1;
1958 set_dac2_rate(s, 8000);
1959 }
1960 spin_lock_irqsave(&s->lock, flags);
1961 if (file->f_mode & FMODE_READ) {
1962 s->sctrl &= ~SCTRL_R1FMT;
1963 if ((minor & 0xf) == SND_DEV_DSP16)
1964 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_R1FMT;
1965 else
1966 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_R1FMT;
1967 }
1968 if (file->f_mode & FMODE_WRITE) {
1969 s->sctrl &= ~SCTRL_P2FMT;
1970 if ((minor & 0xf) == SND_DEV_DSP16)
1971 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P2FMT;
1972 else
1973 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P2FMT;
1974 }
1975 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1976 spin_unlock_irqrestore(&s->lock, flags);
1977 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1978 up(&s->open_sem);
1979 init_MUTEX(&s->sem);
1980 return nonseekable_open(inode, file);
1981 }
1982
1983 static int es1371_release(struct inode *inode, struct file *file)
1984 {
1985 struct es1371_state *s = (struct es1371_state *)file->private_data;
1986
1987 VALIDATE_STATE(s);
1988 lock_kernel();
1989 if (file->f_mode & FMODE_WRITE)
1990 drain_dac2(s, file->f_flags & O_NONBLOCK);
1991 down(&s->open_sem);
1992 if (file->f_mode & FMODE_WRITE) {
1993 stop_dac2(s);
1994 dealloc_dmabuf(s, &s->dma_dac2);
1995 }
1996 if (file->f_mode & FMODE_READ) {
1997 stop_adc(s);
1998 dealloc_dmabuf(s, &s->dma_adc);
1999 }
2000 s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
2001 up(&s->open_sem);
2002 wake_up(&s->open_wait);
2003 unlock_kernel();
2004 return 0;
2005 }
2006
2007 static /*const*/ struct file_operations es1371_audio_fops = {
2008 .owner = THIS_MODULE,
2009 .llseek = no_llseek,
2010 .read = es1371_read,
2011 .write = es1371_write,
2012 .poll = es1371_poll,
2013 .ioctl = es1371_ioctl,
2014 .mmap = es1371_mmap,
2015 .open = es1371_open,
2016 .release = es1371_release,
2017 };
2018
2019 /* --------------------------------------------------------------------- */
2020
2021 static ssize_t es1371_write_dac(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2022 {
2023 struct es1371_state *s = (struct es1371_state *)file->private_data;
2024 DECLARE_WAITQUEUE(wait, current);
2025 ssize_t ret = 0;
2026 unsigned long flags;
2027 unsigned swptr;
2028 int cnt;
2029
2030 VALIDATE_STATE(s);
2031 if (s->dma_dac1.mapped)
2032 return -ENXIO;
2033 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2034 return ret;
2035 if (!access_ok(VERIFY_READ, buffer, count))
2036 return -EFAULT;
2037 add_wait_queue(&s->dma_dac1.wait, &wait);
2038 while (count > 0) {
2039 spin_lock_irqsave(&s->lock, flags);
2040 if (s->dma_dac1.count < 0) {
2041 s->dma_dac1.count = 0;
2042 s->dma_dac1.swptr = s->dma_dac1.hwptr;
2043 }
2044 swptr = s->dma_dac1.swptr;
2045 cnt = s->dma_dac1.dmasize-swptr;
2046 if (s->dma_dac1.count + cnt > s->dma_dac1.dmasize)
2047 cnt = s->dma_dac1.dmasize - s->dma_dac1.count;
2048 if (cnt <= 0)
2049 __set_current_state(TASK_INTERRUPTIBLE);
2050 spin_unlock_irqrestore(&s->lock, flags);
2051 if (cnt > count)
2052 cnt = count;
2053 if (cnt <= 0) {
2054 if (s->dma_dac1.enabled)
2055 start_dac1(s);
2056 if (file->f_flags & O_NONBLOCK) {
2057 if (!ret)
2058 ret = -EAGAIN;
2059 break;
2060 }
2061 schedule();
2062 if (signal_pending(current)) {
2063 if (!ret)
2064 ret = -ERESTARTSYS;
2065 break;
2066 }
2067 continue;
2068 }
2069 if (copy_from_user(s->dma_dac1.rawbuf + swptr, buffer, cnt)) {
2070 if (!ret)
2071 ret = -EFAULT;
2072 break;
2073 }
2074 swptr = (swptr + cnt) % s->dma_dac1.dmasize;
2075 spin_lock_irqsave(&s->lock, flags);
2076 s->dma_dac1.swptr = swptr;
2077 s->dma_dac1.count += cnt;
2078 s->dma_dac1.endcleared = 0;
2079 spin_unlock_irqrestore(&s->lock, flags);
2080 count -= cnt;
2081 buffer += cnt;
2082 ret += cnt;
2083 if (s->dma_dac1.enabled)
2084 start_dac1(s);
2085 }
2086 remove_wait_queue(&s->dma_dac1.wait, &wait);
2087 set_current_state(TASK_RUNNING);
2088 return ret;
2089 }
2090
2091 /* No kernel lock - we have our own spinlock */
2092 static unsigned int es1371_poll_dac(struct file *file, struct poll_table_struct *wait)
2093 {
2094 struct es1371_state *s = (struct es1371_state *)file->private_data;
2095 unsigned long flags;
2096 unsigned int mask = 0;
2097
2098 VALIDATE_STATE(s);
2099 if (!s->dma_dac1.ready && prog_dmabuf_dac1(s))
2100 return 0;
2101 poll_wait(file, &s->dma_dac1.wait, wait);
2102 spin_lock_irqsave(&s->lock, flags);
2103 es1371_update_ptr(s);
2104 if (s->dma_dac1.mapped) {
2105 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
2106 mask |= POLLOUT | POLLWRNORM;
2107 } else {
2108 if ((signed)s->dma_dac1.dmasize >= s->dma_dac1.count + (signed)s->dma_dac1.fragsize)
2109 mask |= POLLOUT | POLLWRNORM;
2110 }
2111 spin_unlock_irqrestore(&s->lock, flags);
2112 return mask;
2113 }
2114
2115 static int es1371_mmap_dac(struct file *file, struct vm_area_struct *vma)
2116 {
2117 struct es1371_state *s = (struct es1371_state *)file->private_data;
2118 int ret;
2119 unsigned long size;
2120
2121 VALIDATE_STATE(s);
2122 if (!(vma->vm_flags & VM_WRITE))
2123 return -EINVAL;
2124 lock_kernel();
2125 if ((ret = prog_dmabuf_dac1(s)) != 0)
2126 goto out;
2127 ret = -EINVAL;
2128 if (vma->vm_pgoff != 0)
2129 goto out;
2130 size = vma->vm_end - vma->vm_start;
2131 if (size > (PAGE_SIZE << s->dma_dac1.buforder))
2132 goto out;
2133 ret = -EAGAIN;
2134 if (remap_pfn_range(vma, vma->vm_start,
2135 virt_to_phys(s->dma_dac1.rawbuf) >> PAGE_SHIFT,
2136 size, vma->vm_page_prot))
2137 goto out;
2138 s->dma_dac1.mapped = 1;
2139 ret = 0;
2140 out:
2141 unlock_kernel();
2142 return ret;
2143 }
2144
2145 static int es1371_ioctl_dac(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2146 {
2147 struct es1371_state *s = (struct es1371_state *)file->private_data;
2148 unsigned long flags;
2149 audio_buf_info abinfo;
2150 count_info cinfo;
2151 int count;
2152 int val, ret;
2153 int __user *p = (int __user *)arg;
2154
2155 VALIDATE_STATE(s);
2156 switch (cmd) {
2157 case OSS_GETVERSION:
2158 return put_user(SOUND_VERSION, p);
2159
2160 case SNDCTL_DSP_SYNC:
2161 return drain_dac1(s, 0/*file->f_flags & O_NONBLOCK*/);
2162
2163 case SNDCTL_DSP_SETDUPLEX:
2164 return -EINVAL;
2165
2166 case SNDCTL_DSP_GETCAPS:
2167 return put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
2168
2169 case SNDCTL_DSP_RESET:
2170 stop_dac1(s);
2171 synchronize_irq(s->irq);
2172 s->dma_dac1.swptr = s->dma_dac1.hwptr = s->dma_dac1.count = s->dma_dac1.total_bytes = 0;
2173 return 0;
2174
2175 case SNDCTL_DSP_SPEED:
2176 if (get_user(val, p))
2177 return -EFAULT;
2178 if (val >= 0) {
2179 stop_dac1(s);
2180 s->dma_dac1.ready = 0;
2181 set_dac1_rate(s, val);
2182 }
2183 return put_user(s->dac1rate, p);
2184
2185 case SNDCTL_DSP_STEREO:
2186 if (get_user(val, p))
2187 return -EFAULT;
2188 stop_dac1(s);
2189 s->dma_dac1.ready = 0;
2190 spin_lock_irqsave(&s->lock, flags);
2191 if (val)
2192 s->sctrl |= SCTRL_P1SMB;
2193 else
2194 s->sctrl &= ~SCTRL_P1SMB;
2195 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2196 spin_unlock_irqrestore(&s->lock, flags);
2197 return 0;
2198
2199 case SNDCTL_DSP_CHANNELS:
2200 if (get_user(val, p))
2201 return -EFAULT;
2202 if (val != 0) {
2203 stop_dac1(s);
2204 s->dma_dac1.ready = 0;
2205 spin_lock_irqsave(&s->lock, flags);
2206 if (val >= 2)
2207 s->sctrl |= SCTRL_P1SMB;
2208 else
2209 s->sctrl &= ~SCTRL_P1SMB;
2210 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2211 spin_unlock_irqrestore(&s->lock, flags);
2212 }
2213 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
2214
2215 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2216 return put_user(AFMT_S16_LE|AFMT_U8, p);
2217
2218 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2219 if (get_user(val, p))
2220 return -EFAULT;
2221 if (val != AFMT_QUERY) {
2222 stop_dac1(s);
2223 s->dma_dac1.ready = 0;
2224 spin_lock_irqsave(&s->lock, flags);
2225 if (val == AFMT_S16_LE)
2226 s->sctrl |= SCTRL_P1SEB;
2227 else
2228 s->sctrl &= ~SCTRL_P1SEB;
2229 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2230 spin_unlock_irqrestore(&s->lock, flags);
2231 }
2232 return put_user((s->sctrl & SCTRL_P1SEB) ? AFMT_S16_LE : AFMT_U8, p);
2233
2234 case SNDCTL_DSP_POST:
2235 return 0;
2236
2237 case SNDCTL_DSP_GETTRIGGER:
2238 return put_user((s->ctrl & CTRL_DAC1_EN) ? PCM_ENABLE_OUTPUT : 0, p);
2239
2240 case SNDCTL_DSP_SETTRIGGER:
2241 if (get_user(val, p))
2242 return -EFAULT;
2243 if (val & PCM_ENABLE_OUTPUT) {
2244 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2245 return ret;
2246 s->dma_dac1.enabled = 1;
2247 start_dac1(s);
2248 } else {
2249 s->dma_dac1.enabled = 0;
2250 stop_dac1(s);
2251 }
2252 return 0;
2253
2254 case SNDCTL_DSP_GETOSPACE:
2255 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2256 return val;
2257 spin_lock_irqsave(&s->lock, flags);
2258 es1371_update_ptr(s);
2259 abinfo.fragsize = s->dma_dac1.fragsize;
2260 count = s->dma_dac1.count;
2261 if (count < 0)
2262 count = 0;
2263 abinfo.bytes = s->dma_dac1.dmasize - count;
2264 abinfo.fragstotal = s->dma_dac1.numfrag;
2265 abinfo.fragments = abinfo.bytes >> s->dma_dac1.fragshift;
2266 spin_unlock_irqrestore(&s->lock, flags);
2267 return copy_to_user((void __user *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2268
2269 case SNDCTL_DSP_NONBLOCK:
2270 file->f_flags |= O_NONBLOCK;
2271 return 0;
2272
2273 case SNDCTL_DSP_GETODELAY:
2274 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2275 return val;
2276 spin_lock_irqsave(&s->lock, flags);
2277 es1371_update_ptr(s);
2278 count = s->dma_dac1.count;
2279 spin_unlock_irqrestore(&s->lock, flags);
2280 if (count < 0)
2281 count = 0;
2282 return put_user(count, p);
2283
2284 case SNDCTL_DSP_GETOPTR:
2285 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2286 return val;
2287 spin_lock_irqsave(&s->lock, flags);
2288 es1371_update_ptr(s);
2289 cinfo.bytes = s->dma_dac1.total_bytes;
2290 count = s->dma_dac1.count;
2291 if (count < 0)
2292 count = 0;
2293 cinfo.blocks = count >> s->dma_dac1.fragshift;
2294 cinfo.ptr = s->dma_dac1.hwptr;
2295 if (s->dma_dac1.mapped)
2296 s->dma_dac1.count &= s->dma_dac1.fragsize-1;
2297 spin_unlock_irqrestore(&s->lock, flags);
2298 if (copy_to_user((void __user *)arg, &cinfo, sizeof(cinfo)))
2299 return -EFAULT;
2300 return 0;
2301
2302 case SNDCTL_DSP_GETBLKSIZE:
2303 if ((val = prog_dmabuf_dac1(s)))
2304 return val;
2305 return put_user(s->dma_dac1.fragsize, p);
2306
2307 case SNDCTL_DSP_SETFRAGMENT:
2308 if (get_user(val, p))
2309 return -EFAULT;
2310 s->dma_dac1.ossfragshift = val & 0xffff;
2311 s->dma_dac1.ossmaxfrags = (val >> 16) & 0xffff;
2312 if (s->dma_dac1.ossfragshift < 4)
2313 s->dma_dac1.ossfragshift = 4;
2314 if (s->dma_dac1.ossfragshift > 15)
2315 s->dma_dac1.ossfragshift = 15;
2316 if (s->dma_dac1.ossmaxfrags < 4)
2317 s->dma_dac1.ossmaxfrags = 4;
2318 return 0;
2319
2320 case SNDCTL_DSP_SUBDIVIDE:
2321 if (s->dma_dac1.subdivision)
2322 return -EINVAL;
2323 if (get_user(val, p))
2324 return -EFAULT;
2325 if (val != 1 && val != 2 && val != 4)
2326 return -EINVAL;
2327 s->dma_dac1.subdivision = val;
2328 return 0;
2329
2330 case SOUND_PCM_READ_RATE:
2331 return put_user(s->dac1rate, p);
2332
2333 case SOUND_PCM_READ_CHANNELS:
2334 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
2335
2336 case SOUND_PCM_READ_BITS:
2337 return put_user((s->sctrl & SCTRL_P1SEB) ? 16 : 8, p);
2338
2339 case SOUND_PCM_WRITE_FILTER:
2340 case SNDCTL_DSP_SETSYNCRO:
2341 case SOUND_PCM_READ_FILTER:
2342 return -EINVAL;
2343
2344 }
2345 return mixdev_ioctl(s->codec, cmd, arg);
2346 }
2347
2348 static int es1371_open_dac(struct inode *inode, struct file *file)
2349 {
2350 int minor = iminor(inode);
2351 DECLARE_WAITQUEUE(wait, current);
2352 unsigned long flags;
2353 struct list_head *list;
2354 struct es1371_state *s;
2355
2356 for (list = devs.next; ; list = list->next) {
2357 if (list == &devs)
2358 return -ENODEV;
2359 s = list_entry(list, struct es1371_state, devs);
2360 if (!((s->dev_dac ^ minor) & ~0xf))
2361 break;
2362 }
2363 VALIDATE_STATE(s);
2364 /* we allow opening with O_RDWR, most programs do it although they will only write */
2365 #if 0
2366 if (file->f_mode & FMODE_READ)
2367 return -EPERM;
2368 #endif
2369 if (!(file->f_mode & FMODE_WRITE))
2370 return -EINVAL;
2371 file->private_data = s;
2372 /* wait for device to become free */
2373 down(&s->open_sem);
2374 while (s->open_mode & FMODE_DAC) {
2375 if (file->f_flags & O_NONBLOCK) {
2376 up(&s->open_sem);
2377 return -EBUSY;
2378 }
2379 add_wait_queue(&s->open_wait, &wait);
2380 __set_current_state(TASK_INTERRUPTIBLE);
2381 up(&s->open_sem);
2382 schedule();
2383 remove_wait_queue(&s->open_wait, &wait);
2384 set_current_state(TASK_RUNNING);
2385 if (signal_pending(current))
2386 return -ERESTARTSYS;
2387 down(&s->open_sem);
2388 }
2389 s->dma_dac1.ossfragshift = s->dma_dac1.ossmaxfrags = s->dma_dac1.subdivision = 0;
2390 s->dma_dac1.enabled = 1;
2391 set_dac1_rate(s, 8000);
2392 spin_lock_irqsave(&s->lock, flags);
2393 s->sctrl &= ~SCTRL_P1FMT;
2394 if ((minor & 0xf) == SND_DEV_DSP16)
2395 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P1FMT;
2396 else
2397 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P1FMT;
2398 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2399 spin_unlock_irqrestore(&s->lock, flags);
2400 s->open_mode |= FMODE_DAC;
2401 up(&s->open_sem);
2402 return nonseekable_open(inode, file);
2403 }
2404
2405 static int es1371_release_dac(struct inode *inode, struct file *file)
2406 {
2407 struct es1371_state *s = (struct es1371_state *)file->private_data;
2408
2409 VALIDATE_STATE(s);
2410 lock_kernel();
2411 drain_dac1(s, file->f_flags & O_NONBLOCK);
2412 down(&s->open_sem);
2413 stop_dac1(s);
2414 dealloc_dmabuf(s, &s->dma_dac1);
2415 s->open_mode &= ~FMODE_DAC;
2416 up(&s->open_sem);
2417 wake_up(&s->open_wait);
2418 unlock_kernel();
2419 return 0;
2420 }
2421
2422 static /*const*/ struct file_operations es1371_dac_fops = {
2423 .owner = THIS_MODULE,
2424 .llseek = no_llseek,
2425 .write = es1371_write_dac,
2426 .poll = es1371_poll_dac,
2427 .ioctl = es1371_ioctl_dac,
2428 .mmap = es1371_mmap_dac,
2429 .open = es1371_open_dac,
2430 .release = es1371_release_dac,
2431 };
2432
2433 /* --------------------------------------------------------------------- */
2434
2435 static ssize_t es1371_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
2436 {
2437 struct es1371_state *s = (struct es1371_state *)file->private_data;
2438 DECLARE_WAITQUEUE(wait, current);
2439 ssize_t ret;
2440 unsigned long flags;
2441 unsigned ptr;
2442 int cnt;
2443
2444 VALIDATE_STATE(s);
2445 if (!access_ok(VERIFY_WRITE, buffer, count))
2446 return -EFAULT;
2447 if (count == 0)
2448 return 0;
2449 ret = 0;
2450 add_wait_queue(&s->midi.iwait, &wait);
2451 while (count > 0) {
2452 spin_lock_irqsave(&s->lock, flags);
2453 ptr = s->midi.ird;
2454 cnt = MIDIINBUF - ptr;
2455 if (s->midi.icnt < cnt)
2456 cnt = s->midi.icnt;
2457 if (cnt <= 0)
2458 __set_current_state(TASK_INTERRUPTIBLE);
2459 spin_unlock_irqrestore(&s->lock, flags);
2460 if (cnt > count)
2461 cnt = count;
2462 if (cnt <= 0) {
2463 if (file->f_flags & O_NONBLOCK) {
2464 if (!ret)
2465 ret = -EAGAIN;
2466 break;
2467 }
2468 schedule();
2469 if (signal_pending(current)) {
2470 if (!ret)
2471 ret = -ERESTARTSYS;
2472 break;
2473 }
2474 continue;
2475 }
2476 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
2477 if (!ret)
2478 ret = -EFAULT;
2479 break;
2480 }
2481 ptr = (ptr + cnt) % MIDIINBUF;
2482 spin_lock_irqsave(&s->lock, flags);
2483 s->midi.ird = ptr;
2484 s->midi.icnt -= cnt;
2485 spin_unlock_irqrestore(&s->lock, flags);
2486 count -= cnt;
2487 buffer += cnt;
2488 ret += cnt;
2489 break;
2490 }
2491 __set_current_state(TASK_RUNNING);
2492 remove_wait_queue(&s->midi.iwait, &wait);
2493 return ret;
2494 }
2495
2496 static ssize_t es1371_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2497 {
2498 struct es1371_state *s = (struct es1371_state *)file->private_data;
2499 DECLARE_WAITQUEUE(wait, current);
2500 ssize_t ret;
2501 unsigned long flags;
2502 unsigned ptr;
2503 int cnt;
2504
2505 VALIDATE_STATE(s);
2506 if (!access_ok(VERIFY_READ, buffer, count))
2507 return -EFAULT;
2508 if (count == 0)
2509 return 0;
2510 ret = 0;
2511 add_wait_queue(&s->midi.owait, &wait);
2512 while (count > 0) {
2513 spin_lock_irqsave(&s->lock, flags);
2514 ptr = s->midi.owr;
2515 cnt = MIDIOUTBUF - ptr;
2516 if (s->midi.ocnt + cnt > MIDIOUTBUF)
2517 cnt = MIDIOUTBUF - s->midi.ocnt;
2518 if (cnt <= 0) {
2519 __set_current_state(TASK_INTERRUPTIBLE);
2520 es1371_handle_midi(s);
2521 }
2522 spin_unlock_irqrestore(&s->lock, flags);
2523 if (cnt > count)
2524 cnt = count;
2525 if (cnt <= 0) {
2526 if (file->f_flags & O_NONBLOCK) {
2527 if (!ret)
2528 ret = -EAGAIN;
2529 break;
2530 }
2531 schedule();
2532 if (signal_pending(current)) {
2533 if (!ret)
2534 ret = -ERESTARTSYS;
2535 break;
2536 }
2537 continue;
2538 }
2539 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
2540 if (!ret)
2541 ret = -EFAULT;
2542 break;
2543 }
2544 ptr = (ptr + cnt) % MIDIOUTBUF;
2545 spin_lock_irqsave(&s->lock, flags);
2546 s->midi.owr = ptr;
2547 s->midi.ocnt += cnt;
2548 spin_unlock_irqrestore(&s->lock, flags);
2549 count -= cnt;
2550 buffer += cnt;
2551 ret += cnt;
2552 spin_lock_irqsave(&s->lock, flags);
2553 es1371_handle_midi(s);
2554 spin_unlock_irqrestore(&s->lock, flags);
2555 }
2556 __set_current_state(TASK_RUNNING);
2557 remove_wait_queue(&s->midi.owait, &wait);
2558 return ret;
2559 }
2560
2561 /* No kernel lock - we have our own spinlock */
2562 static unsigned int es1371_midi_poll(struct file *file, struct poll_table_struct *wait)
2563 {
2564 struct es1371_state *s = (struct es1371_state *)file->private_data;
2565 unsigned long flags;
2566 unsigned int mask = 0;
2567
2568 VALIDATE_STATE(s);
2569 if (file->f_mode & FMODE_WRITE)
2570 poll_wait(file, &s->midi.owait, wait);
2571 if (file->f_mode & FMODE_READ)
2572 poll_wait(file, &s->midi.iwait, wait);
2573 spin_lock_irqsave(&s->lock, flags);
2574 if (file->f_mode & FMODE_READ) {
2575 if (s->midi.icnt > 0)
2576 mask |= POLLIN | POLLRDNORM;
2577 }
2578 if (file->f_mode & FMODE_WRITE) {
2579 if (s->midi.ocnt < MIDIOUTBUF)
2580 mask |= POLLOUT | POLLWRNORM;
2581 }
2582 spin_unlock_irqrestore(&s->lock, flags);
2583 return mask;
2584 }
2585
2586 static int es1371_midi_open(struct inode *inode, struct file *file)
2587 {
2588 int minor = iminor(inode);
2589 DECLARE_WAITQUEUE(wait, current);
2590 unsigned long flags;
2591 struct list_head *list;
2592 struct es1371_state *s;
2593
2594 for (list = devs.next; ; list = list->next) {
2595 if (list == &devs)
2596 return -ENODEV;
2597 s = list_entry(list, struct es1371_state, devs);
2598 if (s->dev_midi == minor)
2599 break;
2600 }
2601 VALIDATE_STATE(s);
2602 file->private_data = s;
2603 /* wait for device to become free */
2604 down(&s->open_sem);
2605 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
2606 if (file->f_flags & O_NONBLOCK) {
2607 up(&s->open_sem);
2608 return -EBUSY;
2609 }
2610 add_wait_queue(&s->open_wait, &wait);
2611 __set_current_state(TASK_INTERRUPTIBLE);
2612 up(&s->open_sem);
2613 schedule();
2614 remove_wait_queue(&s->open_wait, &wait);
2615 set_current_state(TASK_RUNNING);
2616 if (signal_pending(current))
2617 return -ERESTARTSYS;
2618 down(&s->open_sem);
2619 }
2620 spin_lock_irqsave(&s->lock, flags);
2621 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2622 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2623 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2624 outb(UCTRL_CNTRL_SWR, s->io+ES1371_REG_UART_CONTROL);
2625 outb(0, s->io+ES1371_REG_UART_CONTROL);
2626 outb(0, s->io+ES1371_REG_UART_TEST);
2627 }
2628 if (file->f_mode & FMODE_READ) {
2629 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2630 }
2631 if (file->f_mode & FMODE_WRITE) {
2632 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2633 }
2634 s->ctrl |= CTRL_UART_EN;
2635 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2636 es1371_handle_midi(s);
2637 spin_unlock_irqrestore(&s->lock, flags);
2638 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
2639 up(&s->open_sem);
2640 return nonseekable_open(inode, file);
2641 }
2642
2643 static int es1371_midi_release(struct inode *inode, struct file *file)
2644 {
2645 struct es1371_state *s = (struct es1371_state *)file->private_data;
2646 DECLARE_WAITQUEUE(wait, current);
2647 unsigned long flags;
2648 unsigned count, tmo;
2649
2650 VALIDATE_STATE(s);
2651 lock_kernel();
2652 if (file->f_mode & FMODE_WRITE) {
2653 add_wait_queue(&s->midi.owait, &wait);
2654 for (;;) {
2655 __set_current_state(TASK_INTERRUPTIBLE);
2656 spin_lock_irqsave(&s->lock, flags);
2657 count = s->midi.ocnt;
2658 spin_unlock_irqrestore(&s->lock, flags);
2659 if (count <= 0)
2660 break;
2661 if (signal_pending(current))
2662 break;
2663 if (file->f_flags & O_NONBLOCK)
2664 break;
2665 tmo = (count * HZ) / 3100;
2666 if (!schedule_timeout(tmo ? : 1) && tmo)
2667 printk(KERN_DEBUG PFX "midi timed out??\n");
2668 }
2669 remove_wait_queue(&s->midi.owait, &wait);
2670 set_current_state(TASK_RUNNING);
2671 }
2672 down(&s->open_sem);
2673 s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
2674 spin_lock_irqsave(&s->lock, flags);
2675 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2676 s->ctrl &= ~CTRL_UART_EN;
2677 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2678 }
2679 spin_unlock_irqrestore(&s->lock, flags);
2680 up(&s->open_sem);
2681 wake_up(&s->open_wait);
2682 unlock_kernel();
2683 return 0;
2684 }
2685
2686 static /*const*/ struct file_operations es1371_midi_fops = {
2687 .owner = THIS_MODULE,
2688 .llseek = no_llseek,
2689 .read = es1371_midi_read,
2690 .write = es1371_midi_write,
2691 .poll = es1371_midi_poll,
2692 .open = es1371_midi_open,
2693 .release = es1371_midi_release,
2694 };
2695
2696 /* --------------------------------------------------------------------- */
2697
2698 /*
2699 * for debugging purposes, we'll create a proc device that dumps the
2700 * CODEC chipstate
2701 */
2702
2703 #ifdef ES1371_DEBUG
2704 static int proc_es1371_dump (char *buf, char **start, off_t fpos, int length, int *eof, void *data)
2705 {
2706 struct es1371_state *s;
2707 int cnt, len = 0;
2708
2709 if (list_empty(&devs))
2710 return 0;
2711 s = list_entry(devs.next, struct es1371_state, devs);
2712 /* print out header */
2713 len += sprintf(buf + len, "\t\tCreative ES137x Debug Dump-o-matic\n");
2714
2715 /* print out CODEC state */
2716 len += sprintf (buf + len, "AC97 CODEC state\n");
2717 for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
2718 len+= sprintf (buf + len, "reg:0x%02x val:0x%04x\n", cnt, rdcodec(s->codec, cnt));
2719
2720 if (fpos >=len){
2721 *start = buf;
2722 *eof =1;
2723 return 0;
2724 }
2725 *start = buf + fpos;
2726 if ((len -= fpos) > length)
2727 return length;
2728 *eof =1;
2729 return len;
2730
2731 }
2732 #endif /* ES1371_DEBUG */
2733
2734 /* --------------------------------------------------------------------- */
2735
2736 /* maximum number of devices; only used for command line params */
2737 #define NR_DEVICE 5
2738
2739 static int spdif[NR_DEVICE];
2740 static int nomix[NR_DEVICE];
2741 static int amplifier[NR_DEVICE];
2742
2743 static unsigned int devindex;
2744
2745 module_param_array(spdif, bool, NULL, 0);
2746 MODULE_PARM_DESC(spdif, "if 1 the output is in S/PDIF digital mode");
2747 module_param_array(nomix, bool, NULL, 0);
2748 MODULE_PARM_DESC(nomix, "if 1 no analog audio is mixed to the digital output");
2749 module_param_array(amplifier, bool, NULL, 0);
2750 MODULE_PARM_DESC(amplifier, "Set to 1 if the machine needs the amp control enabling (many laptops)");
2751
2752 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2753 MODULE_DESCRIPTION("ES1371 AudioPCI97 Driver");
2754 MODULE_LICENSE("GPL");
2755
2756
2757 /* --------------------------------------------------------------------- */
2758
2759 static struct initvol {
2760 int mixch;
2761 int vol;
2762 } initvol[] __devinitdata = {
2763 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2764 { SOUND_MIXER_WRITE_CD, 0x4040 },
2765 { MIXER_WRITE(SOUND_MIXER_VIDEO), 0x4040 },
2766 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2767 { SOUND_MIXER_WRITE_PCM, 0x4040 },
2768 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2769 { MIXER_WRITE(SOUND_MIXER_PHONEOUT), 0x4040 },
2770 { SOUND_MIXER_WRITE_OGAIN, 0x4040 },
2771 { MIXER_WRITE(SOUND_MIXER_PHONEIN), 0x4040 },
2772 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
2773 { SOUND_MIXER_WRITE_MIC, 0x4040 },
2774 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2775 { SOUND_MIXER_WRITE_IGAIN, 0x4040 }
2776 };
2777
2778 static struct
2779 {
2780 short svid, sdid;
2781 } amplifier_needed[] =
2782 {
2783 { 0x107B, 0x2150 }, /* Gateway Solo 2150 */
2784 { 0x13BD, 0x100C }, /* Mebius PC-MJ100V */
2785 { 0x1102, 0x5938 }, /* Targa Xtender 300 */
2786 { 0x1102, 0x8938 }, /* IPC notebook */
2787 { PCI_ANY_ID, PCI_ANY_ID }
2788 };
2789
2790 static int __devinit es1371_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2791 {
2792 struct es1371_state *s;
2793 struct gameport *gp;
2794 mm_segment_t fs;
2795 int i, gpio, val, res = -1;
2796 int idx;
2797 unsigned long tmo;
2798 signed long tmo2;
2799 unsigned int cssr;
2800
2801 if ((res=pci_enable_device(pcidev)))
2802 return res;
2803
2804 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO))
2805 return -ENODEV;
2806 if (pcidev->irq == 0)
2807 return -ENODEV;
2808 i = pci_set_dma_mask(pcidev, DMA_32BIT_MASK);
2809 if (i) {
2810 printk(KERN_WARNING "es1371: architecture does not support 32bit PCI busmaster DMA\n");
2811 return i;
2812 }
2813 if (!(s = kmalloc(sizeof(struct es1371_state), GFP_KERNEL))) {
2814 printk(KERN_WARNING PFX "out of memory\n");
2815 return -ENOMEM;
2816 }
2817 memset(s, 0, sizeof(struct es1371_state));
2818
2819 s->codec = ac97_alloc_codec();
2820 if(s->codec == NULL)
2821 goto err_codec;
2822
2823 init_waitqueue_head(&s->dma_adc.wait);
2824 init_waitqueue_head(&s->dma_dac1.wait);
2825 init_waitqueue_head(&s->dma_dac2.wait);
2826 init_waitqueue_head(&s->open_wait);
2827 init_waitqueue_head(&s->midi.iwait);
2828 init_waitqueue_head(&s->midi.owait);
2829 init_MUTEX(&s->open_sem);
2830 spin_lock_init(&s->lock);
2831 s->magic = ES1371_MAGIC;
2832 s->dev = pcidev;
2833 s->io = pci_resource_start(pcidev, 0);
2834 s->irq = pcidev->irq;
2835 s->vendor = pcidev->vendor;
2836 s->device = pcidev->device;
2837 pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
2838 s->codec->private_data = s;
2839 s->codec->id = 0;
2840 s->codec->codec_read = rdcodec;
2841 s->codec->codec_write = wrcodec;
2842 printk(KERN_INFO PFX "found chip, vendor id 0x%04x device id 0x%04x revision 0x%02x\n",
2843 s->vendor, s->device, s->rev);
2844 if (!request_region(s->io, ES1371_EXTENT, "es1371")) {
2845 printk(KERN_ERR PFX "io ports %#lx-%#lx in use\n", s->io, s->io+ES1371_EXTENT-1);
2846 res = -EBUSY;
2847 goto err_region;
2848 }
2849 if ((res=request_irq(s->irq, es1371_interrupt, SA_SHIRQ, "es1371",s))) {
2850 printk(KERN_ERR PFX "irq %u in use\n", s->irq);
2851 goto err_irq;
2852 }
2853 printk(KERN_INFO PFX "found es1371 rev %d at io %#lx irq %u\n",
2854 s->rev, s->io, s->irq);
2855 /* register devices */
2856 if ((res=(s->dev_audio = register_sound_dsp(&es1371_audio_fops,-1)))<0)
2857 goto err_dev1;
2858 if ((res=(s->codec->dev_mixer = register_sound_mixer(&es1371_mixer_fops, -1))) < 0)
2859 goto err_dev2;
2860 if ((res=(s->dev_dac = register_sound_dsp(&es1371_dac_fops, -1))) < 0)
2861 goto err_dev3;
2862 if ((res=(s->dev_midi = register_sound_midi(&es1371_midi_fops, -1)))<0 )
2863 goto err_dev4;
2864 #ifdef ES1371_DEBUG
2865 /* initialize the debug proc device */
2866 s->ps = create_proc_read_entry("es1371",0,NULL,proc_es1371_dump,NULL);
2867 #endif /* ES1371_DEBUG */
2868
2869 /* initialize codec registers */
2870 s->ctrl = 0;
2871
2872 /* Check amplifier requirements */
2873
2874 if (amplifier[devindex])
2875 s->ctrl |= CTRL_GPIO_OUT0;
2876 else for(idx = 0; amplifier_needed[idx].svid != PCI_ANY_ID; idx++)
2877 {
2878 if(pcidev->subsystem_vendor == amplifier_needed[idx].svid &&
2879 pcidev->subsystem_device == amplifier_needed[idx].sdid)
2880 {
2881 s->ctrl |= CTRL_GPIO_OUT0; /* turn internal amplifier on */
2882 printk(KERN_INFO PFX "Enabling internal amplifier.\n");
2883 }
2884 }
2885
2886 for (gpio = 0x218; gpio >= 0x200; gpio -= 0x08)
2887 if (request_region(gpio, JOY_EXTENT, "es1371"))
2888 break;
2889
2890 if (gpio < 0x200) {
2891 printk(KERN_ERR PFX "no free joystick address found\n");
2892 } else if (!(s->gameport = gp = gameport_allocate_port())) {
2893 printk(KERN_ERR PFX "can not allocate memory for gameport\n");
2894 release_region(gpio, JOY_EXTENT);
2895 } else {
2896 gameport_set_name(gp, "ESS1371 Gameport");
2897 gameport_set_phys(gp, "isa%04x/gameport0", gpio);
2898 gp->dev.parent = &s->dev->dev;
2899 gp->io = gpio;
2900 s->ctrl |= CTRL_JYSTK_EN | (((gpio >> 3) & CTRL_JOY_MASK) << CTRL_JOY_SHIFT);
2901 }
2902
2903 s->sctrl = 0;
2904 cssr = 0;
2905 s->spdif_volume = -1;
2906 /* check to see if s/pdif mode is being requested */
2907 if (spdif[devindex]) {
2908 if (s->rev >= 4) {
2909 printk(KERN_INFO PFX "enabling S/PDIF output\n");
2910 s->spdif_volume = 0;
2911 cssr |= STAT_EN_SPDIF;
2912 s->ctrl |= CTRL_SPDIFEN_B;
2913 if (nomix[devindex]) /* don't mix analog inputs to s/pdif output */
2914 s->ctrl |= CTRL_RECEN_B;
2915 } else {
2916 printk(KERN_ERR PFX "revision %d does not support S/PDIF\n", s->rev);
2917 }
2918 }
2919 /* initialize the chips */
2920 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2921 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2922 outl(LEGACY_JFAST, s->io+ES1371_REG_LEGACY);
2923 pci_set_master(pcidev); /* enable bus mastering */
2924 /* if we are a 5880 turn on the AC97 */
2925 if (s->vendor == PCI_VENDOR_ID_ENSONIQ &&
2926 ((s->device == PCI_DEVICE_ID_ENSONIQ_CT5880 && s->rev >= CT5880REV_CT5880_C) ||
2927 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_CT5880_A) ||
2928 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_ES1373_8))) {
2929 cssr |= CSTAT_5880_AC97_RST;
2930 outl(cssr, s->io+ES1371_REG_STATUS);
2931 /* need to delay around 20ms(bleech) to give
2932 some CODECs enough time to wakeup */
2933 tmo = jiffies + (HZ / 50) + 1;
2934 for (;;) {
2935 tmo2 = tmo - jiffies;
2936 if (tmo2 <= 0)
2937 break;
2938 schedule_timeout(tmo2);
2939 }
2940 }
2941 /* AC97 warm reset to start the bitclk */
2942 outl(s->ctrl | CTRL_SYNCRES, s->io+ES1371_REG_CONTROL);
2943 udelay(2);
2944 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2945 /* init the sample rate converter */
2946 src_init(s);
2947 /* codec init */
2948 if (!ac97_probe_codec(s->codec)) {
2949 res = -ENODEV;
2950 goto err_gp;
2951 }
2952 /* set default values */
2953
2954 fs = get_fs();
2955 set_fs(KERNEL_DS);
2956 val = SOUND_MASK_LINE;
2957 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2958 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
2959 val = initvol[i].vol;
2960 mixdev_ioctl(s->codec, initvol[i].mixch, (unsigned long)&val);
2961 }
2962 /* mute master and PCM when in S/PDIF mode */
2963 if (s->spdif_volume != -1) {
2964 val = 0x0000;
2965 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_VOLUME, (unsigned long)&val);
2966 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_PCM, (unsigned long)&val);
2967 }
2968 set_fs(fs);
2969 /* turn on S/PDIF output driver if requested */
2970 outl(cssr, s->io+ES1371_REG_STATUS);
2971
2972 /* register gameport */
2973 if (s->gameport)
2974 gameport_register_port(s->gameport);
2975
2976 /* store it in the driver field */
2977 pci_set_drvdata(pcidev, s);
2978 /* put it into driver list */
2979 list_add_tail(&s->devs, &devs);
2980 /* increment devindex */
2981 if (devindex < NR_DEVICE-1)
2982 devindex++;
2983 return 0;
2984
2985 err_gp:
2986 if (s->gameport) {
2987 release_region(s->gameport->io, JOY_EXTENT);
2988 gameport_free_port(s->gameport);
2989 }
2990 #ifdef ES1371_DEBUG
2991 if (s->ps)
2992 remove_proc_entry("es1371", NULL);
2993 #endif
2994 unregister_sound_midi(s->dev_midi);
2995 err_dev4:
2996 unregister_sound_dsp(s->dev_dac);
2997 err_dev3:
2998 unregister_sound_mixer(s->codec->dev_mixer);
2999 err_dev2:
3000 unregister_sound_dsp(s->dev_audio);
3001 err_dev1:
3002 printk(KERN_ERR PFX "cannot register misc device\n");
3003 free_irq(s->irq, s);
3004 err_irq:
3005 release_region(s->io, ES1371_EXTENT);
3006 err_region:
3007 err_codec:
3008 ac97_release_codec(s->codec);
3009 kfree(s);
3010 return res;
3011 }
3012
3013 static void __devexit es1371_remove(struct pci_dev *dev)
3014 {
3015 struct es1371_state *s = pci_get_drvdata(dev);
3016
3017 if (!s)
3018 return;
3019 list_del(&s->devs);
3020 #ifdef ES1371_DEBUG
3021 if (s->ps)
3022 remove_proc_entry("es1371", NULL);
3023 #endif /* ES1371_DEBUG */
3024 outl(0, s->io+ES1371_REG_CONTROL); /* switch everything off */
3025 outl(0, s->io+ES1371_REG_SERIAL_CONTROL); /* clear serial interrupts */
3026 synchronize_irq(s->irq);
3027 free_irq(s->irq, s);
3028 if (s->gameport) {
3029 int gpio = s->gameport->io;
3030 gameport_unregister_port(s->gameport);
3031 release_region(gpio, JOY_EXTENT);
3032 }
3033 release_region(s->io, ES1371_EXTENT);
3034 unregister_sound_dsp(s->dev_audio);
3035 unregister_sound_mixer(s->codec->dev_mixer);
3036 unregister_sound_dsp(s->dev_dac);
3037 unregister_sound_midi(s->dev_midi);
3038 ac97_release_codec(s->codec);
3039 kfree(s);
3040 pci_set_drvdata(dev, NULL);
3041 }
3042
3043 static struct pci_device_id id_table[] = {
3044 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3045 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3046 { PCI_VENDOR_ID_ECTIVA, PCI_DEVICE_ID_ECTIVA_EV1938, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3047 { 0, }
3048 };
3049
3050 MODULE_DEVICE_TABLE(pci, id_table);
3051
3052 static struct pci_driver es1371_driver = {
3053 .name = "es1371",
3054 .id_table = id_table,
3055 .probe = es1371_probe,
3056 .remove = __devexit_p(es1371_remove),
3057 };
3058
3059 static int __init init_es1371(void)
3060 {
3061 printk(KERN_INFO PFX "version v0.32 time " __TIME__ " " __DATE__ "\n");
3062 return pci_module_init(&es1371_driver);
3063 }
3064
3065 static void __exit cleanup_es1371(void)
3066 {
3067 printk(KERN_INFO PFX "unloading\n");
3068 pci_unregister_driver(&es1371_driver);
3069 }
3070
3071 module_init(init_es1371);
3072 module_exit(cleanup_es1371);
3073
3074 /* --------------------------------------------------------------------- */
3075
3076 #ifndef MODULE
3077
3078 /* format is: es1371=[spdif,[nomix,[amplifier]]] */
3079
3080 static int __init es1371_setup(char *str)
3081 {
3082 static unsigned __initdata nr_dev = 0;
3083
3084 if (nr_dev >= NR_DEVICE)
3085 return 0;
3086
3087 (void)
3088 ((get_option(&str, &spdif[nr_dev]) == 2)
3089 && (get_option(&str, &nomix[nr_dev]) == 2)
3090 && (get_option(&str, &amplifier[nr_dev])));
3091
3092 nr_dev++;
3093 return 1;
3094 }
3095
3096 __setup("es1371=", es1371_setup);
3097
3098 #endif /* MODULE */
kernel-based virtual machine