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Input: i8042 - remove SPRUCE support
[linux-2.6/kvm.git] / drivers / hwmon / dme1737.c
blob980c17d5eeae98992345f2a2f413994f3513c79f
1 /*
2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027,
3 * and SCH5127 Super-I/O chips integrated hardware monitoring
4 * features.
5 * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com>
6 *
7 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access
8 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus
9 * if a SCH311x or SCH5127 chip is found. Both types of chips have very
10 * similar hardware monitoring capabilities but differ in the way they can be
11 * accessed.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/jiffies.h>
32 #include <linux/i2c.h>
33 #include <linux/platform_device.h>
34 #include <linux/hwmon.h>
35 #include <linux/hwmon-sysfs.h>
36 #include <linux/hwmon-vid.h>
37 #include <linux/err.h>
38 #include <linux/mutex.h>
39 #include <linux/acpi.h>
40 #include <linux/io.h>
41
42 /* ISA device, if found */
43 static struct platform_device *pdev;
44
45 /* Module load parameters */
46 static int force_start;
47 module_param(force_start, bool, 0);
48 MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs");
49
50 static unsigned short force_id;
51 module_param(force_id, ushort, 0);
52 MODULE_PARM_DESC(force_id, "Override the detected device ID");
53
54 static int probe_all_addr;
55 module_param(probe_all_addr, bool, 0);
56 MODULE_PARM_DESC(probe_all_addr, "Include probing of non-standard LPC "
57 "addresses");
58
59 /* Addresses to scan */
60 static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END};
61
62 enum chips { dme1737, sch5027, sch311x, sch5127 };
63
64 /* ---------------------------------------------------------------------
65 * Registers
66 *
67 * The sensors are defined as follows:
68 *
69 * Voltages Temperatures
70 * -------- ------------
71 * in0 +5VTR (+5V stdby) temp1 Remote diode 1
72 * in1 Vccp (proc core) temp2 Internal temp
73 * in2 VCC (internal +3.3V) temp3 Remote diode 2
74 * in3 +5V
75 * in4 +12V
76 * in5 VTR (+3.3V stby)
77 * in6 Vbat
78 *
79 * --------------------------------------------------------------------- */
80
81 /* Voltages (in) numbered 0-6 (ix) */
82 #define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) \
83 : 0x94 + (ix))
84 #define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \
85 : 0x91 + (ix) * 2)
86 #define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \
87 : 0x92 + (ix) * 2)
88
89 /* Temperatures (temp) numbered 0-2 (ix) */
90 #define DME1737_REG_TEMP(ix) (0x25 + (ix))
91 #define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2)
92 #define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2)
93 #define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \
94 : 0x1c + (ix))
95
96 /* Voltage and temperature LSBs
97 * The LSBs (4 bits each) are stored in 5 registers with the following layouts:
98 * IN_TEMP_LSB(0) = [in5, in6]
99 * IN_TEMP_LSB(1) = [temp3, temp1]
100 * IN_TEMP_LSB(2) = [in4, temp2]
101 * IN_TEMP_LSB(3) = [in3, in0]
102 * IN_TEMP_LSB(4) = [in2, in1] */
103 #define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix))
104 static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0};
105 static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4};
106 static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1};
107 static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0};
108
109 /* Fans numbered 0-5 (ix) */
110 #define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \
111 : 0xa1 + (ix) * 2)
112 #define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \
113 : 0xa5 + (ix) * 2)
114 #define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \
115 : 0xb2 + (ix))
116 #define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */
117
118 /* PWMs numbered 0-2, 4-5 (ix) */
119 #define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \
120 : 0xa1 + (ix))
121 #define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */
122 #define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */
123 #define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \
124 : 0xa3 + (ix))
125 /* The layout of the ramp rate registers is different from the other pwm
126 * registers. The bits for the 3 PWMs are stored in 2 registers:
127 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0]
128 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0] */
129 #define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */
130
131 /* Thermal zones 0-2 */
132 #define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix))
133 #define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix))
134 /* The layout of the hysteresis registers is different from the other zone
135 * registers. The bits for the 3 zones are stored in 2 registers:
136 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
137 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES] */
138 #define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix))
139
140 /* Alarm registers and bit mapping
141 * The 3 8-bit alarm registers will be concatenated to a single 32-bit
142 * alarm value [0, ALARM3, ALARM2, ALARM1]. */
143 #define DME1737_REG_ALARM1 0x41
144 #define DME1737_REG_ALARM2 0x42
145 #define DME1737_REG_ALARM3 0x83
146 static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17};
147 static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6};
148 static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23};
149
150 /* Miscellaneous registers */
151 #define DME1737_REG_DEVICE 0x3d
152 #define DME1737_REG_COMPANY 0x3e
153 #define DME1737_REG_VERSTEP 0x3f
154 #define DME1737_REG_CONFIG 0x40
155 #define DME1737_REG_CONFIG2 0x7f
156 #define DME1737_REG_VID 0x43
157 #define DME1737_REG_TACH_PWM 0x81
158
159 /* ---------------------------------------------------------------------
160 * Misc defines
161 * --------------------------------------------------------------------- */
162
163 /* Chip identification */
164 #define DME1737_COMPANY_SMSC 0x5c
165 #define DME1737_VERSTEP 0x88
166 #define DME1737_VERSTEP_MASK 0xf8
167 #define SCH311X_DEVICE 0x8c
168 #define SCH5027_VERSTEP 0x69
169 #define SCH5127_DEVICE 0x8e
170
171 /* Device ID values (global configuration register index 0x20) */
172 #define DME1737_ID_1 0x77
173 #define DME1737_ID_2 0x78
174 #define SCH3112_ID 0x7c
175 #define SCH3114_ID 0x7d
176 #define SCH3116_ID 0x7f
177 #define SCH5027_ID 0x89
178 #define SCH5127_ID 0x86
179
180 /* Length of ISA address segment */
181 #define DME1737_EXTENT 2
182
183 /* chip-dependent features */
184 #define HAS_TEMP_OFFSET (1 << 0) /* bit 0 */
185 #define HAS_VID (1 << 1) /* bit 1 */
186 #define HAS_ZONE3 (1 << 2) /* bit 2 */
187 #define HAS_ZONE_HYST (1 << 3) /* bit 3 */
188 #define HAS_PWM_MIN (1 << 4) /* bit 4 */
189 #define HAS_FAN(ix) (1 << ((ix) + 5)) /* bits 5-10 */
190 #define HAS_PWM(ix) (1 << ((ix) + 11)) /* bits 11-16 */
191
192 /* ---------------------------------------------------------------------
193 * Data structures and manipulation thereof
194 * --------------------------------------------------------------------- */
195
196 struct dme1737_data {
197 struct i2c_client *client; /* for I2C devices only */
198 struct device *hwmon_dev;
199 const char *name;
200 unsigned int addr; /* for ISA devices only */
201
202 struct mutex update_lock;
203 int valid; /* !=0 if following fields are valid */
204 unsigned long last_update; /* in jiffies */
205 unsigned long last_vbat; /* in jiffies */
206 enum chips type;
207 const int *in_nominal; /* pointer to IN_NOMINAL array */
208
209 u8 vid;
210 u8 pwm_rr_en;
211 u32 has_features;
212
213 /* Register values */
214 u16 in[7];
215 u8 in_min[7];
216 u8 in_max[7];
217 s16 temp[3];
218 s8 temp_min[3];
219 s8 temp_max[3];
220 s8 temp_offset[3];
221 u8 config;
222 u8 config2;
223 u8 vrm;
224 u16 fan[6];
225 u16 fan_min[6];
226 u8 fan_max[2];
227 u8 fan_opt[6];
228 u8 pwm[6];
229 u8 pwm_min[3];
230 u8 pwm_config[3];
231 u8 pwm_acz[3];
232 u8 pwm_freq[6];
233 u8 pwm_rr[2];
234 u8 zone_low[3];
235 u8 zone_abs[3];
236 u8 zone_hyst[2];
237 u32 alarms;
238 };
239
240 /* Nominal voltage values */
241 static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300,
242 3300};
243 static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300,
244 3300};
245 static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300,
246 3300};
247 static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300,
248 3300};
249 #define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \
250 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \
251 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \
252 IN_NOMINAL_DME1737)
253
254 /* Voltage input
255 * Voltage inputs have 16 bits resolution, limit values have 8 bits
256 * resolution. */
257 static inline int IN_FROM_REG(int reg, int nominal, int res)
258 {
259 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2));
260 }
261
262 static inline int IN_TO_REG(int val, int nominal)
263 {
264 return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255);
265 }
266
267 /* Temperature input
268 * The register values represent temperatures in 2's complement notation from
269 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit
270 * values have 8 bits resolution. */
271 static inline int TEMP_FROM_REG(int reg, int res)
272 {
273 return (reg * 1000) >> (res - 8);
274 }
275
276 static inline int TEMP_TO_REG(int val)
277 {
278 return SENSORS_LIMIT((val < 0 ? val - 500 : val + 500) / 1000,
279 -128, 127);
280 }
281
282 /* Temperature range */
283 static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000,
284 10000, 13333, 16000, 20000, 26666, 32000,
285 40000, 53333, 80000};
286
287 static inline int TEMP_RANGE_FROM_REG(int reg)
288 {
289 return TEMP_RANGE[(reg >> 4) & 0x0f];
290 }
291
292 static int TEMP_RANGE_TO_REG(int val, int reg)
293 {
294 int i;
295
296 for (i = 15; i > 0; i--) {
297 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2) {
298 break;
299 }
300 }
301
302 return (reg & 0x0f) | (i << 4);
303 }
304
305 /* Temperature hysteresis
306 * Register layout:
307 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
308 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx] */
309 static inline int TEMP_HYST_FROM_REG(int reg, int ix)
310 {
311 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000;
312 }
313
314 static inline int TEMP_HYST_TO_REG(int val, int ix, int reg)
315 {
316 int hyst = SENSORS_LIMIT((val + 500) / 1000, 0, 15);
317
318 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4);
319 }
320
321 /* Fan input RPM */
322 static inline int FAN_FROM_REG(int reg, int tpc)
323 {
324 if (tpc) {
325 return tpc * reg;
326 } else {
327 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg;
328 }
329 }
330
331 static inline int FAN_TO_REG(int val, int tpc)
332 {
333 if (tpc) {
334 return SENSORS_LIMIT(val / tpc, 0, 0xffff);
335 } else {
336 return (val <= 0) ? 0xffff :
337 SENSORS_LIMIT(90000 * 60 / val, 0, 0xfffe);
338 }
339 }
340
341 /* Fan TPC (tach pulse count)
342 * Converts a register value to a TPC multiplier or returns 0 if the tachometer
343 * is configured in legacy (non-tpc) mode */
344 static inline int FAN_TPC_FROM_REG(int reg)
345 {
346 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03);
347 }
348
349 /* Fan type
350 * The type of a fan is expressed in number of pulses-per-revolution that it
351 * emits */
352 static inline int FAN_TYPE_FROM_REG(int reg)
353 {
354 int edge = (reg >> 1) & 0x03;
355
356 return (edge > 0) ? 1 << (edge - 1) : 0;
357 }
358
359 static inline int FAN_TYPE_TO_REG(int val, int reg)
360 {
361 int edge = (val == 4) ? 3 : val;
362
363 return (reg & 0xf9) | (edge << 1);
364 }
365
366 /* Fan max RPM */
367 static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12,
368 0x11, 0x0f, 0x0e};
369
370 static int FAN_MAX_FROM_REG(int reg)
371 {
372 int i;
373
374 for (i = 10; i > 0; i--) {
375 if (reg == FAN_MAX[i]) {
376 break;
377 }
378 }
379
380 return 1000 + i * 500;
381 }
382
383 static int FAN_MAX_TO_REG(int val)
384 {
385 int i;
386
387 for (i = 10; i > 0; i--) {
388 if (val > (1000 + (i - 1) * 500)) {
389 break;
390 }
391 }
392
393 return FAN_MAX[i];
394 }
395
396 /* PWM enable
397 * Register to enable mapping:
398 * 000: 2 fan on zone 1 auto
399 * 001: 2 fan on zone 2 auto
400 * 010: 2 fan on zone 3 auto
401 * 011: 0 fan full on
402 * 100: -1 fan disabled
403 * 101: 2 fan on hottest of zones 2,3 auto
404 * 110: 2 fan on hottest of zones 1,2,3 auto
405 * 111: 1 fan in manual mode */
406 static inline int PWM_EN_FROM_REG(int reg)
407 {
408 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1};
409
410 return en[(reg >> 5) & 0x07];
411 }
412
413 static inline int PWM_EN_TO_REG(int val, int reg)
414 {
415 int en = (val == 1) ? 7 : 3;
416
417 return (reg & 0x1f) | ((en & 0x07) << 5);
418 }
419
420 /* PWM auto channels zone
421 * Register to auto channels zone mapping (ACZ is a bitfield with bit x
422 * corresponding to zone x+1):
423 * 000: 001 fan on zone 1 auto
424 * 001: 010 fan on zone 2 auto
425 * 010: 100 fan on zone 3 auto
426 * 011: 000 fan full on
427 * 100: 000 fan disabled
428 * 101: 110 fan on hottest of zones 2,3 auto
429 * 110: 111 fan on hottest of zones 1,2,3 auto
430 * 111: 000 fan in manual mode */
431 static inline int PWM_ACZ_FROM_REG(int reg)
432 {
433 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0};
434
435 return acz[(reg >> 5) & 0x07];
436 }
437
438 static inline int PWM_ACZ_TO_REG(int val, int reg)
439 {
440 int acz = (val == 4) ? 2 : val - 1;
441
442 return (reg & 0x1f) | ((acz & 0x07) << 5);
443 }
444
445 /* PWM frequency */
446 static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88,
447 15000, 20000, 30000, 25000, 0, 0, 0, 0};
448
449 static inline int PWM_FREQ_FROM_REG(int reg)
450 {
451 return PWM_FREQ[reg & 0x0f];
452 }
453
454 static int PWM_FREQ_TO_REG(int val, int reg)
455 {
456 int i;
457
458 /* the first two cases are special - stupid chip design! */
459 if (val > 27500) {
460 i = 10;
461 } else if (val > 22500) {
462 i = 11;
463 } else {
464 for (i = 9; i > 0; i--) {
465 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2) {
466 break;
467 }
468 }
469 }
470
471 return (reg & 0xf0) | i;
472 }
473
474 /* PWM ramp rate
475 * Register layout:
476 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0]
477 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0] */
478 static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5};
479
480 static inline int PWM_RR_FROM_REG(int reg, int ix)
481 {
482 int rr = (ix == 1) ? reg >> 4 : reg;
483
484 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0;
485 }
486
487 static int PWM_RR_TO_REG(int val, int ix, int reg)
488 {
489 int i;
490
491 for (i = 0; i < 7; i++) {
492 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2) {
493 break;
494 }
495 }
496
497 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i;
498 }
499
500 /* PWM ramp rate enable */
501 static inline int PWM_RR_EN_FROM_REG(int reg, int ix)
502 {
503 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0;
504 }
505
506 static inline int PWM_RR_EN_TO_REG(int val, int ix, int reg)
507 {
508 int en = (ix == 1) ? 0x80 : 0x08;
509
510 return val ? reg | en : reg & ~en;
511 }
512
513 /* PWM min/off
514 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
515 * the register layout). */
516 static inline int PWM_OFF_FROM_REG(int reg, int ix)
517 {
518 return (reg >> (ix + 5)) & 0x01;
519 }
520
521 static inline int PWM_OFF_TO_REG(int val, int ix, int reg)
522 {
523 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5));
524 }
525
526 /* ---------------------------------------------------------------------
527 * Device I/O access
528 *
529 * ISA access is performed through an index/data register pair and needs to
530 * be protected by a mutex during runtime (not required for initialization).
531 * We use data->update_lock for this and need to ensure that we acquire it
532 * before calling dme1737_read or dme1737_write.
533 * --------------------------------------------------------------------- */
534
535 static u8 dme1737_read(const struct dme1737_data *data, u8 reg)
536 {
537 struct i2c_client *client = data->client;
538 s32 val;
539
540 if (client) { /* I2C device */
541 val = i2c_smbus_read_byte_data(client, reg);
542
543 if (val < 0) {
544 dev_warn(&client->dev, "Read from register "
545 "0x%02x failed! Please report to the driver "
546 "maintainer.\n", reg);
547 }
548 } else { /* ISA device */
549 outb(reg, data->addr);
550 val = inb(data->addr + 1);
551 }
552
553 return val;
554 }
555
556 static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val)
557 {
558 struct i2c_client *client = data->client;
559 s32 res = 0;
560
561 if (client) { /* I2C device */
562 res = i2c_smbus_write_byte_data(client, reg, val);
563
564 if (res < 0) {
565 dev_warn(&client->dev, "Write to register "
566 "0x%02x failed! Please report to the driver "
567 "maintainer.\n", reg);
568 }
569 } else { /* ISA device */
570 outb(reg, data->addr);
571 outb(val, data->addr + 1);
572 }
573
574 return res;
575 }
576
577 static struct dme1737_data *dme1737_update_device(struct device *dev)
578 {
579 struct dme1737_data *data = dev_get_drvdata(dev);
580 int ix;
581 u8 lsb[5];
582
583 mutex_lock(&data->update_lock);
584
585 /* Enable a Vbat monitoring cycle every 10 mins */
586 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) {
587 dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data,
588 DME1737_REG_CONFIG) | 0x10);
589 data->last_vbat = jiffies;
590 }
591
592 /* Sample register contents every 1 sec */
593 if (time_after(jiffies, data->last_update + HZ) || !data->valid) {
594 if (data->has_features & HAS_VID) {
595 data->vid = dme1737_read(data, DME1737_REG_VID) &
596 0x3f;
597 }
598
599 /* In (voltage) registers */
600 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
601 /* Voltage inputs are stored as 16 bit values even
602 * though they have only 12 bits resolution. This is
603 * to make it consistent with the temp inputs. */
604 data->in[ix] = dme1737_read(data,
605 DME1737_REG_IN(ix)) << 8;
606 data->in_min[ix] = dme1737_read(data,
607 DME1737_REG_IN_MIN(ix));
608 data->in_max[ix] = dme1737_read(data,
609 DME1737_REG_IN_MAX(ix));
610 }
611
612 /* Temp registers */
613 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
614 /* Temp inputs are stored as 16 bit values even
615 * though they have only 12 bits resolution. This is
616 * to take advantage of implicit conversions between
617 * register values (2's complement) and temp values
618 * (signed decimal). */
619 data->temp[ix] = dme1737_read(data,
620 DME1737_REG_TEMP(ix)) << 8;
621 data->temp_min[ix] = dme1737_read(data,
622 DME1737_REG_TEMP_MIN(ix));
623 data->temp_max[ix] = dme1737_read(data,
624 DME1737_REG_TEMP_MAX(ix));
625 if (data->has_features & HAS_TEMP_OFFSET) {
626 data->temp_offset[ix] = dme1737_read(data,
627 DME1737_REG_TEMP_OFFSET(ix));
628 }
629 }
630
631 /* In and temp LSB registers
632 * The LSBs are latched when the MSBs are read, so the order in
633 * which the registers are read (MSB first, then LSB) is
634 * important! */
635 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) {
636 lsb[ix] = dme1737_read(data,
637 DME1737_REG_IN_TEMP_LSB(ix));
638 }
639 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
640 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] <<
641 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0;
642 }
643 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
644 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] <<
645 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0;
646 }
647
648 /* Fan registers */
649 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) {
650 /* Skip reading registers if optional fans are not
651 * present */
652 if (!(data->has_features & HAS_FAN(ix))) {
653 continue;
654 }
655 data->fan[ix] = dme1737_read(data,
656 DME1737_REG_FAN(ix));
657 data->fan[ix] |= dme1737_read(data,
658 DME1737_REG_FAN(ix) + 1) << 8;
659 data->fan_min[ix] = dme1737_read(data,
660 DME1737_REG_FAN_MIN(ix));
661 data->fan_min[ix] |= dme1737_read(data,
662 DME1737_REG_FAN_MIN(ix) + 1) << 8;
663 data->fan_opt[ix] = dme1737_read(data,
664 DME1737_REG_FAN_OPT(ix));
665 /* fan_max exists only for fan[5-6] */
666 if (ix > 3) {
667 data->fan_max[ix - 4] = dme1737_read(data,
668 DME1737_REG_FAN_MAX(ix));
669 }
670 }
671
672 /* PWM registers */
673 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) {
674 /* Skip reading registers if optional PWMs are not
675 * present */
676 if (!(data->has_features & HAS_PWM(ix))) {
677 continue;
678 }
679 data->pwm[ix] = dme1737_read(data,
680 DME1737_REG_PWM(ix));
681 data->pwm_freq[ix] = dme1737_read(data,
682 DME1737_REG_PWM_FREQ(ix));
683 /* pwm_config and pwm_min exist only for pwm[1-3] */
684 if (ix < 3) {
685 data->pwm_config[ix] = dme1737_read(data,
686 DME1737_REG_PWM_CONFIG(ix));
687 data->pwm_min[ix] = dme1737_read(data,
688 DME1737_REG_PWM_MIN(ix));
689 }
690 }
691 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) {
692 data->pwm_rr[ix] = dme1737_read(data,
693 DME1737_REG_PWM_RR(ix));
694 }
695
696 /* Thermal zone registers */
697 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) {
698 /* Skip reading registers if zone3 is not present */
699 if ((ix == 2) && !(data->has_features & HAS_ZONE3)) {
700 continue;
701 }
702 /* sch5127 zone2 registers are special */
703 if ((ix == 1) && (data->type == sch5127)) {
704 data->zone_low[1] = dme1737_read(data,
705 DME1737_REG_ZONE_LOW(2));
706 data->zone_abs[1] = dme1737_read(data,
707 DME1737_REG_ZONE_ABS(2));
708 } else {
709 data->zone_low[ix] = dme1737_read(data,
710 DME1737_REG_ZONE_LOW(ix));
711 data->zone_abs[ix] = dme1737_read(data,
712 DME1737_REG_ZONE_ABS(ix));
713 }
714 }
715 if (data->has_features & HAS_ZONE_HYST) {
716 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) {
717 data->zone_hyst[ix] = dme1737_read(data,
718 DME1737_REG_ZONE_HYST(ix));
719 }
720 }
721
722 /* Alarm registers */
723 data->alarms = dme1737_read(data,
724 DME1737_REG_ALARM1);
725 /* Bit 7 tells us if the other alarm registers are non-zero and
726 * therefore also need to be read */
727 if (data->alarms & 0x80) {
728 data->alarms |= dme1737_read(data,
729 DME1737_REG_ALARM2) << 8;
730 data->alarms |= dme1737_read(data,
731 DME1737_REG_ALARM3) << 16;
732 }
733
734 /* The ISA chips require explicit clearing of alarm bits.
735 * Don't worry, an alarm will come back if the condition
736 * that causes it still exists */
737 if (!data->client) {
738 if (data->alarms & 0xff0000) {
739 dme1737_write(data, DME1737_REG_ALARM3,
740 0xff);
741 }
742 if (data->alarms & 0xff00) {
743 dme1737_write(data, DME1737_REG_ALARM2,
744 0xff);
745 }
746 if (data->alarms & 0xff) {
747 dme1737_write(data, DME1737_REG_ALARM1,
748 0xff);
749 }
750 }
751
752 data->last_update = jiffies;
753 data->valid = 1;
754 }
755
756 mutex_unlock(&data->update_lock);
757
758 return data;
759 }
760
761 /* ---------------------------------------------------------------------
762 * Voltage sysfs attributes
763 * ix = [0-5]
764 * --------------------------------------------------------------------- */
765
766 #define SYS_IN_INPUT 0
767 #define SYS_IN_MIN 1
768 #define SYS_IN_MAX 2
769 #define SYS_IN_ALARM 3
770
771 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
772 char *buf)
773 {
774 struct dme1737_data *data = dme1737_update_device(dev);
775 struct sensor_device_attribute_2
776 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
777 int ix = sensor_attr_2->index;
778 int fn = sensor_attr_2->nr;
779 int res;
780
781 switch (fn) {
782 case SYS_IN_INPUT:
783 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16);
784 break;
785 case SYS_IN_MIN:
786 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8);
787 break;
788 case SYS_IN_MAX:
789 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8);
790 break;
791 case SYS_IN_ALARM:
792 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01;
793 break;
794 default:
795 res = 0;
796 dev_dbg(dev, "Unknown function %d.\n", fn);
797 }
798
799 return sprintf(buf, "%d\n", res);
800 }
801
802 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
803 const char *buf, size_t count)
804 {
805 struct dme1737_data *data = dev_get_drvdata(dev);
806 struct sensor_device_attribute_2
807 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
808 int ix = sensor_attr_2->index;
809 int fn = sensor_attr_2->nr;
810 long val = simple_strtol(buf, NULL, 10);
811
812 mutex_lock(&data->update_lock);
813 switch (fn) {
814 case SYS_IN_MIN:
815 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]);
816 dme1737_write(data, DME1737_REG_IN_MIN(ix),
817 data->in_min[ix]);
818 break;
819 case SYS_IN_MAX:
820 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]);
821 dme1737_write(data, DME1737_REG_IN_MAX(ix),
822 data->in_max[ix]);
823 break;
824 default:
825 dev_dbg(dev, "Unknown function %d.\n", fn);
826 }
827 mutex_unlock(&data->update_lock);
828
829 return count;
830 }
831
832 /* ---------------------------------------------------------------------
833 * Temperature sysfs attributes
834 * ix = [0-2]
835 * --------------------------------------------------------------------- */
836
837 #define SYS_TEMP_INPUT 0
838 #define SYS_TEMP_MIN 1
839 #define SYS_TEMP_MAX 2
840 #define SYS_TEMP_OFFSET 3
841 #define SYS_TEMP_ALARM 4
842 #define SYS_TEMP_FAULT 5
843
844 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
845 char *buf)
846 {
847 struct dme1737_data *data = dme1737_update_device(dev);
848 struct sensor_device_attribute_2
849 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
850 int ix = sensor_attr_2->index;
851 int fn = sensor_attr_2->nr;
852 int res;
853
854 switch (fn) {
855 case SYS_TEMP_INPUT:
856 res = TEMP_FROM_REG(data->temp[ix], 16);
857 break;
858 case SYS_TEMP_MIN:
859 res = TEMP_FROM_REG(data->temp_min[ix], 8);
860 break;
861 case SYS_TEMP_MAX:
862 res = TEMP_FROM_REG(data->temp_max[ix], 8);
863 break;
864 case SYS_TEMP_OFFSET:
865 res = TEMP_FROM_REG(data->temp_offset[ix], 8);
866 break;
867 case SYS_TEMP_ALARM:
868 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01;
869 break;
870 case SYS_TEMP_FAULT:
871 res = (((u16)data->temp[ix] & 0xff00) == 0x8000);
872 break;
873 default:
874 res = 0;
875 dev_dbg(dev, "Unknown function %d.\n", fn);
876 }
877
878 return sprintf(buf, "%d\n", res);
879 }
880
881 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
882 const char *buf, size_t count)
883 {
884 struct dme1737_data *data = dev_get_drvdata(dev);
885 struct sensor_device_attribute_2
886 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
887 int ix = sensor_attr_2->index;
888 int fn = sensor_attr_2->nr;
889 long val = simple_strtol(buf, NULL, 10);
890
891 mutex_lock(&data->update_lock);
892 switch (fn) {
893 case SYS_TEMP_MIN:
894 data->temp_min[ix] = TEMP_TO_REG(val);
895 dme1737_write(data, DME1737_REG_TEMP_MIN(ix),
896 data->temp_min[ix]);
897 break;
898 case SYS_TEMP_MAX:
899 data->temp_max[ix] = TEMP_TO_REG(val);
900 dme1737_write(data, DME1737_REG_TEMP_MAX(ix),
901 data->temp_max[ix]);
902 break;
903 case SYS_TEMP_OFFSET:
904 data->temp_offset[ix] = TEMP_TO_REG(val);
905 dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix),
906 data->temp_offset[ix]);
907 break;
908 default:
909 dev_dbg(dev, "Unknown function %d.\n", fn);
910 }
911 mutex_unlock(&data->update_lock);
912
913 return count;
914 }
915
916 /* ---------------------------------------------------------------------
917 * Zone sysfs attributes
918 * ix = [0-2]
919 * --------------------------------------------------------------------- */
920
921 #define SYS_ZONE_AUTO_CHANNELS_TEMP 0
922 #define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1
923 #define SYS_ZONE_AUTO_POINT1_TEMP 2
924 #define SYS_ZONE_AUTO_POINT2_TEMP 3
925 #define SYS_ZONE_AUTO_POINT3_TEMP 4
926
927 static ssize_t show_zone(struct device *dev, struct device_attribute *attr,
928 char *buf)
929 {
930 struct dme1737_data *data = dme1737_update_device(dev);
931 struct sensor_device_attribute_2
932 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
933 int ix = sensor_attr_2->index;
934 int fn = sensor_attr_2->nr;
935 int res;
936
937 switch (fn) {
938 case SYS_ZONE_AUTO_CHANNELS_TEMP:
939 /* check config2 for non-standard temp-to-zone mapping */
940 if ((ix == 1) && (data->config2 & 0x02)) {
941 res = 4;
942 } else {
943 res = 1 << ix;
944 }
945 break;
946 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
947 res = TEMP_FROM_REG(data->zone_low[ix], 8) -
948 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix);
949 break;
950 case SYS_ZONE_AUTO_POINT1_TEMP:
951 res = TEMP_FROM_REG(data->zone_low[ix], 8);
952 break;
953 case SYS_ZONE_AUTO_POINT2_TEMP:
954 /* pwm_freq holds the temp range bits in the upper nibble */
955 res = TEMP_FROM_REG(data->zone_low[ix], 8) +
956 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]);
957 break;
958 case SYS_ZONE_AUTO_POINT3_TEMP:
959 res = TEMP_FROM_REG(data->zone_abs[ix], 8);
960 break;
961 default:
962 res = 0;
963 dev_dbg(dev, "Unknown function %d.\n", fn);
964 }
965
966 return sprintf(buf, "%d\n", res);
967 }
968
969 static ssize_t set_zone(struct device *dev, struct device_attribute *attr,
970 const char *buf, size_t count)
971 {
972 struct dme1737_data *data = dev_get_drvdata(dev);
973 struct sensor_device_attribute_2
974 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
975 int ix = sensor_attr_2->index;
976 int fn = sensor_attr_2->nr;
977 long val = simple_strtol(buf, NULL, 10);
978
979 mutex_lock(&data->update_lock);
980 switch (fn) {
981 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
982 /* Refresh the cache */
983 data->zone_low[ix] = dme1737_read(data,
984 DME1737_REG_ZONE_LOW(ix));
985 /* Modify the temp hyst value */
986 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG(
987 TEMP_FROM_REG(data->zone_low[ix], 8) -
988 val, ix, dme1737_read(data,
989 DME1737_REG_ZONE_HYST(ix == 2)));
990 dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2),
991 data->zone_hyst[ix == 2]);
992 break;
993 case SYS_ZONE_AUTO_POINT1_TEMP:
994 data->zone_low[ix] = TEMP_TO_REG(val);
995 dme1737_write(data, DME1737_REG_ZONE_LOW(ix),
996 data->zone_low[ix]);
997 break;
998 case SYS_ZONE_AUTO_POINT2_TEMP:
999 /* Refresh the cache */
1000 data->zone_low[ix] = dme1737_read(data,
1001 DME1737_REG_ZONE_LOW(ix));
1002 /* Modify the temp range value (which is stored in the upper
1003 * nibble of the pwm_freq register) */
1004 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val -
1005 TEMP_FROM_REG(data->zone_low[ix], 8),
1006 dme1737_read(data,
1007 DME1737_REG_PWM_FREQ(ix)));
1008 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
1009 data->pwm_freq[ix]);
1010 break;
1011 case SYS_ZONE_AUTO_POINT3_TEMP:
1012 data->zone_abs[ix] = TEMP_TO_REG(val);
1013 dme1737_write(data, DME1737_REG_ZONE_ABS(ix),
1014 data->zone_abs[ix]);
1015 break;
1016 default:
1017 dev_dbg(dev, "Unknown function %d.\n", fn);
1018 }
1019 mutex_unlock(&data->update_lock);
1020
1021 return count;
1022 }
1023
1024 /* ---------------------------------------------------------------------
1025 * Fan sysfs attributes
1026 * ix = [0-5]
1027 * --------------------------------------------------------------------- */
1028
1029 #define SYS_FAN_INPUT 0
1030 #define SYS_FAN_MIN 1
1031 #define SYS_FAN_MAX 2
1032 #define SYS_FAN_ALARM 3
1033 #define SYS_FAN_TYPE 4
1034
1035 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1036 char *buf)
1037 {
1038 struct dme1737_data *data = dme1737_update_device(dev);
1039 struct sensor_device_attribute_2
1040 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1041 int ix = sensor_attr_2->index;
1042 int fn = sensor_attr_2->nr;
1043 int res;
1044
1045 switch (fn) {
1046 case SYS_FAN_INPUT:
1047 res = FAN_FROM_REG(data->fan[ix],
1048 ix < 4 ? 0 :
1049 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1050 break;
1051 case SYS_FAN_MIN:
1052 res = FAN_FROM_REG(data->fan_min[ix],
1053 ix < 4 ? 0 :
1054 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1055 break;
1056 case SYS_FAN_MAX:
1057 /* only valid for fan[5-6] */
1058 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]);
1059 break;
1060 case SYS_FAN_ALARM:
1061 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01;
1062 break;
1063 case SYS_FAN_TYPE:
1064 /* only valid for fan[1-4] */
1065 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]);
1066 break;
1067 default:
1068 res = 0;
1069 dev_dbg(dev, "Unknown function %d.\n", fn);
1070 }
1071
1072 return sprintf(buf, "%d\n", res);
1073 }
1074
1075 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1076 const char *buf, size_t count)
1077 {
1078 struct dme1737_data *data = dev_get_drvdata(dev);
1079 struct sensor_device_attribute_2
1080 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1081 int ix = sensor_attr_2->index;
1082 int fn = sensor_attr_2->nr;
1083 long val = simple_strtol(buf, NULL, 10);
1084
1085 mutex_lock(&data->update_lock);
1086 switch (fn) {
1087 case SYS_FAN_MIN:
1088 if (ix < 4) {
1089 data->fan_min[ix] = FAN_TO_REG(val, 0);
1090 } else {
1091 /* Refresh the cache */
1092 data->fan_opt[ix] = dme1737_read(data,
1093 DME1737_REG_FAN_OPT(ix));
1094 /* Modify the fan min value */
1095 data->fan_min[ix] = FAN_TO_REG(val,
1096 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1097 }
1098 dme1737_write(data, DME1737_REG_FAN_MIN(ix),
1099 data->fan_min[ix] & 0xff);
1100 dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1,
1101 data->fan_min[ix] >> 8);
1102 break;
1103 case SYS_FAN_MAX:
1104 /* Only valid for fan[5-6] */
1105 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val);
1106 dme1737_write(data, DME1737_REG_FAN_MAX(ix),
1107 data->fan_max[ix - 4]);
1108 break;
1109 case SYS_FAN_TYPE:
1110 /* Only valid for fan[1-4] */
1111 if (!(val == 1 || val == 2 || val == 4)) {
1112 count = -EINVAL;
1113 dev_warn(dev, "Fan type value %ld not "
1114 "supported. Choose one of 1, 2, or 4.\n",
1115 val);
1116 goto exit;
1117 }
1118 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data,
1119 DME1737_REG_FAN_OPT(ix)));
1120 dme1737_write(data, DME1737_REG_FAN_OPT(ix),
1121 data->fan_opt[ix]);
1122 break;
1123 default:
1124 dev_dbg(dev, "Unknown function %d.\n", fn);
1125 }
1126 exit:
1127 mutex_unlock(&data->update_lock);
1128
1129 return count;
1130 }
1131
1132 /* ---------------------------------------------------------------------
1133 * PWM sysfs attributes
1134 * ix = [0-4]
1135 * --------------------------------------------------------------------- */
1136
1137 #define SYS_PWM 0
1138 #define SYS_PWM_FREQ 1
1139 #define SYS_PWM_ENABLE 2
1140 #define SYS_PWM_RAMP_RATE 3
1141 #define SYS_PWM_AUTO_CHANNELS_ZONE 4
1142 #define SYS_PWM_AUTO_PWM_MIN 5
1143 #define SYS_PWM_AUTO_POINT1_PWM 6
1144 #define SYS_PWM_AUTO_POINT2_PWM 7
1145
1146 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1147 char *buf)
1148 {
1149 struct dme1737_data *data = dme1737_update_device(dev);
1150 struct sensor_device_attribute_2
1151 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1152 int ix = sensor_attr_2->index;
1153 int fn = sensor_attr_2->nr;
1154 int res;
1155
1156 switch (fn) {
1157 case SYS_PWM:
1158 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0) {
1159 res = 255;
1160 } else {
1161 res = data->pwm[ix];
1162 }
1163 break;
1164 case SYS_PWM_FREQ:
1165 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]);
1166 break;
1167 case SYS_PWM_ENABLE:
1168 if (ix >= 3) {
1169 res = 1; /* pwm[5-6] hard-wired to manual mode */
1170 } else {
1171 res = PWM_EN_FROM_REG(data->pwm_config[ix]);
1172 }
1173 break;
1174 case SYS_PWM_RAMP_RATE:
1175 /* Only valid for pwm[1-3] */
1176 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix);
1177 break;
1178 case SYS_PWM_AUTO_CHANNELS_ZONE:
1179 /* Only valid for pwm[1-3] */
1180 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1181 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]);
1182 } else {
1183 res = data->pwm_acz[ix];
1184 }
1185 break;
1186 case SYS_PWM_AUTO_PWM_MIN:
1187 /* Only valid for pwm[1-3] */
1188 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix)) {
1189 res = data->pwm_min[ix];
1190 } else {
1191 res = 0;
1192 }
1193 break;
1194 case SYS_PWM_AUTO_POINT1_PWM:
1195 /* Only valid for pwm[1-3] */
1196 res = data->pwm_min[ix];
1197 break;
1198 case SYS_PWM_AUTO_POINT2_PWM:
1199 /* Only valid for pwm[1-3] */
1200 res = 255; /* hard-wired */
1201 break;
1202 default:
1203 res = 0;
1204 dev_dbg(dev, "Unknown function %d.\n", fn);
1205 }
1206
1207 return sprintf(buf, "%d\n", res);
1208 }
1209
1210 static struct attribute *dme1737_pwm_chmod_attr[];
1211 static void dme1737_chmod_file(struct device*, struct attribute*, mode_t);
1212
1213 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1214 const char *buf, size_t count)
1215 {
1216 struct dme1737_data *data = dev_get_drvdata(dev);
1217 struct sensor_device_attribute_2
1218 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1219 int ix = sensor_attr_2->index;
1220 int fn = sensor_attr_2->nr;
1221 long val = simple_strtol(buf, NULL, 10);
1222
1223 mutex_lock(&data->update_lock);
1224 switch (fn) {
1225 case SYS_PWM:
1226 data->pwm[ix] = SENSORS_LIMIT(val, 0, 255);
1227 dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]);
1228 break;
1229 case SYS_PWM_FREQ:
1230 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data,
1231 DME1737_REG_PWM_FREQ(ix)));
1232 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
1233 data->pwm_freq[ix]);
1234 break;
1235 case SYS_PWM_ENABLE:
1236 /* Only valid for pwm[1-3] */
1237 if (val < 0 || val > 2) {
1238 count = -EINVAL;
1239 dev_warn(dev, "PWM enable %ld not "
1240 "supported. Choose one of 0, 1, or 2.\n",
1241 val);
1242 goto exit;
1243 }
1244 /* Refresh the cache */
1245 data->pwm_config[ix] = dme1737_read(data,
1246 DME1737_REG_PWM_CONFIG(ix));
1247 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) {
1248 /* Bail out if no change */
1249 goto exit;
1250 }
1251 /* Do some housekeeping if we are currently in auto mode */
1252 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1253 /* Save the current zone channel assignment */
1254 data->pwm_acz[ix] = PWM_ACZ_FROM_REG(
1255 data->pwm_config[ix]);
1256 /* Save the current ramp rate state and disable it */
1257 data->pwm_rr[ix > 0] = dme1737_read(data,
1258 DME1737_REG_PWM_RR(ix > 0));
1259 data->pwm_rr_en &= ~(1 << ix);
1260 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) {
1261 data->pwm_rr_en |= (1 << ix);
1262 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix,
1263 data->pwm_rr[ix > 0]);
1264 dme1737_write(data,
1265 DME1737_REG_PWM_RR(ix > 0),
1266 data->pwm_rr[ix > 0]);
1267 }
1268 }
1269 /* Set the new PWM mode */
1270 switch (val) {
1271 case 0:
1272 /* Change permissions of pwm[ix] to read-only */
1273 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1274 S_IRUGO);
1275 /* Turn fan fully on */
1276 data->pwm_config[ix] = PWM_EN_TO_REG(0,
1277 data->pwm_config[ix]);
1278 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1279 data->pwm_config[ix]);
1280 break;
1281 case 1:
1282 /* Turn on manual mode */
1283 data->pwm_config[ix] = PWM_EN_TO_REG(1,
1284 data->pwm_config[ix]);
1285 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1286 data->pwm_config[ix]);
1287 /* Change permissions of pwm[ix] to read-writeable */
1288 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1289 S_IRUGO | S_IWUSR);
1290 break;
1291 case 2:
1292 /* Change permissions of pwm[ix] to read-only */
1293 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1294 S_IRUGO);
1295 /* Turn on auto mode using the saved zone channel
1296 * assignment */
1297 data->pwm_config[ix] = PWM_ACZ_TO_REG(
1298 data->pwm_acz[ix],
1299 data->pwm_config[ix]);
1300 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1301 data->pwm_config[ix]);
1302 /* Enable PWM ramp rate if previously enabled */
1303 if (data->pwm_rr_en & (1 << ix)) {
1304 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix,
1305 dme1737_read(data,
1306 DME1737_REG_PWM_RR(ix > 0)));
1307 dme1737_write(data,
1308 DME1737_REG_PWM_RR(ix > 0),
1309 data->pwm_rr[ix > 0]);
1310 }
1311 break;
1312 }
1313 break;
1314 case SYS_PWM_RAMP_RATE:
1315 /* Only valid for pwm[1-3] */
1316 /* Refresh the cache */
1317 data->pwm_config[ix] = dme1737_read(data,
1318 DME1737_REG_PWM_CONFIG(ix));
1319 data->pwm_rr[ix > 0] = dme1737_read(data,
1320 DME1737_REG_PWM_RR(ix > 0));
1321 /* Set the ramp rate value */
1322 if (val > 0) {
1323 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix,
1324 data->pwm_rr[ix > 0]);
1325 }
1326 /* Enable/disable the feature only if the associated PWM
1327 * output is in automatic mode. */
1328 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1329 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix,
1330 data->pwm_rr[ix > 0]);
1331 }
1332 dme1737_write(data, DME1737_REG_PWM_RR(ix > 0),
1333 data->pwm_rr[ix > 0]);
1334 break;
1335 case SYS_PWM_AUTO_CHANNELS_ZONE:
1336 /* Only valid for pwm[1-3] */
1337 if (!(val == 1 || val == 2 || val == 4 ||
1338 val == 6 || val == 7)) {
1339 count = -EINVAL;
1340 dev_warn(dev, "PWM auto channels zone %ld "
1341 "not supported. Choose one of 1, 2, 4, 6, "
1342 "or 7.\n", val);
1343 goto exit;
1344 }
1345 /* Refresh the cache */
1346 data->pwm_config[ix] = dme1737_read(data,
1347 DME1737_REG_PWM_CONFIG(ix));
1348 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1349 /* PWM is already in auto mode so update the temp
1350 * channel assignment */
1351 data->pwm_config[ix] = PWM_ACZ_TO_REG(val,
1352 data->pwm_config[ix]);
1353 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1354 data->pwm_config[ix]);
1355 } else {
1356 /* PWM is not in auto mode so we save the temp
1357 * channel assignment for later use */
1358 data->pwm_acz[ix] = val;
1359 }
1360 break;
1361 case SYS_PWM_AUTO_PWM_MIN:
1362 /* Only valid for pwm[1-3] */
1363 /* Refresh the cache */
1364 data->pwm_min[ix] = dme1737_read(data,
1365 DME1737_REG_PWM_MIN(ix));
1366 /* There are only 2 values supported for the auto_pwm_min
1367 * value: 0 or auto_point1_pwm. So if the temperature drops
1368 * below the auto_point1_temp_hyst value, the fan either turns
1369 * off or runs at auto_point1_pwm duty-cycle. */
1370 if (val > ((data->pwm_min[ix] + 1) / 2)) {
1371 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix,
1372 dme1737_read(data,
1373 DME1737_REG_PWM_RR(0)));
1374 } else {
1375 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix,
1376 dme1737_read(data,
1377 DME1737_REG_PWM_RR(0)));
1378 }
1379 dme1737_write(data, DME1737_REG_PWM_RR(0),
1380 data->pwm_rr[0]);
1381 break;
1382 case SYS_PWM_AUTO_POINT1_PWM:
1383 /* Only valid for pwm[1-3] */
1384 data->pwm_min[ix] = SENSORS_LIMIT(val, 0, 255);
1385 dme1737_write(data, DME1737_REG_PWM_MIN(ix),
1386 data->pwm_min[ix]);
1387 break;
1388 default:
1389 dev_dbg(dev, "Unknown function %d.\n", fn);
1390 }
1391 exit:
1392 mutex_unlock(&data->update_lock);
1393
1394 return count;
1395 }
1396
1397 /* ---------------------------------------------------------------------
1398 * Miscellaneous sysfs attributes
1399 * --------------------------------------------------------------------- */
1400
1401 static ssize_t show_vrm(struct device *dev, struct device_attribute *attr,
1402 char *buf)
1403 {
1404 struct i2c_client *client = to_i2c_client(dev);
1405 struct dme1737_data *data = i2c_get_clientdata(client);
1406
1407 return sprintf(buf, "%d\n", data->vrm);
1408 }
1409
1410 static ssize_t set_vrm(struct device *dev, struct device_attribute *attr,
1411 const char *buf, size_t count)
1412 {
1413 struct dme1737_data *data = dev_get_drvdata(dev);
1414 long val = simple_strtol(buf, NULL, 10);
1415
1416 data->vrm = val;
1417 return count;
1418 }
1419
1420 static ssize_t show_vid(struct device *dev, struct device_attribute *attr,
1421 char *buf)
1422 {
1423 struct dme1737_data *data = dme1737_update_device(dev);
1424
1425 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1426 }
1427
1428 static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1429 char *buf)
1430 {
1431 struct dme1737_data *data = dev_get_drvdata(dev);
1432
1433 return sprintf(buf, "%s\n", data->name);
1434 }
1435
1436 /* ---------------------------------------------------------------------
1437 * Sysfs device attribute defines and structs
1438 * --------------------------------------------------------------------- */
1439
1440 /* Voltages 0-6 */
1441
1442 #define SENSOR_DEVICE_ATTR_IN(ix) \
1443 static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \
1444 show_in, NULL, SYS_IN_INPUT, ix); \
1445 static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \
1446 show_in, set_in, SYS_IN_MIN, ix); \
1447 static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \
1448 show_in, set_in, SYS_IN_MAX, ix); \
1449 static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \
1450 show_in, NULL, SYS_IN_ALARM, ix)
1451
1452 SENSOR_DEVICE_ATTR_IN(0);
1453 SENSOR_DEVICE_ATTR_IN(1);
1454 SENSOR_DEVICE_ATTR_IN(2);
1455 SENSOR_DEVICE_ATTR_IN(3);
1456 SENSOR_DEVICE_ATTR_IN(4);
1457 SENSOR_DEVICE_ATTR_IN(5);
1458 SENSOR_DEVICE_ATTR_IN(6);
1459
1460 /* Temperatures 1-3 */
1461
1462 #define SENSOR_DEVICE_ATTR_TEMP(ix) \
1463 static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \
1464 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \
1465 static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \
1466 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \
1467 static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \
1468 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \
1469 static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \
1470 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \
1471 static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \
1472 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \
1473 static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \
1474 show_temp, NULL, SYS_TEMP_FAULT, ix-1)
1475
1476 SENSOR_DEVICE_ATTR_TEMP(1);
1477 SENSOR_DEVICE_ATTR_TEMP(2);
1478 SENSOR_DEVICE_ATTR_TEMP(3);
1479
1480 /* Zones 1-3 */
1481
1482 #define SENSOR_DEVICE_ATTR_ZONE(ix) \
1483 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \
1484 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \
1485 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \
1486 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \
1487 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \
1488 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \
1489 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \
1490 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \
1491 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \
1492 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1)
1493
1494 SENSOR_DEVICE_ATTR_ZONE(1);
1495 SENSOR_DEVICE_ATTR_ZONE(2);
1496 SENSOR_DEVICE_ATTR_ZONE(3);
1497
1498 /* Fans 1-4 */
1499
1500 #define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \
1501 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
1502 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
1503 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
1504 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
1505 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
1506 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
1507 static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \
1508 show_fan, set_fan, SYS_FAN_TYPE, ix-1)
1509
1510 SENSOR_DEVICE_ATTR_FAN_1TO4(1);
1511 SENSOR_DEVICE_ATTR_FAN_1TO4(2);
1512 SENSOR_DEVICE_ATTR_FAN_1TO4(3);
1513 SENSOR_DEVICE_ATTR_FAN_1TO4(4);
1514
1515 /* Fans 5-6 */
1516
1517 #define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \
1518 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
1519 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
1520 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
1521 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
1522 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
1523 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
1524 static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \
1525 show_fan, set_fan, SYS_FAN_MAX, ix-1)
1526
1527 SENSOR_DEVICE_ATTR_FAN_5TO6(5);
1528 SENSOR_DEVICE_ATTR_FAN_5TO6(6);
1529
1530 /* PWMs 1-3 */
1531
1532 #define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \
1533 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
1534 show_pwm, set_pwm, SYS_PWM, ix-1); \
1535 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
1536 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
1537 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
1538 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \
1539 static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \
1540 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \
1541 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \
1542 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \
1543 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \
1544 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \
1545 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \
1546 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \
1547 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \
1548 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1)
1549
1550 SENSOR_DEVICE_ATTR_PWM_1TO3(1);
1551 SENSOR_DEVICE_ATTR_PWM_1TO3(2);
1552 SENSOR_DEVICE_ATTR_PWM_1TO3(3);
1553
1554 /* PWMs 5-6 */
1555
1556 #define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \
1557 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
1558 show_pwm, set_pwm, SYS_PWM, ix-1); \
1559 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
1560 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
1561 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
1562 show_pwm, NULL, SYS_PWM_ENABLE, ix-1)
1563
1564 SENSOR_DEVICE_ATTR_PWM_5TO6(5);
1565 SENSOR_DEVICE_ATTR_PWM_5TO6(6);
1566
1567 /* Misc */
1568
1569 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm);
1570 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1571 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */
1572
1573 /* This struct holds all the attributes that are always present and need to be
1574 * created unconditionally. The attributes that need modification of their
1575 * permissions are created read-only and write permissions are added or removed
1576 * on the fly when required */
1577 static struct attribute *dme1737_attr[] ={
1578 /* Voltages */
1579 &sensor_dev_attr_in0_input.dev_attr.attr,
1580 &sensor_dev_attr_in0_min.dev_attr.attr,
1581 &sensor_dev_attr_in0_max.dev_attr.attr,
1582 &sensor_dev_attr_in0_alarm.dev_attr.attr,
1583 &sensor_dev_attr_in1_input.dev_attr.attr,
1584 &sensor_dev_attr_in1_min.dev_attr.attr,
1585 &sensor_dev_attr_in1_max.dev_attr.attr,
1586 &sensor_dev_attr_in1_alarm.dev_attr.attr,
1587 &sensor_dev_attr_in2_input.dev_attr.attr,
1588 &sensor_dev_attr_in2_min.dev_attr.attr,
1589 &sensor_dev_attr_in2_max.dev_attr.attr,
1590 &sensor_dev_attr_in2_alarm.dev_attr.attr,
1591 &sensor_dev_attr_in3_input.dev_attr.attr,
1592 &sensor_dev_attr_in3_min.dev_attr.attr,
1593 &sensor_dev_attr_in3_max.dev_attr.attr,
1594 &sensor_dev_attr_in3_alarm.dev_attr.attr,
1595 &sensor_dev_attr_in4_input.dev_attr.attr,
1596 &sensor_dev_attr_in4_min.dev_attr.attr,
1597 &sensor_dev_attr_in4_max.dev_attr.attr,
1598 &sensor_dev_attr_in4_alarm.dev_attr.attr,
1599 &sensor_dev_attr_in5_input.dev_attr.attr,
1600 &sensor_dev_attr_in5_min.dev_attr.attr,
1601 &sensor_dev_attr_in5_max.dev_attr.attr,
1602 &sensor_dev_attr_in5_alarm.dev_attr.attr,
1603 &sensor_dev_attr_in6_input.dev_attr.attr,
1604 &sensor_dev_attr_in6_min.dev_attr.attr,
1605 &sensor_dev_attr_in6_max.dev_attr.attr,
1606 &sensor_dev_attr_in6_alarm.dev_attr.attr,
1607 /* Temperatures */
1608 &sensor_dev_attr_temp1_input.dev_attr.attr,
1609 &sensor_dev_attr_temp1_min.dev_attr.attr,
1610 &sensor_dev_attr_temp1_max.dev_attr.attr,
1611 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
1612 &sensor_dev_attr_temp1_fault.dev_attr.attr,
1613 &sensor_dev_attr_temp2_input.dev_attr.attr,
1614 &sensor_dev_attr_temp2_min.dev_attr.attr,
1615 &sensor_dev_attr_temp2_max.dev_attr.attr,
1616 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
1617 &sensor_dev_attr_temp2_fault.dev_attr.attr,
1618 &sensor_dev_attr_temp3_input.dev_attr.attr,
1619 &sensor_dev_attr_temp3_min.dev_attr.attr,
1620 &sensor_dev_attr_temp3_max.dev_attr.attr,
1621 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
1622 &sensor_dev_attr_temp3_fault.dev_attr.attr,
1623 /* Zones */
1624 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1625 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1626 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
1627 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr,
1628 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1629 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1630 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
1631 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr,
1632 NULL
1633 };
1634
1635 static const struct attribute_group dme1737_group = {
1636 .attrs = dme1737_attr,
1637 };
1638
1639 /* The following struct holds temp offset attributes, which are not available
1640 * in all chips. The following chips support them:
1641 * DME1737, SCH311x */
1642 static struct attribute *dme1737_temp_offset_attr[] = {
1643 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1644 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1645 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1646 NULL
1647 };
1648
1649 static const struct attribute_group dme1737_temp_offset_group = {
1650 .attrs = dme1737_temp_offset_attr,
1651 };
1652
1653 /* The following struct holds VID related attributes, which are not available
1654 * in all chips. The following chips support them:
1655 * DME1737 */
1656 static struct attribute *dme1737_vid_attr[] = {
1657 &dev_attr_vrm.attr,
1658 &dev_attr_cpu0_vid.attr,
1659 NULL
1660 };
1661
1662 static const struct attribute_group dme1737_vid_group = {
1663 .attrs = dme1737_vid_attr,
1664 };
1665
1666 /* The following struct holds temp zone 3 related attributes, which are not
1667 * available in all chips. The following chips support them:
1668 * DME1737, SCH311x, SCH5027 */
1669 static struct attribute *dme1737_zone3_attr[] = {
1670 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1671 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1672 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
1673 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr,
1674 NULL
1675 };
1676
1677 static const struct attribute_group dme1737_zone3_group = {
1678 .attrs = dme1737_zone3_attr,
1679 };
1680
1681
1682 /* The following struct holds temp zone hysteresis related attributes, which
1683 * are not available in all chips. The following chips support them:
1684 * DME1737, SCH311x */
1685 static struct attribute *dme1737_zone_hyst_attr[] = {
1686 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr,
1687 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr,
1688 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr,
1689 NULL
1690 };
1691
1692 static const struct attribute_group dme1737_zone_hyst_group = {
1693 .attrs = dme1737_zone_hyst_attr,
1694 };
1695
1696 /* The following structs hold the PWM attributes, some of which are optional.
1697 * Their creation depends on the chip configuration which is determined during
1698 * module load. */
1699 static struct attribute *dme1737_pwm1_attr[] = {
1700 &sensor_dev_attr_pwm1.dev_attr.attr,
1701 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1702 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1703 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1704 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
1705 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1706 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
1707 NULL
1708 };
1709 static struct attribute *dme1737_pwm2_attr[] = {
1710 &sensor_dev_attr_pwm2.dev_attr.attr,
1711 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1712 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1713 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1714 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
1715 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1716 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
1717 NULL
1718 };
1719 static struct attribute *dme1737_pwm3_attr[] = {
1720 &sensor_dev_attr_pwm3.dev_attr.attr,
1721 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1722 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1723 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1724 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
1725 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1726 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
1727 NULL
1728 };
1729 static struct attribute *dme1737_pwm5_attr[] = {
1730 &sensor_dev_attr_pwm5.dev_attr.attr,
1731 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
1732 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
1733 NULL
1734 };
1735 static struct attribute *dme1737_pwm6_attr[] = {
1736 &sensor_dev_attr_pwm6.dev_attr.attr,
1737 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
1738 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
1739 NULL
1740 };
1741
1742 static const struct attribute_group dme1737_pwm_group[] = {
1743 { .attrs = dme1737_pwm1_attr },
1744 { .attrs = dme1737_pwm2_attr },
1745 { .attrs = dme1737_pwm3_attr },
1746 { .attrs = NULL },
1747 { .attrs = dme1737_pwm5_attr },
1748 { .attrs = dme1737_pwm6_attr },
1749 };
1750
1751 /* The following struct holds auto PWM min attributes, which are not available
1752 * in all chips. Their creation depends on the chip type which is determined
1753 * during module load. */
1754 static struct attribute *dme1737_auto_pwm_min_attr[] = {
1755 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr,
1756 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr,
1757 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr,
1758 };
1759
1760 /* The following structs hold the fan attributes, some of which are optional.
1761 * Their creation depends on the chip configuration which is determined during
1762 * module load. */
1763 static struct attribute *dme1737_fan1_attr[] = {
1764 &sensor_dev_attr_fan1_input.dev_attr.attr,
1765 &sensor_dev_attr_fan1_min.dev_attr.attr,
1766 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1767 &sensor_dev_attr_fan1_type.dev_attr.attr,
1768 NULL
1769 };
1770 static struct attribute *dme1737_fan2_attr[] = {
1771 &sensor_dev_attr_fan2_input.dev_attr.attr,
1772 &sensor_dev_attr_fan2_min.dev_attr.attr,
1773 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1774 &sensor_dev_attr_fan2_type.dev_attr.attr,
1775 NULL
1776 };
1777 static struct attribute *dme1737_fan3_attr[] = {
1778 &sensor_dev_attr_fan3_input.dev_attr.attr,
1779 &sensor_dev_attr_fan3_min.dev_attr.attr,
1780 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1781 &sensor_dev_attr_fan3_type.dev_attr.attr,
1782 NULL
1783 };
1784 static struct attribute *dme1737_fan4_attr[] = {
1785 &sensor_dev_attr_fan4_input.dev_attr.attr,
1786 &sensor_dev_attr_fan4_min.dev_attr.attr,
1787 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1788 &sensor_dev_attr_fan4_type.dev_attr.attr,
1789 NULL
1790 };
1791 static struct attribute *dme1737_fan5_attr[] = {
1792 &sensor_dev_attr_fan5_input.dev_attr.attr,
1793 &sensor_dev_attr_fan5_min.dev_attr.attr,
1794 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1795 &sensor_dev_attr_fan5_max.dev_attr.attr,
1796 NULL
1797 };
1798 static struct attribute *dme1737_fan6_attr[] = {
1799 &sensor_dev_attr_fan6_input.dev_attr.attr,
1800 &sensor_dev_attr_fan6_min.dev_attr.attr,
1801 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
1802 &sensor_dev_attr_fan6_max.dev_attr.attr,
1803 NULL
1804 };
1805
1806 static const struct attribute_group dme1737_fan_group[] = {
1807 { .attrs = dme1737_fan1_attr },
1808 { .attrs = dme1737_fan2_attr },
1809 { .attrs = dme1737_fan3_attr },
1810 { .attrs = dme1737_fan4_attr },
1811 { .attrs = dme1737_fan5_attr },
1812 { .attrs = dme1737_fan6_attr },
1813 };
1814
1815 /* The permissions of the following zone attributes are changed to read-
1816 * writeable if the chip is *not* locked. Otherwise they stay read-only. */
1817 static struct attribute *dme1737_zone_chmod_attr[] = {
1818 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1819 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1820 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
1821 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1822 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1823 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
1824 NULL
1825 };
1826
1827 static const struct attribute_group dme1737_zone_chmod_group = {
1828 .attrs = dme1737_zone_chmod_attr,
1829 };
1830
1831
1832 /* The permissions of the following zone 3 attributes are changed to read-
1833 * writeable if the chip is *not* locked. Otherwise they stay read-only. */
1834 static struct attribute *dme1737_zone3_chmod_attr[] = {
1835 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1836 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1837 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
1838 NULL
1839 };
1840
1841 static const struct attribute_group dme1737_zone3_chmod_group = {
1842 .attrs = dme1737_zone3_chmod_attr,
1843 };
1844
1845 /* The permissions of the following PWM attributes are changed to read-
1846 * writeable if the chip is *not* locked and the respective PWM is available.
1847 * Otherwise they stay read-only. */
1848 static struct attribute *dme1737_pwm1_chmod_attr[] = {
1849 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1850 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1851 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1852 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
1853 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1854 NULL
1855 };
1856 static struct attribute *dme1737_pwm2_chmod_attr[] = {
1857 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1858 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1859 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1860 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
1861 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1862 NULL
1863 };
1864 static struct attribute *dme1737_pwm3_chmod_attr[] = {
1865 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1866 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1867 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1868 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
1869 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1870 NULL
1871 };
1872 static struct attribute *dme1737_pwm5_chmod_attr[] = {
1873 &sensor_dev_attr_pwm5.dev_attr.attr,
1874 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
1875 NULL
1876 };
1877 static struct attribute *dme1737_pwm6_chmod_attr[] = {
1878 &sensor_dev_attr_pwm6.dev_attr.attr,
1879 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
1880 NULL
1881 };
1882
1883 static const struct attribute_group dme1737_pwm_chmod_group[] = {
1884 { .attrs = dme1737_pwm1_chmod_attr },
1885 { .attrs = dme1737_pwm2_chmod_attr },
1886 { .attrs = dme1737_pwm3_chmod_attr },
1887 { .attrs = NULL },
1888 { .attrs = dme1737_pwm5_chmod_attr },
1889 { .attrs = dme1737_pwm6_chmod_attr },
1890 };
1891
1892 /* Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the
1893 * chip is not locked. Otherwise they are read-only. */
1894 static struct attribute *dme1737_pwm_chmod_attr[] = {
1895 &sensor_dev_attr_pwm1.dev_attr.attr,
1896 &sensor_dev_attr_pwm2.dev_attr.attr,
1897 &sensor_dev_attr_pwm3.dev_attr.attr,
1898 };
1899
1900 /* ---------------------------------------------------------------------
1901 * Super-IO functions
1902 * --------------------------------------------------------------------- */
1903
1904 static inline void dme1737_sio_enter(int sio_cip)
1905 {
1906 outb(0x55, sio_cip);
1907 }
1908
1909 static inline void dme1737_sio_exit(int sio_cip)
1910 {
1911 outb(0xaa, sio_cip);
1912 }
1913
1914 static inline int dme1737_sio_inb(int sio_cip, int reg)
1915 {
1916 outb(reg, sio_cip);
1917 return inb(sio_cip + 1);
1918 }
1919
1920 static inline void dme1737_sio_outb(int sio_cip, int reg, int val)
1921 {
1922 outb(reg, sio_cip);
1923 outb(val, sio_cip + 1);
1924 }
1925
1926 /* ---------------------------------------------------------------------
1927 * Device initialization
1928 * --------------------------------------------------------------------- */
1929
1930 static int dme1737_i2c_get_features(int, struct dme1737_data*);
1931
1932 static void dme1737_chmod_file(struct device *dev,
1933 struct attribute *attr, mode_t mode)
1934 {
1935 if (sysfs_chmod_file(&dev->kobj, attr, mode)) {
1936 dev_warn(dev, "Failed to change permissions of %s.\n",
1937 attr->name);
1938 }
1939 }
1940
1941 static void dme1737_chmod_group(struct device *dev,
1942 const struct attribute_group *group,
1943 mode_t mode)
1944 {
1945 struct attribute **attr;
1946
1947 for (attr = group->attrs; *attr; attr++) {
1948 dme1737_chmod_file(dev, *attr, mode);
1949 }
1950 }
1951
1952 static void dme1737_remove_files(struct device *dev)
1953 {
1954 struct dme1737_data *data = dev_get_drvdata(dev);
1955 int ix;
1956
1957 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
1958 if (data->has_features & HAS_FAN(ix)) {
1959 sysfs_remove_group(&dev->kobj,
1960 &dme1737_fan_group[ix]);
1961 }
1962 }
1963
1964 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
1965 if (data->has_features & HAS_PWM(ix)) {
1966 sysfs_remove_group(&dev->kobj,
1967 &dme1737_pwm_group[ix]);
1968 if ((data->has_features & HAS_PWM_MIN) && ix < 3) {
1969 sysfs_remove_file(&dev->kobj,
1970 dme1737_auto_pwm_min_attr[ix]);
1971 }
1972 }
1973 }
1974
1975 if (data->has_features & HAS_TEMP_OFFSET) {
1976 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group);
1977 }
1978 if (data->has_features & HAS_VID) {
1979 sysfs_remove_group(&dev->kobj, &dme1737_vid_group);
1980 }
1981 if (data->has_features & HAS_ZONE3) {
1982 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group);
1983 }
1984 if (data->has_features & HAS_ZONE_HYST) {
1985 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group);
1986 }
1987 sysfs_remove_group(&dev->kobj, &dme1737_group);
1988
1989 if (!data->client) {
1990 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr);
1991 }
1992 }
1993
1994 static int dme1737_create_files(struct device *dev)
1995 {
1996 struct dme1737_data *data = dev_get_drvdata(dev);
1997 int err, ix;
1998
1999 /* Create a name attribute for ISA devices */
2000 if (!data->client &&
2001 (err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr))) {
2002 goto exit;
2003 }
2004
2005 /* Create standard sysfs attributes */
2006 if ((err = sysfs_create_group(&dev->kobj, &dme1737_group))) {
2007 goto exit_remove;
2008 }
2009
2010 /* Create chip-dependent sysfs attributes */
2011 if ((data->has_features & HAS_TEMP_OFFSET) &&
2012 (err = sysfs_create_group(&dev->kobj,
2013 &dme1737_temp_offset_group))) {
2014 goto exit_remove;
2015 }
2016 if ((data->has_features & HAS_VID) &&
2017 (err = sysfs_create_group(&dev->kobj,
2018 &dme1737_vid_group))) {
2019 goto exit_remove;
2020 }
2021 if ((data->has_features & HAS_ZONE3) &&
2022 (err = sysfs_create_group(&dev->kobj,
2023 &dme1737_zone3_group))) {
2024 goto exit_remove;
2025 }
2026 if ((data->has_features & HAS_ZONE_HYST) &&
2027 (err = sysfs_create_group(&dev->kobj,
2028 &dme1737_zone_hyst_group))) {
2029 goto exit_remove;
2030 }
2031
2032 /* Create fan sysfs attributes */
2033 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
2034 if (data->has_features & HAS_FAN(ix)) {
2035 if ((err = sysfs_create_group(&dev->kobj,
2036 &dme1737_fan_group[ix]))) {
2037 goto exit_remove;
2038 }
2039 }
2040 }
2041
2042 /* Create PWM sysfs attributes */
2043 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
2044 if (data->has_features & HAS_PWM(ix)) {
2045 if ((err = sysfs_create_group(&dev->kobj,
2046 &dme1737_pwm_group[ix]))) {
2047 goto exit_remove;
2048 }
2049 if ((data->has_features & HAS_PWM_MIN) && ix < 3 &&
2050 (err = sysfs_create_file(&dev->kobj,
2051 dme1737_auto_pwm_min_attr[ix]))) {
2052 goto exit_remove;
2053 }
2054 }
2055 }
2056
2057 /* Inform if the device is locked. Otherwise change the permissions of
2058 * selected attributes from read-only to read-writeable. */
2059 if (data->config & 0x02) {
2060 dev_info(dev, "Device is locked. Some attributes "
2061 "will be read-only.\n");
2062 } else {
2063 /* Change permissions of zone sysfs attributes */
2064 dme1737_chmod_group(dev, &dme1737_zone_chmod_group,
2065 S_IRUGO | S_IWUSR);
2066
2067 /* Change permissions of chip-dependent sysfs attributes */
2068 if (data->has_features & HAS_TEMP_OFFSET) {
2069 dme1737_chmod_group(dev, &dme1737_temp_offset_group,
2070 S_IRUGO | S_IWUSR);
2071 }
2072 if (data->has_features & HAS_ZONE3) {
2073 dme1737_chmod_group(dev, &dme1737_zone3_chmod_group,
2074 S_IRUGO | S_IWUSR);
2075 }
2076 if (data->has_features & HAS_ZONE_HYST) {
2077 dme1737_chmod_group(dev, &dme1737_zone_hyst_group,
2078 S_IRUGO | S_IWUSR);
2079 }
2080
2081 /* Change permissions of PWM sysfs attributes */
2082 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) {
2083 if (data->has_features & HAS_PWM(ix)) {
2084 dme1737_chmod_group(dev,
2085 &dme1737_pwm_chmod_group[ix],
2086 S_IRUGO | S_IWUSR);
2087 if ((data->has_features & HAS_PWM_MIN) &&
2088 ix < 3) {
2089 dme1737_chmod_file(dev,
2090 dme1737_auto_pwm_min_attr[ix],
2091 S_IRUGO | S_IWUSR);
2092 }
2093 }
2094 }
2095
2096 /* Change permissions of pwm[1-3] if in manual mode */
2097 for (ix = 0; ix < 3; ix++) {
2098 if ((data->has_features & HAS_PWM(ix)) &&
2099 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) {
2100 dme1737_chmod_file(dev,
2101 dme1737_pwm_chmod_attr[ix],
2102 S_IRUGO | S_IWUSR);
2103 }
2104 }
2105 }
2106
2107 return 0;
2108
2109 exit_remove:
2110 dme1737_remove_files(dev);
2111 exit:
2112 return err;
2113 }
2114
2115 static int dme1737_init_device(struct device *dev)
2116 {
2117 struct dme1737_data *data = dev_get_drvdata(dev);
2118 struct i2c_client *client = data->client;
2119 int ix;
2120 u8 reg;
2121
2122 /* Point to the right nominal voltages array */
2123 data->in_nominal = IN_NOMINAL(data->type);
2124
2125 data->config = dme1737_read(data, DME1737_REG_CONFIG);
2126 /* Inform if part is not monitoring/started */
2127 if (!(data->config & 0x01)) {
2128 if (!force_start) {
2129 dev_err(dev, "Device is not monitoring. "
2130 "Use the force_start load parameter to "
2131 "override.\n");
2132 return -EFAULT;
2133 }
2134
2135 /* Force monitoring */
2136 data->config |= 0x01;
2137 dme1737_write(data, DME1737_REG_CONFIG, data->config);
2138 }
2139 /* Inform if part is not ready */
2140 if (!(data->config & 0x04)) {
2141 dev_err(dev, "Device is not ready.\n");
2142 return -EFAULT;
2143 }
2144
2145 /* Determine which optional fan and pwm features are enabled (only
2146 * valid for I2C devices) */
2147 if (client) { /* I2C chip */
2148 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2);
2149 /* Check if optional fan3 input is enabled */
2150 if (data->config2 & 0x04) {
2151 data->has_features |= HAS_FAN(2);
2152 }
2153
2154 /* Fan4 and pwm3 are only available if the client's I2C address
2155 * is the default 0x2e. Otherwise the I/Os associated with
2156 * these functions are used for addr enable/select. */
2157 if (client->addr == 0x2e) {
2158 data->has_features |= HAS_FAN(3) | HAS_PWM(2);
2159 }
2160
2161 /* Determine which of the optional fan[5-6] and pwm[5-6]
2162 * features are enabled. For this, we need to query the runtime
2163 * registers through the Super-IO LPC interface. Try both
2164 * config ports 0x2e and 0x4e. */
2165 if (dme1737_i2c_get_features(0x2e, data) &&
2166 dme1737_i2c_get_features(0x4e, data)) {
2167 dev_warn(dev, "Failed to query Super-IO for optional "
2168 "features.\n");
2169 }
2170 }
2171
2172 /* Fan[1-2] and pwm[1-2] are present in all chips */
2173 data->has_features |= HAS_FAN(0) | HAS_FAN(1) | HAS_PWM(0) | HAS_PWM(1);
2174
2175 /* Chip-dependent features */
2176 switch (data->type) {
2177 case dme1737:
2178 data->has_features |= HAS_TEMP_OFFSET | HAS_VID | HAS_ZONE3 |
2179 HAS_ZONE_HYST | HAS_PWM_MIN;
2180 break;
2181 case sch311x:
2182 data->has_features |= HAS_TEMP_OFFSET | HAS_ZONE3 |
2183 HAS_ZONE_HYST | HAS_PWM_MIN | HAS_FAN(2) | HAS_PWM(2);
2184 break;
2185 case sch5027:
2186 data->has_features |= HAS_ZONE3;
2187 break;
2188 case sch5127:
2189 data->has_features |= HAS_FAN(2) | HAS_PWM(2);
2190 break;
2191 default:
2192 break;
2193 }
2194
2195 dev_info(dev, "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, "
2196 "fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n",
2197 (data->has_features & HAS_PWM(2)) ? "yes" : "no",
2198 (data->has_features & HAS_PWM(4)) ? "yes" : "no",
2199 (data->has_features & HAS_PWM(5)) ? "yes" : "no",
2200 (data->has_features & HAS_FAN(2)) ? "yes" : "no",
2201 (data->has_features & HAS_FAN(3)) ? "yes" : "no",
2202 (data->has_features & HAS_FAN(4)) ? "yes" : "no",
2203 (data->has_features & HAS_FAN(5)) ? "yes" : "no");
2204
2205 reg = dme1737_read(data, DME1737_REG_TACH_PWM);
2206 /* Inform if fan-to-pwm mapping differs from the default */
2207 if (client && reg != 0xa4) { /* I2C chip */
2208 dev_warn(dev, "Non-standard fan to pwm mapping: "
2209 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, "
2210 "fan4->pwm%d. Please report to the driver "
2211 "maintainer.\n",
2212 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2213 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1);
2214 } else if (!client && reg != 0x24) { /* ISA chip */
2215 dev_warn(dev, "Non-standard fan to pwm mapping: "
2216 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. "
2217 "Please report to the driver maintainer.\n",
2218 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2219 ((reg >> 4) & 0x03) + 1);
2220 }
2221
2222 /* Switch pwm[1-3] to manual mode if they are currently disabled and
2223 * set the duty-cycles to 0% (which is identical to the PWMs being
2224 * disabled). */
2225 if (!(data->config & 0x02)) {
2226 for (ix = 0; ix < 3; ix++) {
2227 data->pwm_config[ix] = dme1737_read(data,
2228 DME1737_REG_PWM_CONFIG(ix));
2229 if ((data->has_features & HAS_PWM(ix)) &&
2230 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) {
2231 dev_info(dev, "Switching pwm%d to "
2232 "manual mode.\n", ix + 1);
2233 data->pwm_config[ix] = PWM_EN_TO_REG(1,
2234 data->pwm_config[ix]);
2235 dme1737_write(data, DME1737_REG_PWM(ix), 0);
2236 dme1737_write(data,
2237 DME1737_REG_PWM_CONFIG(ix),
2238 data->pwm_config[ix]);
2239 }
2240 }
2241 }
2242
2243 /* Initialize the default PWM auto channels zone (acz) assignments */
2244 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */
2245 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */
2246 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */
2247
2248 /* Set VRM */
2249 if (data->has_features & HAS_VID) {
2250 data->vrm = vid_which_vrm();
2251 }
2252
2253 return 0;
2254 }
2255
2256 /* ---------------------------------------------------------------------
2257 * I2C device detection and registration
2258 * --------------------------------------------------------------------- */
2259
2260 static struct i2c_driver dme1737_i2c_driver;
2261
2262 static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data)
2263 {
2264 int err = 0, reg;
2265 u16 addr;
2266
2267 dme1737_sio_enter(sio_cip);
2268
2269 /* Check device ID
2270 * We currently know about two kinds of DME1737 and SCH5027. */
2271 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2272 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 ||
2273 reg == SCH5027_ID)) {
2274 err = -ENODEV;
2275 goto exit;
2276 }
2277
2278 /* Select logical device A (runtime registers) */
2279 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2280
2281 /* Get the base address of the runtime registers */
2282 if (!(addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2283 dme1737_sio_inb(sio_cip, 0x61))) {
2284 err = -ENODEV;
2285 goto exit;
2286 }
2287
2288 /* Read the runtime registers to determine which optional features
2289 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set
2290 * to '10' if the respective feature is enabled. */
2291 if ((inb(addr + 0x43) & 0x0c) == 0x08) { /* fan6 */
2292 data->has_features |= HAS_FAN(5);
2293 }
2294 if ((inb(addr + 0x44) & 0x0c) == 0x08) { /* pwm6 */
2295 data->has_features |= HAS_PWM(5);
2296 }
2297 if ((inb(addr + 0x45) & 0x0c) == 0x08) { /* fan5 */
2298 data->has_features |= HAS_FAN(4);
2299 }
2300 if ((inb(addr + 0x46) & 0x0c) == 0x08) { /* pwm5 */
2301 data->has_features |= HAS_PWM(4);
2302 }
2303
2304 exit:
2305 dme1737_sio_exit(sio_cip);
2306
2307 return err;
2308 }
2309
2310 /* Return 0 if detection is successful, -ENODEV otherwise */
2311 static int dme1737_i2c_detect(struct i2c_client *client,
2312 struct i2c_board_info *info)
2313 {
2314 struct i2c_adapter *adapter = client->adapter;
2315 struct device *dev = &adapter->dev;
2316 u8 company, verstep = 0;
2317 const char *name;
2318
2319 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
2320 return -ENODEV;
2321 }
2322
2323 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY);
2324 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP);
2325
2326 if (company == DME1737_COMPANY_SMSC &&
2327 verstep == SCH5027_VERSTEP) {
2328 name = "sch5027";
2329 } else if (company == DME1737_COMPANY_SMSC &&
2330 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) {
2331 name = "dme1737";
2332 } else {
2333 return -ENODEV;
2334 }
2335
2336 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n",
2337 verstep == SCH5027_VERSTEP ? "SCH5027" : "DME1737",
2338 client->addr, verstep);
2339 strlcpy(info->type, name, I2C_NAME_SIZE);
2340
2341 return 0;
2342 }
2343
2344 static int dme1737_i2c_probe(struct i2c_client *client,
2345 const struct i2c_device_id *id)
2346 {
2347 struct dme1737_data *data;
2348 struct device *dev = &client->dev;
2349 int err;
2350
2351 data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL);
2352 if (!data) {
2353 err = -ENOMEM;
2354 goto exit;
2355 }
2356
2357 i2c_set_clientdata(client, data);
2358 data->type = id->driver_data;
2359 data->client = client;
2360 data->name = client->name;
2361 mutex_init(&data->update_lock);
2362
2363 /* Initialize the DME1737 chip */
2364 if ((err = dme1737_init_device(dev))) {
2365 dev_err(dev, "Failed to initialize device.\n");
2366 goto exit_kfree;
2367 }
2368
2369 /* Create sysfs files */
2370 if ((err = dme1737_create_files(dev))) {
2371 dev_err(dev, "Failed to create sysfs files.\n");
2372 goto exit_kfree;
2373 }
2374
2375 /* Register device */
2376 data->hwmon_dev = hwmon_device_register(dev);
2377 if (IS_ERR(data->hwmon_dev)) {
2378 dev_err(dev, "Failed to register device.\n");
2379 err = PTR_ERR(data->hwmon_dev);
2380 goto exit_remove;
2381 }
2382
2383 return 0;
2384
2385 exit_remove:
2386 dme1737_remove_files(dev);
2387 exit_kfree:
2388 kfree(data);
2389 exit:
2390 return err;
2391 }
2392
2393 static int dme1737_i2c_remove(struct i2c_client *client)
2394 {
2395 struct dme1737_data *data = i2c_get_clientdata(client);
2396
2397 hwmon_device_unregister(data->hwmon_dev);
2398 dme1737_remove_files(&client->dev);
2399
2400 kfree(data);
2401 return 0;
2402 }
2403
2404 static const struct i2c_device_id dme1737_id[] = {
2405 { "dme1737", dme1737 },
2406 { "sch5027", sch5027 },
2407 { }
2408 };
2409 MODULE_DEVICE_TABLE(i2c, dme1737_id);
2410
2411 static struct i2c_driver dme1737_i2c_driver = {
2412 .class = I2C_CLASS_HWMON,
2413 .driver = {
2414 .name = "dme1737",
2415 },
2416 .probe = dme1737_i2c_probe,
2417 .remove = dme1737_i2c_remove,
2418 .id_table = dme1737_id,
2419 .detect = dme1737_i2c_detect,
2420 .address_list = normal_i2c,
2421 };
2422
2423 /* ---------------------------------------------------------------------
2424 * ISA device detection and registration
2425 * --------------------------------------------------------------------- */
2426
2427 static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr)
2428 {
2429 int err = 0, reg;
2430 unsigned short base_addr;
2431
2432 dme1737_sio_enter(sio_cip);
2433
2434 /* Check device ID
2435 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127 */
2436 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2437 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID ||
2438 reg == SCH5127_ID)) {
2439 err = -ENODEV;
2440 goto exit;
2441 }
2442
2443 /* Select logical device A (runtime registers) */
2444 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2445
2446 /* Get the base address of the runtime registers */
2447 if (!(base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2448 dme1737_sio_inb(sio_cip, 0x61))) {
2449 printk(KERN_ERR "dme1737: Base address not set.\n");
2450 err = -ENODEV;
2451 goto exit;
2452 }
2453
2454 /* Access to the hwmon registers is through an index/data register
2455 * pair located at offset 0x70/0x71. */
2456 *addr = base_addr + 0x70;
2457
2458 exit:
2459 dme1737_sio_exit(sio_cip);
2460 return err;
2461 }
2462
2463 static int __init dme1737_isa_device_add(unsigned short addr)
2464 {
2465 struct resource res = {
2466 .start = addr,
2467 .end = addr + DME1737_EXTENT - 1,
2468 .name = "dme1737",
2469 .flags = IORESOURCE_IO,
2470 };
2471 int err;
2472
2473 err = acpi_check_resource_conflict(&res);
2474 if (err)
2475 goto exit;
2476
2477 if (!(pdev = platform_device_alloc("dme1737", addr))) {
2478 printk(KERN_ERR "dme1737: Failed to allocate device.\n");
2479 err = -ENOMEM;
2480 goto exit;
2481 }
2482
2483 if ((err = platform_device_add_resources(pdev, &res, 1))) {
2484 printk(KERN_ERR "dme1737: Failed to add device resource "
2485 "(err = %d).\n", err);
2486 goto exit_device_put;
2487 }
2488
2489 if ((err = platform_device_add(pdev))) {
2490 printk(KERN_ERR "dme1737: Failed to add device (err = %d).\n",
2491 err);
2492 goto exit_device_put;
2493 }
2494
2495 return 0;
2496
2497 exit_device_put:
2498 platform_device_put(pdev);
2499 pdev = NULL;
2500 exit:
2501 return err;
2502 }
2503
2504 static int __devinit dme1737_isa_probe(struct platform_device *pdev)
2505 {
2506 u8 company, device;
2507 struct resource *res;
2508 struct dme1737_data *data;
2509 struct device *dev = &pdev->dev;
2510 int err;
2511
2512 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2513 if (!request_region(res->start, DME1737_EXTENT, "dme1737")) {
2514 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n",
2515 (unsigned short)res->start,
2516 (unsigned short)res->start + DME1737_EXTENT - 1);
2517 err = -EBUSY;
2518 goto exit;
2519 }
2520
2521 if (!(data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL))) {
2522 err = -ENOMEM;
2523 goto exit_release_region;
2524 }
2525
2526 data->addr = res->start;
2527 platform_set_drvdata(pdev, data);
2528
2529 /* Skip chip detection if module is loaded with force_id parameter */
2530 switch (force_id) {
2531 case SCH3112_ID:
2532 case SCH3114_ID:
2533 case SCH3116_ID:
2534 data->type = sch311x;
2535 break;
2536 case SCH5127_ID:
2537 data->type = sch5127;
2538 break;
2539 default:
2540 company = dme1737_read(data, DME1737_REG_COMPANY);
2541 device = dme1737_read(data, DME1737_REG_DEVICE);
2542
2543 if ((company == DME1737_COMPANY_SMSC) &&
2544 (device == SCH311X_DEVICE)) {
2545 data->type = sch311x;
2546 } else if ((company == DME1737_COMPANY_SMSC) &&
2547 (device == SCH5127_DEVICE)) {
2548 data->type = sch5127;
2549 } else {
2550 err = -ENODEV;
2551 goto exit_kfree;
2552 }
2553 }
2554
2555 if (data->type == sch5127) {
2556 data->name = "sch5127";
2557 } else {
2558 data->name = "sch311x";
2559 }
2560
2561 /* Initialize the mutex */
2562 mutex_init(&data->update_lock);
2563
2564 dev_info(dev, "Found a %s chip at 0x%04x\n",
2565 data->type == sch5127 ? "SCH5127" : "SCH311x", data->addr);
2566
2567 /* Initialize the chip */
2568 if ((err = dme1737_init_device(dev))) {
2569 dev_err(dev, "Failed to initialize device.\n");
2570 goto exit_kfree;
2571 }
2572
2573 /* Create sysfs files */
2574 if ((err = dme1737_create_files(dev))) {
2575 dev_err(dev, "Failed to create sysfs files.\n");
2576 goto exit_kfree;
2577 }
2578
2579 /* Register device */
2580 data->hwmon_dev = hwmon_device_register(dev);
2581 if (IS_ERR(data->hwmon_dev)) {
2582 dev_err(dev, "Failed to register device.\n");
2583 err = PTR_ERR(data->hwmon_dev);
2584 goto exit_remove_files;
2585 }
2586
2587 return 0;
2588
2589 exit_remove_files:
2590 dme1737_remove_files(dev);
2591 exit_kfree:
2592 platform_set_drvdata(pdev, NULL);
2593 kfree(data);
2594 exit_release_region:
2595 release_region(res->start, DME1737_EXTENT);
2596 exit:
2597 return err;
2598 }
2599
2600 static int __devexit dme1737_isa_remove(struct platform_device *pdev)
2601 {
2602 struct dme1737_data *data = platform_get_drvdata(pdev);
2603
2604 hwmon_device_unregister(data->hwmon_dev);
2605 dme1737_remove_files(&pdev->dev);
2606 release_region(data->addr, DME1737_EXTENT);
2607 platform_set_drvdata(pdev, NULL);
2608 kfree(data);
2609
2610 return 0;
2611 }
2612
2613 static struct platform_driver dme1737_isa_driver = {
2614 .driver = {
2615 .owner = THIS_MODULE,
2616 .name = "dme1737",
2617 },
2618 .probe = dme1737_isa_probe,
2619 .remove = __devexit_p(dme1737_isa_remove),
2620 };
2621
2622 /* ---------------------------------------------------------------------
2623 * Module initialization and cleanup
2624 * --------------------------------------------------------------------- */
2625
2626 static int __init dme1737_init(void)
2627 {
2628 int err;
2629 unsigned short addr;
2630
2631 if ((err = i2c_add_driver(&dme1737_i2c_driver))) {
2632 goto exit;
2633 }
2634
2635 if (dme1737_isa_detect(0x2e, &addr) &&
2636 dme1737_isa_detect(0x4e, &addr) &&
2637 (!probe_all_addr ||
2638 (dme1737_isa_detect(0x162e, &addr) &&
2639 dme1737_isa_detect(0x164e, &addr)))) {
2640 /* Return 0 if we didn't find an ISA device */
2641 return 0;
2642 }
2643
2644 if ((err = platform_driver_register(&dme1737_isa_driver))) {
2645 goto exit_del_i2c_driver;
2646 }
2647
2648 /* Sets global pdev as a side effect */
2649 if ((err = dme1737_isa_device_add(addr))) {
2650 goto exit_del_isa_driver;
2651 }
2652
2653 return 0;
2654
2655 exit_del_isa_driver:
2656 platform_driver_unregister(&dme1737_isa_driver);
2657 exit_del_i2c_driver:
2658 i2c_del_driver(&dme1737_i2c_driver);
2659 exit:
2660 return err;
2661 }
2662
2663 static void __exit dme1737_exit(void)
2664 {
2665 if (pdev) {
2666 platform_device_unregister(pdev);
2667 platform_driver_unregister(&dme1737_isa_driver);
2668 }
2669
2670 i2c_del_driver(&dme1737_i2c_driver);
2671 }
2672
2673 MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>");
2674 MODULE_DESCRIPTION("DME1737 sensors");
2675 MODULE_LICENSE("GPL");
2676
2677 module_init(dme1737_init);
2678 module_exit(dme1737_exit);
kernel-based virtual machine