include/asm-m68knommu/mcfcache.h

   1 /****************************************************************************/
   2
   3 /*
   4  *      mcfcache.h -- ColdFire CPU cache support code
   5  *
   6  *      (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com>
   7  */
   8
   9 /****************************************************************************/
  10 #ifndef __M68KNOMMU_MCFCACHE_H
  11 #define __M68KNOMMU_MCFCACHE_H
  12 /****************************************************************************/
  13
  14 #include <linux/config.h>
  15
  16 /*
  17  *      The different ColdFire families have different cache arrangments.
  18  *      Everything from a small instruction only cache, to configurable
  19  *      data and/or instruction cache, to unified instruction/data, to
  20  *      harvard style separate instruction and data caches.
  21  */
  22
  23 #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
  24 /*
  25  *      Simple version 2 core cache. These have instruction cache only,
  26  *      we just need to invalidate it and enable it.
  27  */
  28 .macro CACHE_ENABLE
  29         movel   #0x01000000,%d0         /* invalidate cache cmd */
  30         movec   %d0,%CACR               /* do invalidate cache */
  31         movel   #0x80000100,%d0         /* setup cache mask */
  32         movec   %d0,%CACR               /* enable cache */
  33 .endm
  34 #endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
  35
  36 #if defined(CONFIG_M523x) || defined(CONFIG_M527x)
  37 /*
  38  *      New version 2 cores have a configurable split cache arrangement.
  39  *      For now I am just enabling instruction cache - but ultimately I
  40  *      think a split instruction/data cache would be better.
  41  */
  42 .macro CACHE_ENABLE
  43         movel   #0x01400000,%d0
  44         movec   %d0,%CACR               /* invalidate cache */
  45         nop
  46         movel   #0x0000c000,%d0         /* set SDRAM cached only */
  47         movec   %d0,%ACR0
  48         movel   #0x00000000,%d0         /* no other regions cached */
  49         movec   %d0,%ACR1
  50         movel   #0x80400100,%d0         /* configure cache */
  51         movec   %d0,%CACR               /* enable cache */
  52         nop
  53 .endm
  54 #endif /* CONFIG_M523x || CONFIG_M527x */
  55
  56 #if defined(CONFIG_M528x)
  57 .macro CACHE_ENABLE
  58         nop
  59         movel   #0x01000000, %d0
  60         movec   %d0, %CACR              /* Invalidate cache */
  61         nop
  62         movel   #0x0000c020, %d0        /* Set SDRAM cached only */
  63         movec   %d0, %ACR0
  64         movel   #0xff00c000, %d0        /* Cache Flash also */
  65         movec   %d0, %ACR1
  66         movel   #0x80000200, %d0        /* Setup cache mask */
  67         movec   %d0, %CACR              /* Enable cache */
  68         nop
  69 .endm
  70 #endif /* CONFIG_M528x */
  71
  72 #if defined(CONFIG_M5249) || defined(CONFIG_M5307)
  73 /*
  74  *      The version 3 core cache. Oddly enough the version 2 core 5249
  75  *      has the same SDRAM and cache setup as the version 3 cores.
  76  *      This is a single unified instruction/data cache.
  77  */
  78 .macro CACHE_ENABLE
  79         movel   #0x01000000,%d0         /* invalidate whole cache */
  80         movec   %d0,%CACR
  81         nop
  82 #if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3)
  83         movel   #0x0000c000,%d0         /* set SDRAM cached (write-thru) */
  84 #else
  85         movel   #0x0000c020,%d0         /* set SDRAM cached (copyback) */
  86 #endif
  87         movec   %d0,%ACR0
  88         movel   #0x00000000,%d0         /* no other regions cached */
  89         movec   %d0,%ACR1
  90         movel   #0xa0000200,%d0         /* enable cache */
  91         movec   %d0,%CACR
  92         nop
  93 .endm
  94 #endif /* CONFIG_M5249 || CONFIG_M5307 */
  95
  96 #if defined(CONFIG_M5407)
  97 /*
  98  *      Version 4 cores have a true harvard style separate instruction
  99  *      and data cache. Invalidate and enable cache, also enable write
 100  *      buffers and branch accelerator.
 101  */
 102 .macro CACHE_ENABLE
 103         movel   #0x01040100,%d0         /* invalidate whole cache */
 104         movec   %d0,%CACR
 105         nop
 106         movel   #0x000fc000,%d0         /* set SDRAM cached only */
 107         movec   %d0, %ACR0
 108         movel   #0x00000000,%d0         /* no other regions cached */
 109         movec   %d0, %ACR1
 110         movel   #0x000fc000,%d0         /* set SDRAM cached only */
 111         movec   %d0, %ACR2
 112         movel   #0x00000000,%d0         /* no other regions cached */
 113         movec   %d0, %ACR3
 114         movel   #0xb6088400,%d0         /* enable caches */
 115         movec   %d0,%CACR
 116         nop
 117 .endm
 118 #endif /* CONFIG_M5407 */
 119
 120 #if defined(CONFIG_M520x)
 121 .macro CACHE_ENABLE
 122         move.l  #0x01000000,%d0         /* invalidate whole cache */
 123         movec   %d0,%CACR
 124         nop
 125         move.l  #0x0000c000,%d0         /* set SDRAM cached (write-thru) */
 126         movec   %d0,%ACR0
 127         move.l  #0x00000000,%d0         /* no other regions cached */
 128         movec   %d0,%ACR1
 129         move.l  #0x80400000,%d0         /* enable 8K instruction cache */
 130         movec   %d0,%CACR
 131         nop
 132 .endm
 133 #endif /* CONFIG_M520x */
 134
 135 /****************************************************************************/
 136 #endif  /* __M68KNOMMU_MCFCACHE_H */