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[SUNRPC]: print unsigned integers in stats
[linux-2.6/kvm.git] / sound / pci / intel8x0.c
blob7b548416dcefc086295511b6845359975bb8dda8
1 /*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29 #include <sound/driver.h>
30 #include <asm/io.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/slab.h>
36 #include <linux/moduleparam.h>
37 #include <sound/core.h>
38 #include <sound/pcm.h>
39 #include <sound/ac97_codec.h>
40 #include <sound/info.h>
41 #include <sound/initval.h>
42 /* for 440MX workaround */
43 #include <asm/pgtable.h>
44 #include <asm/cacheflush.h>
45
46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48 MODULE_LICENSE("GPL");
49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50 "{Intel,82901AB-ICH0},"
51 "{Intel,82801BA-ICH2},"
52 "{Intel,82801CA-ICH3},"
53 "{Intel,82801DB-ICH4},"
54 "{Intel,ICH5},"
55 "{Intel,ICH6},"
56 "{Intel,ICH7},"
57 "{Intel,6300ESB},"
58 "{Intel,ESB2},"
59 "{Intel,MX440},"
60 "{SiS,SI7012},"
61 "{NVidia,nForce Audio},"
62 "{NVidia,nForce2 Audio},"
63 "{AMD,AMD768},"
64 "{AMD,AMD8111},"
65 "{ALI,M5455}}");
66
67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
69 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
70 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
71 static char *ac97_quirk[SNDRV_CARDS];
72 static int buggy_irq[SNDRV_CARDS];
73 static int xbox[SNDRV_CARDS];
74
75 #ifdef SUPPORT_MIDI
76 static int mpu_port[SNDRV_CARDS]; /* disabled */
77 #endif
78
79 module_param_array(index, int, NULL, 0444);
80 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
81 module_param_array(id, charp, NULL, 0444);
82 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
83 module_param_array(enable, bool, NULL, 0444);
84 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
85 module_param_array(ac97_clock, int, NULL, 0444);
86 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
87 module_param_array(ac97_quirk, charp, NULL, 0444);
88 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
89 module_param_array(buggy_irq, bool, NULL, 0444);
90 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
91 module_param_array(xbox, bool, NULL, 0444);
92 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
93
94 /*
95 * Direct registers
96 */
97
98 #ifndef PCI_DEVICE_ID_INTEL_82801
99 #define PCI_DEVICE_ID_INTEL_82801 0x2415
100 #endif
101 #ifndef PCI_DEVICE_ID_INTEL_82901
102 #define PCI_DEVICE_ID_INTEL_82901 0x2425
103 #endif
104 #ifndef PCI_DEVICE_ID_INTEL_82801BA
105 #define PCI_DEVICE_ID_INTEL_82801BA 0x2445
106 #endif
107 #ifndef PCI_DEVICE_ID_INTEL_440MX
108 #define PCI_DEVICE_ID_INTEL_440MX 0x7195
109 #endif
110 #ifndef PCI_DEVICE_ID_INTEL_ICH3
111 #define PCI_DEVICE_ID_INTEL_ICH3 0x2485
112 #endif
113 #ifndef PCI_DEVICE_ID_INTEL_ICH4
114 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c5
115 #endif
116 #ifndef PCI_DEVICE_ID_INTEL_ICH5
117 #define PCI_DEVICE_ID_INTEL_ICH5 0x24d5
118 #endif
119 #ifndef PCI_DEVICE_ID_INTEL_ESB_5
120 #define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
121 #endif
122 #ifndef PCI_DEVICE_ID_INTEL_ICH6_18
123 #define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e
124 #endif
125 #ifndef PCI_DEVICE_ID_INTEL_ICH7_20
126 #define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
127 #endif
128 #ifndef PCI_DEVICE_ID_INTEL_ESB2_14
129 #define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698
130 #endif
131 #ifndef PCI_DEVICE_ID_SI_7012
132 #define PCI_DEVICE_ID_SI_7012 0x7012
133 #endif
134 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
135 #define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
136 #endif
137 #ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
138 #define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
139 #endif
140 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
141 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
142 #endif
143 #ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
144 #define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a
145 #endif
146 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
147 #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
148 #endif
149 #ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
150 #define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
151 #endif
152
153 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
154
155 #define ICHREG(x) ICH_REG_##x
156
157 #define DEFINE_REGSET(name,base) \
158 enum { \
159 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
160 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
161 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
162 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
163 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
164 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
165 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
166 };
167
168 /* busmaster blocks */
169 DEFINE_REGSET(OFF, 0); /* offset */
170 DEFINE_REGSET(PI, 0x00); /* PCM in */
171 DEFINE_REGSET(PO, 0x10); /* PCM out */
172 DEFINE_REGSET(MC, 0x20); /* Mic in */
173
174 /* ICH4 busmaster blocks */
175 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
176 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
177 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
178
179 /* values for each busmaster block */
180
181 /* LVI */
182 #define ICH_REG_LVI_MASK 0x1f
183
184 /* SR */
185 #define ICH_FIFOE 0x10 /* FIFO error */
186 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
187 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
188 #define ICH_CELV 0x02 /* current equals last valid */
189 #define ICH_DCH 0x01 /* DMA controller halted */
190
191 /* PIV */
192 #define ICH_REG_PIV_MASK 0x1f /* mask */
193
194 /* CR */
195 #define ICH_IOCE 0x10 /* interrupt on completion enable */
196 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
197 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
198 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
199 #define ICH_STARTBM 0x01 /* start busmaster operation */
200
201
202 /* global block */
203 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
204 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
205 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
206 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
207 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
208 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
209 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
210 #define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
211 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
212 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
213 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
214 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
215 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
216 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
217 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
218 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
219 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
220 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
221 #define ICH_ACLINK 0x00000008 /* AClink shut off */
222 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
223 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
224 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
225 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
226 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
227 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
228 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
229 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
230 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
231 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
232 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
233 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
234 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
235 #define ICH_MD3 0x00020000 /* modem power down semaphore */
236 #define ICH_AD3 0x00010000 /* audio power down semaphore */
237 #define ICH_RCS 0x00008000 /* read completion status */
238 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
239 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
240 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
241 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
242 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
243 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
244 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
245 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
246 #define ICH_POINT 0x00000040 /* playback interrupt */
247 #define ICH_PIINT 0x00000020 /* capture interrupt */
248 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
249 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
250 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
251 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
252 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
253 #define ICH_CAS 0x01 /* codec access semaphore */
254 #define ICH_REG_SDM 0x80
255 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
256 #define ICH_DI2L_SHIFT 6
257 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
258 #define ICH_DI1L_SHIFT 4
259 #define ICH_SE 0x00000008 /* steer enable */
260 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
261
262 #define ICH_MAX_FRAGS 32 /* max hw frags */
263
264
265 /*
266 * registers for Ali5455
267 */
268
269 /* ALi 5455 busmaster blocks */
270 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
271 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
272 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
273 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
274 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
275 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
276 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
277 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
278 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
279 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
280 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
281
282 enum {
283 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
284 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
285 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
286 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
287 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
288 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
289 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
290 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
291 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
292 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
293 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
294 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
295 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
296 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
297 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
298 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
299 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
300 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
301 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
302 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
303 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
304 };
305
306 #define ALI_CAS_SEM_BUSY 0x80000000
307 #define ALI_CPR_ADDR_SECONDARY 0x100
308 #define ALI_CPR_ADDR_READ 0x80
309 #define ALI_CSPSR_CODEC_READY 0x08
310 #define ALI_CSPSR_READ_OK 0x02
311 #define ALI_CSPSR_WRITE_OK 0x01
312
313 /* interrupts for the whole chip by interrupt status register finish */
314
315 #define ALI_INT_MICIN2 (1<<26)
316 #define ALI_INT_PCMIN2 (1<<25)
317 #define ALI_INT_I2SIN (1<<24)
318 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
319 #define ALI_INT_SPDIFIN (1<<22)
320 #define ALI_INT_LFEOUT (1<<21)
321 #define ALI_INT_CENTEROUT (1<<20)
322 #define ALI_INT_CODECSPDIFOUT (1<<19)
323 #define ALI_INT_MICIN (1<<18)
324 #define ALI_INT_PCMOUT (1<<17)
325 #define ALI_INT_PCMIN (1<<16)
326 #define ALI_INT_CPRAIS (1<<7) /* command port available */
327 #define ALI_INT_SPRAIS (1<<5) /* status port available */
328 #define ALI_INT_GPIO (1<<1)
329 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
330
331 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
332 #define ICH_ALI_SC_AC97_DBL (1<<30)
333 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
334 #define ICH_ALI_SC_IN_BITS (3<<18)
335 #define ICH_ALI_SC_OUT_BITS (3<<16)
336 #define ICH_ALI_SC_6CH_CFG (3<<14)
337 #define ICH_ALI_SC_PCM_4 (1<<8)
338 #define ICH_ALI_SC_PCM_6 (2<<8)
339 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
340
341 #define ICH_ALI_SS_SEC_ID (3<<5)
342 #define ICH_ALI_SS_PRI_ID (3<<3)
343
344 #define ICH_ALI_IF_AC97SP (1<<21)
345 #define ICH_ALI_IF_MC (1<<20)
346 #define ICH_ALI_IF_PI (1<<19)
347 #define ICH_ALI_IF_MC2 (1<<18)
348 #define ICH_ALI_IF_PI2 (1<<17)
349 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
350 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
351 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
352 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
353 #define ICH_ALI_IF_PO_SPDF (1<<3)
354 #define ICH_ALI_IF_PO (1<<1)
355
356 /*
357 *
358 */
359
360 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
361 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
362 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
363
364 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
365
366 typedef struct {
367 unsigned int ichd; /* ich device number */
368 unsigned long reg_offset; /* offset to bmaddr */
369 u32 *bdbar; /* CPU address (32bit) */
370 unsigned int bdbar_addr; /* PCI bus address (32bit) */
371 snd_pcm_substream_t *substream;
372 unsigned int physbuf; /* physical address (32bit) */
373 unsigned int size;
374 unsigned int fragsize;
375 unsigned int fragsize1;
376 unsigned int position;
377 unsigned int pos_shift;
378 int frags;
379 int lvi;
380 int lvi_frag;
381 int civ;
382 int ack;
383 int ack_reload;
384 unsigned int ack_bit;
385 unsigned int roff_sr;
386 unsigned int roff_picb;
387 unsigned int int_sta_mask; /* interrupt status mask */
388 unsigned int ali_slot; /* ALI DMA slot */
389 struct ac97_pcm *pcm;
390 int pcm_open_flag;
391 unsigned int page_attr_changed: 1;
392 unsigned int suspended: 1;
393 } ichdev_t;
394
395 typedef struct _snd_intel8x0 intel8x0_t;
396
397 struct _snd_intel8x0 {
398 unsigned int device_type;
399
400 int irq;
401
402 unsigned int mmio;
403 unsigned long addr;
404 void __iomem *remap_addr;
405 unsigned int bm_mmio;
406 unsigned long bmaddr;
407 void __iomem *remap_bmaddr;
408
409 struct pci_dev *pci;
410 snd_card_t *card;
411
412 int pcm_devs;
413 snd_pcm_t *pcm[6];
414 ichdev_t ichd[6];
415
416 unsigned multi4: 1,
417 multi6: 1,
418 dra: 1,
419 smp20bit: 1;
420 unsigned in_ac97_init: 1,
421 in_sdin_init: 1;
422 unsigned in_measurement: 1; /* during ac97 clock measurement */
423 unsigned fix_nocache: 1; /* workaround for 440MX */
424 unsigned buggy_irq: 1; /* workaround for buggy mobos */
425 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
426
427 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
428 unsigned int sdm_saved; /* SDM reg value */
429
430 ac97_bus_t *ac97_bus;
431 ac97_t *ac97[3];
432 unsigned int ac97_sdin[3];
433
434 spinlock_t reg_lock;
435
436 u32 bdbars_count;
437 struct snd_dma_buffer bdbars;
438 u32 int_sta_reg; /* interrupt status register */
439 u32 int_sta_mask; /* interrupt status mask */
440 };
441
442 static struct pci_device_id snd_intel8x0_ids[] = {
443 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
444 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
445 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
446 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
447 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
448 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
449 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
450 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
451 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
452 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
453 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
454 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
455 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
456 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
457 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
458 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
459 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
460 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
461 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
462 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
463 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
464 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
465 { 0, }
466 };
467
468 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
469
470 /*
471 * Lowlevel I/O - busmaster
472 */
473
474 static u8 igetbyte(intel8x0_t *chip, u32 offset)
475 {
476 if (chip->bm_mmio)
477 return readb(chip->remap_bmaddr + offset);
478 else
479 return inb(chip->bmaddr + offset);
480 }
481
482 static u16 igetword(intel8x0_t *chip, u32 offset)
483 {
484 if (chip->bm_mmio)
485 return readw(chip->remap_bmaddr + offset);
486 else
487 return inw(chip->bmaddr + offset);
488 }
489
490 static u32 igetdword(intel8x0_t *chip, u32 offset)
491 {
492 if (chip->bm_mmio)
493 return readl(chip->remap_bmaddr + offset);
494 else
495 return inl(chip->bmaddr + offset);
496 }
497
498 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
499 {
500 if (chip->bm_mmio)
501 writeb(val, chip->remap_bmaddr + offset);
502 else
503 outb(val, chip->bmaddr + offset);
504 }
505
506 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
507 {
508 if (chip->bm_mmio)
509 writew(val, chip->remap_bmaddr + offset);
510 else
511 outw(val, chip->bmaddr + offset);
512 }
513
514 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
515 {
516 if (chip->bm_mmio)
517 writel(val, chip->remap_bmaddr + offset);
518 else
519 outl(val, chip->bmaddr + offset);
520 }
521
522 /*
523 * Lowlevel I/O - AC'97 registers
524 */
525
526 static u16 iagetword(intel8x0_t *chip, u32 offset)
527 {
528 if (chip->mmio)
529 return readw(chip->remap_addr + offset);
530 else
531 return inw(chip->addr + offset);
532 }
533
534 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
535 {
536 if (chip->mmio)
537 writew(val, chip->remap_addr + offset);
538 else
539 outw(val, chip->addr + offset);
540 }
541
542 /*
543 * Basic I/O
544 */
545
546 /*
547 * access to AC97 codec via normal i/o (for ICH and SIS7012)
548 */
549
550 /* return the GLOB_STA bit for the corresponding codec */
551 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
552 {
553 static unsigned int codec_bit[3] = {
554 ICH_PCR, ICH_SCR, ICH_TCR
555 };
556 snd_assert(codec < 3, return ICH_PCR);
557 if (chip->device_type == DEVICE_INTEL_ICH4)
558 codec = chip->ac97_sdin[codec];
559 return codec_bit[codec];
560 }
561
562 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
563 {
564 int time;
565
566 if (codec > 2)
567 return -EIO;
568 if (chip->in_sdin_init) {
569 /* we don't know the ready bit assignment at the moment */
570 /* so we check any */
571 codec = ICH_PCR | ICH_SCR | ICH_TCR;
572 } else {
573 codec = get_ich_codec_bit(chip, codec);
574 }
575
576 /* codec ready ? */
577 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
578 return -EIO;
579
580 /* Anyone holding a semaphore for 1 msec should be shot... */
581 time = 100;
582 do {
583 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
584 return 0;
585 udelay(10);
586 } while (time--);
587
588 /* access to some forbidden (non existant) ac97 registers will not
589 * reset the semaphore. So even if you don't get the semaphore, still
590 * continue the access. We don't need the semaphore anyway. */
591 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
592 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
593 iagetword(chip, 0); /* clear semaphore flag */
594 /* I don't care about the semaphore */
595 return -EBUSY;
596 }
597
598 static void snd_intel8x0_codec_write(ac97_t *ac97,
599 unsigned short reg,
600 unsigned short val)
601 {
602 intel8x0_t *chip = ac97->private_data;
603
604 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
605 if (! chip->in_ac97_init)
606 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
607 }
608 iaputword(chip, reg + ac97->num * 0x80, val);
609 }
610
611 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
612 unsigned short reg)
613 {
614 intel8x0_t *chip = ac97->private_data;
615 unsigned short res;
616 unsigned int tmp;
617
618 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
619 if (! chip->in_ac97_init)
620 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
621 res = 0xffff;
622 } else {
623 res = iagetword(chip, reg + ac97->num * 0x80);
624 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
625 /* reset RCS and preserve other R/WC bits */
626 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
627 if (! chip->in_ac97_init)
628 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
629 res = 0xffff;
630 }
631 }
632 return res;
633 }
634
635 static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
636 {
637 unsigned int tmp;
638
639 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
640 iagetword(chip, codec * 0x80);
641 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
642 /* reset RCS and preserve other R/WC bits */
643 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
644 }
645 }
646 }
647
648 /*
649 * access to AC97 for Ali5455
650 */
651 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
652 {
653 int count = 0;
654 for (count = 0; count < 0x7f; count++) {
655 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
656 if (val & mask)
657 return 0;
658 }
659 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
660 return -EBUSY;
661 }
662
663 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
664 {
665 int time = 100;
666 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
667 udelay(1);
668 if (! time)
669 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
670 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
671 }
672
673 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
674 {
675 intel8x0_t *chip = ac97->private_data;
676 unsigned short data = 0xffff;
677
678 if (snd_intel8x0_ali_codec_semaphore(chip))
679 goto __err;
680 reg |= ALI_CPR_ADDR_READ;
681 if (ac97->num)
682 reg |= ALI_CPR_ADDR_SECONDARY;
683 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
684 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
685 goto __err;
686 data = igetword(chip, ICHREG(ALI_SPR));
687 __err:
688 return data;
689 }
690
691 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
692 {
693 intel8x0_t *chip = ac97->private_data;
694
695 if (snd_intel8x0_ali_codec_semaphore(chip))
696 return;
697 iputword(chip, ICHREG(ALI_CPR), val);
698 if (ac97->num)
699 reg |= ALI_CPR_ADDR_SECONDARY;
700 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
701 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
702 }
703
704
705 /*
706 * DMA I/O
707 */
708 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
709 {
710 int idx;
711 u32 *bdbar = ichdev->bdbar;
712 unsigned long port = ichdev->reg_offset;
713
714 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
715 if (ichdev->size == ichdev->fragsize) {
716 ichdev->ack_reload = ichdev->ack = 2;
717 ichdev->fragsize1 = ichdev->fragsize >> 1;
718 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
719 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
720 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
721 ichdev->fragsize1 >> ichdev->pos_shift);
722 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
723 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
724 ichdev->fragsize1 >> ichdev->pos_shift);
725 }
726 ichdev->frags = 2;
727 } else {
728 ichdev->ack_reload = ichdev->ack = 1;
729 ichdev->fragsize1 = ichdev->fragsize;
730 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
731 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
732 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
733 ichdev->fragsize >> ichdev->pos_shift);
734 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
735 }
736 ichdev->frags = ichdev->size / ichdev->fragsize;
737 }
738 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
739 ichdev->civ = 0;
740 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
741 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
742 ichdev->position = 0;
743 #if 0
744 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
745 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
746 #endif
747 /* clear interrupts */
748 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
749 }
750
751 #ifdef __i386__
752 /*
753 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
754 * which aborts PCI busmaster for audio transfer. A workaround is to set
755 * the pages as non-cached. For details, see the errata in
756 * http://www.intel.com/design/chipsets/specupdt/245051.htm
757 */
758 static void fill_nocache(void *buf, int size, int nocache)
759 {
760 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
761 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
762 global_flush_tlb();
763 }
764 #else
765 #define fill_nocache(buf,size,nocache)
766 #endif
767
768 /*
769 * Interrupt handler
770 */
771
772 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
773 {
774 unsigned long port = ichdev->reg_offset;
775 int status, civ, i, step;
776 int ack = 0;
777
778 spin_lock(&chip->reg_lock);
779 status = igetbyte(chip, port + ichdev->roff_sr);
780 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
781 if (!(status & ICH_BCIS)) {
782 step = 0;
783 } else if (civ == ichdev->civ) {
784 // snd_printd("civ same %d\n", civ);
785 step = 1;
786 ichdev->civ++;
787 ichdev->civ &= ICH_REG_LVI_MASK;
788 } else {
789 step = civ - ichdev->civ;
790 if (step < 0)
791 step += ICH_REG_LVI_MASK + 1;
792 // if (step != 1)
793 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
794 ichdev->civ = civ;
795 }
796
797 ichdev->position += step * ichdev->fragsize1;
798 if (! chip->in_measurement)
799 ichdev->position %= ichdev->size;
800 ichdev->lvi += step;
801 ichdev->lvi &= ICH_REG_LVI_MASK;
802 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
803 for (i = 0; i < step; i++) {
804 ichdev->lvi_frag++;
805 ichdev->lvi_frag %= ichdev->frags;
806 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
807 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
808 if (--ichdev->ack == 0) {
809 ichdev->ack = ichdev->ack_reload;
810 ack = 1;
811 }
812 }
813 spin_unlock(&chip->reg_lock);
814 if (ack && ichdev->substream) {
815 snd_pcm_period_elapsed(ichdev->substream);
816 }
817 iputbyte(chip, port + ichdev->roff_sr,
818 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
819 }
820
821 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
822 {
823 intel8x0_t *chip = dev_id;
824 ichdev_t *ichdev;
825 unsigned int status;
826 unsigned int i;
827
828 status = igetdword(chip, chip->int_sta_reg);
829 if (status == 0xffffffff) /* we are not yet resumed */
830 return IRQ_NONE;
831
832 if ((status & chip->int_sta_mask) == 0) {
833 if (status) {
834 /* ack */
835 iputdword(chip, chip->int_sta_reg, status);
836 if (! chip->buggy_irq)
837 status = 0;
838 }
839 return IRQ_RETVAL(status);
840 }
841
842 for (i = 0; i < chip->bdbars_count; i++) {
843 ichdev = &chip->ichd[i];
844 if (status & ichdev->int_sta_mask)
845 snd_intel8x0_update(chip, ichdev);
846 }
847
848 /* ack them */
849 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
850
851 return IRQ_HANDLED;
852 }
853
854 /*
855 * PCM part
856 */
857
858 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
859 {
860 intel8x0_t *chip = snd_pcm_substream_chip(substream);
861 ichdev_t *ichdev = get_ichdev(substream);
862 unsigned char val = 0;
863 unsigned long port = ichdev->reg_offset;
864
865 switch (cmd) {
866 case SNDRV_PCM_TRIGGER_RESUME:
867 ichdev->suspended = 0;
868 /* fallthru */
869 case SNDRV_PCM_TRIGGER_START:
870 val = ICH_IOCE | ICH_STARTBM;
871 break;
872 case SNDRV_PCM_TRIGGER_SUSPEND:
873 ichdev->suspended = 1;
874 /* fallthru */
875 case SNDRV_PCM_TRIGGER_STOP:
876 val = 0;
877 break;
878 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
879 val = ICH_IOCE;
880 break;
881 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
882 val = ICH_IOCE | ICH_STARTBM;
883 break;
884 default:
885 return -EINVAL;
886 }
887 iputbyte(chip, port + ICH_REG_OFF_CR, val);
888 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
889 /* wait until DMA stopped */
890 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
891 /* reset whole DMA things */
892 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
893 }
894 return 0;
895 }
896
897 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
898 {
899 intel8x0_t *chip = snd_pcm_substream_chip(substream);
900 ichdev_t *ichdev = get_ichdev(substream);
901 unsigned long port = ichdev->reg_offset;
902 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
903 unsigned int val, fifo;
904
905 val = igetdword(chip, ICHREG(ALI_DMACR));
906 switch (cmd) {
907 case SNDRV_PCM_TRIGGER_RESUME:
908 ichdev->suspended = 0;
909 /* fallthru */
910 case SNDRV_PCM_TRIGGER_START:
911 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
912 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
913 /* clear FIFO for synchronization of channels */
914 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
915 fifo &= ~(0xff << (ichdev->ali_slot % 4));
916 fifo |= 0x83 << (ichdev->ali_slot % 4);
917 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
918 }
919 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
920 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
921 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
922 break;
923 case SNDRV_PCM_TRIGGER_SUSPEND:
924 ichdev->suspended = 1;
925 /* fallthru */
926 case SNDRV_PCM_TRIGGER_STOP:
927 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
928 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
929 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
930 while (igetbyte(chip, port + ICH_REG_OFF_CR))
931 ;
932 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
933 break;
934 /* reset whole DMA things */
935 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
936 /* clear interrupts */
937 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
938 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
939 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
940 break;
941 default:
942 return -EINVAL;
943 }
944 return 0;
945 }
946
947 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
948 snd_pcm_hw_params_t * hw_params)
949 {
950 intel8x0_t *chip = snd_pcm_substream_chip(substream);
951 ichdev_t *ichdev = get_ichdev(substream);
952 snd_pcm_runtime_t *runtime = substream->runtime;
953 int dbl = params_rate(hw_params) > 48000;
954 int err;
955
956 if (chip->fix_nocache && ichdev->page_attr_changed) {
957 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
958 ichdev->page_attr_changed = 0;
959 }
960 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
961 if (err < 0)
962 return err;
963 if (chip->fix_nocache) {
964 if (runtime->dma_area && ! ichdev->page_attr_changed) {
965 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
966 ichdev->page_attr_changed = 1;
967 }
968 }
969 if (ichdev->pcm_open_flag) {
970 snd_ac97_pcm_close(ichdev->pcm);
971 ichdev->pcm_open_flag = 0;
972 }
973 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
974 params_channels(hw_params),
975 ichdev->pcm->r[dbl].slots);
976 if (err >= 0) {
977 ichdev->pcm_open_flag = 1;
978 /* Force SPDIF setting */
979 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
980 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
981 }
982 return err;
983 }
984
985 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
986 {
987 intel8x0_t *chip = snd_pcm_substream_chip(substream);
988 ichdev_t *ichdev = get_ichdev(substream);
989
990 if (ichdev->pcm_open_flag) {
991 snd_ac97_pcm_close(ichdev->pcm);
992 ichdev->pcm_open_flag = 0;
993 }
994 if (chip->fix_nocache && ichdev->page_attr_changed) {
995 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
996 ichdev->page_attr_changed = 0;
997 }
998 return snd_pcm_lib_free_pages(substream);
999 }
1000
1001 static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
1002 snd_pcm_runtime_t *runtime)
1003 {
1004 unsigned int cnt;
1005 int dbl = runtime->rate > 48000;
1006
1007 spin_lock_irq(&chip->reg_lock);
1008 switch (chip->device_type) {
1009 case DEVICE_ALI:
1010 cnt = igetdword(chip, ICHREG(ALI_SCR));
1011 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1012 if (runtime->channels == 4 || dbl)
1013 cnt |= ICH_ALI_SC_PCM_4;
1014 else if (runtime->channels == 6)
1015 cnt |= ICH_ALI_SC_PCM_6;
1016 iputdword(chip, ICHREG(ALI_SCR), cnt);
1017 break;
1018 case DEVICE_SIS:
1019 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1020 cnt &= ~ICH_SIS_PCM_246_MASK;
1021 if (runtime->channels == 4 || dbl)
1022 cnt |= ICH_SIS_PCM_4;
1023 else if (runtime->channels == 6)
1024 cnt |= ICH_SIS_PCM_6;
1025 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1026 break;
1027 default:
1028 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1029 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1030 if (runtime->channels == 4 || dbl)
1031 cnt |= ICH_PCM_4;
1032 else if (runtime->channels == 6)
1033 cnt |= ICH_PCM_6;
1034 if (chip->device_type == DEVICE_NFORCE) {
1035 /* reset to 2ch once to keep the 6 channel data in alignment,
1036 * to start from Front Left always
1037 */
1038 if (cnt & ICH_PCM_246_MASK) {
1039 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1040 spin_unlock_irq(&chip->reg_lock);
1041 msleep(50); /* grrr... */
1042 spin_lock_irq(&chip->reg_lock);
1043 }
1044 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1045 if (runtime->sample_bits > 16)
1046 cnt |= ICH_PCM_20BIT;
1047 }
1048 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1049 break;
1050 }
1051 spin_unlock_irq(&chip->reg_lock);
1052 }
1053
1054 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1055 {
1056 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1057 snd_pcm_runtime_t *runtime = substream->runtime;
1058 ichdev_t *ichdev = get_ichdev(substream);
1059
1060 ichdev->physbuf = runtime->dma_addr;
1061 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1062 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1063 if (ichdev->ichd == ICHD_PCMOUT) {
1064 snd_intel8x0_setup_pcm_out(chip, runtime);
1065 if (chip->device_type == DEVICE_INTEL_ICH4)
1066 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1067 }
1068 snd_intel8x0_setup_periods(chip, ichdev);
1069 return 0;
1070 }
1071
1072 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1073 {
1074 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1075 ichdev_t *ichdev = get_ichdev(substream);
1076 size_t ptr1, ptr;
1077 int civ, timeout = 100;
1078 unsigned int position;
1079
1080 spin_lock(&chip->reg_lock);
1081 do {
1082 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1083 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1084 position = ichdev->position;
1085 if (ptr1 == 0) {
1086 udelay(10);
1087 continue;
1088 }
1089 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1090 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1091 break;
1092 } while (timeout--);
1093 ptr1 <<= ichdev->pos_shift;
1094 ptr = ichdev->fragsize1 - ptr1;
1095 ptr += position;
1096 spin_unlock(&chip->reg_lock);
1097 if (ptr >= ichdev->size)
1098 return 0;
1099 return bytes_to_frames(substream->runtime, ptr);
1100 }
1101
1102 static snd_pcm_hardware_t snd_intel8x0_stream =
1103 {
1104 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1105 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1106 SNDRV_PCM_INFO_MMAP_VALID |
1107 SNDRV_PCM_INFO_PAUSE |
1108 SNDRV_PCM_INFO_RESUME),
1109 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1110 .rates = SNDRV_PCM_RATE_48000,
1111 .rate_min = 48000,
1112 .rate_max = 48000,
1113 .channels_min = 2,
1114 .channels_max = 2,
1115 .buffer_bytes_max = 128 * 1024,
1116 .period_bytes_min = 32,
1117 .period_bytes_max = 128 * 1024,
1118 .periods_min = 1,
1119 .periods_max = 1024,
1120 .fifo_size = 0,
1121 };
1122
1123 static unsigned int channels4[] = {
1124 2, 4,
1125 };
1126
1127 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1128 .count = ARRAY_SIZE(channels4),
1129 .list = channels4,
1130 .mask = 0,
1131 };
1132
1133 static unsigned int channels6[] = {
1134 2, 4, 6,
1135 };
1136
1137 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1138 .count = ARRAY_SIZE(channels6),
1139 .list = channels6,
1140 .mask = 0,
1141 };
1142
1143 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1144 {
1145 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1146 snd_pcm_runtime_t *runtime = substream->runtime;
1147 int err;
1148
1149 ichdev->substream = substream;
1150 runtime->hw = snd_intel8x0_stream;
1151 runtime->hw.rates = ichdev->pcm->rates;
1152 snd_pcm_limit_hw_rates(runtime);
1153 if (chip->device_type == DEVICE_SIS) {
1154 runtime->hw.buffer_bytes_max = 64*1024;
1155 runtime->hw.period_bytes_max = 64*1024;
1156 }
1157 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1158 return err;
1159 runtime->private_data = ichdev;
1160 return 0;
1161 }
1162
1163 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1164 {
1165 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1166 snd_pcm_runtime_t *runtime = substream->runtime;
1167 int err;
1168
1169 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1170 if (err < 0)
1171 return err;
1172
1173 if (chip->multi6) {
1174 runtime->hw.channels_max = 6;
1175 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1176 } else if (chip->multi4) {
1177 runtime->hw.channels_max = 4;
1178 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1179 }
1180 if (chip->dra) {
1181 snd_ac97_pcm_double_rate_rules(runtime);
1182 }
1183 if (chip->smp20bit) {
1184 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1185 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1186 }
1187 return 0;
1188 }
1189
1190 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1191 {
1192 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1193
1194 chip->ichd[ICHD_PCMOUT].substream = NULL;
1195 return 0;
1196 }
1197
1198 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1199 {
1200 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1201
1202 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1203 }
1204
1205 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1206 {
1207 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1208
1209 chip->ichd[ICHD_PCMIN].substream = NULL;
1210 return 0;
1211 }
1212
1213 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1214 {
1215 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1216
1217 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1218 }
1219
1220 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1221 {
1222 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1223
1224 chip->ichd[ICHD_MIC].substream = NULL;
1225 return 0;
1226 }
1227
1228 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1229 {
1230 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1231
1232 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1233 }
1234
1235 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1236 {
1237 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1238
1239 chip->ichd[ICHD_MIC2].substream = NULL;
1240 return 0;
1241 }
1242
1243 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1244 {
1245 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1246
1247 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1248 }
1249
1250 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1251 {
1252 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1253
1254 chip->ichd[ICHD_PCM2IN].substream = NULL;
1255 return 0;
1256 }
1257
1258 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1259 {
1260 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1261 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1262
1263 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1264 }
1265
1266 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1267 {
1268 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1269 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1270
1271 chip->ichd[idx].substream = NULL;
1272 return 0;
1273 }
1274
1275 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1276 {
1277 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1278 unsigned int val;
1279
1280 spin_lock_irq(&chip->reg_lock);
1281 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1282 val |= ICH_ALI_IF_AC97SP;
1283 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1284 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1285 spin_unlock_irq(&chip->reg_lock);
1286
1287 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1288 }
1289
1290 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1291 {
1292 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1293 unsigned int val;
1294
1295 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1296 spin_lock_irq(&chip->reg_lock);
1297 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1298 val &= ~ICH_ALI_IF_AC97SP;
1299 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1300 spin_unlock_irq(&chip->reg_lock);
1301
1302 return 0;
1303 }
1304
1305 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1306 {
1307 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1308
1309 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1310 }
1311
1312 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1313 {
1314 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1315
1316 chip->ichd[ALID_SPDIFIN].substream = NULL;
1317 return 0;
1318 }
1319
1320 #if 0 // NYI
1321 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1322 {
1323 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1324
1325 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1326 }
1327
1328 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1329 {
1330 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1331
1332 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1333 return 0;
1334 }
1335 #endif
1336
1337 static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1338 .open = snd_intel8x0_playback_open,
1339 .close = snd_intel8x0_playback_close,
1340 .ioctl = snd_pcm_lib_ioctl,
1341 .hw_params = snd_intel8x0_hw_params,
1342 .hw_free = snd_intel8x0_hw_free,
1343 .prepare = snd_intel8x0_pcm_prepare,
1344 .trigger = snd_intel8x0_pcm_trigger,
1345 .pointer = snd_intel8x0_pcm_pointer,
1346 };
1347
1348 static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1349 .open = snd_intel8x0_capture_open,
1350 .close = snd_intel8x0_capture_close,
1351 .ioctl = snd_pcm_lib_ioctl,
1352 .hw_params = snd_intel8x0_hw_params,
1353 .hw_free = snd_intel8x0_hw_free,
1354 .prepare = snd_intel8x0_pcm_prepare,
1355 .trigger = snd_intel8x0_pcm_trigger,
1356 .pointer = snd_intel8x0_pcm_pointer,
1357 };
1358
1359 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1360 .open = snd_intel8x0_mic_open,
1361 .close = snd_intel8x0_mic_close,
1362 .ioctl = snd_pcm_lib_ioctl,
1363 .hw_params = snd_intel8x0_hw_params,
1364 .hw_free = snd_intel8x0_hw_free,
1365 .prepare = snd_intel8x0_pcm_prepare,
1366 .trigger = snd_intel8x0_pcm_trigger,
1367 .pointer = snd_intel8x0_pcm_pointer,
1368 };
1369
1370 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1371 .open = snd_intel8x0_mic2_open,
1372 .close = snd_intel8x0_mic2_close,
1373 .ioctl = snd_pcm_lib_ioctl,
1374 .hw_params = snd_intel8x0_hw_params,
1375 .hw_free = snd_intel8x0_hw_free,
1376 .prepare = snd_intel8x0_pcm_prepare,
1377 .trigger = snd_intel8x0_pcm_trigger,
1378 .pointer = snd_intel8x0_pcm_pointer,
1379 };
1380
1381 static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1382 .open = snd_intel8x0_capture2_open,
1383 .close = snd_intel8x0_capture2_close,
1384 .ioctl = snd_pcm_lib_ioctl,
1385 .hw_params = snd_intel8x0_hw_params,
1386 .hw_free = snd_intel8x0_hw_free,
1387 .prepare = snd_intel8x0_pcm_prepare,
1388 .trigger = snd_intel8x0_pcm_trigger,
1389 .pointer = snd_intel8x0_pcm_pointer,
1390 };
1391
1392 static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1393 .open = snd_intel8x0_spdif_open,
1394 .close = snd_intel8x0_spdif_close,
1395 .ioctl = snd_pcm_lib_ioctl,
1396 .hw_params = snd_intel8x0_hw_params,
1397 .hw_free = snd_intel8x0_hw_free,
1398 .prepare = snd_intel8x0_pcm_prepare,
1399 .trigger = snd_intel8x0_pcm_trigger,
1400 .pointer = snd_intel8x0_pcm_pointer,
1401 };
1402
1403 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1404 .open = snd_intel8x0_playback_open,
1405 .close = snd_intel8x0_playback_close,
1406 .ioctl = snd_pcm_lib_ioctl,
1407 .hw_params = snd_intel8x0_hw_params,
1408 .hw_free = snd_intel8x0_hw_free,
1409 .prepare = snd_intel8x0_pcm_prepare,
1410 .trigger = snd_intel8x0_ali_trigger,
1411 .pointer = snd_intel8x0_pcm_pointer,
1412 };
1413
1414 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1415 .open = snd_intel8x0_capture_open,
1416 .close = snd_intel8x0_capture_close,
1417 .ioctl = snd_pcm_lib_ioctl,
1418 .hw_params = snd_intel8x0_hw_params,
1419 .hw_free = snd_intel8x0_hw_free,
1420 .prepare = snd_intel8x0_pcm_prepare,
1421 .trigger = snd_intel8x0_ali_trigger,
1422 .pointer = snd_intel8x0_pcm_pointer,
1423 };
1424
1425 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1426 .open = snd_intel8x0_mic_open,
1427 .close = snd_intel8x0_mic_close,
1428 .ioctl = snd_pcm_lib_ioctl,
1429 .hw_params = snd_intel8x0_hw_params,
1430 .hw_free = snd_intel8x0_hw_free,
1431 .prepare = snd_intel8x0_pcm_prepare,
1432 .trigger = snd_intel8x0_ali_trigger,
1433 .pointer = snd_intel8x0_pcm_pointer,
1434 };
1435
1436 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1437 .open = snd_intel8x0_ali_ac97spdifout_open,
1438 .close = snd_intel8x0_ali_ac97spdifout_close,
1439 .ioctl = snd_pcm_lib_ioctl,
1440 .hw_params = snd_intel8x0_hw_params,
1441 .hw_free = snd_intel8x0_hw_free,
1442 .prepare = snd_intel8x0_pcm_prepare,
1443 .trigger = snd_intel8x0_ali_trigger,
1444 .pointer = snd_intel8x0_pcm_pointer,
1445 };
1446
1447 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1448 .open = snd_intel8x0_ali_spdifin_open,
1449 .close = snd_intel8x0_ali_spdifin_close,
1450 .ioctl = snd_pcm_lib_ioctl,
1451 .hw_params = snd_intel8x0_hw_params,
1452 .hw_free = snd_intel8x0_hw_free,
1453 .prepare = snd_intel8x0_pcm_prepare,
1454 .trigger = snd_intel8x0_pcm_trigger,
1455 .pointer = snd_intel8x0_pcm_pointer,
1456 };
1457
1458 #if 0 // NYI
1459 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1460 .open = snd_intel8x0_ali_spdifout_open,
1461 .close = snd_intel8x0_ali_spdifout_close,
1462 .ioctl = snd_pcm_lib_ioctl,
1463 .hw_params = snd_intel8x0_hw_params,
1464 .hw_free = snd_intel8x0_hw_free,
1465 .prepare = snd_intel8x0_pcm_prepare,
1466 .trigger = snd_intel8x0_pcm_trigger,
1467 .pointer = snd_intel8x0_pcm_pointer,
1468 };
1469 #endif // NYI
1470
1471 struct ich_pcm_table {
1472 char *suffix;
1473 snd_pcm_ops_t *playback_ops;
1474 snd_pcm_ops_t *capture_ops;
1475 size_t prealloc_size;
1476 size_t prealloc_max_size;
1477 int ac97_idx;
1478 };
1479
1480 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1481 {
1482 snd_pcm_t *pcm;
1483 int err;
1484 char name[32];
1485
1486 if (rec->suffix)
1487 sprintf(name, "Intel ICH - %s", rec->suffix);
1488 else
1489 strcpy(name, "Intel ICH");
1490 err = snd_pcm_new(chip->card, name, device,
1491 rec->playback_ops ? 1 : 0,
1492 rec->capture_ops ? 1 : 0, &pcm);
1493 if (err < 0)
1494 return err;
1495
1496 if (rec->playback_ops)
1497 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1498 if (rec->capture_ops)
1499 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1500
1501 pcm->private_data = chip;
1502 pcm->info_flags = 0;
1503 if (rec->suffix)
1504 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1505 else
1506 strcpy(pcm->name, chip->card->shortname);
1507 chip->pcm[device] = pcm;
1508
1509 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1510 rec->prealloc_size, rec->prealloc_max_size);
1511
1512 return 0;
1513 }
1514
1515 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1516 {
1517 .playback_ops = &snd_intel8x0_playback_ops,
1518 .capture_ops = &snd_intel8x0_capture_ops,
1519 .prealloc_size = 64 * 1024,
1520 .prealloc_max_size = 128 * 1024,
1521 },
1522 {
1523 .suffix = "MIC ADC",
1524 .capture_ops = &snd_intel8x0_capture_mic_ops,
1525 .prealloc_size = 0,
1526 .prealloc_max_size = 128 * 1024,
1527 .ac97_idx = ICHD_MIC,
1528 },
1529 {
1530 .suffix = "MIC2 ADC",
1531 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1532 .prealloc_size = 0,
1533 .prealloc_max_size = 128 * 1024,
1534 .ac97_idx = ICHD_MIC2,
1535 },
1536 {
1537 .suffix = "ADC2",
1538 .capture_ops = &snd_intel8x0_capture2_ops,
1539 .prealloc_size = 0,
1540 .prealloc_max_size = 128 * 1024,
1541 .ac97_idx = ICHD_PCM2IN,
1542 },
1543 {
1544 .suffix = "IEC958",
1545 .playback_ops = &snd_intel8x0_spdif_ops,
1546 .prealloc_size = 64 * 1024,
1547 .prealloc_max_size = 128 * 1024,
1548 .ac97_idx = ICHD_SPBAR,
1549 },
1550 };
1551
1552 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1553 {
1554 .playback_ops = &snd_intel8x0_playback_ops,
1555 .capture_ops = &snd_intel8x0_capture_ops,
1556 .prealloc_size = 64 * 1024,
1557 .prealloc_max_size = 128 * 1024,
1558 },
1559 {
1560 .suffix = "MIC ADC",
1561 .capture_ops = &snd_intel8x0_capture_mic_ops,
1562 .prealloc_size = 0,
1563 .prealloc_max_size = 128 * 1024,
1564 .ac97_idx = NVD_MIC,
1565 },
1566 {
1567 .suffix = "IEC958",
1568 .playback_ops = &snd_intel8x0_spdif_ops,
1569 .prealloc_size = 64 * 1024,
1570 .prealloc_max_size = 128 * 1024,
1571 .ac97_idx = NVD_SPBAR,
1572 },
1573 };
1574
1575 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1576 {
1577 .playback_ops = &snd_intel8x0_ali_playback_ops,
1578 .capture_ops = &snd_intel8x0_ali_capture_ops,
1579 .prealloc_size = 64 * 1024,
1580 .prealloc_max_size = 128 * 1024,
1581 },
1582 {
1583 .suffix = "MIC ADC",
1584 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1585 .prealloc_size = 0,
1586 .prealloc_max_size = 128 * 1024,
1587 .ac97_idx = ALID_MIC,
1588 },
1589 {
1590 .suffix = "IEC958",
1591 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1592 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1593 .prealloc_size = 64 * 1024,
1594 .prealloc_max_size = 128 * 1024,
1595 .ac97_idx = ALID_AC97SPDIFOUT,
1596 },
1597 #if 0 // NYI
1598 {
1599 .suffix = "HW IEC958",
1600 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1601 .prealloc_size = 64 * 1024,
1602 .prealloc_max_size = 128 * 1024,
1603 },
1604 #endif
1605 };
1606
1607 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1608 {
1609 int i, tblsize, device, err;
1610 struct ich_pcm_table *tbl, *rec;
1611
1612 switch (chip->device_type) {
1613 case DEVICE_INTEL_ICH4:
1614 tbl = intel_pcms;
1615 tblsize = ARRAY_SIZE(intel_pcms);
1616 break;
1617 case DEVICE_NFORCE:
1618 tbl = nforce_pcms;
1619 tblsize = ARRAY_SIZE(nforce_pcms);
1620 break;
1621 case DEVICE_ALI:
1622 tbl = ali_pcms;
1623 tblsize = ARRAY_SIZE(ali_pcms);
1624 break;
1625 default:
1626 tbl = intel_pcms;
1627 tblsize = 2;
1628 break;
1629 }
1630
1631 device = 0;
1632 for (i = 0; i < tblsize; i++) {
1633 rec = tbl + i;
1634 if (i > 0 && rec->ac97_idx) {
1635 /* activate PCM only when associated AC'97 codec */
1636 if (! chip->ichd[rec->ac97_idx].pcm)
1637 continue;
1638 }
1639 err = snd_intel8x0_pcm1(chip, device, rec);
1640 if (err < 0)
1641 return err;
1642 device++;
1643 }
1644
1645 chip->pcm_devs = device;
1646 return 0;
1647 }
1648
1649
1650 /*
1651 * Mixer part
1652 */
1653
1654 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1655 {
1656 intel8x0_t *chip = bus->private_data;
1657 chip->ac97_bus = NULL;
1658 }
1659
1660 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1661 {
1662 intel8x0_t *chip = ac97->private_data;
1663 chip->ac97[ac97->num] = NULL;
1664 }
1665
1666 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1667 /* front PCM */
1668 {
1669 .exclusive = 1,
1670 .r = { {
1671 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1672 (1 << AC97_SLOT_PCM_RIGHT) |
1673 (1 << AC97_SLOT_PCM_CENTER) |
1674 (1 << AC97_SLOT_PCM_SLEFT) |
1675 (1 << AC97_SLOT_PCM_SRIGHT) |
1676 (1 << AC97_SLOT_LFE)
1677 },
1678 {
1679 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1680 (1 << AC97_SLOT_PCM_RIGHT) |
1681 (1 << AC97_SLOT_PCM_LEFT_0) |
1682 (1 << AC97_SLOT_PCM_RIGHT_0)
1683 }
1684 }
1685 },
1686 /* PCM IN #1 */
1687 {
1688 .stream = 1,
1689 .exclusive = 1,
1690 .r = { {
1691 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1692 (1 << AC97_SLOT_PCM_RIGHT)
1693 }
1694 }
1695 },
1696 /* MIC IN #1 */
1697 {
1698 .stream = 1,
1699 .exclusive = 1,
1700 .r = { {
1701 .slots = (1 << AC97_SLOT_MIC)
1702 }
1703 }
1704 },
1705 /* S/PDIF PCM */
1706 {
1707 .exclusive = 1,
1708 .spdif = 1,
1709 .r = { {
1710 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1711 (1 << AC97_SLOT_SPDIF_RIGHT2)
1712 }
1713 }
1714 },
1715 /* PCM IN #2 */
1716 {
1717 .stream = 1,
1718 .exclusive = 1,
1719 .r = { {
1720 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1721 (1 << AC97_SLOT_PCM_RIGHT)
1722 }
1723 }
1724 },
1725 /* MIC IN #2 */
1726 {
1727 .stream = 1,
1728 .exclusive = 1,
1729 .r = { {
1730 .slots = (1 << AC97_SLOT_MIC)
1731 }
1732 }
1733 },
1734 };
1735
1736 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1737 {
1738 .subvendor = 0x0e11,
1739 .subdevice = 0x008a,
1740 .name = "Compaq Evo W4000", /* AD1885 */
1741 .type = AC97_TUNE_HP_ONLY
1742 },
1743 {
1744 .subvendor = 0x0e11,
1745 .subdevice = 0x00b8,
1746 .name = "Compaq Evo D510C",
1747 .type = AC97_TUNE_HP_ONLY
1748 },
1749 {
1750 .subvendor = 0x0e11,
1751 .subdevice = 0x0860,
1752 .name = "HP/Compaq nx7010",
1753 .type = AC97_TUNE_MUTE_LED
1754 },
1755 {
1756 .subvendor = 0x1014,
1757 .subdevice = 0x1f00,
1758 .name = "MS-9128",
1759 .type = AC97_TUNE_ALC_JACK
1760 },
1761 {
1762 .subvendor = 0x1028,
1763 .subdevice = 0x00d8,
1764 .name = "Dell Precision 530", /* AD1885 */
1765 .type = AC97_TUNE_HP_ONLY
1766 },
1767 {
1768 .subvendor = 0x1028,
1769 .subdevice = 0x010d,
1770 .name = "Dell", /* which model? AD1885 */
1771 .type = AC97_TUNE_HP_ONLY
1772 },
1773 {
1774 .subvendor = 0x1028,
1775 .subdevice = 0x0126,
1776 .name = "Dell Optiplex GX260", /* AD1981A */
1777 .type = AC97_TUNE_HP_ONLY
1778 },
1779 {
1780 .subvendor = 0x1028,
1781 .subdevice = 0x012c,
1782 .name = "Dell Precision 650", /* AD1981A */
1783 .type = AC97_TUNE_HP_ONLY
1784 },
1785 {
1786 .subvendor = 0x1028,
1787 .subdevice = 0x012d,
1788 .name = "Dell Precision 450", /* AD1981B*/
1789 .type = AC97_TUNE_HP_ONLY
1790 },
1791 {
1792 .subvendor = 0x1028,
1793 .subdevice = 0x0147,
1794 .name = "Dell", /* which model? AD1981B*/
1795 .type = AC97_TUNE_HP_ONLY
1796 },
1797 {
1798 .subvendor = 0x1028,
1799 .subdevice = 0x0163,
1800 .name = "Dell Unknown", /* STAC9750/51 */
1801 .type = AC97_TUNE_HP_ONLY
1802 },
1803 {
1804 .subvendor = 0x103c,
1805 .subdevice = 0x006d,
1806 .name = "HP zv5000",
1807 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1808 },
1809 { /* FIXME: which codec? */
1810 .subvendor = 0x103c,
1811 .subdevice = 0x00c3,
1812 .name = "HP xw6000",
1813 .type = AC97_TUNE_HP_ONLY
1814 },
1815 {
1816 .subvendor = 0x103c,
1817 .subdevice = 0x088c,
1818 .name = "HP nc8000",
1819 .type = AC97_TUNE_MUTE_LED
1820 },
1821 {
1822 .subvendor = 0x103c,
1823 .subdevice = 0x0890,
1824 .name = "HP nc6000",
1825 .type = AC97_TUNE_MUTE_LED
1826 },
1827 {
1828 .subvendor = 0x103c,
1829 .subdevice = 0x0934,
1830 .name = "HP nx8220",
1831 .type = AC97_TUNE_MUTE_LED
1832 },
1833 {
1834 .subvendor = 0x103c,
1835 .subdevice = 0x099c,
1836 .name = "HP nx6110", /* AD1981B */
1837 .type = AC97_TUNE_HP_ONLY
1838 },
1839 {
1840 .subvendor = 0x103c,
1841 .subdevice = 0x129d,
1842 .name = "HP xw8000",
1843 .type = AC97_TUNE_HP_ONLY
1844 },
1845 {
1846 .subvendor = 0x103c,
1847 .subdevice = 0x12f1,
1848 .name = "HP xw8200", /* AD1981B*/
1849 .type = AC97_TUNE_HP_ONLY
1850 },
1851 {
1852 .subvendor = 0x103c,
1853 .subdevice = 0x12f2,
1854 .name = "HP xw6200",
1855 .type = AC97_TUNE_HP_ONLY
1856 },
1857 {
1858 .subvendor = 0x103c,
1859 .subdevice = 0x3008,
1860 .name = "HP xw4200", /* AD1981B*/
1861 .type = AC97_TUNE_HP_ONLY
1862 },
1863 {
1864 .subvendor = 0x104d,
1865 .subdevice = 0x8197,
1866 .name = "Sony S1XP",
1867 .type = AC97_TUNE_INV_EAPD
1868 },
1869 {
1870 .subvendor = 0x1043,
1871 .subdevice = 0x80f3,
1872 .name = "ASUS ICH5/AD1985",
1873 .type = AC97_TUNE_AD_SHARING
1874 },
1875 {
1876 .subvendor = 0x10cf,
1877 .subdevice = 0x11c3,
1878 .name = "Fujitsu-Siemens E4010",
1879 .type = AC97_TUNE_HP_ONLY
1880 },
1881 {
1882 .subvendor = 0x10cf,
1883 .subdevice = 0x1225,
1884 .name = "Fujitsu-Siemens T3010",
1885 .type = AC97_TUNE_HP_ONLY
1886 },
1887 {
1888 .subvendor = 0x10cf,
1889 .subdevice = 0x1253,
1890 .name = "Fujitsu S6210", /* STAC9750/51 */
1891 .type = AC97_TUNE_HP_ONLY
1892 },
1893 {
1894 .subvendor = 0x10cf,
1895 .subdevice = 0x12ec,
1896 .name = "Fujitsu-Siemens 4010",
1897 .type = AC97_TUNE_HP_ONLY
1898 },
1899 {
1900 .subvendor = 0x10f1,
1901 .subdevice = 0x2665,
1902 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1903 .type = AC97_TUNE_HP_ONLY
1904 },
1905 {
1906 .subvendor = 0x10f1,
1907 .subdevice = 0x2885,
1908 .name = "AMD64 Mobo", /* ALC650 */
1909 .type = AC97_TUNE_HP_ONLY
1910 },
1911 {
1912 .subvendor = 0x110a,
1913 .subdevice = 0x0056,
1914 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1915 .type = AC97_TUNE_HP_ONLY
1916 },
1917 {
1918 .subvendor = 0x11d4,
1919 .subdevice = 0x5375,
1920 .name = "ADI AD1985 (discrete)",
1921 .type = AC97_TUNE_HP_ONLY
1922 },
1923 {
1924 .subvendor = 0x1462,
1925 .subdevice = 0x5470,
1926 .name = "MSI P4 ATX 645 Ultra",
1927 .type = AC97_TUNE_HP_ONLY
1928 },
1929 {
1930 .subvendor = 0x1734,
1931 .subdevice = 0x0088,
1932 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1933 .type = AC97_TUNE_HP_ONLY
1934 },
1935 {
1936 .subvendor = 0x8086,
1937 .subdevice = 0x2000,
1938 .mask = 0xfff0,
1939 .name = "Intel ICH5/AD1985",
1940 .type = AC97_TUNE_AD_SHARING
1941 },
1942 {
1943 .subvendor = 0x8086,
1944 .subdevice = 0x4000,
1945 .mask = 0xfff0,
1946 .name = "Intel ICH5/AD1985",
1947 .type = AC97_TUNE_AD_SHARING
1948 },
1949 {
1950 .subvendor = 0x8086,
1951 .subdevice = 0x4856,
1952 .name = "Intel D845WN (82801BA)",
1953 .type = AC97_TUNE_SWAP_HP
1954 },
1955 {
1956 .subvendor = 0x8086,
1957 .subdevice = 0x4d44,
1958 .name = "Intel D850EMV2", /* AD1885 */
1959 .type = AC97_TUNE_HP_ONLY
1960 },
1961 {
1962 .subvendor = 0x8086,
1963 .subdevice = 0x4d56,
1964 .name = "Intel ICH/AD1885",
1965 .type = AC97_TUNE_HP_ONLY
1966 },
1967 {
1968 .subvendor = 0x8086,
1969 .subdevice = 0x6000,
1970 .mask = 0xfff0,
1971 .name = "Intel ICH5/AD1985",
1972 .type = AC97_TUNE_AD_SHARING
1973 },
1974 {
1975 .subvendor = 0x8086,
1976 .subdevice = 0xe000,
1977 .mask = 0xfff0,
1978 .name = "Intel ICH5/AD1985",
1979 .type = AC97_TUNE_AD_SHARING
1980 },
1981 #if 0 /* FIXME: this seems wrong on most boards */
1982 {
1983 .subvendor = 0x8086,
1984 .subdevice = 0xa000,
1985 .mask = 0xfff0,
1986 .name = "Intel ICH5/AD1985",
1987 .type = AC97_TUNE_HP_ONLY
1988 },
1989 #endif
1990 { } /* terminator */
1991 };
1992
1993 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override)
1994 {
1995 ac97_bus_t *pbus;
1996 ac97_template_t ac97;
1997 int err;
1998 unsigned int i, codecs;
1999 unsigned int glob_sta = 0;
2000 ac97_bus_ops_t *ops;
2001 static ac97_bus_ops_t standard_bus_ops = {
2002 .write = snd_intel8x0_codec_write,
2003 .read = snd_intel8x0_codec_read,
2004 };
2005 static ac97_bus_ops_t ali_bus_ops = {
2006 .write = snd_intel8x0_ali_codec_write,
2007 .read = snd_intel8x0_ali_codec_read,
2008 };
2009
2010 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2011 switch (chip->device_type) {
2012 case DEVICE_NFORCE:
2013 chip->spdif_idx = NVD_SPBAR;
2014 break;
2015 case DEVICE_ALI:
2016 chip->spdif_idx = ALID_AC97SPDIFOUT;
2017 break;
2018 case DEVICE_INTEL_ICH4:
2019 chip->spdif_idx = ICHD_SPBAR;
2020 break;
2021 };
2022
2023 chip->in_ac97_init = 1;
2024
2025 memset(&ac97, 0, sizeof(ac97));
2026 ac97.private_data = chip;
2027 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2028 ac97.scaps = AC97_SCAP_SKIP_MODEM;
2029 if (chip->xbox)
2030 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2031 if (chip->device_type != DEVICE_ALI) {
2032 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2033 ops = &standard_bus_ops;
2034 if (chip->device_type == DEVICE_INTEL_ICH4) {
2035 codecs = 0;
2036 if (glob_sta & ICH_PCR)
2037 codecs++;
2038 if (glob_sta & ICH_SCR)
2039 codecs++;
2040 if (glob_sta & ICH_TCR)
2041 codecs++;
2042 chip->in_sdin_init = 1;
2043 for (i = 0; i < codecs; i++) {
2044 snd_intel8x0_codec_read_test(chip, i);
2045 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2046 }
2047 chip->in_sdin_init = 0;
2048 } else {
2049 codecs = glob_sta & ICH_SCR ? 2 : 1;
2050 }
2051 } else {
2052 ops = &ali_bus_ops;
2053 codecs = 1;
2054 /* detect the secondary codec */
2055 for (i = 0; i < 100; i++) {
2056 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2057 if (reg & 0x40) {
2058 codecs = 2;
2059 break;
2060 }
2061 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2062 udelay(1);
2063 }
2064 }
2065 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2066 goto __err;
2067 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2068 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with modem driver */
2069 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2070 pbus->clock = ac97_clock;
2071 /* FIXME: my test board doesn't work well with VRA... */
2072 if (chip->device_type == DEVICE_ALI)
2073 pbus->no_vra = 1;
2074 else
2075 pbus->dra = 1;
2076 chip->ac97_bus = pbus;
2077
2078 ac97.pci = chip->pci;
2079 for (i = 0; i < codecs; i++) {
2080 ac97.num = i;
2081 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2082 if (err != -EACCES)
2083 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2084 if (i == 0)
2085 goto __err;
2086 continue;
2087 }
2088 }
2089 /* tune up the primary codec */
2090 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2091 /* enable separate SDINs for ICH4 */
2092 if (chip->device_type == DEVICE_INTEL_ICH4)
2093 pbus->isdin = 1;
2094 /* find the available PCM streams */
2095 i = ARRAY_SIZE(ac97_pcm_defs);
2096 if (chip->device_type != DEVICE_INTEL_ICH4)
2097 i -= 2; /* do not allocate PCM2IN and MIC2 */
2098 if (chip->spdif_idx < 0)
2099 i--; /* do not allocate S/PDIF */
2100 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2101 if (err < 0)
2102 goto __err;
2103 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2104 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2105 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2106 if (chip->spdif_idx >= 0)
2107 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2108 if (chip->device_type == DEVICE_INTEL_ICH4) {
2109 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2110 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2111 }
2112 /* enable separate SDINs for ICH4 */
2113 if (chip->device_type == DEVICE_INTEL_ICH4) {
2114 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2115 u8 tmp = igetbyte(chip, ICHREG(SDM));
2116 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2117 if (pcm) {
2118 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2119 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2120 for (i = 1; i < 4; i++) {
2121 if (pcm->r[0].codec[i]) {
2122 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2123 break;
2124 }
2125 }
2126 } else {
2127 tmp &= ~ICH_SE; /* steer disable */
2128 }
2129 iputbyte(chip, ICHREG(SDM), tmp);
2130 }
2131 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2132 chip->multi4 = 1;
2133 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2134 chip->multi6 = 1;
2135 }
2136 if (pbus->pcms[0].r[1].rslots[0]) {
2137 chip->dra = 1;
2138 }
2139 if (chip->device_type == DEVICE_INTEL_ICH4) {
2140 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2141 chip->smp20bit = 1;
2142 }
2143 if (chip->device_type == DEVICE_NFORCE) {
2144 /* 48kHz only */
2145 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2146 }
2147 if (chip->device_type == DEVICE_INTEL_ICH4) {
2148 /* use slot 10/11 for SPDIF */
2149 u32 val;
2150 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2151 val |= ICH_PCM_SPDIF_1011;
2152 iputdword(chip, ICHREG(GLOB_CNT), val);
2153 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2154 }
2155 chip->in_ac97_init = 0;
2156 return 0;
2157
2158 __err:
2159 /* clear the cold-reset bit for the next chance */
2160 if (chip->device_type != DEVICE_ALI)
2161 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2162 return err;
2163 }
2164
2165
2166 /*
2167 *
2168 */
2169
2170 static void do_ali_reset(intel8x0_t *chip)
2171 {
2172 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2173 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2174 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2175 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2176 iputdword(chip, ICHREG(ALI_INTERFACECR),
2177 ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2178 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2179 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2180 }
2181
2182 #define do_delay(chip) do {\
2183 set_current_state(TASK_UNINTERRUPTIBLE);\
2184 schedule_timeout(1);\
2185 } while (0)
2186
2187 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2188 {
2189 unsigned long end_time;
2190 unsigned int cnt, status, nstatus;
2191
2192 /* put logic to right state */
2193 /* first clear status bits */
2194 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2195 if (chip->device_type == DEVICE_NFORCE)
2196 status |= ICH_NVSPINT;
2197 cnt = igetdword(chip, ICHREG(GLOB_STA));
2198 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2199
2200 /* ACLink on, 2 channels */
2201 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2202 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2203 /* finish cold or do warm reset */
2204 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2205 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2206 end_time = (jiffies + (HZ / 4)) + 1;
2207 do {
2208 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2209 goto __ok;
2210 do_delay(chip);
2211 } while (time_after_eq(end_time, jiffies));
2212 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2213 return -EIO;
2214
2215 __ok:
2216 if (probing) {
2217 /* wait for any codec ready status.
2218 * Once it becomes ready it should remain ready
2219 * as long as we do not disable the ac97 link.
2220 */
2221 end_time = jiffies + HZ;
2222 do {
2223 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2224 if (status)
2225 break;
2226 do_delay(chip);
2227 } while (time_after_eq(end_time, jiffies));
2228 if (! status) {
2229 /* no codec is found */
2230 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2231 return -EIO;
2232 }
2233
2234 if (chip->device_type == DEVICE_INTEL_ICH4)
2235 /* ICH4 can have three codecs */
2236 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2237 else
2238 /* others up to two codecs */
2239 nstatus = ICH_PCR | ICH_SCR;
2240
2241 /* wait for other codecs ready status. */
2242 end_time = jiffies + HZ / 4;
2243 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2244 do_delay(chip);
2245 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2246 }
2247
2248 } else {
2249 /* resume phase */
2250 int i;
2251 status = 0;
2252 for (i = 0; i < 3; i++)
2253 if (chip->ac97[i])
2254 status |= get_ich_codec_bit(chip, i);
2255 /* wait until all the probed codecs are ready */
2256 end_time = jiffies + HZ;
2257 do {
2258 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2259 if (status == nstatus)
2260 break;
2261 do_delay(chip);
2262 } while (time_after_eq(end_time, jiffies));
2263 }
2264
2265 if (chip->device_type == DEVICE_SIS) {
2266 /* unmute the output on SIS7012 */
2267 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2268 }
2269 if (chip->device_type == DEVICE_NFORCE) {
2270 /* enable SPDIF interrupt */
2271 unsigned int val;
2272 pci_read_config_dword(chip->pci, 0x4c, &val);
2273 val |= 0x1000000;
2274 pci_write_config_dword(chip->pci, 0x4c, val);
2275 }
2276 return 0;
2277 }
2278
2279 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2280 {
2281 u32 reg;
2282 int i = 0;
2283
2284 reg = igetdword(chip, ICHREG(ALI_SCR));
2285 if ((reg & 2) == 0) /* Cold required */
2286 reg |= 2;
2287 else
2288 reg |= 1; /* Warm */
2289 reg &= ~0x80000000; /* ACLink on */
2290 iputdword(chip, ICHREG(ALI_SCR), reg);
2291
2292 for (i = 0; i < HZ / 2; i++) {
2293 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2294 goto __ok;
2295 do_delay(chip);
2296 }
2297 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2298 if (probing)
2299 return -EIO;
2300
2301 __ok:
2302 for (i = 0; i < HZ / 2; i++) {
2303 reg = igetdword(chip, ICHREG(ALI_RTSR));
2304 if (reg & 0x80) /* primary codec */
2305 break;
2306 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2307 do_delay(chip);
2308 }
2309
2310 do_ali_reset(chip);
2311 return 0;
2312 }
2313
2314 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2315 {
2316 unsigned int i;
2317 int err;
2318
2319 if (chip->device_type != DEVICE_ALI) {
2320 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2321 return err;
2322 iagetword(chip, 0); /* clear semaphore flag */
2323 } else {
2324 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2325 return err;
2326 }
2327
2328 /* disable interrupts */
2329 for (i = 0; i < chip->bdbars_count; i++)
2330 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2331 /* reset channels */
2332 for (i = 0; i < chip->bdbars_count; i++)
2333 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2334 /* initialize Buffer Descriptor Lists */
2335 for (i = 0; i < chip->bdbars_count; i++)
2336 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2337 return 0;
2338 }
2339
2340 static int snd_intel8x0_free(intel8x0_t *chip)
2341 {
2342 unsigned int i;
2343
2344 if (chip->irq < 0)
2345 goto __hw_end;
2346 /* disable interrupts */
2347 for (i = 0; i < chip->bdbars_count; i++)
2348 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2349 /* reset channels */
2350 for (i = 0; i < chip->bdbars_count; i++)
2351 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2352 if (chip->device_type == DEVICE_NFORCE) {
2353 /* stop the spdif interrupt */
2354 unsigned int val;
2355 pci_read_config_dword(chip->pci, 0x4c, &val);
2356 val &= ~0x1000000;
2357 pci_write_config_dword(chip->pci, 0x4c, val);
2358 }
2359 /* --- */
2360 synchronize_irq(chip->irq);
2361 __hw_end:
2362 if (chip->irq >= 0)
2363 free_irq(chip->irq, (void *)chip);
2364 if (chip->bdbars.area) {
2365 if (chip->fix_nocache)
2366 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2367 snd_dma_free_pages(&chip->bdbars);
2368 }
2369 if (chip->remap_addr)
2370 iounmap(chip->remap_addr);
2371 if (chip->remap_bmaddr)
2372 iounmap(chip->remap_bmaddr);
2373 pci_release_regions(chip->pci);
2374 pci_disable_device(chip->pci);
2375 kfree(chip);
2376 return 0;
2377 }
2378
2379 #ifdef CONFIG_PM
2380 /*
2381 * power management
2382 */
2383 static int intel8x0_suspend(snd_card_t *card, pm_message_t state)
2384 {
2385 intel8x0_t *chip = card->pm_private_data;
2386 int i;
2387
2388 for (i = 0; i < chip->pcm_devs; i++)
2389 snd_pcm_suspend_all(chip->pcm[i]);
2390 /* clear nocache */
2391 if (chip->fix_nocache) {
2392 for (i = 0; i < chip->bdbars_count; i++) {
2393 ichdev_t *ichdev = &chip->ichd[i];
2394 if (ichdev->substream && ichdev->page_attr_changed) {
2395 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2396 if (runtime->dma_area)
2397 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2398 }
2399 }
2400 }
2401 for (i = 0; i < 3; i++)
2402 if (chip->ac97[i])
2403 snd_ac97_suspend(chip->ac97[i]);
2404 if (chip->device_type == DEVICE_INTEL_ICH4)
2405 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2406
2407 if (chip->irq >= 0)
2408 free_irq(chip->irq, (void *)chip);
2409 pci_disable_device(chip->pci);
2410 return 0;
2411 }
2412
2413 static int intel8x0_resume(snd_card_t *card)
2414 {
2415 intel8x0_t *chip = card->pm_private_data;
2416 int i;
2417
2418 pci_enable_device(chip->pci);
2419 pci_set_master(chip->pci);
2420 request_irq(chip->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip);
2421 synchronize_irq(chip->irq);
2422 snd_intel8x0_chip_init(chip, 1);
2423
2424 /* re-initialize mixer stuff */
2425 if (chip->device_type == DEVICE_INTEL_ICH4) {
2426 /* enable separate SDINs for ICH4 */
2427 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2428 /* use slot 10/11 for SPDIF */
2429 iputdword(chip, ICHREG(GLOB_CNT),
2430 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2431 ICH_PCM_SPDIF_1011);
2432 }
2433
2434 /* refill nocache */
2435 if (chip->fix_nocache)
2436 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2437
2438 for (i = 0; i < 3; i++)
2439 if (chip->ac97[i])
2440 snd_ac97_resume(chip->ac97[i]);
2441
2442 /* refill nocache */
2443 if (chip->fix_nocache) {
2444 for (i = 0; i < chip->bdbars_count; i++) {
2445 ichdev_t *ichdev = &chip->ichd[i];
2446 if (ichdev->substream && ichdev->page_attr_changed) {
2447 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2448 if (runtime->dma_area)
2449 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2450 }
2451 }
2452 }
2453
2454 /* resume status */
2455 for (i = 0; i < chip->bdbars_count; i++) {
2456 ichdev_t *ichdev = &chip->ichd[i];
2457 unsigned long port = ichdev->reg_offset;
2458 if (! ichdev->substream || ! ichdev->suspended)
2459 continue;
2460 if (ichdev->ichd == ICHD_PCMOUT)
2461 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2462 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2463 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2464 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2465 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2466 }
2467
2468 return 0;
2469 }
2470 #endif /* CONFIG_PM */
2471
2472 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2473
2474 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2475 {
2476 snd_pcm_substream_t *subs;
2477 ichdev_t *ichdev;
2478 unsigned long port;
2479 unsigned long pos, t;
2480 struct timeval start_time, stop_time;
2481
2482 if (chip->ac97_bus->clock != 48000)
2483 return; /* specified in module option */
2484
2485 subs = chip->pcm[0]->streams[0].substream;
2486 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2487 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2488 return;
2489 }
2490 ichdev = &chip->ichd[ICHD_PCMOUT];
2491 ichdev->physbuf = subs->dma_buffer.addr;
2492 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2493 ichdev->substream = NULL; /* don't process interrupts */
2494
2495 /* set rate */
2496 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2497 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2498 return;
2499 }
2500 snd_intel8x0_setup_periods(chip, ichdev);
2501 port = ichdev->reg_offset;
2502 spin_lock_irq(&chip->reg_lock);
2503 chip->in_measurement = 1;
2504 /* trigger */
2505 if (chip->device_type != DEVICE_ALI)
2506 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2507 else {
2508 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2509 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2510 }
2511 do_gettimeofday(&start_time);
2512 spin_unlock_irq(&chip->reg_lock);
2513 msleep(50);
2514 spin_lock_irq(&chip->reg_lock);
2515 /* check the position */
2516 pos = ichdev->fragsize1;
2517 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2518 pos += ichdev->position;
2519 chip->in_measurement = 0;
2520 do_gettimeofday(&stop_time);
2521 /* stop */
2522 if (chip->device_type == DEVICE_ALI) {
2523 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2524 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2525 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2526 ;
2527 } else {
2528 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2529 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2530 ;
2531 }
2532 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2533 spin_unlock_irq(&chip->reg_lock);
2534
2535 t = stop_time.tv_sec - start_time.tv_sec;
2536 t *= 1000000;
2537 t += stop_time.tv_usec - start_time.tv_usec;
2538 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2539 if (t == 0) {
2540 snd_printk(KERN_ERR "?? calculation error..\n");
2541 return;
2542 }
2543 pos = (pos / 4) * 1000;
2544 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2545 if (pos < 40000 || pos >= 60000)
2546 /* abnormal value. hw problem? */
2547 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2548 else if (pos < 47500 || pos > 48500)
2549 /* not 48000Hz, tuning the clock.. */
2550 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2551 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2552 }
2553
2554 static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2555 snd_info_buffer_t * buffer)
2556 {
2557 intel8x0_t *chip = entry->private_data;
2558 unsigned int tmp;
2559
2560 snd_iprintf(buffer, "Intel8x0\n\n");
2561 if (chip->device_type == DEVICE_ALI)
2562 return;
2563 tmp = igetdword(chip, ICHREG(GLOB_STA));
2564 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2565 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2566 if (chip->device_type == DEVICE_INTEL_ICH4)
2567 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2568 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2569 tmp & ICH_PCR ? " primary" : "",
2570 tmp & ICH_SCR ? " secondary" : "",
2571 tmp & ICH_TCR ? " tertiary" : "",
2572 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2573 if (chip->device_type == DEVICE_INTEL_ICH4)
2574 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2575 chip->ac97_sdin[0],
2576 chip->ac97_sdin[1],
2577 chip->ac97_sdin[2]);
2578 }
2579
2580 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2581 {
2582 snd_info_entry_t *entry;
2583
2584 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2585 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2586 }
2587
2588 static int snd_intel8x0_dev_free(snd_device_t *device)
2589 {
2590 intel8x0_t *chip = device->device_data;
2591 return snd_intel8x0_free(chip);
2592 }
2593
2594 struct ich_reg_info {
2595 unsigned int int_sta_mask;
2596 unsigned int offset;
2597 };
2598
2599 static int __devinit snd_intel8x0_create(snd_card_t * card,
2600 struct pci_dev *pci,
2601 unsigned long device_type,
2602 intel8x0_t ** r_intel8x0)
2603 {
2604 intel8x0_t *chip;
2605 int err;
2606 unsigned int i;
2607 unsigned int int_sta_masks;
2608 ichdev_t *ichdev;
2609 static snd_device_ops_t ops = {
2610 .dev_free = snd_intel8x0_dev_free,
2611 };
2612
2613 static unsigned int bdbars[] = {
2614 3, /* DEVICE_INTEL */
2615 6, /* DEVICE_INTEL_ICH4 */
2616 3, /* DEVICE_SIS */
2617 6, /* DEVICE_ALI */
2618 4, /* DEVICE_NFORCE */
2619 };
2620 static struct ich_reg_info intel_regs[6] = {
2621 { ICH_PIINT, 0 },
2622 { ICH_POINT, 0x10 },
2623 { ICH_MCINT, 0x20 },
2624 { ICH_M2INT, 0x40 },
2625 { ICH_P2INT, 0x50 },
2626 { ICH_SPINT, 0x60 },
2627 };
2628 static struct ich_reg_info nforce_regs[4] = {
2629 { ICH_PIINT, 0 },
2630 { ICH_POINT, 0x10 },
2631 { ICH_MCINT, 0x20 },
2632 { ICH_NVSPINT, 0x70 },
2633 };
2634 static struct ich_reg_info ali_regs[6] = {
2635 { ALI_INT_PCMIN, 0x40 },
2636 { ALI_INT_PCMOUT, 0x50 },
2637 { ALI_INT_MICIN, 0x60 },
2638 { ALI_INT_CODECSPDIFOUT, 0x70 },
2639 { ALI_INT_SPDIFIN, 0xa0 },
2640 { ALI_INT_SPDIFOUT, 0xb0 },
2641 };
2642 struct ich_reg_info *tbl;
2643
2644 *r_intel8x0 = NULL;
2645
2646 if ((err = pci_enable_device(pci)) < 0)
2647 return err;
2648
2649 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2650 if (chip == NULL) {
2651 pci_disable_device(pci);
2652 return -ENOMEM;
2653 }
2654 spin_lock_init(&chip->reg_lock);
2655 chip->device_type = device_type;
2656 chip->card = card;
2657 chip->pci = pci;
2658 chip->irq = -1;
2659
2660 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2661 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2662 chip->fix_nocache = 1; /* enable workaround */
2663
2664 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2665 * Needs to return IRQ_HANDLED for unknown irqs.
2666 */
2667 if (device_type == DEVICE_NFORCE)
2668 chip->buggy_irq = 1;
2669
2670 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2671 kfree(chip);
2672 pci_disable_device(pci);
2673 return err;
2674 }
2675
2676 if (device_type == DEVICE_ALI) {
2677 /* ALI5455 has no ac97 region */
2678 chip->bmaddr = pci_resource_start(pci, 0);
2679 goto port_inited;
2680 }
2681
2682 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2683 chip->mmio = 1;
2684 chip->addr = pci_resource_start(pci, 2);
2685 chip->remap_addr = ioremap_nocache(chip->addr,
2686 pci_resource_len(pci, 2));
2687 if (chip->remap_addr == NULL) {
2688 snd_printk("AC'97 space ioremap problem\n");
2689 snd_intel8x0_free(chip);
2690 return -EIO;
2691 }
2692 } else {
2693 chip->addr = pci_resource_start(pci, 0);
2694 }
2695 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2696 chip->bm_mmio = 1;
2697 chip->bmaddr = pci_resource_start(pci, 3);
2698 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2699 pci_resource_len(pci, 3));
2700 if (chip->remap_bmaddr == NULL) {
2701 snd_printk("Controller space ioremap problem\n");
2702 snd_intel8x0_free(chip);
2703 return -EIO;
2704 }
2705 } else {
2706 chip->bmaddr = pci_resource_start(pci, 1);
2707 }
2708
2709 port_inited:
2710 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2711 snd_printk("unable to grab IRQ %d\n", pci->irq);
2712 snd_intel8x0_free(chip);
2713 return -EBUSY;
2714 }
2715 chip->irq = pci->irq;
2716 pci_set_master(pci);
2717 synchronize_irq(chip->irq);
2718
2719 chip->bdbars_count = bdbars[device_type];
2720
2721 /* initialize offsets */
2722 switch (device_type) {
2723 case DEVICE_NFORCE:
2724 tbl = nforce_regs;
2725 break;
2726 case DEVICE_ALI:
2727 tbl = ali_regs;
2728 break;
2729 default:
2730 tbl = intel_regs;
2731 break;
2732 }
2733 for (i = 0; i < chip->bdbars_count; i++) {
2734 ichdev = &chip->ichd[i];
2735 ichdev->ichd = i;
2736 ichdev->reg_offset = tbl[i].offset;
2737 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2738 if (device_type == DEVICE_SIS) {
2739 /* SiS 7012 swaps the registers */
2740 ichdev->roff_sr = ICH_REG_OFF_PICB;
2741 ichdev->roff_picb = ICH_REG_OFF_SR;
2742 } else {
2743 ichdev->roff_sr = ICH_REG_OFF_SR;
2744 ichdev->roff_picb = ICH_REG_OFF_PICB;
2745 }
2746 if (device_type == DEVICE_ALI)
2747 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2748 /* SIS7012 handles the pcm data in bytes, others are in samples */
2749 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2750 }
2751
2752 /* allocate buffer descriptor lists */
2753 /* the start of each lists must be aligned to 8 bytes */
2754 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2755 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2756 &chip->bdbars) < 0) {
2757 snd_intel8x0_free(chip);
2758 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2759 return -ENOMEM;
2760 }
2761 /* tables must be aligned to 8 bytes here, but the kernel pages
2762 are much bigger, so we don't care (on i386) */
2763 /* workaround for 440MX */
2764 if (chip->fix_nocache)
2765 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2766 int_sta_masks = 0;
2767 for (i = 0; i < chip->bdbars_count; i++) {
2768 ichdev = &chip->ichd[i];
2769 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2770 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2771 int_sta_masks |= ichdev->int_sta_mask;
2772 }
2773 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2774 chip->int_sta_mask = int_sta_masks;
2775
2776 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2777 snd_intel8x0_free(chip);
2778 return err;
2779 }
2780
2781 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2782
2783 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2784 snd_intel8x0_free(chip);
2785 return err;
2786 }
2787
2788 snd_card_set_dev(card, &pci->dev);
2789
2790 *r_intel8x0 = chip;
2791 return 0;
2792 }
2793
2794 static struct shortname_table {
2795 unsigned int id;
2796 const char *s;
2797 } shortnames[] __devinitdata = {
2798 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2799 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2800 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2801 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2802 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2803 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2804 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2805 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2806 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2807 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2808 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2809 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2810 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2811 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2812 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2813 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2814 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2815 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2816 { 0x003a, "NVidia MCP04" },
2817 { 0x746d, "AMD AMD8111" },
2818 { 0x7445, "AMD AMD768" },
2819 { 0x5455, "ALi M5455" },
2820 { 0, NULL },
2821 };
2822
2823 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2824 const struct pci_device_id *pci_id)
2825 {
2826 static int dev;
2827 snd_card_t *card;
2828 intel8x0_t *chip;
2829 int err;
2830 struct shortname_table *name;
2831
2832 if (dev >= SNDRV_CARDS)
2833 return -ENODEV;
2834 if (!enable[dev]) {
2835 dev++;
2836 return -ENOENT;
2837 }
2838
2839 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2840 if (card == NULL)
2841 return -ENOMEM;
2842
2843 switch (pci_id->driver_data) {
2844 case DEVICE_NFORCE:
2845 strcpy(card->driver, "NFORCE");
2846 break;
2847 case DEVICE_INTEL_ICH4:
2848 strcpy(card->driver, "ICH4");
2849 break;
2850 default:
2851 strcpy(card->driver, "ICH");
2852 break;
2853 }
2854
2855 strcpy(card->shortname, "Intel ICH");
2856 for (name = shortnames; name->id; name++) {
2857 if (pci->device == name->id) {
2858 strcpy(card->shortname, name->s);
2859 break;
2860 }
2861 }
2862
2863 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2864 snd_card_free(card);
2865 return err;
2866 }
2867 if (buggy_irq[dev])
2868 chip->buggy_irq = 1;
2869 if (xbox[dev])
2870 chip->xbox = 1;
2871
2872 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2873 snd_card_free(card);
2874 return err;
2875 }
2876 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2877 snd_card_free(card);
2878 return err;
2879 }
2880
2881 snd_intel8x0_proc_init(chip);
2882
2883 snprintf(card->longname, sizeof(card->longname),
2884 "%s with %s at %#lx, irq %i", card->shortname,
2885 snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2886
2887 if (! ac97_clock[dev])
2888 intel8x0_measure_ac97_clock(chip);
2889
2890 if ((err = snd_card_register(card)) < 0) {
2891 snd_card_free(card);
2892 return err;
2893 }
2894 pci_set_drvdata(pci, card);
2895 dev++;
2896 return 0;
2897 }
2898
2899 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2900 {
2901 snd_card_free(pci_get_drvdata(pci));
2902 pci_set_drvdata(pci, NULL);
2903 }
2904
2905 static struct pci_driver driver = {
2906 .name = "Intel ICH",
2907 .id_table = snd_intel8x0_ids,
2908 .probe = snd_intel8x0_probe,
2909 .remove = __devexit_p(snd_intel8x0_remove),
2910 SND_PCI_PM_CALLBACKS
2911 };
2912
2913
2914 static int __init alsa_card_intel8x0_init(void)
2915 {
2916 return pci_register_driver(&driver);
2917 }
2918
2919 static void __exit alsa_card_intel8x0_exit(void)
2920 {
2921 pci_unregister_driver(&driver);
2922 }
2923
2924 module_init(alsa_card_intel8x0_init)
2925 module_exit(alsa_card_intel8x0_exit)
kernel-based virtual machine