drivers/net/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _IGB_H_
  32 #define _IGB_H_
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36
  37 #include <linux/clocksource.h>
  38 #include <linux/timecompare.h>
  39 #include <linux/net_tstamp.h>
  40
  41 struct igb_adapter;
  42
  43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
  44 #define IGB_START_ITR 648
  45
  46 /* TX/RX descriptor defines */
  47 #define IGB_DEFAULT_TXD                  256
  48 #define IGB_MIN_TXD                       80
  49 #define IGB_MAX_TXD                     4096
  50
  51 #define IGB_DEFAULT_RXD                  256
  52 #define IGB_MIN_RXD                       80
  53 #define IGB_MAX_RXD                     4096
  54
  55 #define IGB_DEFAULT_ITR                    3 /* dynamic */
  56 #define IGB_MAX_ITR_USECS              10000
  57 #define IGB_MIN_ITR_USECS                 10
  58 #define NON_Q_VECTORS                      1
  59 #define MAX_Q_VECTORS                      8
  60
  61 /* Transmit and receive queues */
  62 #define IGB_MAX_RX_QUEUES     (adapter->vfs_allocated_count ? \
  63                                (adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
  64 #define IGB_MAX_TX_QUEUES     IGB_MAX_RX_QUEUES
  65 #define IGB_ABS_MAX_TX_QUEUES     4
  66
  67 #define IGB_MAX_VF_MC_ENTRIES              30
  68 #define IGB_MAX_VF_FUNCTIONS               8
  69 #define IGB_MAX_VFTA_ENTRIES               128
  70
  71 struct vf_data_storage {
  72         unsigned char vf_mac_addresses[ETH_ALEN];
  73         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
  74         u16 num_vf_mc_hashes;
  75         u16 vlans_enabled;
  76         bool clear_to_send;
  77 };
  78
  79 /* RX descriptor control thresholds.
  80  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
  81  *           descriptors available in its onboard memory.
  82  *           Setting this to 0 disables RX descriptor prefetch.
  83  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
  84  *           available in host memory.
  85  *           If PTHRESH is 0, this should also be 0.
  86  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
  87  *           descriptors until either it has this many to write back, or the
  88  *           ITR timer expires.
  89  */
  90 #define IGB_RX_PTHRESH                    16
  91 #define IGB_RX_HTHRESH                     8
  92 #define IGB_RX_WTHRESH                     1
  93
  94 /* this is the size past which hardware will drop packets when setting LPE=0 */
  95 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
  96
  97 /* Supported Rx Buffer Sizes */
  98 #define IGB_RXBUFFER_128   128    /* Used for packet split */
  99 #define IGB_RXBUFFER_1024  1024
 100 #define IGB_RXBUFFER_2048  2048
 101 #define IGB_RXBUFFER_16384 16384
 102
 103 #define MAX_STD_JUMBO_FRAME_SIZE 9234
 104
 105 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
 106 #define IGB_TX_QUEUE_WAKE       16
 107 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 108 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
 109
 110 #define AUTO_ALL_MODES            0
 111 #define IGB_EEPROM_APME         0x0400
 112
 113 #ifndef IGB_MASTER_SLAVE
 114 /* Switch to override PHY master/slave setting */
 115 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 116 #endif
 117
 118 #define IGB_MNG_VLAN_NONE -1
 119
 120 /* wrapper around a pointer to a socket buffer,
 121  * so a DMA handle can be stored along with the buffer */
 122 struct igb_buffer {
 123         struct sk_buff *skb;
 124         dma_addr_t dma;
 125         union {
 126                 /* TX */
 127                 struct {
 128                         unsigned long time_stamp;
 129                         u16 length;
 130                         u16 next_to_watch;
 131                 };
 132                 /* RX */
 133                 struct {
 134                         struct page *page;
 135                         u64 page_dma;
 136                         unsigned int page_offset;
 137                 };
 138         };
 139 };
 140
 141 struct igb_tx_queue_stats {
 142         u64 packets;
 143         u64 bytes;
 144 };
 145
 146 struct igb_rx_queue_stats {
 147         u64 packets;
 148         u64 bytes;
 149         u64 drops;
 150 };
 151
 152 struct igb_q_vector {
 153         struct igb_adapter *adapter; /* backlink */
 154         struct igb_ring *rx_ring;
 155         struct igb_ring *tx_ring;
 156         struct napi_struct napi;
 157
 158         u32 eims_value;
 159         u16 cpu;
 160
 161         u16 itr_val;
 162         u8 set_itr;
 163         u8 itr_shift;
 164         void __iomem *itr_register;
 165
 166         char name[IFNAMSIZ + 9];
 167 };
 168
 169 struct igb_ring {
 170         struct igb_q_vector *q_vector; /* backlink to q_vector */
 171         void *desc;                    /* descriptor ring memory */
 172         dma_addr_t dma;                /* phys address of the ring */
 173         unsigned int size;             /* length of desc. ring in bytes */
 174         unsigned int count;            /* number of desc. in the ring */
 175         u16 next_to_use;
 176         u16 next_to_clean;
 177         u16 head;
 178         u16 tail;
 179         struct igb_buffer *buffer_info; /* array of buffer info structs */
 180
 181         u8 queue_index;
 182         u8 reg_idx;
 183
 184         unsigned int total_bytes;
 185         unsigned int total_packets;
 186
 187         union {
 188                 /* TX */
 189                 struct {
 190                         struct igb_tx_queue_stats tx_stats;
 191                         bool detect_tx_hung;
 192                 };
 193                 /* RX */
 194                 struct {
 195                         struct igb_rx_queue_stats rx_stats;
 196                         u64 rx_queue_drops;
 197                 };
 198         };
 199 };
 200
 201 #define E1000_RX_DESC_ADV(R, i)     \
 202         (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
 203 #define E1000_TX_DESC_ADV(R, i)     \
 204         (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
 205 #define E1000_TX_CTXTDESC_ADV(R, i)         \
 206         (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
 207
 208 /* board specific private data structure */
 209
 210 struct igb_adapter {
 211         struct timer_list watchdog_timer;
 212         struct timer_list phy_info_timer;
 213         struct vlan_group *vlgrp;
 214         u16 mng_vlan_id;
 215         u32 bd_number;
 216         u32 rx_buffer_len;
 217         u32 wol;
 218         u32 en_mng_pt;
 219         u16 link_speed;
 220         u16 link_duplex;
 221         unsigned int total_tx_bytes;
 222         unsigned int total_tx_packets;
 223         unsigned int total_rx_bytes;
 224         unsigned int total_rx_packets;
 225         /* Interrupt Throttle Rate */
 226         u32 itr;
 227         u32 itr_setting;
 228         u16 tx_itr;
 229         u16 rx_itr;
 230
 231         struct work_struct reset_task;
 232         struct work_struct watchdog_task;
 233         bool fc_autoneg;
 234         u8  tx_timeout_factor;
 235         struct timer_list blink_timer;
 236         unsigned long led_status;
 237
 238         /* TX */
 239         struct igb_ring *tx_ring;      /* One per active queue */
 240         unsigned int restart_queue;
 241         unsigned long tx_queue_len;
 242         u32 txd_cmd;
 243         u32 gotc;
 244         u64 gotc_old;
 245         u64 tpt_old;
 246         u64 colc_old;
 247         u32 tx_timeout_count;
 248
 249         /* RX */
 250         struct igb_ring *rx_ring;      /* One per active queue */
 251         int num_tx_queues;
 252         int num_rx_queues;
 253
 254         u64 hw_csum_err;
 255         u32 alloc_rx_buff_failed;
 256         u32 gorc;
 257         u64 gorc_old;
 258         u16 rx_ps_hdr_size;
 259         u32 max_frame_size;
 260         u32 min_frame_size;
 261
 262         /* OS defined structs */
 263         struct net_device *netdev;
 264         struct pci_dev *pdev;
 265         struct cyclecounter cycles;
 266         struct timecounter clock;
 267         struct timecompare compare;
 268         struct hwtstamp_config hwtstamp_config;
 269
 270         /* structs defined in e1000_hw.h */
 271         struct e1000_hw hw;
 272         struct e1000_hw_stats stats;
 273         struct e1000_phy_info phy_info;
 274         struct e1000_phy_stats phy_stats;
 275
 276         u32 test_icr;
 277         struct igb_ring test_tx_ring;
 278         struct igb_ring test_rx_ring;
 279
 280         int msg_enable;
 281
 282         unsigned int num_q_vectors;
 283         struct igb_q_vector *q_vector[MAX_Q_VECTORS];
 284         struct msix_entry *msix_entries;
 285         u32 eims_enable_mask;
 286         u32 eims_other;
 287
 288         /* to not mess up cache alignment, always add to the bottom */
 289         unsigned long state;
 290         unsigned int flags;
 291         u32 eeprom_wol;
 292
 293         struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
 294         unsigned int tx_ring_count;
 295         unsigned int rx_ring_count;
 296         unsigned int vfs_allocated_count;
 297         struct vf_data_storage *vf_data;
 298 };
 299
 300 #define IGB_FLAG_HAS_MSI           (1 << 0)
 301 #define IGB_FLAG_DCA_ENABLED       (1 << 1)
 302 #define IGB_FLAG_QUAD_PORT_A       (1 << 2)
 303 #define IGB_FLAG_NEED_CTX_IDX      (1 << 3)
 304 #define IGB_FLAG_RX_CSUM_DISABLED  (1 << 4)
 305
 306 enum e1000_state_t {
 307         __IGB_TESTING,
 308         __IGB_RESETTING,
 309         __IGB_DOWN
 310 };
 311
 312 enum igb_boards {
 313         board_82575,
 314 };
 315
 316 extern char igb_driver_name[];
 317 extern char igb_driver_version[];
 318
 319 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 320 extern int igb_up(struct igb_adapter *);
 321 extern void igb_down(struct igb_adapter *);
 322 extern void igb_reinit_locked(struct igb_adapter *);
 323 extern void igb_reset(struct igb_adapter *);
 324 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
 325 extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
 326 extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
 327 extern void igb_free_tx_resources(struct igb_ring *);
 328 extern void igb_free_rx_resources(struct igb_ring *);
 329 extern void igb_update_stats(struct igb_adapter *);
 330 extern void igb_set_ethtool_ops(struct net_device *);
 331
 332 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 333 {
 334         if (hw->phy.ops.reset)
 335                 return hw->phy.ops.reset(hw);
 336
 337         return 0;
 338 }
 339
 340 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 341 {
 342         if (hw->phy.ops.read_reg)
 343                 return hw->phy.ops.read_reg(hw, offset, data);
 344
 345         return 0;
 346 }
 347
 348 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 349 {
 350         if (hw->phy.ops.write_reg)
 351                 return hw->phy.ops.write_reg(hw, offset, data);
 352
 353         return 0;
 354 }
 355
 356 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 357 {
 358         if (hw->phy.ops.get_phy_info)
 359                 return hw->phy.ops.get_phy_info(hw);
 360
 361         return 0;
 362 }
 363
 364 #endif /* _IGB_H_ */