2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * Implementation of transmit path.
23 #define BITS_PER_BYTE 8
24 #define OFDM_PLCP_BITS 22
25 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
26 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
32 #define HT_LTF(_ns) (4 * (_ns))
33 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
34 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
35 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
36 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 #define OFDM_SIFS_TIME 16
40 static u32 bits_per_symbol
[][2] = {
42 { 26, 54 }, /* 0: BPSK */
43 { 52, 108 }, /* 1: QPSK 1/2 */
44 { 78, 162 }, /* 2: QPSK 3/4 */
45 { 104, 216 }, /* 3: 16-QAM 1/2 */
46 { 156, 324 }, /* 4: 16-QAM 3/4 */
47 { 208, 432 }, /* 5: 64-QAM 2/3 */
48 { 234, 486 }, /* 6: 64-QAM 3/4 */
49 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 { 52, 108 }, /* 8: BPSK */
51 { 104, 216 }, /* 9: QPSK 1/2 */
52 { 156, 324 }, /* 10: QPSK 3/4 */
53 { 208, 432 }, /* 11: 16-QAM 1/2 */
54 { 312, 648 }, /* 12: 16-QAM 3/4 */
55 { 416, 864 }, /* 13: 64-QAM 2/3 */
56 { 468, 972 }, /* 14: 64-QAM 3/4 */
57 { 520, 1080 }, /* 15: 64-QAM 5/6 */
60 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
63 * Insert a chain of ath_buf (descriptors) on a multicast txq
64 * but do NOT start tx DMA on this queue.
65 * NB: must be called with txq lock held
68 static void ath_tx_mcastqaddbuf(struct ath_softc
*sc
,
70 struct list_head
*head
)
72 struct ath_hal
*ah
= sc
->sc_ah
;
79 * Insert the frame on the outbound list and
80 * pass it on to the hardware.
82 bf
= list_first_entry(head
, struct ath_buf
, list
);
85 * The CAB queue is started from the SWBA handler since
86 * frames only go out on DTIM and to avoid possible races.
88 ath9k_hw_set_interrupts(ah
, 0);
91 * If there is anything in the mcastq, we want to set
92 * the "more data" bit in the last item in the queue to
93 * indicate that there is "more data". It makes sense to add
94 * it here since you are *always* going to have
95 * more data when adding to this queue, no matter where
101 struct ieee80211_hdr
*hdr
;
104 * Add the "more data flag" to the last frame
107 lbf
= list_entry(txq
->axq_q
.prev
, struct ath_buf
, list
);
108 hdr
= (struct ieee80211_hdr
*)
109 ((struct sk_buff
*)(lbf
->bf_mpdu
))->data
;
110 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
114 * Now, concat the frame onto the queue
116 list_splice_tail_init(head
, &txq
->axq_q
);
118 txq
->axq_totalqueued
++;
119 txq
->axq_linkbuf
= list_entry(txq
->axq_q
.prev
, struct ath_buf
, list
);
121 DPRINTF(sc
, ATH_DBG_QUEUE
,
122 "%s: txq depth = %d\n", __func__
, txq
->axq_depth
);
123 if (txq
->axq_link
!= NULL
) {
124 *txq
->axq_link
= bf
->bf_daddr
;
125 DPRINTF(sc
, ATH_DBG_XMIT
,
126 "%s: link[%u](%p)=%llx (%p)\n",
128 txq
->axq_qnum
, txq
->axq_link
,
129 ito64(bf
->bf_daddr
), bf
->bf_desc
);
131 txq
->axq_link
= &(bf
->bf_lastbf
->bf_desc
->ds_link
);
132 ath9k_hw_set_interrupts(ah
, sc
->sc_imask
);
136 * Insert a chain of ath_buf (descriptors) on a txq and
137 * assume the descriptors are already chained together by caller.
138 * NB: must be called with txq lock held
141 static void ath_tx_txqaddbuf(struct ath_softc
*sc
,
142 struct ath_txq
*txq
, struct list_head
*head
)
144 struct ath_hal
*ah
= sc
->sc_ah
;
147 * Insert the frame on the outbound list and
148 * pass it on to the hardware.
151 if (list_empty(head
))
154 bf
= list_first_entry(head
, struct ath_buf
, list
);
156 list_splice_tail_init(head
, &txq
->axq_q
);
158 txq
->axq_totalqueued
++;
159 txq
->axq_linkbuf
= list_entry(txq
->axq_q
.prev
, struct ath_buf
, list
);
161 DPRINTF(sc
, ATH_DBG_QUEUE
,
162 "%s: txq depth = %d\n", __func__
, txq
->axq_depth
);
164 if (txq
->axq_link
== NULL
) {
165 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
166 DPRINTF(sc
, ATH_DBG_XMIT
,
167 "%s: TXDP[%u] = %llx (%p)\n",
168 __func__
, txq
->axq_qnum
,
169 ito64(bf
->bf_daddr
), bf
->bf_desc
);
171 *txq
->axq_link
= bf
->bf_daddr
;
172 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: link[%u] (%p)=%llx (%p)\n",
174 txq
->axq_qnum
, txq
->axq_link
,
175 ito64(bf
->bf_daddr
), bf
->bf_desc
);
177 txq
->axq_link
= &(bf
->bf_lastbf
->bf_desc
->ds_link
);
178 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
181 /* Get transmit rate index using rate in Kbps */
183 static int ath_tx_findindex(const struct ath9k_rate_table
*rt
, int rate
)
188 for (i
= 0; i
< rt
->rateCount
; i
++) {
189 if (rt
->info
[i
].rateKbps
== rate
) {
198 /* Check if it's okay to send out aggregates */
200 static int ath_aggr_query(struct ath_softc
*sc
,
201 struct ath_node
*an
, u8 tidno
)
203 struct ath_atx_tid
*tid
;
204 tid
= ATH_AN_2_TID(an
, tidno
);
206 if (tid
->addba_exchangecomplete
|| tid
->addba_exchangeinprogress
)
212 static enum ath9k_pkt_type
get_hal_packet_type(struct ieee80211_hdr
*hdr
)
214 enum ath9k_pkt_type htype
;
217 fc
= hdr
->frame_control
;
219 /* Calculate Atheros packet type from IEEE80211 packet header */
221 if (ieee80211_is_beacon(fc
))
222 htype
= ATH9K_PKT_TYPE_BEACON
;
223 else if (ieee80211_is_probe_resp(fc
))
224 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
225 else if (ieee80211_is_atim(fc
))
226 htype
= ATH9K_PKT_TYPE_ATIM
;
227 else if (ieee80211_is_pspoll(fc
))
228 htype
= ATH9K_PKT_TYPE_PSPOLL
;
230 htype
= ATH9K_PKT_TYPE_NORMAL
;
235 static void fill_min_rates(struct sk_buff
*skb
, struct ath_tx_control
*txctl
)
237 struct ieee80211_hdr
*hdr
;
238 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
239 struct ath_tx_info_priv
*tx_info_priv
;
242 hdr
= (struct ieee80211_hdr
*)skb
->data
;
243 fc
= hdr
->frame_control
;
244 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
246 if (ieee80211_is_mgmt(fc
) || ieee80211_is_ctl(fc
)) {
247 txctl
->use_minrate
= 1;
248 txctl
->min_rate
= tx_info_priv
->min_rate
;
249 } else if (ieee80211_is_data(fc
)) {
250 if (ieee80211_is_nullfunc(fc
) ||
251 /* Port Access Entity (IEEE 802.1X) */
252 (skb
->protocol
== cpu_to_be16(0x888E))) {
253 txctl
->use_minrate
= 1;
254 txctl
->min_rate
= tx_info_priv
->min_rate
;
256 if (is_multicast_ether_addr(hdr
->addr1
))
257 txctl
->mcast_rate
= tx_info_priv
->min_rate
;
262 /* This function will setup additional txctl information, mostly rate stuff */
263 /* FIXME: seqno, ps */
264 static int ath_tx_prepare(struct ath_softc
*sc
,
266 struct ath_tx_control
*txctl
)
268 struct ieee80211_hw
*hw
= sc
->hw
;
269 struct ieee80211_hdr
*hdr
;
270 struct ath_rc_series
*rcs
;
271 struct ath_txq
*txq
= NULL
;
272 const struct ath9k_rate_table
*rt
;
273 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
274 struct ath_tx_info_priv
*tx_info_priv
;
280 memset(txctl
, 0, sizeof(struct ath_tx_control
));
283 hdr
= (struct ieee80211_hdr
*)skb
->data
;
284 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
285 fc
= hdr
->frame_control
;
287 rt
= sc
->sc_currates
;
290 /* Fill misc fields */
292 spin_lock_bh(&sc
->node_lock
);
293 txctl
->an
= ath_node_get(sc
, hdr
->addr1
);
294 /* create a temp node, if the node is not there already */
296 txctl
->an
= ath_node_attach(sc
, hdr
->addr1
, 0);
297 spin_unlock_bh(&sc
->node_lock
);
299 if (ieee80211_is_data_qos(fc
)) {
300 qc
= ieee80211_get_qos_ctl(hdr
);
301 txctl
->tidno
= qc
[0] & 0xf;
305 txctl
->nextfraglen
= 0;
306 txctl
->frmlen
= skb
->len
+ FCS_LEN
- (hdrlen
& 3);
307 txctl
->txpower
= MAX_RATE_POWER
; /* FIXME */
309 /* Fill Key related fields */
311 txctl
->keytype
= ATH9K_KEY_TYPE_CLEAR
;
312 txctl
->keyix
= ATH9K_TXKEYIX_INVALID
;
314 if (tx_info
->control
.hw_key
) {
315 txctl
->keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
316 txctl
->frmlen
+= tx_info
->control
.icv_len
;
318 if (sc
->sc_keytype
== ATH9K_CIPHER_WEP
)
319 txctl
->keytype
= ATH9K_KEY_TYPE_WEP
;
320 else if (sc
->sc_keytype
== ATH9K_CIPHER_TKIP
)
321 txctl
->keytype
= ATH9K_KEY_TYPE_TKIP
;
322 else if (sc
->sc_keytype
== ATH9K_CIPHER_AES_CCM
)
323 txctl
->keytype
= ATH9K_KEY_TYPE_AES
;
326 /* Fill packet type */
328 txctl
->atype
= get_hal_packet_type(hdr
);
332 txctl
->qnum
= ath_get_hal_qnum(skb_get_queue_mapping(skb
), sc
);
333 txq
= &sc
->sc_txq
[txctl
->qnum
];
334 spin_lock_bh(&txq
->axq_lock
);
336 /* Try to avoid running out of descriptors */
337 if (txq
->axq_depth
>= (ATH_TXBUF
- 20)) {
338 DPRINTF(sc
, ATH_DBG_FATAL
,
339 "%s: TX queue: %d is full, depth: %d\n",
343 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
345 spin_unlock_bh(&txq
->axq_lock
);
349 spin_unlock_bh(&txq
->axq_lock
);
353 fill_min_rates(skb
, txctl
);
357 txctl
->flags
= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
359 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
360 tx_info
->flags
|= ATH9K_TXDESC_NOACK
;
361 if (tx_info
->flags
& IEEE80211_TX_CTL_USE_RTS_CTS
)
362 tx_info
->flags
|= ATH9K_TXDESC_RTSENA
;
365 * Setup for rate calculations.
367 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
368 rcs
= tx_info_priv
->rcs
;
370 if (ieee80211_is_data(fc
) && !txctl
->use_minrate
) {
372 /* Enable HT only for DATA frames and not for EAPOL */
373 txctl
->ht
= (hw
->conf
.ht_conf
.ht_supported
&&
374 (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
));
376 if (is_multicast_ether_addr(hdr
->addr1
)) {
378 ath_tx_findindex(rt
, txctl
->mcast_rate
);
381 * mcast packets are not re-tried.
385 /* For HT capable stations, we save tidno for later use.
386 * We also override seqno set by upper layer with the one
387 * in tx aggregation state.
389 * First, the fragmentation stat is determined.
390 * If fragmentation is on, the sequence number is
391 * not overridden, since it has been
392 * incremented by the fragmentation routine.
394 if (likely(!(txctl
->flags
& ATH9K_TXDESC_FRAG_IS_ON
)) &&
395 txctl
->ht
&& (sc
->sc_flags
& SC_OP_TXAGGR
)) {
396 struct ath_atx_tid
*tid
;
398 tid
= ATH_AN_2_TID(txctl
->an
, txctl
->tidno
);
400 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<<
401 IEEE80211_SEQ_SEQ_SHIFT
);
402 txctl
->seqno
= tid
->seq_next
;
403 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
406 /* for management and control frames,
407 * or for NULL and EAPOL frames */
409 rcs
[0].rix
= ath_rate_findrateix(sc
, txctl
->min_rate
);
412 rcs
[0].tries
= ATH_MGT_TXMAXTRY
;
417 * Calculate duration. This logically belongs in the 802.11
418 * layer but it lacks sufficient information to calculate it.
420 if ((txctl
->flags
& ATH9K_TXDESC_NOACK
) == 0 && !ieee80211_is_ctl(fc
)) {
423 * XXX not right with fragmentation.
425 if (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
)
426 dur
= rt
->info
[rix
].spAckDuration
;
428 dur
= rt
->info
[rix
].lpAckDuration
;
430 if (le16_to_cpu(hdr
->frame_control
) &
431 IEEE80211_FCTL_MOREFRAGS
) {
432 dur
+= dur
; /* Add additional 'SIFS + ACK' */
435 ** Compute size of next fragment in order to compute
436 ** durations needed to update NAV.
437 ** The last fragment uses the ACK duration only.
438 ** Add time for next fragment.
440 dur
+= ath9k_hw_computetxtime(sc
->sc_ah
, rt
,
443 (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
));
446 if (ieee80211_has_morefrags(fc
) ||
447 (le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
)) {
449 ** Force hardware to use computed duration for next
450 ** fragment by disabling multi-rate retry, which
451 ** updates duration based on the multi-rate
454 rcs
[1].tries
= rcs
[2].tries
= rcs
[3].tries
= 0;
455 rcs
[1].rix
= rcs
[2].rix
= rcs
[3].rix
= 0;
456 /* reset tries but keep rate index */
457 rcs
[0].tries
= ATH_TXMAXTRY
;
460 hdr
->duration_id
= cpu_to_le16(dur
);
464 * Determine if a tx interrupt should be generated for
465 * this descriptor. We take a tx interrupt to reap
466 * descriptors when the h/w hits an EOL condition or
467 * when the descriptor is specifically marked to generate
468 * an interrupt. We periodically mark descriptors in this
469 * way to insure timely replenishing of the supply needed
470 * for sending frames. Defering interrupts reduces system
471 * load and potentially allows more concurrent work to be
472 * done but if done to aggressively can cause senders to
475 * NB: use >= to deal with sc_txintrperiod changing
476 * dynamically through sysctl.
478 spin_lock_bh(&txq
->axq_lock
);
479 if ((++txq
->axq_intrcnt
>= sc
->sc_txintrperiod
)) {
480 txctl
->flags
|= ATH9K_TXDESC_INTREQ
;
481 txq
->axq_intrcnt
= 0;
483 spin_unlock_bh(&txq
->axq_lock
);
485 if (is_multicast_ether_addr(hdr
->addr1
)) {
486 antenna
= sc
->sc_mcastantenna
+ 1;
487 sc
->sc_mcastantenna
= (sc
->sc_mcastantenna
+ 1) & 0x1;
489 antenna
= sc
->sc_txantenna
;
491 #ifdef USE_LEGACY_HAL
492 txctl
->antenna
= antenna
;
497 /* To complete a chain of buffers associated a frame */
499 static void ath_tx_complete_buf(struct ath_softc
*sc
,
501 struct list_head
*bf_q
,
502 int txok
, int sendbar
)
504 struct sk_buff
*skb
= bf
->bf_mpdu
;
505 struct ath_xmit_status tx_status
;
509 * Set retry information.
510 * NB: Don't use the information in the descriptor, because the frame
511 * could be software retried.
513 tx_status
.retries
= bf
->bf_retries
;
517 tx_status
.flags
= ATH_TX_BAR
;
520 tx_status
.flags
|= ATH_TX_ERROR
;
522 if (bf_isxretried(bf
))
523 tx_status
.flags
|= ATH_TX_XRETRY
;
525 /* Unmap this frame */
526 pa
= get_dma_mem_context(bf
, bf_dmacontext
);
527 pci_unmap_single(sc
->pdev
,
531 /* complete this frame */
532 ath_tx_complete(sc
, skb
, &tx_status
, bf
->bf_node
);
535 * Return the list of ath_buf of this mpdu to free queue
537 spin_lock_bh(&sc
->sc_txbuflock
);
538 list_splice_tail_init(bf_q
, &sc
->sc_txbuf
);
539 spin_unlock_bh(&sc
->sc_txbuflock
);
543 * queue up a dest/ac pair for tx scheduling
544 * NB: must be called with txq lock held
547 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
549 struct ath_atx_ac
*ac
= tid
->ac
;
552 * if tid is paused, hold off
558 * add tid to ac atmost once
564 list_add_tail(&tid
->list
, &ac
->tid_q
);
567 * add node ac to txq atmost once
573 list_add_tail(&ac
->list
, &txq
->axq_acq
);
578 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
580 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
582 spin_lock_bh(&txq
->axq_lock
);
586 spin_unlock_bh(&txq
->axq_lock
);
589 /* resume a tid and schedule aggregate */
591 void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
593 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
595 ASSERT(tid
->paused
> 0);
596 spin_lock_bh(&txq
->axq_lock
);
603 if (list_empty(&tid
->buf_q
))
607 * Add this TID to scheduler and try to send out aggregates
609 ath_tx_queue_tid(txq
, tid
);
610 ath_txq_schedule(sc
, txq
);
612 spin_unlock_bh(&txq
->axq_lock
);
615 /* Compute the number of bad frames */
617 static int ath_tx_num_badfrms(struct ath_softc
*sc
,
618 struct ath_buf
*bf
, int txok
)
620 struct ath_node
*an
= bf
->bf_node
;
621 int isnodegone
= (an
->an_flags
& ATH_NODE_CLEAN
);
622 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
623 struct ath_desc
*ds
= bf_last
->bf_desc
;
625 u32 ba
[WME_BA_BMP_SIZE
>> 5];
630 if (isnodegone
|| ds
->ds_txstat
.ts_flags
== ATH9K_TX_SW_ABORTED
)
633 isaggr
= bf_isaggr(bf
);
635 seq_st
= ATH_DS_BA_SEQ(ds
);
636 memcpy(ba
, ATH_DS_BA_BITMAP(ds
), WME_BA_BMP_SIZE
>> 3);
640 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
641 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
650 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_buf
*bf
)
653 struct ieee80211_hdr
*hdr
;
655 bf
->bf_state
.bf_type
|= BUF_RETRY
;
659 hdr
= (struct ieee80211_hdr
*)skb
->data
;
660 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
663 /* Update block ack window */
665 static void ath_tx_update_baw(struct ath_softc
*sc
,
666 struct ath_atx_tid
*tid
, int seqno
)
670 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
671 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
673 tid
->tx_buf
[cindex
] = NULL
;
675 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
676 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
677 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
682 * ath_pkt_dur - compute packet duration (NB: not NAV)
685 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
686 * width - 0 for 20 MHz, 1 for 40 MHz
687 * half_gi - to use 4us v/s 3.6 us for symbol time
690 static u32
ath_pkt_duration(struct ath_softc
*sc
,
697 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
698 u32 nbits
, nsymbits
, duration
, nsymbols
;
702 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
703 rc
= rt
->info
[rix
].rateCode
;
706 * for legacy rates, use old function to compute packet duration
709 return ath9k_hw_computetxtime(sc
->sc_ah
,
715 * find number of symbols: PLCP + data
717 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
718 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
719 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
722 duration
= SYMBOL_TIME(nsymbols
);
724 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
727 * addup duration for legacy/ht training and signal fields
729 streams
= HT_RC_2_STREAMS(rc
);
730 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
734 /* Rate module function to set rate related fields in tx descriptor */
736 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
738 struct ath_hal
*ah
= sc
->sc_ah
;
739 const struct ath9k_rate_table
*rt
;
740 struct ath_desc
*ds
= bf
->bf_desc
;
741 struct ath_desc
*lastds
= bf
->bf_lastbf
->bf_desc
;
742 struct ath9k_11n_rate_series series
[4];
743 int i
, flags
, rtsctsena
= 0, dynamic_mimops
= 0;
745 u8 rix
= 0, cix
, ctsrate
= 0;
746 u32 aggr_limit_with_rts
= sc
->sc_rtsaggrlimit
;
747 struct ath_node
*an
= (struct ath_node
*) bf
->bf_node
;
750 * get the cix for the lowest valid rix.
752 rt
= sc
->sc_currates
;
754 if (bf
->bf_rcs
[i
].tries
) {
755 rix
= bf
->bf_rcs
[i
].rix
;
759 flags
= (bf
->bf_flags
& (ATH9K_TXDESC_RTSENA
| ATH9K_TXDESC_CTSENA
));
760 cix
= rt
->info
[rix
].controlRate
;
763 * If 802.11g protection is enabled, determine whether
764 * to use RTS/CTS or just CTS. Note that this is only
765 * done for OFDM/HT unicast frames.
767 if (sc
->sc_protmode
!= PROT_M_NONE
&&
768 (rt
->info
[rix
].phy
== PHY_OFDM
||
769 rt
->info
[rix
].phy
== PHY_HT
) &&
770 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
771 if (sc
->sc_protmode
== PROT_M_RTSCTS
)
772 flags
= ATH9K_TXDESC_RTSENA
;
773 else if (sc
->sc_protmode
== PROT_M_CTSONLY
)
774 flags
= ATH9K_TXDESC_CTSENA
;
776 cix
= rt
->info
[sc
->sc_protrix
].controlRate
;
780 /* For 11n, the default behavior is to enable RTS for
781 * hw retried frames. We enable the global flag here and
782 * let rate series flags determine which rates will actually
785 if ((ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
) && bf_isdata(bf
)) {
788 * 802.11g protection not needed, use our default behavior
791 flags
= ATH9K_TXDESC_RTSENA
;
793 * For dynamic MIMO PS, RTS needs to precede the first aggregate
794 * and the second aggregate should have any protection at all.
796 if (an
->an_smmode
== ATH_SM_PWRSAV_DYNAMIC
) {
797 if (!bf_isaggrburst(bf
)) {
798 flags
= ATH9K_TXDESC_RTSENA
;
807 * Set protection if aggregate protection on
809 if (sc
->sc_config
.ath_aggr_prot
&&
810 (!bf_isaggr(bf
) || (bf_isaggr(bf
) && bf
->bf_al
< 8192))) {
811 flags
= ATH9K_TXDESC_RTSENA
;
812 cix
= rt
->info
[sc
->sc_protrix
].controlRate
;
817 * For AR5416 - RTS cannot be followed by a frame larger than 8K.
819 if (bf_isaggr(bf
) && (bf
->bf_al
> aggr_limit_with_rts
)) {
821 * Ensure that in the case of SM Dynamic power save
822 * while we are bursting the second aggregate the
825 flags
&= ~(ATH9K_TXDESC_RTSENA
);
829 * CTS transmit rate is derived from the transmit rate
830 * by looking in the h/w rate table. We must also factor
831 * in whether or not a short preamble is to be used.
833 /* NB: cix is set above where RTS/CTS is enabled */
835 ctsrate
= rt
->info
[cix
].rateCode
|
836 (bf_isshpreamble(bf
) ? rt
->info
[cix
].shortPreamble
: 0);
839 * Setup HAL rate series
841 memzero(series
, sizeof(struct ath9k_11n_rate_series
) * 4);
843 for (i
= 0; i
< 4; i
++) {
844 if (!bf
->bf_rcs
[i
].tries
)
847 rix
= bf
->bf_rcs
[i
].rix
;
849 series
[i
].Rate
= rt
->info
[rix
].rateCode
|
850 (bf_isshpreamble(bf
) ? rt
->info
[rix
].shortPreamble
: 0);
852 series
[i
].Tries
= bf
->bf_rcs
[i
].tries
;
854 series
[i
].RateFlags
= (
855 (bf
->bf_rcs
[i
].flags
& ATH_RC_RTSCTS_FLAG
) ?
856 ATH9K_RATESERIES_RTS_CTS
: 0) |
857 ((bf
->bf_rcs
[i
].flags
& ATH_RC_CW40_FLAG
) ?
858 ATH9K_RATESERIES_2040
: 0) |
859 ((bf
->bf_rcs
[i
].flags
& ATH_RC_SGI_FLAG
) ?
860 ATH9K_RATESERIES_HALFGI
: 0);
862 series
[i
].PktDuration
= ath_pkt_duration(
864 (bf
->bf_rcs
[i
].flags
& ATH_RC_CW40_FLAG
) != 0,
865 (bf
->bf_rcs
[i
].flags
& ATH_RC_SGI_FLAG
),
866 bf_isshpreamble(bf
));
868 if ((an
->an_smmode
== ATH_SM_PWRSAV_STATIC
) &&
869 (bf
->bf_rcs
[i
].flags
& ATH_RC_DS_FLAG
) == 0) {
871 * When sending to an HT node that has enabled static
872 * SM/MIMO power save, send at single stream rates but
873 * use maximum allowed transmit chains per user,
874 * hardware, regulatory, or country limits for
877 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
881 ath_chainmask_sel_logic(sc
, an
);
883 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
887 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
890 * Set RTS for all rates if node is in dynamic powersave
891 * mode and we are using dual stream rates.
893 if (dynamic_mimops
&& (bf
->bf_rcs
[i
].flags
& ATH_RC_DS_FLAG
))
894 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
898 * For non-HT devices, calculate RTS/CTS duration in software
899 * and disable multi-rate retry.
901 if (flags
&& !(ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
)) {
903 * Compute the transmit duration based on the frame
904 * size and the size of an ACK frame. We call into the
905 * HAL to do the computation since it depends on the
906 * characteristics of the actual PHY being used.
908 * NB: CTS is assumed the same size as an ACK so we can
909 * use the precalculated ACK durations.
911 if (flags
& ATH9K_TXDESC_RTSENA
) { /* SIFS + CTS */
912 ctsduration
+= bf_isshpreamble(bf
) ?
913 rt
->info
[cix
].spAckDuration
:
914 rt
->info
[cix
].lpAckDuration
;
917 ctsduration
+= series
[0].PktDuration
;
919 if ((bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) { /* SIFS + ACK */
920 ctsduration
+= bf_isshpreamble(bf
) ?
921 rt
->info
[rix
].spAckDuration
:
922 rt
->info
[rix
].lpAckDuration
;
926 * Disable multi-rate retry when using RTS/CTS by clearing
929 memzero(&series
[1], sizeof(struct ath9k_11n_rate_series
) * 3);
933 * set dur_update_en for l-sig computation except for PS-Poll frames
935 ath9k_hw_set11n_ratescenario(ah
, ds
, lastds
,
940 if (sc
->sc_config
.ath_aggr_prot
&& flags
)
941 ath9k_hw_set11n_burstduration(ah
, ds
, 8192);
945 * Function to send a normal HT (non-AMPDU) frame
946 * NB: must be called with txq lock held
949 static int ath_tx_send_normal(struct ath_softc
*sc
,
951 struct ath_atx_tid
*tid
,
952 struct list_head
*bf_head
)
956 struct ieee80211_tx_info
*tx_info
;
957 struct ath_tx_info_priv
*tx_info_priv
;
959 BUG_ON(list_empty(bf_head
));
961 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
962 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
; /* regular HT frame */
964 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
965 tx_info
= IEEE80211_SKB_CB(skb
);
966 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
967 memcpy(bf
->bf_rcs
, tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
969 /* update starting sequence number for subsequent ADDBA request */
970 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
972 /* Queue to h/w without aggregation */
974 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
975 ath_buf_set_rate(sc
, bf
);
976 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
981 /* flush tid's software queue and send frames as non-ampdu's */
983 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
985 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
987 struct list_head bf_head
;
988 INIT_LIST_HEAD(&bf_head
);
990 ASSERT(tid
->paused
> 0);
991 spin_lock_bh(&txq
->axq_lock
);
995 if (tid
->paused
> 0) {
996 spin_unlock_bh(&txq
->axq_lock
);
1000 while (!list_empty(&tid
->buf_q
)) {
1001 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1002 ASSERT(!bf_isretried(bf
));
1003 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1004 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
1007 spin_unlock_bh(&txq
->axq_lock
);
1010 /* Completion routine of an aggregate */
1012 static void ath_tx_complete_aggr_rifs(struct ath_softc
*sc
,
1013 struct ath_txq
*txq
,
1015 struct list_head
*bf_q
,
1018 struct ath_node
*an
= bf
->bf_node
;
1019 struct ath_atx_tid
*tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1020 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
1021 struct ath_desc
*ds
= bf_last
->bf_desc
;
1022 struct ath_buf
*bf_next
, *bf_lastq
= NULL
;
1023 struct list_head bf_head
, bf_pending
;
1025 u32 ba
[WME_BA_BMP_SIZE
>> 5];
1026 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0;
1027 int isnodegone
= (an
->an_flags
& ATH_NODE_CLEAN
);
1029 isaggr
= bf_isaggr(bf
);
1032 if (ATH_DS_TX_BA(ds
)) {
1034 * extract starting sequence and
1037 seq_st
= ATH_DS_BA_SEQ(ds
);
1039 ATH_DS_BA_BITMAP(ds
),
1040 WME_BA_BMP_SIZE
>> 3);
1042 memzero(ba
, WME_BA_BMP_SIZE
>> 3);
1045 * AR5416 can become deaf/mute when BA
1046 * issue happens. Chip needs to be reset.
1047 * But AP code may have sychronization issues
1048 * when perform internal reset in this routine.
1049 * Only enable reset in STA mode for now.
1051 if (sc
->sc_ah
->ah_opmode
== ATH9K_M_STA
)
1055 memzero(ba
, WME_BA_BMP_SIZE
>> 3);
1059 INIT_LIST_HEAD(&bf_pending
);
1060 INIT_LIST_HEAD(&bf_head
);
1063 txfail
= txpending
= 0;
1064 bf_next
= bf
->bf_next
;
1066 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
1067 /* transmit completion, subframe is
1068 * acked by block ack */
1069 } else if (!isaggr
&& txok
) {
1070 /* transmit completion */
1073 if (!tid
->cleanup_inprogress
&& !isnodegone
&&
1074 ds
->ds_txstat
.ts_flags
!= ATH9K_TX_SW_ABORTED
) {
1075 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
1076 ath_tx_set_retry(sc
, bf
);
1079 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
1085 * cleanup in progress, just fail
1086 * the un-acked sub-frames
1092 * Remove ath_buf's of this sub-frame from aggregate queue.
1094 if (bf_next
== NULL
) { /* last subframe in the aggregate */
1095 ASSERT(bf
->bf_lastfrm
== bf_last
);
1098 * The last descriptor of the last sub frame could be
1099 * a holding descriptor for h/w. If that's the case,
1100 * bf->bf_lastfrm won't be in the bf_q.
1101 * Make sure we handle bf_q properly here.
1104 if (!list_empty(bf_q
)) {
1105 bf_lastq
= list_entry(bf_q
->prev
,
1106 struct ath_buf
, list
);
1107 list_cut_position(&bf_head
,
1108 bf_q
, &bf_lastq
->list
);
1111 * XXX: if the last subframe only has one
1112 * descriptor which is also being used as
1113 * a holding descriptor. Then the ath_buf
1114 * is not in the bf_q at all.
1116 INIT_LIST_HEAD(&bf_head
);
1119 ASSERT(!list_empty(bf_q
));
1120 list_cut_position(&bf_head
,
1121 bf_q
, &bf
->bf_lastfrm
->list
);
1126 * complete the acked-ones/xretried ones; update
1129 spin_lock_bh(&txq
->axq_lock
);
1130 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
1131 spin_unlock_bh(&txq
->axq_lock
);
1133 /* complete this sub-frame */
1134 ath_tx_complete_buf(sc
, bf
, &bf_head
, !txfail
, sendbar
);
1137 * retry the un-acked ones
1140 * XXX: if the last descriptor is holding descriptor,
1141 * in order to requeue the frame to software queue, we
1142 * need to allocate a new descriptor and
1143 * copy the content of holding descriptor to it.
1145 if (bf
->bf_next
== NULL
&&
1146 bf_last
->bf_status
& ATH_BUFSTATUS_STALE
) {
1147 struct ath_buf
*tbf
;
1149 /* allocate new descriptor */
1150 spin_lock_bh(&sc
->sc_txbuflock
);
1151 ASSERT(!list_empty((&sc
->sc_txbuf
)));
1152 tbf
= list_first_entry(&sc
->sc_txbuf
,
1153 struct ath_buf
, list
);
1154 list_del(&tbf
->list
);
1155 spin_unlock_bh(&sc
->sc_txbuflock
);
1157 ATH_TXBUF_RESET(tbf
);
1159 /* copy descriptor content */
1160 tbf
->bf_mpdu
= bf_last
->bf_mpdu
;
1161 tbf
->bf_node
= bf_last
->bf_node
;
1162 tbf
->bf_buf_addr
= bf_last
->bf_buf_addr
;
1163 *(tbf
->bf_desc
) = *(bf_last
->bf_desc
);
1165 /* link it to the frame */
1167 bf_lastq
->bf_desc
->ds_link
=
1169 bf
->bf_lastfrm
= tbf
;
1170 ath9k_hw_cleartxdesc(sc
->sc_ah
,
1171 bf
->bf_lastfrm
->bf_desc
);
1173 tbf
->bf_state
= bf_last
->bf_state
;
1174 tbf
->bf_lastfrm
= tbf
;
1175 ath9k_hw_cleartxdesc(sc
->sc_ah
,
1176 tbf
->bf_lastfrm
->bf_desc
);
1178 /* copy the DMA context */
1179 copy_dma_mem_context(
1180 get_dma_mem_context(tbf
,
1182 get_dma_mem_context(bf_last
,
1185 list_add_tail(&tbf
->list
, &bf_head
);
1188 * Clear descriptor status words for
1191 ath9k_hw_cleartxdesc(sc
->sc_ah
,
1192 bf
->bf_lastfrm
->bf_desc
);
1196 * Put this buffer to the temporary pending
1197 * queue to retain ordering
1199 list_splice_tail_init(&bf_head
, &bf_pending
);
1206 * node is already gone. no more assocication
1207 * with the node. the node might have been freed
1208 * any node acces can result in panic.note tid
1209 * is part of the node.
1214 if (tid
->cleanup_inprogress
) {
1215 /* check to see if we're done with cleaning the h/w queue */
1216 spin_lock_bh(&txq
->axq_lock
);
1218 if (tid
->baw_head
== tid
->baw_tail
) {
1219 tid
->addba_exchangecomplete
= 0;
1220 tid
->addba_exchangeattempts
= 0;
1221 spin_unlock_bh(&txq
->axq_lock
);
1223 tid
->cleanup_inprogress
= false;
1225 /* send buffered frames as singles */
1226 ath_tx_flush_tid(sc
, tid
);
1228 spin_unlock_bh(&txq
->axq_lock
);
1234 * prepend un-acked frames to the beginning of the pending frame queue
1236 if (!list_empty(&bf_pending
)) {
1237 spin_lock_bh(&txq
->axq_lock
);
1238 /* Note: we _prepend_, we _do_not_ at to
1239 * the end of the queue ! */
1240 list_splice(&bf_pending
, &tid
->buf_q
);
1241 ath_tx_queue_tid(txq
, tid
);
1242 spin_unlock_bh(&txq
->axq_lock
);
1246 ath_reset(sc
, false);
1251 /* Process completed xmit descriptors from the specified queue */
1253 static int ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1255 struct ath_hal
*ah
= sc
->sc_ah
;
1256 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
1257 struct list_head bf_head
;
1258 struct ath_desc
*ds
, *tmp_ds
;
1259 struct sk_buff
*skb
;
1260 struct ieee80211_tx_info
*tx_info
;
1261 struct ath_tx_info_priv
*tx_info_priv
;
1262 int nacked
, txok
, nbad
= 0, isrifs
= 0;
1265 DPRINTF(sc
, ATH_DBG_QUEUE
,
1266 "%s: tx queue %d (%x), link %p\n", __func__
,
1267 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
1272 spin_lock_bh(&txq
->axq_lock
);
1273 txq
->axq_intrcnt
= 0; /* reset periodic desc intr count */
1274 if (list_empty(&txq
->axq_q
)) {
1275 txq
->axq_link
= NULL
;
1276 txq
->axq_linkbuf
= NULL
;
1277 spin_unlock_bh(&txq
->axq_lock
);
1280 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
1283 * There is a race condition that a BH gets scheduled
1284 * after sw writes TxE and before hw re-load the last
1285 * descriptor to get the newly chained one.
1286 * Software must keep the last DONE descriptor as a
1287 * holding descriptor - software does so by marking
1288 * it with the STALE flag.
1291 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
1293 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
1295 * The holding descriptor is the last
1296 * descriptor in queue. It's safe to remove
1297 * the last holding descriptor in BH context.
1299 spin_unlock_bh(&txq
->axq_lock
);
1302 /* Lets work with the next buffer now */
1303 bf
= list_entry(bf_held
->list
.next
,
1304 struct ath_buf
, list
);
1308 lastbf
= bf
->bf_lastbf
;
1309 ds
= lastbf
->bf_desc
; /* NB: last decriptor */
1311 status
= ath9k_hw_txprocdesc(ah
, ds
);
1312 if (status
== -EINPROGRESS
) {
1313 spin_unlock_bh(&txq
->axq_lock
);
1316 if (bf
->bf_desc
== txq
->axq_lastdsWithCTS
)
1317 txq
->axq_lastdsWithCTS
= NULL
;
1318 if (ds
== txq
->axq_gatingds
)
1319 txq
->axq_gatingds
= NULL
;
1322 * Remove ath_buf's of the same transmit unit from txq,
1323 * however leave the last descriptor back as the holding
1324 * descriptor for hw.
1326 lastbf
->bf_status
|= ATH_BUFSTATUS_STALE
;
1327 INIT_LIST_HEAD(&bf_head
);
1329 if (!list_is_singular(&lastbf
->list
))
1330 list_cut_position(&bf_head
,
1331 &txq
->axq_q
, lastbf
->list
.prev
);
1336 txq
->axq_aggr_depth
--;
1338 txok
= (ds
->ds_txstat
.ts_status
== 0);
1340 spin_unlock_bh(&txq
->axq_lock
);
1343 list_del(&bf_held
->list
);
1344 spin_lock_bh(&sc
->sc_txbuflock
);
1345 list_add_tail(&bf_held
->list
, &sc
->sc_txbuf
);
1346 spin_unlock_bh(&sc
->sc_txbuflock
);
1349 if (!bf_isampdu(bf
)) {
1351 * This frame is sent out as a single frame.
1352 * Use hardware retry status for this frame.
1354 bf
->bf_retries
= ds
->ds_txstat
.ts_longretry
;
1355 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_XRETRY
)
1356 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
1359 nbad
= ath_tx_num_badfrms(sc
, bf
, txok
);
1362 tx_info
= IEEE80211_SKB_CB(skb
);
1363 tx_info_priv
= (struct ath_tx_info_priv
*)
1364 tx_info
->driver_data
[0];
1365 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
)
1366 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1367 if ((ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
) == 0 &&
1368 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
1369 if (ds
->ds_txstat
.ts_status
== 0)
1372 if (bf_isdata(bf
)) {
1374 tmp_ds
= bf
->bf_rifslast
->bf_desc
;
1377 memcpy(&tx_info_priv
->tx
,
1379 sizeof(tx_info_priv
->tx
));
1380 tx_info_priv
->n_frames
= bf
->bf_nframes
;
1381 tx_info_priv
->n_bad_frames
= nbad
;
1386 * Complete this transmit unit
1389 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, txok
);
1391 ath_tx_complete_buf(sc
, bf
, &bf_head
, txok
, 0);
1393 /* Wake up mac80211 queue */
1395 spin_lock_bh(&txq
->axq_lock
);
1396 if (txq
->stopped
&& ath_txq_depth(sc
, txq
->axq_qnum
) <=
1399 qnum
= ath_get_mac80211_qnum(txq
->axq_qnum
, sc
);
1401 ieee80211_wake_queue(sc
->hw
, qnum
);
1408 * schedule any pending packets if aggregation is enabled
1410 if (sc
->sc_flags
& SC_OP_TXAGGR
)
1411 ath_txq_schedule(sc
, txq
);
1412 spin_unlock_bh(&txq
->axq_lock
);
1417 static void ath_tx_stopdma(struct ath_softc
*sc
, struct ath_txq
*txq
)
1419 struct ath_hal
*ah
= sc
->sc_ah
;
1421 (void) ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1422 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: tx queue [%u] %x, link %p\n",
1423 __func__
, txq
->axq_qnum
,
1424 ath9k_hw_gettxbuf(ah
, txq
->axq_qnum
), txq
->axq_link
);
1427 /* Drain only the data queues */
1429 static void ath_drain_txdataq(struct ath_softc
*sc
, bool retry_tx
)
1431 struct ath_hal
*ah
= sc
->sc_ah
;
1434 enum ath9k_ht_macmode ht_macmode
= ath_cwm_macmode(sc
);
1436 /* XXX return value */
1437 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
1438 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1439 if (ATH_TXQ_SETUP(sc
, i
)) {
1440 ath_tx_stopdma(sc
, &sc
->sc_txq
[i
]);
1442 /* The TxDMA may not really be stopped.
1443 * Double check the hal tx pending count */
1444 npend
+= ath9k_hw_numtxpending(ah
,
1445 sc
->sc_txq
[i
].axq_qnum
);
1453 /* TxDMA not stopped, reset the hal */
1454 DPRINTF(sc
, ATH_DBG_XMIT
,
1455 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__
);
1457 spin_lock_bh(&sc
->sc_resetlock
);
1458 if (!ath9k_hw_reset(ah
,
1459 sc
->sc_ah
->ah_curchan
, ht_macmode
,
1460 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
,
1461 sc
->sc_ht_extprotspacing
, true, &status
)) {
1463 DPRINTF(sc
, ATH_DBG_FATAL
,
1464 "%s: unable to reset hardware; hal status %u\n",
1468 spin_unlock_bh(&sc
->sc_resetlock
);
1471 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1472 if (ATH_TXQ_SETUP(sc
, i
))
1473 ath_tx_draintxq(sc
, &sc
->sc_txq
[i
], retry_tx
);
1477 /* Add a sub-frame to block ack window */
1479 static void ath_tx_addto_baw(struct ath_softc
*sc
,
1480 struct ath_atx_tid
*tid
,
1485 if (bf_isretried(bf
))
1488 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
1489 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
1491 ASSERT(tid
->tx_buf
[cindex
] == NULL
);
1492 tid
->tx_buf
[cindex
] = bf
;
1494 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
1495 (ATH_TID_MAX_BUFS
- 1))) {
1496 tid
->baw_tail
= cindex
;
1497 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
1502 * Function to send an A-MPDU
1503 * NB: must be called with txq lock held
1506 static int ath_tx_send_ampdu(struct ath_softc
*sc
,
1507 struct ath_txq
*txq
,
1508 struct ath_atx_tid
*tid
,
1509 struct list_head
*bf_head
,
1510 struct ath_tx_control
*txctl
)
1513 struct sk_buff
*skb
;
1514 struct ieee80211_tx_info
*tx_info
;
1515 struct ath_tx_info_priv
*tx_info_priv
;
1517 BUG_ON(list_empty(bf_head
));
1519 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1520 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1521 bf
->bf_seqno
= txctl
->seqno
; /* save seqno and tidno in buffer */
1522 bf
->bf_tidno
= txctl
->tidno
;
1525 * Do not queue to h/w when any of the following conditions is true:
1526 * - there are pending frames in software queue
1527 * - the TID is currently paused for ADDBA/BAR request
1528 * - seqno is not within block-ack window
1529 * - h/w queue depth exceeds low water mark
1531 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1532 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1533 txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1535 * Add this frame to software queue for scheduling later
1538 list_splice_tail_init(bf_head
, &tid
->buf_q
);
1539 ath_tx_queue_tid(txq
, tid
);
1543 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1544 tx_info
= IEEE80211_SKB_CB(skb
);
1545 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
1546 memcpy(bf
->bf_rcs
, tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
1548 /* Add sub-frame to BAW */
1549 ath_tx_addto_baw(sc
, tid
, bf
);
1551 /* Queue to h/w without aggregation */
1553 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
1554 ath_buf_set_rate(sc
, bf
);
1555 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
1561 * returns aggr limit based on lowest of the rates
1564 static u32
ath_lookup_rate(struct ath_softc
*sc
,
1567 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
1568 struct sk_buff
*skb
;
1569 struct ieee80211_tx_info
*tx_info
;
1570 struct ath_tx_info_priv
*tx_info_priv
;
1571 u32 max_4ms_framelen
, frame_length
;
1572 u16 aggr_limit
, legacy
= 0, maxampdu
;
1576 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1577 tx_info
= IEEE80211_SKB_CB(skb
);
1578 tx_info_priv
= (struct ath_tx_info_priv
*)
1579 tx_info
->driver_data
[0];
1581 tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
1584 * Find the lowest frame length among the rate series that will have a
1585 * 4ms transmit duration.
1586 * TODO - TXOP limit needs to be considered.
1588 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
1590 for (i
= 0; i
< 4; i
++) {
1591 if (bf
->bf_rcs
[i
].tries
) {
1592 frame_length
= bf
->bf_rcs
[i
].max_4ms_framelen
;
1594 if (rt
->info
[bf
->bf_rcs
[i
].rix
].phy
!= PHY_HT
) {
1599 max_4ms_framelen
= min(max_4ms_framelen
, frame_length
);
1604 * limit aggregate size by the minimum rate if rate selected is
1605 * not a probe rate, if rate selected is a probe rate then
1606 * avoid aggregation of this packet.
1608 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
1611 aggr_limit
= min(max_4ms_framelen
,
1612 (u32
)ATH_AMPDU_LIMIT_DEFAULT
);
1615 * h/w can accept aggregates upto 16 bit lengths (65535).
1616 * The IE, however can hold upto 65536, which shows up here
1617 * as zero. Ignore 65536 since we are constrained by hw.
1619 maxampdu
= sc
->sc_ht_info
.maxampdu
;
1621 aggr_limit
= min(aggr_limit
, maxampdu
);
1627 * returns the number of delimiters to be added to
1628 * meet the minimum required mpdudensity.
1629 * caller should make sure that the rate is HT rate .
1632 static int ath_compute_num_delims(struct ath_softc
*sc
,
1636 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
1637 u32 nsymbits
, nsymbols
, mpdudensity
;
1640 int width
, half_gi
, ndelim
, mindelim
;
1642 /* Select standard number of delimiters based on frame length alone */
1643 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
1646 * If encryption enabled, hardware requires some more padding between
1648 * TODO - this could be improved to be dependent on the rate.
1649 * The hardware can keep up at lower rates, but not higher rates
1651 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
1652 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
1655 * Convert desired mpdu density from microeconds to bytes based
1656 * on highest rate in rate series (i.e. first rate) to determine
1657 * required minimum length for subframe. Take into account
1658 * whether high rate is 20 or 40Mhz and half or full GI.
1660 mpdudensity
= sc
->sc_ht_info
.mpdudensity
;
1663 * If there is no mpdu density restriction, no further calculation
1666 if (mpdudensity
== 0)
1669 rix
= bf
->bf_rcs
[0].rix
;
1670 flags
= bf
->bf_rcs
[0].flags
;
1671 rc
= rt
->info
[rix
].rateCode
;
1672 width
= (flags
& ATH_RC_CW40_FLAG
) ? 1 : 0;
1673 half_gi
= (flags
& ATH_RC_SGI_FLAG
) ? 1 : 0;
1676 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity
);
1678 nsymbols
= NUM_SYMBOLS_PER_USEC(mpdudensity
);
1683 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
1684 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
1686 /* Is frame shorter than required minimum length? */
1687 if (frmlen
< minlen
) {
1688 /* Get the minimum number of delimiters required. */
1689 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
1690 ndelim
= max(mindelim
, ndelim
);
1697 * For aggregation from software buffer queue.
1698 * NB: must be called with txq lock held
1701 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
1702 struct ath_atx_tid
*tid
,
1703 struct list_head
*bf_q
,
1704 struct ath_buf
**bf_last
,
1705 struct aggr_rifs_param
*param
,
1708 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1709 struct ath_buf
*bf
, *tbf
, *bf_first
, *bf_prev
= NULL
;
1710 struct list_head bf_head
;
1711 int rl
= 0, nframes
= 0, ndelim
;
1712 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
1713 al_delta
, h_baw
= tid
->baw_size
/ 2;
1714 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
1715 int prev_al
= 0, is_ds_rate
= 0;
1716 INIT_LIST_HEAD(&bf_head
);
1718 BUG_ON(list_empty(&tid
->buf_q
));
1720 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1723 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1726 * do not step over block-ack window
1728 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
1729 status
= ATH_AGGR_BAW_CLOSED
;
1734 aggr_limit
= ath_lookup_rate(sc
, bf
);
1737 * Is rate dual stream
1740 (bf
->bf_rcs
[0].flags
& ATH_RC_DS_FLAG
) ? 1 : 0;
1744 * do not exceed aggregation limit
1746 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
1748 if (nframes
&& (aggr_limit
<
1749 (al
+ bpad
+ al_delta
+ prev_al
))) {
1750 status
= ATH_AGGR_LIMITED
;
1755 * do not exceed subframe limit
1757 if ((nframes
+ *prev_frames
) >=
1758 min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
1759 status
= ATH_AGGR_LIMITED
;
1764 * add padding for previous frame to aggregation length
1766 al
+= bpad
+ al_delta
;
1769 * Get the delimiters needed to meet the MPDU
1770 * density for this node.
1772 ndelim
= ath_compute_num_delims(sc
, bf_first
, bf
->bf_frmlen
);
1774 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
1777 bf
->bf_lastfrm
->bf_desc
->ds_link
= 0;
1780 * this packet is part of an aggregate
1781 * - remove all descriptors belonging to this frame from
1783 * - add it to block ack window
1784 * - set up descriptors for aggregation
1786 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1787 ath_tx_addto_baw(sc
, tid
, bf
);
1789 list_for_each_entry(tbf
, &bf_head
, list
) {
1790 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
,
1791 tbf
->bf_desc
, ndelim
);
1795 * link buffers of this frame to the aggregate
1797 list_splice_tail_init(&bf_head
, bf_q
);
1801 bf_prev
->bf_next
= bf
;
1802 bf_prev
->bf_lastfrm
->bf_desc
->ds_link
= bf
->bf_daddr
;
1808 * terminate aggregation on a small packet boundary
1810 if (bf
->bf_frmlen
< ATH_AGGR_MINPLEN
) {
1811 status
= ATH_AGGR_SHORTPKT
;
1815 } while (!list_empty(&tid
->buf_q
));
1817 bf_first
->bf_al
= al
;
1818 bf_first
->bf_nframes
= nframes
;
1825 * process pending frames possibly doing a-mpdu aggregation
1826 * NB: must be called with txq lock held
1829 static void ath_tx_sched_aggr(struct ath_softc
*sc
,
1830 struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
1832 struct ath_buf
*bf
, *tbf
, *bf_last
, *bf_lastaggr
= NULL
;
1833 enum ATH_AGGR_STATUS status
;
1834 struct list_head bf_q
;
1835 struct aggr_rifs_param param
= {0, 0, 0, 0, NULL
};
1836 int prev_frames
= 0;
1839 if (list_empty(&tid
->buf_q
))
1842 INIT_LIST_HEAD(&bf_q
);
1844 status
= ath_tx_form_aggr(sc
, tid
, &bf_q
, &bf_lastaggr
, ¶m
,
1848 * no frames picked up to be aggregated; block-ack
1849 * window is not open
1851 if (list_empty(&bf_q
))
1854 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1855 bf_last
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1856 bf
->bf_lastbf
= bf_last
;
1859 * if only one frame, send as non-aggregate
1861 if (bf
->bf_nframes
== 1) {
1862 ASSERT(bf
->bf_lastfrm
== bf_last
);
1864 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1866 * clear aggr bits for every descriptor
1867 * XXX TODO: is there a way to optimize it?
1869 list_for_each_entry(tbf
, &bf_q
, list
) {
1870 ath9k_hw_clr11n_aggr(sc
->sc_ah
, tbf
->bf_desc
);
1873 ath_buf_set_rate(sc
, bf
);
1874 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1879 * setup first desc with rate and aggr info
1881 bf
->bf_state
.bf_type
|= BUF_AGGR
;
1882 ath_buf_set_rate(sc
, bf
);
1883 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
1886 * anchor last frame of aggregate correctly
1888 ASSERT(bf_lastaggr
);
1889 ASSERT(bf_lastaggr
->bf_lastfrm
== bf_last
);
1891 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1893 /* XXX: We don't enter into this loop, consider removing this */
1894 while (!list_empty(&bf_q
) && !list_is_last(&tbf
->list
, &bf_q
)) {
1895 tbf
= list_entry(tbf
->list
.next
, struct ath_buf
, list
);
1896 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1899 txq
->axq_aggr_depth
++;
1902 * Normal aggregate, queue to hardware
1904 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1906 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
1907 status
!= ATH_AGGR_BAW_CLOSED
);
1910 /* Called with txq lock held */
1912 static void ath_tid_drain(struct ath_softc
*sc
,
1913 struct ath_txq
*txq
,
1914 struct ath_atx_tid
*tid
,
1918 struct list_head bf_head
;
1919 INIT_LIST_HEAD(&bf_head
);
1922 if (list_empty(&tid
->buf_q
))
1924 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1926 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1928 /* update baw for software retried frame */
1929 if (bf_isretried(bf
))
1930 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
1933 * do not indicate packets while holding txq spinlock.
1934 * unlock is intentional here
1936 if (likely(bh_flag
))
1937 spin_unlock_bh(&txq
->axq_lock
);
1939 spin_unlock(&txq
->axq_lock
);
1941 /* complete this sub-frame */
1942 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
1944 if (likely(bh_flag
))
1945 spin_lock_bh(&txq
->axq_lock
);
1947 spin_lock(&txq
->axq_lock
);
1951 * TODO: For frame(s) that are in the retry state, we will reuse the
1952 * sequence number(s) without setting the retry bit. The
1953 * alternative is to give up on these and BAR the receiver's window
1956 tid
->seq_next
= tid
->seq_start
;
1957 tid
->baw_tail
= tid
->baw_head
;
1961 * Drain all pending buffers
1962 * NB: must be called with txq lock held
1965 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
1966 struct ath_txq
*txq
,
1969 struct ath_atx_ac
*ac
, *ac_tmp
;
1970 struct ath_atx_tid
*tid
, *tid_tmp
;
1972 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1973 list_del(&ac
->list
);
1975 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
1976 list_del(&tid
->list
);
1978 ath_tid_drain(sc
, txq
, tid
, bh_flag
);
1983 static int ath_tx_start_dma(struct ath_softc
*sc
,
1984 struct sk_buff
*skb
,
1985 struct scatterlist
*sg
,
1987 struct ath_tx_control
*txctl
)
1989 struct ath_node
*an
= txctl
->an
;
1990 struct ath_buf
*bf
= NULL
;
1991 struct list_head bf_head
;
1992 struct ath_desc
*ds
;
1993 struct ath_hal
*ah
= sc
->sc_ah
;
1994 struct ath_txq
*txq
= &sc
->sc_txq
[txctl
->qnum
];
1995 struct ath_tx_info_priv
*tx_info_priv
;
1996 struct ath_rc_series
*rcs
;
1997 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1998 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1999 __le16 fc
= hdr
->frame_control
;
2001 /* For each sglist entry, allocate an ath_buf for DMA */
2002 INIT_LIST_HEAD(&bf_head
);
2003 spin_lock_bh(&sc
->sc_txbuflock
);
2004 if (unlikely(list_empty(&sc
->sc_txbuf
))) {
2005 spin_unlock_bh(&sc
->sc_txbuflock
);
2009 bf
= list_first_entry(&sc
->sc_txbuf
, struct ath_buf
, list
);
2010 list_del(&bf
->list
);
2011 spin_unlock_bh(&sc
->sc_txbuflock
);
2013 list_add_tail(&bf
->list
, &bf_head
);
2015 /* set up this buffer */
2016 ATH_TXBUF_RESET(bf
);
2017 bf
->bf_frmlen
= txctl
->frmlen
;
2019 ieee80211_is_data(fc
) ?
2020 (bf
->bf_state
.bf_type
|= BUF_DATA
) :
2021 (bf
->bf_state
.bf_type
&= ~BUF_DATA
);
2022 ieee80211_is_back_req(fc
) ?
2023 (bf
->bf_state
.bf_type
|= BUF_BAR
) :
2024 (bf
->bf_state
.bf_type
&= ~BUF_BAR
);
2025 ieee80211_is_pspoll(fc
) ?
2026 (bf
->bf_state
.bf_type
|= BUF_PSPOLL
) :
2027 (bf
->bf_state
.bf_type
&= ~BUF_PSPOLL
);
2028 (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
) ?
2029 (bf
->bf_state
.bf_type
|= BUF_SHORT_PREAMBLE
) :
2030 (bf
->bf_state
.bf_type
&= ~BUF_SHORT_PREAMBLE
);
2032 bf
->bf_flags
= txctl
->flags
;
2033 bf
->bf_keytype
= txctl
->keytype
;
2034 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
2035 rcs
= tx_info_priv
->rcs
;
2036 bf
->bf_rcs
[0] = rcs
[0];
2037 bf
->bf_rcs
[1] = rcs
[1];
2038 bf
->bf_rcs
[2] = rcs
[2];
2039 bf
->bf_rcs
[3] = rcs
[3];
2042 bf
->bf_buf_addr
= sg_dma_address(sg
);
2044 /* setup descriptor */
2047 ds
->ds_data
= bf
->bf_buf_addr
;
2050 * Save the DMA context in the first ath_buf
2052 copy_dma_mem_context(get_dma_mem_context(bf
, bf_dmacontext
),
2053 get_dma_mem_context(txctl
, dmacontext
));
2056 * Formulate first tx descriptor with tx controls.
2058 ath9k_hw_set11n_txdesc(ah
,
2060 bf
->bf_frmlen
, /* frame length */
2061 txctl
->atype
, /* Atheros packet type */
2062 min(txctl
->txpower
, (u16
)60), /* txpower */
2063 txctl
->keyix
, /* key cache index */
2064 txctl
->keytype
, /* key type */
2065 txctl
->flags
); /* flags */
2066 ath9k_hw_filltxdesc(ah
,
2068 sg_dma_len(sg
), /* segment length */
2069 true, /* first segment */
2070 (n_sg
== 1) ? true : false, /* last segment */
2071 ds
); /* first descriptor */
2073 bf
->bf_lastfrm
= bf
;
2075 (bf
->bf_state
.bf_type
|= BUF_HT
) :
2076 (bf
->bf_state
.bf_type
&= ~BUF_HT
);
2078 spin_lock_bh(&txq
->axq_lock
);
2080 if (txctl
->ht
&& (sc
->sc_flags
& SC_OP_TXAGGR
)) {
2081 struct ath_atx_tid
*tid
= ATH_AN_2_TID(an
, txctl
->tidno
);
2082 if (ath_aggr_query(sc
, an
, txctl
->tidno
)) {
2084 * Try aggregation if it's a unicast data frame
2085 * and the destination is HT capable.
2087 ath_tx_send_ampdu(sc
, txq
, tid
, &bf_head
, txctl
);
2090 * Send this frame as regular when ADDBA exchange
2091 * is neither complete nor pending.
2093 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
2098 ath_buf_set_rate(sc
, bf
);
2100 if (ieee80211_is_back_req(fc
)) {
2101 /* This is required for resuming tid
2102 * during BAR completion */
2103 bf
->bf_tidno
= txctl
->tidno
;
2106 if (is_multicast_ether_addr(hdr
->addr1
)) {
2107 struct ath_vap
*avp
= sc
->sc_vaps
[txctl
->if_id
];
2110 * When servicing one or more stations in power-save
2111 * mode (or) if there is some mcast data waiting on
2112 * mcast queue (to prevent out of order delivery of
2113 * mcast,bcast packets) multicast frames must be
2114 * buffered until after the beacon. We use the private
2115 * mcast queue for that.
2117 /* XXX? more bit in 802.11 frame header */
2118 spin_lock_bh(&avp
->av_mcastq
.axq_lock
);
2119 if (txctl
->ps
|| avp
->av_mcastq
.axq_depth
)
2120 ath_tx_mcastqaddbuf(sc
,
2121 &avp
->av_mcastq
, &bf_head
);
2123 ath_tx_txqaddbuf(sc
, txq
, &bf_head
);
2124 spin_unlock_bh(&avp
->av_mcastq
.axq_lock
);
2126 ath_tx_txqaddbuf(sc
, txq
, &bf_head
);
2128 spin_unlock_bh(&txq
->axq_lock
);
2132 static void xmit_map_sg(struct ath_softc
*sc
,
2133 struct sk_buff
*skb
,
2135 struct ath_tx_control
*txctl
)
2137 struct ath_xmit_status tx_status
;
2138 struct ath_atx_tid
*tid
;
2139 struct scatterlist sg
;
2141 *pa
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
, PCI_DMA_TODEVICE
);
2143 /* setup S/G list */
2144 memset(&sg
, 0, sizeof(struct scatterlist
));
2145 sg_dma_address(&sg
) = *pa
;
2146 sg_dma_len(&sg
) = skb
->len
;
2148 if (ath_tx_start_dma(sc
, skb
, &sg
, 1, txctl
) != 0) {
2150 * We have to do drop frame here.
2152 pci_unmap_single(sc
->pdev
, *pa
, skb
->len
, PCI_DMA_TODEVICE
);
2154 tx_status
.retries
= 0;
2155 tx_status
.flags
= ATH_TX_ERROR
;
2157 if (txctl
->ht
&& (sc
->sc_flags
& SC_OP_TXAGGR
)) {
2158 /* Reclaim the seqno. */
2159 tid
= ATH_AN_2_TID((struct ath_node
*)
2160 txctl
->an
, txctl
->tidno
);
2161 DECR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
2163 ath_tx_complete(sc
, skb
, &tx_status
, txctl
->an
);
2167 /* Initialize TX queue and h/w */
2169 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2174 spin_lock_init(&sc
->sc_txbuflock
);
2176 /* Setup tx descriptors */
2177 error
= ath_descdma_setup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
,
2180 DPRINTF(sc
, ATH_DBG_FATAL
,
2181 "%s: failed to allocate tx descriptors: %d\n",
2186 /* XXX allocate beacon state together with vap */
2187 error
= ath_descdma_setup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
,
2188 "beacon", ATH_BCBUF
, 1);
2190 DPRINTF(sc
, ATH_DBG_FATAL
,
2191 "%s: failed to allocate "
2192 "beacon descripotrs: %d\n",
2205 /* Reclaim all tx queue resources */
2207 int ath_tx_cleanup(struct ath_softc
*sc
)
2209 /* cleanup beacon descriptors */
2210 if (sc
->sc_bdma
.dd_desc_len
!= 0)
2211 ath_descdma_cleanup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
);
2213 /* cleanup tx descriptors */
2214 if (sc
->sc_txdma
.dd_desc_len
!= 0)
2215 ath_descdma_cleanup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
);
2220 /* Setup a h/w transmit queue */
2222 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
2224 struct ath_hal
*ah
= sc
->sc_ah
;
2225 struct ath9k_tx_queue_info qi
;
2228 memzero(&qi
, sizeof(qi
));
2229 qi
.tqi_subtype
= subtype
;
2230 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
2231 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
2232 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
2233 qi
.tqi_physCompBuf
= 0;
2236 * Enable interrupts only for EOL and DESC conditions.
2237 * We mark tx descriptors to receive a DESC interrupt
2238 * when a tx queue gets deep; otherwise waiting for the
2239 * EOL to reap descriptors. Note that this is done to
2240 * reduce interrupt load and this only defers reaping
2241 * descriptors, never transmitting frames. Aside from
2242 * reducing interrupts this also permits more concurrency.
2243 * The only potential downside is if the tx queue backs
2244 * up in which case the top half of the kernel may backup
2245 * due to a lack of tx descriptors.
2247 * The UAPSD queue is an exception, since we take a desc-
2248 * based intr on the EOSP frames.
2250 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
2251 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
2253 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
2254 TXQ_FLAG_TXDESCINT_ENABLE
;
2255 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
2258 * NB: don't print a message, this happens
2259 * normally on parts with too few tx queues
2263 if (qnum
>= ARRAY_SIZE(sc
->sc_txq
)) {
2264 DPRINTF(sc
, ATH_DBG_FATAL
,
2265 "%s: hal qnum %u out of range, max %u!\n",
2266 __func__
, qnum
, (unsigned int)ARRAY_SIZE(sc
->sc_txq
));
2267 ath9k_hw_releasetxqueue(ah
, qnum
);
2270 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
2271 struct ath_txq
*txq
= &sc
->sc_txq
[qnum
];
2273 txq
->axq_qnum
= qnum
;
2274 txq
->axq_link
= NULL
;
2275 INIT_LIST_HEAD(&txq
->axq_q
);
2276 INIT_LIST_HEAD(&txq
->axq_acq
);
2277 spin_lock_init(&txq
->axq_lock
);
2279 txq
->axq_aggr_depth
= 0;
2280 txq
->axq_totalqueued
= 0;
2281 txq
->axq_intrcnt
= 0;
2282 txq
->axq_linkbuf
= NULL
;
2283 sc
->sc_txqsetup
|= 1<<qnum
;
2285 return &sc
->sc_txq
[qnum
];
2288 /* Reclaim resources for a setup queue */
2290 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2292 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
2293 sc
->sc_txqsetup
&= ~(1<<txq
->axq_qnum
);
2297 * Setup a hardware data transmit queue for the specified
2298 * access control. The hal may not support all requested
2299 * queues in which case it will return a reference to a
2300 * previously setup queue. We record the mapping from ac's
2301 * to h/w queues for use by ath_tx_start and also track
2302 * the set of h/w queues being used to optimize work in the
2303 * transmit interrupt handler and related routines.
2306 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
2308 struct ath_txq
*txq
;
2310 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
2311 DPRINTF(sc
, ATH_DBG_FATAL
,
2312 "%s: HAL AC %u out of range, max %zu!\n",
2313 __func__
, haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
2316 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
2318 sc
->sc_haltype2q
[haltype
] = txq
->axq_qnum
;
2324 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
)
2329 case ATH9K_TX_QUEUE_DATA
:
2330 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
2331 DPRINTF(sc
, ATH_DBG_FATAL
,
2332 "%s: HAL AC %u out of range, max %zu!\n",
2334 haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
2337 qnum
= sc
->sc_haltype2q
[haltype
];
2339 case ATH9K_TX_QUEUE_BEACON
:
2340 qnum
= sc
->sc_bhalq
;
2342 case ATH9K_TX_QUEUE_CAB
:
2343 qnum
= sc
->sc_cabq
->axq_qnum
;
2351 /* Update parameters for a transmit queue */
2353 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
2354 struct ath9k_tx_queue_info
*qinfo
)
2356 struct ath_hal
*ah
= sc
->sc_ah
;
2358 struct ath9k_tx_queue_info qi
;
2360 if (qnum
== sc
->sc_bhalq
) {
2362 * XXX: for beacon queue, we just save the parameter.
2363 * It will be picked up by ath_beaconq_config when
2366 sc
->sc_beacon_qi
= *qinfo
;
2370 ASSERT(sc
->sc_txq
[qnum
].axq_qnum
== qnum
);
2372 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
2373 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
2374 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
2375 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
2376 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
2377 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
2379 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
2380 DPRINTF(sc
, ATH_DBG_FATAL
,
2381 "%s: unable to update hardware queue %u!\n",
2385 ath9k_hw_resettxqueue(ah
, qnum
); /* push to h/w */
2391 int ath_cabq_update(struct ath_softc
*sc
)
2393 struct ath9k_tx_queue_info qi
;
2394 int qnum
= sc
->sc_cabq
->axq_qnum
;
2395 struct ath_beacon_config conf
;
2397 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
2399 * Ensure the readytime % is within the bounds.
2401 if (sc
->sc_config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
2402 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
2403 else if (sc
->sc_config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
2404 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
2406 ath_get_beaconconfig(sc
, ATH_IF_ID_ANY
, &conf
);
2408 (conf
.beacon_interval
* sc
->sc_config
.cabqReadytime
) / 100;
2409 ath_txq_update(sc
, qnum
, &qi
);
2414 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
)
2416 struct ath_tx_control txctl
;
2419 error
= ath_tx_prepare(sc
, skb
, &txctl
);
2422 * Start DMA mapping.
2423 * ath_tx_start_dma() will be called either synchronously
2424 * or asynchrounsly once DMA is complete.
2426 xmit_map_sg(sc
, skb
,
2427 get_dma_mem_context(&txctl
, dmacontext
),
2430 ath_node_put(sc
, txctl
.an
, ATH9K_BH_STATUS_CHANGE
);
2432 /* failed packets will be dropped by the caller */
2436 /* Deferred processing of transmit interrupt */
2438 void ath_tx_tasklet(struct ath_softc
*sc
)
2440 u64 tsf
= ath9k_hw_gettsf64(sc
->sc_ah
);
2442 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2444 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2447 * Process each active queue.
2449 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2450 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2451 nacked
+= ath_tx_processq(sc
, &sc
->sc_txq
[i
]);
2454 sc
->sc_lastrx
= tsf
;
2457 void ath_tx_draintxq(struct ath_softc
*sc
,
2458 struct ath_txq
*txq
, bool retry_tx
)
2460 struct ath_buf
*bf
, *lastbf
;
2461 struct list_head bf_head
;
2463 INIT_LIST_HEAD(&bf_head
);
2466 * NB: this assumes output has been stopped and
2467 * we do not need to block ath_tx_tasklet
2470 spin_lock_bh(&txq
->axq_lock
);
2472 if (list_empty(&txq
->axq_q
)) {
2473 txq
->axq_link
= NULL
;
2474 txq
->axq_linkbuf
= NULL
;
2475 spin_unlock_bh(&txq
->axq_lock
);
2479 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2481 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
2482 list_del(&bf
->list
);
2483 spin_unlock_bh(&txq
->axq_lock
);
2485 spin_lock_bh(&sc
->sc_txbuflock
);
2486 list_add_tail(&bf
->list
, &sc
->sc_txbuf
);
2487 spin_unlock_bh(&sc
->sc_txbuflock
);
2491 lastbf
= bf
->bf_lastbf
;
2493 lastbf
->bf_desc
->ds_txstat
.ts_flags
=
2494 ATH9K_TX_SW_ABORTED
;
2496 /* remove ath_buf's of the same mpdu from txq */
2497 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
2500 spin_unlock_bh(&txq
->axq_lock
);
2503 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, 0);
2505 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2508 /* flush any pending frames if aggregation is enabled */
2509 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2511 spin_lock_bh(&txq
->axq_lock
);
2512 ath_txq_drain_pending_buffers(sc
, txq
,
2513 ATH9K_BH_STATUS_CHANGE
);
2514 spin_unlock_bh(&txq
->axq_lock
);
2519 /* Drain the transmit queues and reclaim resources */
2521 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
)
2523 /* stop beacon queue. The beacon will be freed when
2524 * we go to INIT state */
2525 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2526 (void) ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->sc_bhalq
);
2527 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: beacon queue %x\n", __func__
,
2528 ath9k_hw_gettxbuf(sc
->sc_ah
, sc
->sc_bhalq
));
2531 ath_drain_txdataq(sc
, retry_tx
);
2534 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
)
2536 return sc
->sc_txq
[qnum
].axq_depth
;
2539 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
)
2541 return sc
->sc_txq
[qnum
].axq_aggr_depth
;
2544 /* Check if an ADDBA is required. A valid node must be passed. */
2545 enum ATH_AGGR_CHECK
ath_tx_aggr_check(struct ath_softc
*sc
,
2546 struct ath_node
*an
,
2549 struct ath_atx_tid
*txtid
;
2550 DECLARE_MAC_BUF(mac
);
2552 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
2553 return AGGR_NOT_REQUIRED
;
2555 /* ADDBA exchange must be completed before sending aggregates */
2556 txtid
= ATH_AN_2_TID(an
, tidno
);
2558 if (txtid
->addba_exchangecomplete
)
2559 return AGGR_EXCHANGE_DONE
;
2561 if (txtid
->cleanup_inprogress
)
2562 return AGGR_CLEANUP_PROGRESS
;
2564 if (txtid
->addba_exchangeinprogress
)
2565 return AGGR_EXCHANGE_PROGRESS
;
2567 if (!txtid
->addba_exchangecomplete
) {
2568 if (!txtid
->addba_exchangeinprogress
&&
2569 (txtid
->addba_exchangeattempts
< ADDBA_EXCHANGE_ATTEMPTS
)) {
2570 txtid
->addba_exchangeattempts
++;
2571 return AGGR_REQUIRED
;
2575 return AGGR_NOT_REQUIRED
;
2578 /* Start TX aggregation */
2580 int ath_tx_aggr_start(struct ath_softc
*sc
,
2585 struct ath_atx_tid
*txtid
;
2586 struct ath_node
*an
;
2588 spin_lock_bh(&sc
->node_lock
);
2589 an
= ath_node_find(sc
, (u8
*) addr
);
2590 spin_unlock_bh(&sc
->node_lock
);
2593 DPRINTF(sc
, ATH_DBG_AGGR
,
2594 "%s: Node not found to initialize "
2595 "TX aggregation\n", __func__
);
2599 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2600 txtid
= ATH_AN_2_TID(an
, tid
);
2601 txtid
->addba_exchangeinprogress
= 1;
2602 ath_tx_pause_tid(sc
, txtid
);
2608 /* Stop tx aggregation */
2610 int ath_tx_aggr_stop(struct ath_softc
*sc
,
2614 struct ath_node
*an
;
2616 spin_lock_bh(&sc
->node_lock
);
2617 an
= ath_node_find(sc
, (u8
*) addr
);
2618 spin_unlock_bh(&sc
->node_lock
);
2621 DPRINTF(sc
, ATH_DBG_AGGR
,
2622 "%s: TX aggr stop for non-existent node\n", __func__
);
2626 ath_tx_aggr_teardown(sc
, an
, tid
);
2631 * Performs transmit side cleanup when TID changes from aggregated to
2633 * - Pause the TID and mark cleanup in progress
2634 * - Discard all retry frames from the s/w queue.
2637 void ath_tx_aggr_teardown(struct ath_softc
*sc
,
2638 struct ath_node
*an
, u8 tid
)
2640 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
2641 struct ath_txq
*txq
= &sc
->sc_txq
[txtid
->ac
->qnum
];
2643 struct list_head bf_head
;
2644 INIT_LIST_HEAD(&bf_head
);
2646 DPRINTF(sc
, ATH_DBG_AGGR
, "%s: teardown TX aggregation\n", __func__
);
2648 if (txtid
->cleanup_inprogress
) /* cleanup is in progress */
2651 if (!txtid
->addba_exchangecomplete
) {
2652 txtid
->addba_exchangeattempts
= 0;
2656 /* TID must be paused first */
2657 ath_tx_pause_tid(sc
, txtid
);
2659 /* drop all software retried frames and mark this TID */
2660 spin_lock_bh(&txq
->axq_lock
);
2661 while (!list_empty(&txtid
->buf_q
)) {
2662 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
2663 if (!bf_isretried(bf
)) {
2665 * NB: it's based on the assumption that
2666 * software retried frame will always stay
2667 * at the head of software queue.
2671 list_cut_position(&bf_head
,
2672 &txtid
->buf_q
, &bf
->bf_lastfrm
->list
);
2673 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
2675 /* complete this sub-frame */
2676 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2679 if (txtid
->baw_head
!= txtid
->baw_tail
) {
2680 spin_unlock_bh(&txq
->axq_lock
);
2681 txtid
->cleanup_inprogress
= true;
2683 txtid
->addba_exchangecomplete
= 0;
2684 txtid
->addba_exchangeattempts
= 0;
2685 spin_unlock_bh(&txq
->axq_lock
);
2686 ath_tx_flush_tid(sc
, txtid
);
2691 * Tx scheduling logic
2692 * NB: must be called with txq lock held
2695 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
2697 struct ath_atx_ac
*ac
;
2698 struct ath_atx_tid
*tid
;
2700 /* nothing to schedule */
2701 if (list_empty(&txq
->axq_acq
))
2704 * get the first node/ac pair on the queue
2706 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
2707 list_del(&ac
->list
);
2711 * process a single tid per destination
2714 /* nothing to schedule */
2715 if (list_empty(&ac
->tid_q
))
2718 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
2719 list_del(&tid
->list
);
2722 if (tid
->paused
) /* check next tid to keep h/w busy */
2725 if (!(tid
->an
->an_smmode
== ATH_SM_PWRSAV_DYNAMIC
) ||
2726 ((txq
->axq_depth
% 2) == 0)) {
2727 ath_tx_sched_aggr(sc
, txq
, tid
);
2731 * add tid to round-robin queue if more frames
2732 * are pending for the tid
2734 if (!list_empty(&tid
->buf_q
))
2735 ath_tx_queue_tid(txq
, tid
);
2737 /* only schedule one TID at a time */
2739 } while (!list_empty(&ac
->tid_q
));
2742 * schedule AC if more TIDs need processing
2744 if (!list_empty(&ac
->tid_q
)) {
2746 * add dest ac to txq if not already added
2750 list_add_tail(&ac
->list
, &txq
->axq_acq
);
2755 /* Initialize per-node transmit state */
2757 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2759 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2760 struct ath_atx_tid
*tid
;
2761 struct ath_atx_ac
*ac
;
2764 sc
->sc_ht_info
.maxampdu
= ATH_AMPDU_LIMIT_DEFAULT
;
2767 * Init per tid tx state
2769 for (tidno
= 0, tid
= &an
->an_aggr
.tx
.tid
[tidno
];
2770 tidno
< WME_NUM_TID
;
2774 tid
->seq_start
= tid
->seq_next
= 0;
2775 tid
->baw_size
= WME_MAX_BA
;
2776 tid
->baw_head
= tid
->baw_tail
= 0;
2778 tid
->paused
= false;
2779 tid
->cleanup_inprogress
= false;
2780 INIT_LIST_HEAD(&tid
->buf_q
);
2782 acno
= TID_TO_WME_AC(tidno
);
2783 tid
->ac
= &an
->an_aggr
.tx
.ac
[acno
];
2786 tid
->addba_exchangecomplete
= 0;
2787 tid
->addba_exchangeinprogress
= 0;
2788 tid
->addba_exchangeattempts
= 0;
2792 * Init per ac tx state
2794 for (acno
= 0, ac
= &an
->an_aggr
.tx
.ac
[acno
];
2795 acno
< WME_NUM_AC
; acno
++, ac
++) {
2797 INIT_LIST_HEAD(&ac
->tid_q
);
2801 ac
->qnum
= ath_tx_get_qnum(sc
,
2802 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
2805 ac
->qnum
= ath_tx_get_qnum(sc
,
2806 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BK
);
2809 ac
->qnum
= ath_tx_get_qnum(sc
,
2810 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VI
);
2813 ac
->qnum
= ath_tx_get_qnum(sc
,
2814 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VO
);
2821 /* Cleanupthe pending buffers for the node. */
2823 void ath_tx_node_cleanup(struct ath_softc
*sc
,
2824 struct ath_node
*an
, bool bh_flag
)
2827 struct ath_atx_ac
*ac
, *ac_tmp
;
2828 struct ath_atx_tid
*tid
, *tid_tmp
;
2829 struct ath_txq
*txq
;
2830 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2831 if (ATH_TXQ_SETUP(sc
, i
)) {
2832 txq
= &sc
->sc_txq
[i
];
2834 if (likely(bh_flag
))
2835 spin_lock_bh(&txq
->axq_lock
);
2837 spin_lock(&txq
->axq_lock
);
2839 list_for_each_entry_safe(ac
,
2840 ac_tmp
, &txq
->axq_acq
, list
) {
2841 tid
= list_first_entry(&ac
->tid_q
,
2842 struct ath_atx_tid
, list
);
2843 if (tid
&& tid
->an
!= an
)
2845 list_del(&ac
->list
);
2848 list_for_each_entry_safe(tid
,
2849 tid_tmp
, &ac
->tid_q
, list
) {
2850 list_del(&tid
->list
);
2852 ath_tid_drain(sc
, txq
, tid
, bh_flag
);
2853 tid
->addba_exchangecomplete
= 0;
2854 tid
->addba_exchangeattempts
= 0;
2855 tid
->cleanup_inprogress
= false;
2859 if (likely(bh_flag
))
2860 spin_unlock_bh(&txq
->axq_lock
);
2862 spin_unlock(&txq
->axq_lock
);
2867 /* Cleanup per node transmit state */
2869 void ath_tx_node_free(struct ath_softc
*sc
, struct ath_node
*an
)
2871 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2872 struct ath_atx_tid
*tid
;
2875 /* Init per tid rx state */
2876 for (tidno
= 0, tid
= &an
->an_aggr
.tx
.tid
[tidno
];
2877 tidno
< WME_NUM_TID
;
2880 for (i
= 0; i
< ATH_TID_MAX_BUFS
; i
++)
2881 ASSERT(tid
->tx_buf
[i
] == NULL
);