drivers/net/wireless/ath9k/core.h

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef CORE_H
  18 #define CORE_H
  19
  20 #include <linux/version.h>
  21 #include <linux/autoconf.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/skbuff.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/ip.h>
  30 #include <linux/tcp.h>
  31 #include <linux/in.h>
  32 #include <linux/delay.h>
  33 #include <linux/wait.h>
  34 #include <linux/pci.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/sched.h>
  37 #include <linux/list.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/scatterlist.h>
  40 #include <asm/page.h>
  41 #include <net/mac80211.h>
  42
  43 #include "ath9k.h"
  44 #include "rc.h"
  45
  46 struct ath_node;
  47
  48 /******************/
  49 /* Utility macros */
  50 /******************/
  51
  52 /* Macro to expand scalars to 64-bit objects */
  53
  54 #define ito64(x) (sizeof(x) == 8) ?                     \
  55         (((unsigned long long int)(x)) & (0xff)) :      \
  56         (sizeof(x) == 16) ?                             \
  57         (((unsigned long long int)(x)) & 0xffff) :      \
  58         ((sizeof(x) == 32) ?                            \
  59          (((unsigned long long int)(x)) & 0xffffffff) : \
  60          (unsigned long long int)(x))
  61
  62 /* increment with wrap-around */
  63 #define INCR(_l, _sz)   do {                    \
  64                 (_l)++;                         \
  65                 (_l) &= ((_sz) - 1);            \
  66         } while (0)
  67
  68 /* decrement with wrap-around */
  69 #define DECR(_l,  _sz)  do {                    \
  70                 (_l)--;                         \
  71                 (_l) &= ((_sz) - 1);            \
  72         } while (0)
  73
  74 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  75
  76 #define ASSERT(exp) do {                        \
  77                 if (unlikely(!(exp))) {         \
  78                         BUG();                  \
  79                 }                               \
  80         } while (0)
  81
  82 /* XXX: remove */
  83 #define memzero(_buf, _len) memset(_buf, 0, _len)
  84
  85 #define get_dma_mem_context(var, field) (&((var)->field))
  86 #define copy_dma_mem_context(dst, src)  (*dst = *src)
  87
  88 #define ATH9K_BH_STATUS_INTACT          0
  89 #define ATH9K_BH_STATUS_CHANGE          1
  90
  91 #define ATH_TXQ_SETUP(sc, i)        ((sc)->sc_txqsetup & (1<<i))
  92
  93 static inline unsigned long get_timestamp(void)
  94 {
  95         return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
  96 }
  97
  98 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  99
 100 /*************/
 101 /* Debugging */
 102 /*************/
 103
 104 enum ATH_DEBUG {
 105         ATH_DBG_RESET           = 0x00000001,
 106         ATH_DBG_PHY_IO          = 0x00000002,
 107         ATH_DBG_REG_IO          = 0x00000004,
 108         ATH_DBG_QUEUE           = 0x00000008,
 109         ATH_DBG_EEPROM          = 0x00000010,
 110         ATH_DBG_NF_CAL          = 0x00000020,
 111         ATH_DBG_CALIBRATE       = 0x00000040,
 112         ATH_DBG_CHANNEL         = 0x00000080,
 113         ATH_DBG_INTERRUPT       = 0x00000100,
 114         ATH_DBG_REGULATORY      = 0x00000200,
 115         ATH_DBG_ANI             = 0x00000400,
 116         ATH_DBG_POWER_MGMT      = 0x00000800,
 117         ATH_DBG_XMIT            = 0x00001000,
 118         ATH_DBG_BEACON          = 0x00002000,
 119         ATH_DBG_RATE            = 0x00004000,
 120         ATH_DBG_CONFIG          = 0x00008000,
 121         ATH_DBG_KEYCACHE        = 0x00010000,
 122         ATH_DBG_AGGR            = 0x00020000,
 123         ATH_DBG_FATAL           = 0x00040000,
 124         ATH_DBG_ANY             = 0xffffffff
 125 };
 126
 127 #define DBG_DEFAULT (ATH_DBG_FATAL)
 128
 129 #define DPRINTF(sc, _m, _fmt, ...) do {                 \
 130                 if (sc->sc_debug & (_m))                \
 131                         printk(_fmt , ##__VA_ARGS__);   \
 132         } while (0)
 133
 134 /***************************/
 135 /* Load-time Configuration */
 136 /***************************/
 137
 138 /* Per-instance load-time (note: NOT run-time) configurations
 139  * for Atheros Device */
 140 struct ath_config {
 141         u32 ath_aggr_prot;
 142         u16 txpowlimit;
 143         u16 txpowlimit_override;
 144         u8 cabqReadytime; /* Cabq Readytime % */
 145         u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
 146 };
 147
 148 /***********************/
 149 /* Chainmask Selection */
 150 /***********************/
 151
 152 #define ATH_CHAINMASK_SEL_TIMEOUT          6000
 153 /* Default - Number of last RSSI values that is used for
 154  * chainmask selection */
 155 #define ATH_CHAINMASK_SEL_RSSI_CNT         10
 156 /* Means use 3x3 chainmask instead of configured chainmask */
 157 #define ATH_CHAINMASK_SEL_3X3              7
 158 /* Default - Rssi threshold below which we have to switch to 3x3 */
 159 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES    20
 160 /* Default - Rssi threshold above which we have to switch to
 161  * user configured values */
 162 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES  35
 163 /* Struct to store the chainmask select related info */
 164 struct ath_chainmask_sel {
 165         struct timer_list timer;
 166         int cur_tx_mask;        /* user configured or 3x3 */
 167         int cur_rx_mask;        /* user configured or 3x3 */
 168         int tx_avgrssi;
 169         u8 switch_allowed:1,    /* timer will set this */
 170            cm_sel_enabled : 1;
 171 };
 172
 173 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
 174 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 175
 176 /*************************/
 177 /* Descriptor Management */
 178 /*************************/
 179
 180 #define ATH_TXBUF_RESET(_bf) do {                               \
 181                 (_bf)->bf_status = 0;                           \
 182                 (_bf)->bf_lastbf = NULL;                        \
 183                 (_bf)->bf_lastfrm = NULL;                       \
 184                 (_bf)->bf_next = NULL;                          \
 185                 memzero(&((_bf)->bf_state),                     \
 186                             sizeof(struct ath_buf_state));      \
 187         } while (0)
 188
 189 enum buffer_type {
 190         BUF_DATA                = BIT(0),
 191         BUF_AGGR                = BIT(1),
 192         BUF_AMPDU               = BIT(2),
 193         BUF_HT                  = BIT(3),
 194         BUF_RETRY               = BIT(4),
 195         BUF_XRETRY              = BIT(5),
 196         BUF_SHORT_PREAMBLE      = BIT(6),
 197         BUF_BAR                 = BIT(7),
 198         BUF_PSPOLL              = BIT(8),
 199         BUF_AGGR_BURST          = BIT(9),
 200         BUF_CALC_AIRTIME        = BIT(10),
 201 };
 202
 203 struct ath_buf_state {
 204         int bfs_nframes;                        /* # frames in aggregate */
 205         u16 bfs_al;                             /* length of aggregate */
 206         u16 bfs_frmlen;                         /* length of frame */
 207         int bfs_seqno;                          /* sequence number */
 208         int bfs_tidno;                          /* tid of this frame */
 209         int bfs_retries;                        /* current retries */
 210         struct ath_rc_series bfs_rcs[4];        /* rate series */
 211         u32 bf_type;                            /* BUF_* (enum buffer_type) */
 212         /* key type use to encrypt this frame */
 213         enum ath9k_key_type bfs_keytype;
 214 };
 215
 216 #define bf_nframes              bf_state.bfs_nframes
 217 #define bf_al                   bf_state.bfs_al
 218 #define bf_frmlen               bf_state.bfs_frmlen
 219 #define bf_retries              bf_state.bfs_retries
 220 #define bf_seqno                bf_state.bfs_seqno
 221 #define bf_tidno                bf_state.bfs_tidno
 222 #define bf_rcs                  bf_state.bfs_rcs
 223 #define bf_keytype              bf_state.bfs_keytype
 224 #define bf_isdata(bf)           (bf->bf_state.bf_type & BUF_DATA)
 225 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 226 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 227 #define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 228 #define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 229 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 230 #define bf_isshpreamble(bf)     (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
 231 #define bf_isbar(bf)            (bf->bf_state.bf_type & BUF_BAR)
 232 #define bf_ispspoll(bf)         (bf->bf_state.bf_type & BUF_PSPOLL)
 233 #define bf_isaggrburst(bf)      (bf->bf_state.bf_type & BUF_AGGR_BURST)
 234
 235 /*
 236  * Abstraction of a contiguous buffer to transmit/receive.  There is only
 237  * a single hw descriptor encapsulated here.
 238  */
 239 struct ath_buf {
 240         struct list_head list;
 241         struct list_head *last;
 242         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 243                                            an aggregate) */
 244         struct ath_buf *bf_lastfrm;     /* last buf of this frame */
 245         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 246         struct ath_buf *bf_rifslast;    /* last buf for RIFS burst */
 247         void *bf_mpdu;                  /* enclosing frame structure */
 248         void *bf_node;                  /* pointer to the node */
 249         struct ath_desc *bf_desc;       /* virtual addr of desc */
 250         dma_addr_t bf_daddr;            /* physical addr of desc */
 251         dma_addr_t bf_buf_addr;         /* physical addr of data buffer */
 252         u32 bf_status;
 253         u16 bf_flags;                   /* tx descriptor flags */
 254         struct ath_buf_state bf_state;  /* buffer state */
 255         dma_addr_t bf_dmacontext;
 256 };
 257
 258 /*
 259  * reset the rx buffer.
 260  * any new fields added to the athbuf and require
 261  * reset need to be added to this macro.
 262  * currently bf_status is the only one requires that
 263  * requires reset.
 264  */
 265 #define ATH_RXBUF_RESET(_bf)    ((_bf)->bf_status = 0)
 266
 267 /* hw processing complete, desc processed by hal */
 268 #define ATH_BUFSTATUS_DONE      0x00000001
 269 /* hw processing complete, desc hold for hw */
 270 #define ATH_BUFSTATUS_STALE     0x00000002
 271 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
 272 #define ATH_BUFSTATUS_FREE      0x00000004
 273
 274 /* DMA state for tx/rx descriptors */
 275
 276 struct ath_descdma {
 277         const char *dd_name;
 278         struct ath_desc *dd_desc;       /* descriptors  */
 279         dma_addr_t dd_desc_paddr;       /* physical addr of dd_desc  */
 280         u32 dd_desc_len;                /* size of dd_desc  */
 281         struct ath_buf *dd_bufptr;      /* associated buffers */
 282         dma_addr_t dd_dmacontext;
 283 };
 284
 285 /* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
 286
 287 struct ath_rx_context {
 288         struct ath_buf *ctx_rxbuf;      /* associated ath_buf for rx */
 289 };
 290 #define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
 291
 292 int ath_descdma_setup(struct ath_softc *sc,
 293                       struct ath_descdma *dd,
 294                       struct list_head *head,
 295                       const char *name,
 296                       int nbuf,
 297                       int ndesc);
 298 int ath_desc_alloc(struct ath_softc *sc);
 299 void ath_desc_free(struct ath_softc *sc);
 300 void ath_descdma_cleanup(struct ath_softc *sc,
 301                          struct ath_descdma *dd,
 302                          struct list_head *head);
 303
 304 /******/
 305 /* RX */
 306 /******/
 307
 308 #define ATH_MAX_ANTENNA          3
 309 #define ATH_RXBUF                512
 310 #define ATH_RX_TIMEOUT           40      /* 40 milliseconds */
 311 #define WME_NUM_TID              16
 312 #define IEEE80211_BAR_CTL_TID_M  0xF000  /* tid mask */
 313 #define IEEE80211_BAR_CTL_TID_S  2       /* tid shift */
 314
 315 enum ATH_RX_TYPE {
 316         ATH_RX_NON_CONSUMED = 0,
 317         ATH_RX_CONSUMED
 318 };
 319
 320 /* per frame rx status block */
 321 struct ath_recv_status {
 322         u64 tsf;                /* mac tsf */
 323         int8_t rssi;            /* RSSI (noise floor ajusted) */
 324         int8_t rssictl[ATH_MAX_ANTENNA];        /* RSSI (noise floor ajusted) */
 325         int8_t rssiextn[ATH_MAX_ANTENNA];       /* RSSI (noise floor ajusted) */
 326         int8_t abs_rssi;        /* absolute RSSI */
 327         u8 rateieee;            /* data rate received (IEEE rate code) */
 328         u8 ratecode;            /* phy rate code */
 329         int rateKbps;           /* data rate received (Kbps) */
 330         int antenna;            /* rx antenna */
 331         int flags;              /* status of associated skb */
 332 #define ATH_RX_FCS_ERROR        0x01
 333 #define ATH_RX_MIC_ERROR        0x02
 334 #define ATH_RX_DECRYPT_ERROR    0x04
 335 #define ATH_RX_RSSI_VALID       0x08
 336 /* if any of ctl,extn chainrssis are valid */
 337 #define ATH_RX_CHAIN_RSSI_VALID 0x10
 338 /* if extn chain rssis are valid */
 339 #define ATH_RX_RSSI_EXTN_VALID  0x20
 340 /* set if 40Mhz, clear if 20Mhz */
 341 #define ATH_RX_40MHZ            0x40
 342 /* set if short GI, clear if full GI */
 343 #define ATH_RX_SHORT_GI         0x80
 344 };
 345
 346 struct ath_rxbuf {
 347         struct sk_buff *rx_wbuf;
 348         unsigned long rx_time;                  /* system time when received */
 349         struct ath_recv_status rx_status;       /* cached rx status */
 350 };
 351
 352 /* Per-TID aggregate receiver state for a node */
 353 struct ath_arx_tid {
 354         struct ath_node *an;
 355         struct ath_rxbuf *rxbuf;        /* re-ordering buffer */
 356         struct timer_list timer;
 357         spinlock_t tidlock;
 358         int baw_head;                   /* seq_next at head */
 359         int baw_tail;                   /* tail of block-ack window */
 360         int seq_reset;                  /* need to reset start sequence */
 361         int addba_exchangecomplete;
 362         u16 seq_next;                   /* next expected sequence */
 363         u16 baw_size;                   /* block-ack window size */
 364 };
 365
 366 /* Per-node receiver aggregate state */
 367 struct ath_arx {
 368         struct ath_arx_tid tid[WME_NUM_TID];
 369 };
 370
 371 int ath_startrecv(struct ath_softc *sc);
 372 bool ath_stoprecv(struct ath_softc *sc);
 373 void ath_flushrecv(struct ath_softc *sc);
 374 u32 ath_calcrxfilter(struct ath_softc *sc);
 375 void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
 376 void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
 377 void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 378 void ath_handle_rx_intr(struct ath_softc *sc);
 379 int ath_rx_init(struct ath_softc *sc, int nbufs);
 380 void ath_rx_cleanup(struct ath_softc *sc);
 381 int ath_rx_tasklet(struct ath_softc *sc, int flush);
 382 int ath_rx_input(struct ath_softc *sc,
 383                  struct ath_node *node,
 384                  int is_ampdu,
 385                  struct sk_buff *skb,
 386                  struct ath_recv_status *rx_status,
 387                  enum ATH_RX_TYPE *status);
 388 int ath__rx_indicate(struct ath_softc *sc,
 389                     struct sk_buff *skb,
 390                     struct ath_recv_status *status,
 391                     u16 keyix);
 392 int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
 393                     struct ath_recv_status *status);
 394
 395 /******/
 396 /* TX */
 397 /******/
 398
 399 #define ATH_TXBUF               512
 400 /* max number of transmit attempts (tries) */
 401 #define ATH_TXMAXTRY            13
 402 /* max number of 11n transmit attempts (tries) */
 403 #define ATH_11N_TXMAXTRY        10
 404 /* max number of tries for management and control frames */
 405 #define ATH_MGT_TXMAXTRY        4
 406 #define WME_BA_BMP_SIZE         64
 407 #define WME_MAX_BA              WME_BA_BMP_SIZE
 408 #define ATH_TID_MAX_BUFS        (2 * WME_MAX_BA)
 409 #define TID_TO_WME_AC(_tid)                             \
 410         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 411          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 412          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 413          WME_AC_VO)
 414
 415
 416 /* Wireless Multimedia Extension Defines */
 417 #define WME_AC_BE               0 /* best effort */
 418 #define WME_AC_BK               1 /* background */
 419 #define WME_AC_VI               2 /* video */
 420 #define WME_AC_VO               3 /* voice */
 421 #define WME_NUM_AC              4
 422
 423 enum ATH_SM_PWRSAV{
 424         ATH_SM_ENABLE,
 425         ATH_SM_PWRSAV_STATIC,
 426         ATH_SM_PWRSAV_DYNAMIC,
 427 };
 428
 429 /*
 430  * Data transmit queue state.  One of these exists for each
 431  * hardware transmit queue.  Packets sent to us from above
 432  * are assigned to queues based on their priority.  Not all
 433  * devices support a complete set of hardware transmit queues.
 434  * For those devices the array sc_ac2q will map multiple
 435  * priorities to fewer hardware queues (typically all to one
 436  * hardware queue).
 437  */
 438 struct ath_txq {
 439         u32 axq_qnum;                   /* hardware q number */
 440         u32 *axq_link;                  /* link ptr in last TX desc */
 441         struct list_head axq_q;         /* transmit queue */
 442         spinlock_t axq_lock;
 443         unsigned long axq_lockflags;    /* intr state when must cli */
 444         u32 axq_depth;                  /* queue depth */
 445         u8 axq_aggr_depth;              /* aggregates queued */
 446         u32 axq_totalqueued;            /* total ever queued */
 447
 448         /* count to determine if descriptor should generate int on this txq. */
 449         u32 axq_intrcnt;
 450
 451         bool stopped;                   /* Is mac80211 queue stopped ? */
 452         struct ath_buf *axq_linkbuf;    /* virtual addr of last buffer*/
 453
 454         /* first desc of the last descriptor that contains CTS */
 455         struct ath_desc *axq_lastdsWithCTS;
 456
 457         /* final desc of the gating desc that determines whether
 458            lastdsWithCTS has been DMA'ed or not */
 459         struct ath_desc *axq_gatingds;
 460
 461         struct list_head axq_acq;
 462 };
 463
 464 /* per TID aggregate tx state for a destination */
 465 struct ath_atx_tid {
 466         struct list_head list;          /* round-robin tid entry */
 467         struct list_head buf_q;         /* pending buffers */
 468         struct ath_node *an;
 469         struct ath_atx_ac *ac;
 470         struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
 471         u16 seq_start;
 472         u16 seq_next;
 473         u16 baw_size;
 474         int tidno;
 475         int baw_head;                   /* first un-acked tx buffer */
 476         int baw_tail;                   /* next unused tx buffer slot */
 477         int sched;
 478         int paused;
 479         int cleanup_inprogress;
 480         u32 addba_exchangecomplete:1;
 481         int32_t addba_exchangeinprogress;
 482         int addba_exchangeattempts;
 483 };
 484
 485 /* per access-category aggregate tx state for a destination */
 486 struct ath_atx_ac {
 487         int sched;                      /* dest-ac is scheduled */
 488         int qnum;                       /* H/W queue number associated
 489                                            with this AC */
 490         struct list_head list;          /* round-robin txq entry */
 491         struct list_head tid_q;         /* queue of TIDs with buffers */
 492 };
 493
 494 /* per dest tx state */
 495 struct ath_atx {
 496         struct ath_atx_tid tid[WME_NUM_TID];
 497         struct ath_atx_ac ac[WME_NUM_AC];
 498 };
 499
 500 /* per-frame tx control block */
 501 struct ath_tx_control {
 502         struct ath_node *an;
 503         int if_id;
 504         int qnum;
 505         u32 ht:1;
 506         u32 ps:1;
 507         u32 use_minrate:1;
 508         enum ath9k_pkt_type atype;
 509         enum ath9k_key_type keytype;
 510         u32 flags;
 511         u16 seqno;
 512         u16 tidno;
 513         u16 txpower;
 514         u16 frmlen;
 515         u32 keyix;
 516         int min_rate;
 517         int mcast_rate;
 518         u16 nextfraglen;
 519         struct ath_softc *dev;
 520         dma_addr_t dmacontext;
 521 };
 522
 523 /* per frame tx status block */
 524 struct ath_xmit_status {
 525         int retries;    /* number of retries to successufully
 526                            transmit this frame */
 527         int flags;      /* status of transmit */
 528 #define ATH_TX_ERROR        0x01
 529 #define ATH_TX_XRETRY       0x02
 530 #define ATH_TX_BAR          0x04
 531 };
 532
 533 struct ath_tx_stat {
 534         int rssi;               /* RSSI (noise floor ajusted) */
 535         int rssictl[ATH_MAX_ANTENNA];   /* RSSI (noise floor ajusted) */
 536         int rssiextn[ATH_MAX_ANTENNA];  /* RSSI (noise floor ajusted) */
 537         int rateieee;           /* data rate xmitted (IEEE rate code) */
 538         int rateKbps;           /* data rate xmitted (Kbps) */
 539         int ratecode;           /* phy rate code */
 540         int flags;              /* validity flags */
 541 /* if any of ctl,extn chain rssis are valid */
 542 #define ATH_TX_CHAIN_RSSI_VALID 0x01
 543 /* if extn chain rssis are valid */
 544 #define ATH_TX_RSSI_EXTN_VALID  0x02
 545         u32 airtime;    /* time on air per final tx rate */
 546 };
 547
 548 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 549 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 550 int ath_tx_setup(struct ath_softc *sc, int haltype);
 551 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
 552 void ath_tx_draintxq(struct ath_softc *sc,
 553                      struct ath_txq *txq, bool retry_tx);
 554 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 555 void ath_tx_node_cleanup(struct ath_softc *sc,
 556                          struct ath_node *an, bool bh_flag);
 557 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
 558 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 559 int ath_tx_init(struct ath_softc *sc, int nbufs);
 560 int ath_tx_cleanup(struct ath_softc *sc);
 561 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
 562 int ath_txq_update(struct ath_softc *sc, int qnum,
 563                    struct ath9k_tx_queue_info *q);
 564 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
 565 void ath_tx_tasklet(struct ath_softc *sc);
 566 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
 567 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
 568 void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
 569 void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 570                      struct ath_xmit_status *tx_status, struct ath_node *an);
 571
 572 /**********************/
 573 /* Node / Aggregation */
 574 /**********************/
 575
 576 /* indicates the node is clened up */
 577 #define ATH_NODE_CLEAN          0x1
 578 /* indicates the node is 80211 power save */
 579 #define ATH_NODE_PWRSAVE        0x2
 580
 581 #define ADDBA_EXCHANGE_ATTEMPTS    10
 582 #define ATH_AGGR_DELIM_SZ          4   /* delimiter size   */
 583 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 584 /* number of delimiters for encryption padding */
 585 #define ATH_AGGR_ENCRYPTDELIM      10
 586 /* minimum h/w qdepth to be sustained to maximize aggregation */
 587 #define ATH_AGGR_MIN_QDEPTH        2
 588 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 589 #define IEEE80211_SEQ_SEQ_SHIFT    4
 590 #define IEEE80211_SEQ_MAX          4096
 591 #define IEEE80211_MIN_AMPDU_BUF    0x8
 592
 593 /* return whether a bit at index _n in bitmap _bm is set
 594  * _sz is the size of the bitmap  */
 595 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 596                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 597
 598 /* return block-ack bitmap index given sequence and starting sequence */
 599 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 600
 601 /* returns delimiter padding required given the packet length */
 602 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 603         (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
 604           (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
 605
 606 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 607         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 608
 609 #define ATH_DS_BA_SEQ(_ds)               ((_ds)->ds_us.tx.ts_seqnum)
 610 #define ATH_DS_BA_BITMAP(_ds)            (&(_ds)->ds_us.tx.ba_low)
 611 #define ATH_DS_TX_BA(_ds)       ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
 612 #define ATH_AN_2_TID(_an, _tidno)        (&(_an)->an_aggr.tx.tid[(_tidno)])
 613
 614 enum ATH_AGGR_STATUS {
 615         ATH_AGGR_DONE,
 616         ATH_AGGR_BAW_CLOSED,
 617         ATH_AGGR_LIMITED,
 618         ATH_AGGR_SHORTPKT,
 619         ATH_AGGR_8K_LIMITED,
 620 };
 621
 622 enum ATH_AGGR_CHECK {
 623         AGGR_NOT_REQUIRED,
 624         AGGR_REQUIRED,
 625         AGGR_CLEANUP_PROGRESS,
 626         AGGR_EXCHANGE_PROGRESS,
 627         AGGR_EXCHANGE_DONE
 628 };
 629
 630 struct aggr_rifs_param {
 631         int param_max_frames;
 632         int param_max_len;
 633         int param_rl;
 634         int param_al;
 635         struct ath_rc_series *param_rcs;
 636 };
 637
 638 /* Per-node aggregation state */
 639 struct ath_node_aggr {
 640         struct ath_atx tx;      /* node transmit state */
 641         struct ath_arx rx;      /* node receive state */
 642 };
 643
 644 /* driver-specific node state */
 645 struct ath_node {
 646         struct list_head list;
 647         struct ath_softc *an_sc;
 648         atomic_t an_refcnt;
 649         struct ath_chainmask_sel an_chainmask_sel;
 650         struct ath_node_aggr an_aggr;
 651         u8 an_smmode; /* SM Power save mode */
 652         u8 an_flags;
 653         u8 an_addr[ETH_ALEN];
 654 };
 655
 656 void ath_tx_resume_tid(struct ath_softc *sc,
 657         struct ath_atx_tid *tid);
 658 enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
 659         struct ath_node *an, u8 tidno);
 660 void ath_tx_aggr_teardown(struct ath_softc *sc,
 661         struct ath_node *an, u8 tidno);
 662 void ath_rx_aggr_teardown(struct ath_softc *sc,
 663         struct ath_node *an, u8 tidno);
 664 int ath_rx_aggr_start(struct ath_softc *sc,
 665                       const u8 *addr,
 666                       u16 tid,
 667                       u16 *ssn);
 668 int ath_rx_aggr_stop(struct ath_softc *sc,
 669                      const u8 *addr,
 670                      u16 tid);
 671 int ath_tx_aggr_start(struct ath_softc *sc,
 672                       const u8 *addr,
 673                       u16 tid,
 674                       u16 *ssn);
 675 int ath_tx_aggr_stop(struct ath_softc *sc,
 676                      const u8 *addr,
 677                      u16 tid);
 678 void ath_newassoc(struct ath_softc *sc,
 679         struct ath_node *node, int isnew, int isuapsd);
 680 struct ath_node *ath_node_attach(struct ath_softc *sc,
 681         u8 addr[ETH_ALEN], int if_id);
 682 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
 683 struct ath_node *ath_node_get(struct ath_softc *sc, u8 addr[ETH_ALEN]);
 684 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
 685 struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr);
 686
 687 /*******************/
 688 /* Beacon Handling */
 689 /*******************/
 690
 691 /*
 692  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 693  * number of BSSIDs) if a given beacon does not go out even after waiting this
 694  * number of beacon intervals, the game's up.
 695  */
 696 #define BSTUCK_THRESH                   (9 * ATH_BCBUF)
 697 #define ATH_BCBUF                       4   /* number of beacon buffers */
 698 #define ATH_DEFAULT_BINTVAL             100 /* default beacon interval in TU */
 699 #define ATH_DEFAULT_BMISS_LIMIT         10
 700 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 701
 702 /* beacon configuration */
 703 struct ath_beacon_config {
 704         u16 beacon_interval;
 705         u16 listen_interval;
 706         u16 dtim_period;
 707         u16 bmiss_timeout;
 708         u8 dtim_count;
 709         u8 tim_offset;
 710         union {
 711                 u64 last_tsf;
 712                 u8 last_tstamp[8];
 713         } u; /* last received beacon/probe response timestamp of this BSS. */
 714 };
 715
 716 /* offsets in a beacon frame for
 717  * quick acess of beacon content by low-level driver */
 718 struct ath_beacon_offset {
 719         u8 *bo_tim;     /* start of atim/dtim */
 720 };
 721
 722 void ath9k_beacon_tasklet(unsigned long data);
 723 void ath_beacon_config(struct ath_softc *sc, int if_id);
 724 int ath_beaconq_setup(struct ath_hal *ah);
 725 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
 726 void ath_bstuck_process(struct ath_softc *sc);
 727 void ath_beacon_tasklet(struct ath_softc *sc, int *needmark);
 728 void ath_beacon_free(struct ath_softc *sc);
 729 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
 730 void ath_beacon_sync(struct ath_softc *sc, int if_id);
 731 void ath_update_beacon_info(struct ath_softc *sc, int avgbrssi);
 732 void ath_get_beaconconfig(struct ath_softc *sc,
 733                           int if_id,
 734                           struct ath_beacon_config *conf);
 735 int ath_update_beacon(struct ath_softc *sc,
 736                       int if_id,
 737                       struct ath_beacon_offset *bo,
 738                       struct sk_buff *skb,
 739                       int mcast);
 740 /********/
 741 /* VAPs */
 742 /********/
 743
 744 /*
 745  * Define the scheme that we select MAC address for multiple
 746  * BSS on the same radio. The very first VAP will just use the MAC
 747  * address from the EEPROM. For the next 3 VAPs, we set the
 748  * U/L bit (bit 1) in MAC address, and use the next two bits as the
 749  * index of the VAP.
 750  */
 751
 752 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
 753         ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
 754
 755 /* VAP configuration (from protocol layer) */
 756 struct ath_vap_config {
 757         u32 av_fixed_rateset;
 758         u32 av_fixed_retryset;
 759 };
 760
 761 /* driver-specific vap state */
 762 struct ath_vap {
 763         struct ieee80211_vif *av_if_data;
 764         enum ath9k_opmode av_opmode;    /* VAP operational mode */
 765         struct ath_buf *av_bcbuf;       /* beacon buffer */
 766         struct ath_beacon_offset av_boff; /* dynamic update state */
 767         struct ath_tx_control av_btxctl;  /* txctl information for beacon */
 768         int av_bslot;                   /* beacon slot index */
 769         struct ath_txq av_mcastq;       /* multicast transmit queue */
 770         struct ath_vap_config av_config;/* vap configuration parameters*/
 771         struct ath_rate_node *rc_node;
 772 };
 773
 774 int ath_vap_attach(struct ath_softc *sc,
 775                    int if_id,
 776                    struct ieee80211_vif *if_data,
 777                    enum ath9k_opmode opmode);
 778 int ath_vap_detach(struct ath_softc *sc, int if_id);
 779 int ath_vap_config(struct ath_softc *sc,
 780         int if_id, struct ath_vap_config *if_config);
 781 int ath_vap_listen(struct ath_softc *sc, int if_id);
 782
 783 /*********************/
 784 /* Antenna diversity */
 785 /*********************/
 786
 787 #define ATH_ANT_DIV_MAX_CFG      2
 788 #define ATH_ANT_DIV_MIN_IDLE_US  1000000  /* us */
 789 #define ATH_ANT_DIV_MIN_SCAN_US  50000    /* us */
 790
 791 enum ATH_ANT_DIV_STATE{
 792         ATH_ANT_DIV_IDLE,
 793         ATH_ANT_DIV_SCAN,       /* evaluating antenna */
 794 };
 795
 796 struct ath_antdiv {
 797         struct ath_softc *antdiv_sc;
 798         u8 antdiv_start;
 799         enum ATH_ANT_DIV_STATE antdiv_state;
 800         u8 antdiv_num_antcfg;
 801         u8 antdiv_curcfg;
 802         u8 antdiv_bestcfg;
 803         int32_t antdivf_rssitrig;
 804         int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
 805         u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
 806         u64 antdiv_laststatetsf;
 807         u8 antdiv_bssid[ETH_ALEN];
 808 };
 809
 810 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
 811         struct ath_softc *sc, int32_t rssitrig);
 812 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
 813                             u8 num_antcfg,
 814                             const u8 *bssid);
 815 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
 816 void ath_slow_ant_div(struct ath_antdiv *antdiv,
 817                       struct ieee80211_hdr *wh,
 818                       struct ath_rx_status *rx_stats);
 819 void ath_setdefantenna(void *sc, u32 antenna);
 820
 821 /********************/
 822 /* Main driver core */
 823 /********************/
 824
 825 /*
 826  * Default cache line size, in bytes.
 827  * Used when PCI device not fully initialized by bootrom/BIOS
 828 */
 829 #define DEFAULT_CACHELINE       32
 830 #define ATH_DEFAULT_NOISE_FLOOR -95
 831 #define ATH_REGCLASSIDS_MAX     10
 832 #define ATH_CABQ_READY_TIME     80  /* % of beacon interval */
 833 #define ATH_MAX_SW_RETRIES      10
 834 #define ATH_CHAN_MAX            255
 835 #define IEEE80211_WEP_NKID      4       /* number of key ids */
 836 #define IEEE80211_RATE_VAL      0x7f
 837 /*
 838  * The key cache is used for h/w cipher state and also for
 839  * tracking station state such as the current tx antenna.
 840  * We also setup a mapping table between key cache slot indices
 841  * and station state to short-circuit node lookups on rx.
 842  * Different parts have different size key caches.  We handle
 843  * up to ATH_KEYMAX entries (could dynamically allocate state).
 844  */
 845 #define ATH_KEYMAX              128        /* max key cache size we handle */
 846
 847 #define ATH_IF_ID_ANY           0xff
 848 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 849
 850 #define RSSI_LPF_THRESHOLD         -20
 851 #define ATH_RSSI_EP_MULTIPLIER     (1<<7)  /* pow2 to optimize out * and / */
 852 #define ATH_RATE_DUMMY_MARKER      0
 853 #define ATH_RSSI_LPF_LEN           10
 854 #define ATH_RSSI_DUMMY_MARKER      0x127
 855
 856 #define ATH_EP_MUL(x, mul)         ((x) * (mul))
 857 #define ATH_EP_RND(x, mul)                                              \
 858         ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
 859 #define ATH_RSSI_OUT(x)                                                 \
 860         (((x) != ATH_RSSI_DUMMY_MARKER) ?                               \
 861          (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
 862 #define ATH_RSSI_IN(x)                                  \
 863         (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
 864 #define ATH_LPF_RSSI(x, y, len)                                         \
 865         ((x != ATH_RSSI_DUMMY_MARKER) ? \
 866                 (((x) * ((len) - 1) + (y)) / (len)) : (y))
 867 #define ATH_RSSI_LPF(x, y) do {                                         \
 868                 if ((y) >= RSSI_LPF_THRESHOLD)                          \
 869                         x = ATH_LPF_RSSI((x), \
 870                                 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
 871         } while (0)
 872
 873
 874 enum PROT_MODE {
 875         PROT_M_NONE = 0,
 876         PROT_M_RTSCTS,
 877         PROT_M_CTSONLY
 878 };
 879
 880 enum RATE_TYPE {
 881         NORMAL_RATE = 0,
 882         HALF_RATE,
 883         QUARTER_RATE
 884 };
 885
 886 struct ath_ht_info {
 887         enum ath9k_ht_macmode tx_chan_width;
 888         u16 maxampdu;
 889         u8 mpdudensity;
 890         u8 ext_chan_offset;
 891 };
 892
 893 #define SC_OP_INVALID           BIT(0)
 894 #define SC_OP_BEACONS           BIT(1)
 895 #define SC_OP_RXAGGR            BIT(2)
 896 #define SC_OP_TXAGGR            BIT(3)
 897 #define SC_OP_CHAINMASK_UPDATE  BIT(4)
 898 #define SC_OP_FULL_RESET        BIT(5)
 899 #define SC_OP_PREAMBLE_SHORT    BIT(6)
 900 #define SC_OP_PROTECT_ENABLE    BIT(7)
 901
 902 struct ath_softc {
 903         struct ieee80211_hw *hw;
 904         struct pci_dev *pdev;
 905         struct tasklet_struct intr_tq;
 906         struct tasklet_struct bcon_tasklet;
 907         struct ath_config sc_config;
 908         struct ath_hal *sc_ah;
 909         struct ath_rate_softc *sc_rc;
 910         void __iomem *mem;
 911
 912         int sc_debug;
 913         u32 sc_intrstatus;
 914         u32 sc_flags; /* SC_OP_* */
 915         unsigned int rx_filter;
 916
 917         enum wireless_mode sc_curmode;  /* current phy mode */
 918         u16 sc_curtxpow;
 919         u16 sc_curaid;
 920         u8 sc_curbssid[ETH_ALEN];
 921         u8 sc_myaddr[ETH_ALEN];
 922         enum PROT_MODE sc_protmode;
 923         u8 sc_mcastantenna;
 924         u8 sc_txantenna;                /* data tx antenna (fixed or auto) */
 925         u8 sc_nbcnvaps;                 /* # of vaps sending beacons */
 926         u16 sc_nvaps;                   /* # of active virtual ap's */
 927         struct ath_vap *sc_vaps[ATH_BCBUF];
 928         enum ath9k_int sc_imask;
 929         u8 sc_bssidmask[ETH_ALEN];
 930         u8 sc_defant;                   /* current default antenna */
 931         u8 sc_rxotherant;               /* rx's on non-default antenna */
 932         u16 sc_cachelsz;
 933         int sc_slotupdate;              /* slot to next advance fsm */
 934         int sc_slottime;
 935         u8 sc_noreset;
 936         int sc_bslot[ATH_BCBUF];
 937         struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
 938         struct list_head node_list;
 939         struct ath_ht_info sc_ht_info;
 940         int16_t sc_noise_floor;         /* signal noise floor in dBm */
 941         enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
 942         u8 sc_tx_chainmask;
 943         u8 sc_rx_chainmask;
 944         u8 sc_rxchaindetect_ref;
 945         u8 sc_rxchaindetect_thresh5GHz;
 946         u8 sc_rxchaindetect_thresh2GHz;
 947         u8 sc_rxchaindetect_delta5GHz;
 948         u8 sc_rxchaindetect_delta2GHz;
 949         u32 sc_rtsaggrlimit;            /* Chipset specific aggr limit */
 950 #ifdef CONFIG_SLOW_ANT_DIV
 951         struct ath_antdiv sc_antdiv;
 952 #endif
 953         enum {
 954                 OK,             /* no change needed */
 955                 UPDATE,         /* update pending */
 956                 COMMIT          /* beacon sent, commit change */
 957         } sc_updateslot;        /* slot time update fsm */
 958
 959         /* Crypto */
 960         u32 sc_keymax;          /* size of key cache */
 961         DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);  /* key use bit map */
 962         u8 sc_splitmic;         /* split TKIP MIC keys */
 963         int sc_keytype;
 964
 965         /* RX */
 966         struct list_head sc_rxbuf;
 967         struct ath_descdma sc_rxdma;
 968         int sc_rxbufsize;       /* rx size based on mtu */
 969         u32 *sc_rxlink;         /* link ptr in last RX desc */
 970         u32 sc_rxflush;         /* rx flush in progress */
 971         u64 sc_lastrx;          /* tsf of last rx'd frame */
 972
 973         /* TX */
 974         struct list_head sc_txbuf;
 975         struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
 976         struct ath_descdma sc_txdma;
 977         u32 sc_txqsetup;
 978         u32 sc_txintrperiod;    /* tx interrupt batching */
 979         int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
 980         u32 sc_ant_tx[8];       /* recent tx frames/antenna */
 981
 982         /* Beacon */
 983         struct ath9k_tx_queue_info sc_beacon_qi;
 984         struct ath_descdma sc_bdma;
 985         struct ath_txq *sc_cabq;
 986         struct list_head sc_bbuf;
 987         u32 sc_bhalq;
 988         u32 sc_bmisscount;
 989         u32 ast_be_xmit;        /* beacons transmitted */
 990
 991         /* Rate */
 992         struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
 993         const struct ath9k_rate_table *sc_currates;
 994         u8 sc_rixmap[256];      /* IEEE to h/w rate table ix */
 995         u8 sc_protrix;          /* protection rate index */
 996         struct {
 997                 u32 rateKbps;   /* transfer rate in kbs */
 998                 u8 ieeerate;    /* IEEE rate */
 999         } sc_hwmap[256];        /* h/w rate ix mappings */
1000
1001         /* Channel, Band */
1002         struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
1003         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1004
1005         /* Locks */
1006         spinlock_t sc_rxflushlock;
1007         spinlock_t sc_rxbuflock;
1008         spinlock_t sc_txbuflock;
1009         spinlock_t sc_resetlock;
1010         spinlock_t node_lock;
1011 };
1012
1013 int ath_init(u16 devid, struct ath_softc *sc);
1014 void ath_deinit(struct ath_softc *sc);
1015 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
1016 int ath_suspend(struct ath_softc *sc);
1017 irqreturn_t ath_isr(int irq, void *dev);
1018 int ath_reset(struct ath_softc *sc, bool retry_tx);
1019 void ath_scan_start(struct ath_softc *sc);
1020 void ath_scan_end(struct ath_softc *sc);
1021 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
1022 void ath_setup_rate(struct ath_softc *sc,
1023                     enum wireless_mode wMode,
1024                     enum RATE_TYPE type,
1025                     const struct ath9k_rate_table *rt);
1026
1027 /*********************/
1028 /* Utility Functions */
1029 /*********************/
1030
1031 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
1032 int ath_keyset(struct ath_softc *sc,
1033                u16 keyix,
1034                struct ath9k_keyval *hk,
1035                const u8 mac[ETH_ALEN]);
1036 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1037 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
1038 void ath_setslottime(struct ath_softc *sc);
1039 void ath_update_txpow(struct ath_softc *sc);
1040 int ath_cabq_update(struct ath_softc *);
1041 void ath_get_currentCountry(struct ath_softc *sc,
1042         struct ath9k_country_entry *ctry);
1043 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
1044 u32 ath_chan2flags(struct ieee80211_channel *chan, struct ath_softc *sc);
1045 dma_addr_t ath_skb_map_single(struct ath_softc *sc,
1046                               struct sk_buff *skb,
1047                               int direction,
1048                               dma_addr_t *pa);
1049 void ath_skb_unmap_single(struct ath_softc *sc,
1050                           struct sk_buff *skb,
1051                           int direction,
1052                           dma_addr_t *pa);
1053 void ath_mcast_merge(struct ath_softc *sc, u32 mfilt[2]);
1054 enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
1055
1056 #endif /* CORE_H */