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[MIPS] TXx9: cleanup and fix some sparse warnings
[linux-2.6/kvm.git] / arch / mips / txx9 / rbtx4927 / setup.c
blob1657fd935da80bb99f58dc8d25d2ae39f21eaf7d
1 /*
2 * Toshiba rbtx4927 specific setup
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2001-2002 MontaVista Software Inc.
8 *
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
13 *
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
16 *
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
19 *
20 * Copyright (C) 2000-2001 Toshiba Corporation
21 *
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
29 *
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
44 */
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/ioport.h>
49 #include <linux/interrupt.h>
50 #include <linux/pm.h>
51 #include <linux/platform_device.h>
52 #include <linux/delay.h>
53 #include <asm/io.h>
54 #include <asm/processor.h>
55 #include <asm/reboot.h>
56 #include <asm/time.h>
57 #include <asm/txx9tmr.h>
58 #include <asm/txx9/generic.h>
59 #include <asm/txx9/pci.h>
60 #include <asm/txx9/rbtx4927.h>
61 #include <asm/txx9/tx4938.h> /* for TX4937 */
62 #ifdef CONFIG_SERIAL_TXX9
63 #include <linux/serial_core.h>
64 #endif
65
66 static int tx4927_ccfg_toeon = 1;
67
68 #ifdef CONFIG_PCI
69 static void __init tx4927_pci_setup(void)
70 {
71 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
72 struct pci_controller *c = &txx9_primary_pcic;
73
74 register_pci_controller(c);
75
76 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
77 txx9_pci_option =
78 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
79 TXX9_PCI_OPT_CLK_66; /* already configured */
80
81 /* Reset PCI Bus */
82 writeb(1, rbtx4927_pcireset_addr);
83 /* Reset PCIC */
84 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
85 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
86 TXX9_PCI_OPT_CLK_66)
87 tx4927_pciclk66_setup();
88 mdelay(10);
89 /* clear PCIC reset */
90 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
91 writeb(0, rbtx4927_pcireset_addr);
92 iob();
93
94 tx4927_report_pciclk();
95 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
96 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
97 TXX9_PCI_OPT_CLK_AUTO &&
98 txx9_pci66_check(c, 0, 0)) {
99 /* Reset PCI Bus */
100 writeb(1, rbtx4927_pcireset_addr);
101 /* Reset PCIC */
102 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
103 tx4927_pciclk66_setup();
104 mdelay(10);
105 /* clear PCIC reset */
106 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
107 writeb(0, rbtx4927_pcireset_addr);
108 iob();
109 /* Reinitialize PCIC */
110 tx4927_report_pciclk();
111 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
112 }
113 }
114
115 static void __init tx4937_pci_setup(void)
116 {
117 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
118 struct pci_controller *c = &txx9_primary_pcic;
119
120 register_pci_controller(c);
121
122 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
123 txx9_pci_option =
124 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
125 TXX9_PCI_OPT_CLK_66; /* already configured */
126
127 /* Reset PCI Bus */
128 writeb(1, rbtx4927_pcireset_addr);
129 /* Reset PCIC */
130 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
131 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
132 TXX9_PCI_OPT_CLK_66)
133 tx4938_pciclk66_setup();
134 mdelay(10);
135 /* clear PCIC reset */
136 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
137 writeb(0, rbtx4927_pcireset_addr);
138 iob();
139
140 tx4938_report_pciclk();
141 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
142 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
143 TXX9_PCI_OPT_CLK_AUTO &&
144 txx9_pci66_check(c, 0, 0)) {
145 /* Reset PCI Bus */
146 writeb(1, rbtx4927_pcireset_addr);
147 /* Reset PCIC */
148 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
149 tx4938_pciclk66_setup();
150 mdelay(10);
151 /* clear PCIC reset */
152 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
153 writeb(0, rbtx4927_pcireset_addr);
154 iob();
155 /* Reinitialize PCIC */
156 tx4938_report_pciclk();
157 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
158 }
159 }
160
161 static void __init rbtx4927_arch_init(void)
162 {
163 tx4927_pci_setup();
164 }
165
166 static void __init rbtx4937_arch_init(void)
167 {
168 tx4937_pci_setup();
169 }
170 #else
171 #define rbtx4927_arch_init NULL
172 #define rbtx4937_arch_init NULL
173 #endif /* CONFIG_PCI */
174
175 static void __noreturn wait_forever(void)
176 {
177 while (1)
178 if (cpu_wait)
179 (*cpu_wait)();
180 }
181
182 static void toshiba_rbtx4927_restart(char *command)
183 {
184 printk(KERN_NOTICE "System Rebooting...\n");
185
186 /* enable the s/w reset register */
187 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
188
189 /* wait for enable to be seen */
190 while ((readb(RBTX4927_SW_RESET_ENABLE) &
191 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
192
193 /* do a s/w reset */
194 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
195
196 /* do something passive while waiting for reset */
197 local_irq_disable();
198 wait_forever();
199 /* no return */
200 }
201
202 static void toshiba_rbtx4927_halt(void)
203 {
204 printk(KERN_NOTICE "System Halted\n");
205 local_irq_disable();
206 wait_forever();
207 /* no return */
208 }
209
210 static void toshiba_rbtx4927_power_off(void)
211 {
212 toshiba_rbtx4927_halt();
213 /* no return */
214 }
215
216 static void __init rbtx4927_mem_setup(void)
217 {
218 int i;
219 u32 cp0_config;
220 char *argptr;
221
222 /* f/w leaves this on at startup */
223 clear_c0_status(ST0_ERL);
224
225 /* enable caches -- HCP5 does this, pmon does not */
226 cp0_config = read_c0_config();
227 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
228 write_c0_config(cp0_config);
229
230 ioport_resource.end = 0xffffffff;
231 iomem_resource.end = 0xffffffff;
232
233 _machine_restart = toshiba_rbtx4927_restart;
234 _machine_halt = toshiba_rbtx4927_halt;
235 pm_power_off = toshiba_rbtx4927_power_off;
236
237 for (i = 0; i < TX4927_NR_TMR; i++)
238 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
239
240 #ifdef CONFIG_PCI
241 txx9_alloc_pci_controller(&txx9_primary_pcic,
242 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
243 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
244 #else
245 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
246 #endif
247
248 /* CCFG */
249 /* do reset on watchdog */
250 tx4927_ccfg_set(TX4927_CCFG_WR);
251 /* enable Timeout BusError */
252 if (tx4927_ccfg_toeon)
253 tx4927_ccfg_set(TX4927_CCFG_TOE);
254
255 #ifdef CONFIG_SERIAL_TXX9
256 {
257 extern int early_serial_txx9_setup(struct uart_port *port);
258 struct uart_port req;
259 for(i = 0; i < 2; i++) {
260 memset(&req, 0, sizeof(req));
261 req.line = i;
262 req.iotype = UPIO_MEM;
263 req.membase = (char *)(0xff1ff300 + i * 0x100);
264 req.mapbase = 0xff1ff300 + i * 0x100;
265 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
266 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
267 req.uartclk = 50000000;
268 early_serial_txx9_setup(&req);
269 }
270 }
271 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
272 argptr = prom_getcmdline();
273 if (strstr(argptr, "console=") == NULL) {
274 strcat(argptr, " console=ttyS0,38400");
275 }
276 #endif
277 #endif
278
279 #ifdef CONFIG_ROOT_NFS
280 argptr = prom_getcmdline();
281 if (strstr(argptr, "root=") == NULL) {
282 strcat(argptr, " root=/dev/nfs rw");
283 }
284 #endif
285
286 #ifdef CONFIG_IP_PNP
287 argptr = prom_getcmdline();
288 if (strstr(argptr, "ip=") == NULL) {
289 strcat(argptr, " ip=any");
290 }
291 #endif
292 }
293
294 static void __init rbtx49x7_common_time_init(void)
295 {
296 /* change default value to udelay/mdelay take reasonable time */
297 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
298
299 mips_hpt_frequency = txx9_cpu_clock / 2;
300 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
301 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
302 TXX9_IRQ_BASE + 17,
303 50000000);
304 }
305
306 static void __init rbtx4927_time_init(void)
307 {
308 /*
309 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
310 *
311 * For TX4927:
312 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
313 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
314 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
315 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
316 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
317 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
318 */
319 switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
320 TX4927_CCFG_PCIDIVMODE_MASK) {
321 case TX4927_CCFG_PCIDIVMODE_2_5:
322 case TX4927_CCFG_PCIDIVMODE_5:
323 txx9_cpu_clock = 166666666; /* 166MHz */
324 break;
325 default:
326 txx9_cpu_clock = 200000000; /* 200MHz */
327 }
328
329 rbtx49x7_common_time_init();
330 }
331
332 static void __init rbtx4937_time_init(void)
333 {
334 /*
335 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
336 *
337 * For TX4937:
338 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
339 * PCIDIVMODE[10] is 0.
340 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
341 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
342 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
343 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
344 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
345 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
346 */
347 switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
348 TX4938_CCFG_PCIDIVMODE_MASK) {
349 case TX4938_CCFG_PCIDIVMODE_8:
350 case TX4938_CCFG_PCIDIVMODE_4:
351 txx9_cpu_clock = 266666666; /* 266MHz */
352 break;
353 case TX4938_CCFG_PCIDIVMODE_9:
354 case TX4938_CCFG_PCIDIVMODE_4_5:
355 txx9_cpu_clock = 300000000; /* 300MHz */
356 break;
357 default:
358 txx9_cpu_clock = 333333333; /* 333MHz */
359 }
360
361 rbtx49x7_common_time_init();
362 }
363
364 static int __init toshiba_rbtx4927_rtc_init(void)
365 {
366 static struct resource __initdata res = {
367 .start = 0x1c010000,
368 .end = 0x1c010000 + 0x800 - 1,
369 .flags = IORESOURCE_MEM,
370 };
371 struct platform_device *dev =
372 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
373 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
374 }
375
376 static int __init rbtx4927_ne_init(void)
377 {
378 static struct resource __initdata res[] = {
379 {
380 .start = RBTX4927_RTL_8019_BASE,
381 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
382 .flags = IORESOURCE_IO,
383 }, {
384 .start = RBTX4927_RTL_8019_IRQ,
385 .flags = IORESOURCE_IRQ,
386 }
387 };
388 struct platform_device *dev =
389 platform_device_register_simple("ne", -1,
390 res, ARRAY_SIZE(res));
391 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
392 }
393
394 /* Watchdog support */
395
396 static int __init txx9_wdt_init(unsigned long base)
397 {
398 struct resource res = {
399 .start = base,
400 .end = base + 0x100 - 1,
401 .flags = IORESOURCE_MEM,
402 };
403 struct platform_device *dev =
404 platform_device_register_simple("txx9wdt", -1, &res, 1);
405 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
406 }
407
408 static int __init rbtx4927_wdt_init(void)
409 {
410 return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
411 }
412
413 static void __init rbtx4927_device_init(void)
414 {
415 toshiba_rbtx4927_rtc_init();
416 rbtx4927_ne_init();
417 rbtx4927_wdt_init();
418 }
419
420 struct txx9_board_vec rbtx4927_vec __initdata = {
421 .system = "Toshiba RBTX4927",
422 .prom_init = rbtx4927_prom_init,
423 .mem_setup = rbtx4927_mem_setup,
424 .irq_setup = rbtx4927_irq_setup,
425 .time_init = rbtx4927_time_init,
426 .device_init = rbtx4927_device_init,
427 .arch_init = rbtx4927_arch_init,
428 #ifdef CONFIG_PCI
429 .pci_map_irq = rbtx4927_pci_map_irq,
430 #endif
431 };
432 struct txx9_board_vec rbtx4937_vec __initdata = {
433 .system = "Toshiba RBTX4937",
434 .prom_init = rbtx4927_prom_init,
435 .mem_setup = rbtx4927_mem_setup,
436 .irq_setup = rbtx4927_irq_setup,
437 .time_init = rbtx4937_time_init,
438 .device_init = rbtx4927_device_init,
439 .arch_init = rbtx4937_arch_init,
440 #ifdef CONFIG_PCI
441 .pci_map_irq = rbtx4927_pci_map_irq,
442 #endif
443 };
kernel-based virtual machine